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2021-09-28mtd: nand: raw: convert nand_dt_init() to ofnode_xx() interfacePatrice Chotard1-3/+3
nand_dt_init() is still using fdtdec_xx() interface. If OF_LIVE flag is enabled, dt property can't be get anymore. Updating all fdtdec_xx() interface to ofnode_xx() to solve this issue. For doing this, node parameter type must be ofnode. First idea was to convert "node" parameter to ofnode type inside nand_dt_init() using offset_to_ofnode(node). But offset_to_ofnode() is not bijective, in case OF_LIVE flag is enabled, it performs an assert(). So, this leads to update nand_chip struct flash_node field from int to ofnode and to update all nand_dt_init() callers. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-09-28mtd: spi: nor: force mtd name to "nor%d"Patrick Delaunay1-0/+2
Force the mtd name of spi-nor to "nor" + the driver sequence number: "nor0", "nor1"... beginning after the existing nor devices. This patch is coherent with existing "nand" and "spi-nand" mtd device names. When CFI MTD NOR device are supported, the spi-nor index is chosen after the last CFI device defined by CONFIG_SYS_MAX_FLASH_BANKS. When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is activated, this config is replaced by to cfi_flash_num_flash_banks in the include file mtd/cfi_flash.h. This generic name "nor%d" can be use to identify the mtd spi-nor device without knowing the real device name or the DT path of the device, used with API get_mtd_device_nm() and is used in mtdparts command. This patch also avoids issue when the same NOR device is present 2 times, for example on STM32MP15F-EV1: STM32MP> mtd list SF: Detected mx66l51235l with page size 256 Bytes, erase size 64 KiB, \ total 64 MiB List of MTD devices: * nand0 - type: NAND flash - block size: 0x40000 bytes - min I/O: 0x1000 bytes - OOB size: 224 bytes - OOB available: 118 bytes - ECC strength: 8 bits - ECC step size: 512 bytes - bitflip threshold: 6 bits - 0x000000000000-0x000040000000 : "nand0" * mx66l51235l - device: mx66l51235l@0 - parent: spi@58003000 - driver: jedec_spi_nor - path: /soc/spi@58003000/mx66l51235l@0 - type: NOR flash - block size: 0x10000 bytes - min I/O: 0x1 bytes - 0x000000000000-0x000004000000 : "mx66l51235l" * mx66l51235l - device: mx66l51235l@1 - parent: spi@58003000 - driver: jedec_spi_nor - path: /soc/spi@58003000/mx66l51235l@1 - type: NOR flash - block size: 0x10000 bytes - min I/O: 0x1 bytes - 0x000000000000-0x000004000000 : "mx66l51235l" The same mtd name "mx66l51235l" identify the 2 instances mx66l51235l@0 and mx66l51235l@1. This patch fixes a ST32CubeProgrammer / stm32prog command issue with nor0 target on STM32MP157C-EV1 board introduced by commit b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when DM is enabled"). Fixes: b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when DM is enabled") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> [trini: Add <dm/device.h> to <mtd.h> for DM_MAX_SEQ_STR] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-24mtd: remove SPEAr flash driver st_smiPatrick Delaunay1-100/+0
Remove the driver st_smic.c used in SPEAr products and the associated config CONFIG_ST_SMI; this driver is no more used in U-Boot after the commit 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support"). Fixes: 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2021-09-22usb: add support for ULPI/SERIAL/HSIC PHY modesMatthias Schiffer1-0/+3
Import usb_phy_interface enum values and DT match strings from the Linux kernel. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
2021-09-17firmware: ti_sci: Include linux/err.h in ti_sci_protocol.hSuman Anna1-1/+3
The common TI SCI header file uses some macros from err.h and these get exercised when CONFIG_TI_SCI_PROTOCOL is not defined. Include the linux/err.h header file in this header file directly rather than relying on source files to include it to eliminate any potential build errors. While at this, reorder the existing header file include to the beginning of the file. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
2021-07-26net: ethtool: Add ethernet speed macros for higher speedsAshok Reddy Soma1-0/+8
Add speed macro's for higher ethernet speeds to be used in u-boot networking drivers. Added Macros for speeds 14G, 20G, 25G, 40G, 50G, 56G, 100G and 200G inline with linux. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-15soc: ti: pruss: Add a platform driver for PRUSS in TI SoCsKeerthy1-0/+227
The Programmable Real-Time Unit - Industrial Communication Subsystem (PRU-ICSS) is present of various TI SoCs such as AM335x or AM437x or the AM654x family. Each SoC can have one or more PRUSS instances that may or may not be identical. The PRUSS consists of dual 32-bit RISC cores called the Programmable Real-Time Units (PRUs), some shared, data and instruction memories, some internal peripheral modules, and an interrupt controller. The programmable nature of the PRUs provide flexibility to implement custom peripheral interfaces, fast real-time responses, or specialized data handling. Add support for pruss driver. Currently am654x family is supported. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210622063431.3151-2-lokeshvutla@ti.com
2021-07-01build_bug.h: add wrapper for _Static_assertRasmus Villemoes1-0/+19
[Linux commit 6bab69c65013bed5fce9f101a64a84d0385b3946] BUILD_BUG_ON() is a little annoying, since it cannot be used outside function scope. So one cannot put assertions about the sizeof() a struct next to the struct definition, but has to hide that in some more or less arbitrary function. Since gcc 4.6 (which is now also the required minimum), there is support for the C11 _Static_assert in all C modes, including gnu89. So add a simple wrapper for that. _Static_assert() requires a message argument, which is usually quite redundant (and I believe that bug got fixed at least in newer C++ standards), but we can easily work around that with a little macro magic, making it optional. For example, adding static_assert(sizeof(struct printf_spec) == 8); in vsprintf.c and modifying that struct to violate it, one gets ./include/linux/build_bug.h:78:41: error: static assertion failed: "sizeof(struct printf_spec) == 8" #define __static_assert(expr, msg, ...) _Static_assert(expr, "" msg "") godbolt.org suggests that _Static_assert() has been support by clang since at least 3.0.0. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-29mtd: spi-nor-core: Add fixups for Cypress s25hl-t/s25hs-tTakahiro Kuwano1-0/+3
The nor->ready() and spansion_sr_ready() introduced earlier in this series are used for multi-die package parts. The nor->quad_enable() sets the volatile QE bit on each die. The nor->erase() is hooked if the device is not configured to uniform sectors, assuming it has 32 x 4KB sectors overlaid on bottom address. Other configurations, top and split, are not supported at this point. Will submit additional patches to support it as needed. The post_bfpt/sfdp() fixes the params wrongly advertised in SFDP. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29mtd: spi-nor-core: Add Cypress manufacturer ID in set_4byteTakahiro Kuwano1-0/+1
Cypress chips support SPINOR_OP_EN4B(B7h) to enable 4-byte addressing mode. Cypress chips support B8h to disable 4-byte addressing mode instead of SPINOR_OP_EX4B(E9h). This patch defines new opcode and updates set_4byte() to support enable/disable 4-byte addressing mode for Cypress chips. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29mtd: spi-nor-core: Read status by Read Any RegisterTakahiro Kuwano1-0/+1
The spansion_sr_ready() reads status register 1 by Read Any Register commnad. This function is called from Flash specific hook with die address and dummy cycles to support multi-die package parts from Spansion/Cypress. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29mtd: spi-nor-core: Add the ->ready() hookTakahiro Kuwano1-0/+2
For dual/quad die package devices from Spansion/Cypress, the device's status needs to be checked by reading status registers in all dies, by using Read Any Register command. To support this, a Flash specific hook that can overwrite the legacy status check is needed. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29mtd: spi-nor-core: Add support for volatile QE bitTakahiro Kuwano1-0/+1
Some of Spansion/Cypress chips support volatile version of configuration registers and it is recommended to update volatile registers in the field application due to a risk of the non-volatile registers corruption by power interrupt. This patch adds a function to set Quad Enable bit in CFR1 volatile. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29mtd: spi-nor-core: Add support for Read/Write Any RegisterTakahiro Kuwano1-0/+2
Some of Spansion/Cypress chips support Read/Write Any Register commands. These commands are mainly used to write volatile registers and access to the registers in second and subsequent die for multi-die package parts. The Read Any Register instruction (65h) is followed by register address and dummy cycles, then the selected register byte is returned. The Write Any Register instruction (71h) is followed by register address and register byte to write. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29mtd: spi-nor: Add Cypress manufacturer IDTakahiro Kuwano1-0/+1
This patch adds Cypress manufacturer ID (34h) definition. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Allow using Micron mt35xu512aba in Octal DTR modePratyush Yadav1-0/+6
Since this flash doesn't have a Profile 1.0 table, the Octal DTR capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D fast read settings. Enable Octal DTR mode with 20 dummy cycles to allow running at the maximum supported frequency of 200Mhz. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Add support for Cypress Semper flashPratyush Yadav1-0/+13
The Cypress Semper flash is an xSPI compliant octal DTR flash. Add support for using it in octal DTR mode. The flash by default boots in a hybrid sector mode. Switch to uniform sector mode on boot. Use the default 20 dummy cycles for a read fast command. The SFDP programming on some older versions of the flash was incorrect. Fixes for that are included in the fixup hooks. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Perform a Soft Reset on shutdownPratyush Yadav1-0/+17
On probe, the SPI NOR core will put a flash in 8D-8D-8D mode if it supports it. But Linux as of now expects to get the flash in 1S-1S-1S mode. Handing the flash to Linux in Octal DTR mode means the kernel will fail to detect the flash. So, we need to reset to Power-on-Reset (POR) state before handing off the flash. A Software Reset command can be used to do this. One limitation of the soft reset is that it will restore state from non-volatile registers in some flashes. This means that if the flash was set to 8D mode in a non-volatile configuration, a soft reset won't help. This commit assumes that we don't set any non-volatile bits anywhere, and the flash doesn't have any non-volatile Octal DTR mode configuration. Since spi-nor-tiny doesn't (and likely shouldn't) have spi_nor_soft_reset(), add a dummy spi_nor_remove() for it that does nothing. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Detect Soft Reset sequence support from BFPTPratyush Yadav1-0/+1
A Soft Reset sequence will return the flash to Power-on-Reset (POR) state. It consists of two commands: Soft Reset Enable and Soft Reset. Find out if the sequence is supported from BFPT DWORD 16. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Enable octal DTR mode when possiblePratyush Yadav1-0/+2
Allow flashes to specify a hook to enable octal DTR mode. Use this hook whenever possible to get optimal transfer speeds. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Parse xSPI Profile 1.0 tablePratyush Yadav1-0/+7
This table is indication that the flash is xSPI compliant and hence supports octal DTR mode. Extract information like the fast read opcode, the number of dummy cycles needed for a Read Status Register command, and the number of address bytes needed for a Read Status Register command. The default dummy cycles for a fast octal DTR read are set to 20. Since there is no simple way of determining the dummy cycles needed for the fast read command, flashes that use a different value should update it in their flash-specific hooks. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Add support for DTR protocolPratyush Yadav1-12/+38
Double Transfer Rate (DTR) is SPI protocol in which data is transferred on each clock edge as opposed to on each clock cycle. Make framework-level changes to allow supporting flashes in DTR mode. Right now, mixed DTR modes are not supported. So, for example a mode like 4S-4D-4D will not work. All phases need to be either DTR or STR. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Rework hwcaps selectionPratyush Yadav1-2/+15
The spi-mem layer provides a spi_mem_supports_op() function to check whether a specific operation is supported by the controller or not. This is much more accurate than the hwcaps selection logic based on SPI_{RX,TX}_ flags. Rework the hwcaps selection logic to use spi_mem_supports_op(). To make sure the build doesn't break for boards not using CONFIG_DM_SPI, add a simple SPI_{RX,TX}_ based hwcaps selection logic in spi-mem-nodm similar to spi_mem_default_supports_op(). This change is only compile-tested. To avoid SPL size problems on the x530 board, the old hwcaps selection is still kept around. Leaving the code in-place was getting difficult to read and understand, so the code is restructured to have it all in one isolated function. As a result of this, the parameter hwcaps to spi_nor_setup() is no longer needed. Remove it. Based on the Linux commit c76f5089796a (mtd: spi-nor: Rework hwcaps selection for the spi-mem case, 2019-08-06) Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Introduce flash-specific fixup hooksPratyush Yadav1-0/+2
Sometimes the information in a flash's SFDP tables is wrong. Sometimes some information just can't be expressed in the SFDP table. So, introduce the fixup hooks to allow tailoring settings for a specific flash. Three hooks are added: default_init, post_sfdp, and post_bfpt. These allow tweaking the flash settings at different point in the probe sequence. Since the hooks reside in nor->info, set that value just before the call to spi_nor_init_params(). The hooks and at what points they are executed mimics Linux's spi-nor framework. One major difference is that Linux puts the struct spi_nor_fixups in nor->info. This is not possible in U-Boot because the spi-nor-ids list is shared between spi-nor-core.c and spi-nor-tiny.c. Since spi-nor-tiny shouldn't have those fixup hooks populated, add a separate function that lets flashes populate their fixup hooks. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Add a ->setup() hookPratyush Yadav1-61/+131
nor->setup() can be used by flashes to configure settings in case they have any peculiarities that can't be easily expressed by the generic spi-nor framework. This includes things like different opcodes, dummy cycles, page size, uniform/non-uniform sector sizes, etc. Move related declarations to avoid forward declarations. Inspired by the Linux kernel's setup() hook. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-24mtd: add support for parsing partitions defined in OFMarek Behún1-0/+10
Add support for parsing partitions defined in device-trees via the `partitions` node with `fixed-partitions` compatible. The `mtdparts`/`mtdids` mechanism takes precedence. If some partitions are defined for a MTD device via this mechanism, the code won't register partitions for that MTD device from OF, even if they are defined. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com>
2021-06-11clk: fixed_rate: add API for directly registering fixed rate clocksTero Kristo1-0/+3
Current driver only supports registering fixed rate clocks from DT. Add new API which makes it possible to register fixed rate clocks directly from e.g. platform specific clock drivers. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11lib: rational: copy the rational fraction lib routines from LinuxTero Kristo1-0/+20
Copy the best rational approximation calculation routines from Linux. Typical usecase for these routines is to calculate the M/N divider values for PLLs to reach a specific clock rate. This is based on linux kernel commit: "lib/math/rational.c: fix possible incorrect result from rational fractions helper" (sha1: 323dd2c3ed0641f49e89b4e420f9eef5d3d5a881) Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-05-24compiler.h: align the __ADDRESSABLE macro with Linux' versionMarek Behún1-1/+1
Use UNIQUE_ID in the __ADDRESSABLE macro. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-24treewide: Convert macro and uses of __section(foo) to __section("foo")Marek Behún2-5/+5
This commit does the same thing as Linux commit 33def8498fdd. Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-12soc: ti: k3-navss-ringacc: Remove unused ring modesVignesh Raghavendra1-6/+1
With AM64x supporting only K3_NAV_RINGACC_RING_MODE_RING or the exposed ring mode, all other K3 SoCs have also been moved to this common baseline. Therefore drop other modes such as K3_NAV_RINGACC_RING_MODE_MESSAGE (and proxy) to save on SPL footprint. There is a saving of ~800 bytes with this change for am65x_evm_r5_defconfig. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2021-05-12soc: ti: k3-navss-ringacc: Add AM64 ringacc supportVignesh Raghavendra1-0/+15
AM64 dual mode rings are modeled as pair of Rings objects which has common configuration and memory buffer, but separate real-time control register sets for each direction mem2dev (forward) and dev2mem (reverse). AM64 rings must be requested only using k3_ringacc_request_rings_pair(), and forward ring must always be initialized/configured. After this any other Ringacc APIs can be used without any callers changes. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12firmware: ti_sci: Update ti_sci_cmd_rm_udmap_tx_ch_cfg() API to the latestVignesh Raghavendra1-0/+14
Update struct ti_sci_msg_rm_udmap_tx_ch_cfg_req to latest ABI to support AM64x BCDMA Block copy channels. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-04-20psci: add features/reset2 supportIgor Opaniuk1-0/+3
Adds support for: * PSCI_FEATURES, which was introduced in PSCI 1.0. This provides API that allows discovering whether a specific PSCI function is implemented and its features. * SYSTEM_RESET2, which was introduced in PSCI 1.1, which extends existing SYSTEM_RESET. It provides support for vendor-specific resets, providing reset_type as an additional param. For additional details visit [1]. Implementations of some functions were borrowed from Linux PSCI driver code [2]. [1] https://developer.arm.com/documentation/den0022/latest/ [2] drivers/firmware/psci/psci.c Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2021-04-20psci: add v1.0/v1.1 definitions from LinuxIgor Opaniuk1-0/+28
Sync and add PSCI API versions 1.0/1.1 definitions from Linux. Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2021-04-13lib: string: Implement strlcatSean Anderson1-0/+3
This introduces strlcat, which provides a safer interface than strncat. It never copies more than its size bytes, including the terminating nul. In addition, it never reads past dest[size - 1], even if dest is not nul-terminated. This also removes the stub for dwc3 now that we have a proper implementation. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-08arm: socfpga: smc: Add function to get usercodeSiew Chin Lim1-0/+18
Add function to send mailbox command via SMC to get usercode from SDM. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-04-08arm: socfpga: smc: Remove unused SMC function IDSiew Chin Lim1-52/+0
Remove unused SMC function ID 61 and 62. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-03-26clk: fixed-rate: Export driver parts for OF_PLATDATA_INSTSimon Glass1-0/+5
We need to allow SoCs to create their own drivers for this so that they can use their own of-platdata structs. To minimise code duplication, export the driver operations and the ofdata_to_plat() setup function. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-01log: convert pr_*() to loggingHeinrich Schuchardt2-38/+48
In drivers we use a family of printing functions including pr_err() and pr_cont(). CONFIG_LOGLEVEL is used to control which of these lead to output via printf(). Our logging functions allow finer grained control of output. So replace printf() by the matching logging functions. The usage of CONFIG_LOGLEVEL remains unchanged. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-02-26mtd: spi-nor-core: Fix typo in documentationSean Anderson1-1/+1
This line should come before the docs for the next function. Fixes: 7aeedac0153 ("mtd: spi: Port SPI NOR framework from Linux") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-26mtd: spi-nor.h: Change spaces to tabsBin Meng1-10/+10
U-Boot coding convention prefers tabs over spaces. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-22clk: remove a redundant headerDario Binacchi1-1/+0
The linux/err.h header file was included twice. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-31usb: gadget: add super speed supportLi Jun2-0/+10
This patch is to add usb gadget super speed support in common driver, including BOS descriptor and select the super speed descriptor from function driver. Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peter Chen <peter.chen@nxp.com> Tested-by: faqiang.zhu <faqiang.zhu@nxp.com> Signed-off-by: Li Jun <jun.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-01-31usb: gadget: OS Feature Descriptors supportLi Jun1-0/+57
This is a proting patch from linux kernel: 37a3a533429e ("usb: gadget: OS Feature Descriptors support"), the original commit log see below: There is a custom (non-USB IF) extension to the USB standard: http://msdn.microsoft.com/library/windows/hardware/gg463182 They grant permission to use the specification - there is "Microsoft OS Descriptor Specification License Agreement" under the link mentioned above, and its Section 2 "Grant of License", letter (b) reads: "Patent license. Microsoft hereby grants to You a nonexclusive, royalty-free, nontransferable, worldwide license under Microsoft鈥檚 patents embodied solely within the Specification and that are owned or licensable by Microsoft to make, use, import, offer to sell, sell and distribute directly or indirectly to Your Licensees Your Implementation. You may sublicense this patent license to Your Licensees under the same terms and conditions." The said extension is maintained by Microsoft for Microsoft. Yet it is fairly common for various devices to use it, and a popular proprietary operating system expects devices to provide "OS descriptors", so Linux-based USB gadgets whishing to be able to talk to a variety of operating systems should be able to provide the "OS descriptors". This patch adds optional support for gadgets whishing to expose the so called "OS Feature Descriptors", that is "Extended Compatibility ID" and "Extended Properties". Hosts which do request "OS descriptors" from gadgets do so during the enumeration phase and before the configuration is set with SET_CONFIGURATION. What is more, those hosts never ask for configurations at indices other than 0. Therefore, gadgets whishing to provide "OS descriptors" must designate one configuration to be used with this kind of hosts - this is what os_desc_config is added for in struct usb_composite_dev. There is an additional advantage to it: if a gadget provides "OS descriptors" and designates one configuration to be used with such non-USB-compliant hosts it can invoke "usb_add_config" in any order because the designated configuration will be reported to be at index 0 anyway. This patch also adds handling vendor-specific requests addressed at device or interface and related to handling "OS descriptors"." Signed-off-by: Li Jun <jun.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-01-31usb: gadget: move utf8_to_utf16le to header fileLi Jun1-0/+75
As other users may use utf8_to_utf16le() to convert the utf8 to utf16 for usb, so move it to head file. Signed-off-by: Li Jun <jun.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-01-31usb: gadget: OS String supportLi Jun1-0/+10
This is a porting patch from linux kernel: 19824d5eeece ("usb: gadget: OS String support"), original commit log see below: "There is a custom (non-USB IF) extension to the USB standard: http://msdn.microsoft.com/library/windows/hardware/gg463182 They grant permission to use the specification - there is "Microsoft OS Descriptor Specification License Agreement" under the link mentioned above, and its Section 2 "Grant of License", letter (b) reads: "Patent license. Microsoft hereby grants to You a nonexclusive, royalty-free, nontransferable, worldwide license under Microsoft鈥檚 patents embodied solely within the Specification and that are owned or licensable by Microsoft to make, use, import, offer to sell, sell and distribute directly or indirectly to Your Licensees Your Implementation. You may sublicense this patent license to Your Licensees under the same terms and conditions." The said extension is maintained by Microsoft for Microsoft. Yet it is fairly common for various devices to use it, and a popular proprietary operating system expects devices to provide "OS descriptors", so Linux-based USB gadgets whishing to be able to talk to a variety of operating systems should be able to provide the "OS descriptors". This patch adds optional support for gadgets whishing to expose the so called "OS String" under index 0xEE of language 0. The contents of the string is generated based on the qw_sign array and b_vendor_code. Interested gadgets need to set the cdev->use_os_string flag, fill cdev->qw_sign with appropriate values and fill cdev->b_vendor_code with a value of their choice. This patch does not however implement responding to any vendor-specific USB requests." Signed-off-by: Li Jun <jun.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-01-31usb: gadget: Add ep_config call back to usb_gadget_opsYe Li1-0/+3
Since some new fields in usb_ep structure been moved to usb_ss_ep. The CDNS3 gadget driver should replies on this operation to bind the usb_ss_ep with the endpoint descriptor when function layer uses usb_ep_autoconfig to add endpoint descriptors to gadget. So that CDNS3 driver can know the EP information and configure the EP once the set configuration request is received. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-01-28smccc: fix sign bit expansionVolodymyr Babchuk1-2/+2
Signed ARM_SMCCC_FAST_CALL value is shifted to 31'st bit. Then, it is expanded to 64 bit value, which results in 1s in higher 32 bits. This causes corrupted values in 64-bit SMC IDs and issues in buggy handlers of 32-bit calls. We need to make ARM_SMCCC_FAST_CALL unsigned long, so it would work properly on 32 bit architectures. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2021-01-15arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP servicesChee Hong Ang1-0/+573
This header file defines the Secure Monitor Call (SMC) message protocol for ATF (BL31) PSCI runtime services. It includes all the PSCI SiP function identifiers for the secure runtime services provided by ATF. The secure runtime services include System Manager's registers access, 2nd phase bitstream FPGA reconfiguration, Remote System Update (RSU) and etc. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>