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2022-01-19doc: replace @return by Return:Heinrich Schuchardt3-9/+9
Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-13stddef: Avoid warning with clang with offsetof()Simon Glass1-1/+7
Some bright sparks have decided that a cast on a constant cannot be a constant, so offsetof() produces this warning on clang-10: include/intel_gnvs.h:113:1: error: static_assert expression is not an integral constant expression check_member(acpi_global_nvs, unused2, GNVS_CHROMEOS_ACPI_OFFSET); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/linux/kernel.h:284:2: note: expanded from macro 'check_member' offsetof(struct structure, member) == (offset), \ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/linux/stddef.h:20:32: note: expanded from macro 'offsetof' ^ include/intel_gnvs.h:113:1: note: cast that performs the conversions of a reinterpret_cast is ot allowed in a constant expression include/linux/stddef.h:20:33: note: expanded from macro 'offsetof' Fix it by using the compiler built-in version, if available. This syncs the function to the same implementation as Linux v5.16 in this header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-19include/linux/byteorder: Fix compilation of __constant_cpu_to_be32()Pali Rohár1-0/+4
The macro __constant_cpu_to_be32() uses ___constant_swab32(), which for some reason is not defined and causes the following error during compilation: include/linux/byteorder/little_endian.h:28:52: warning: implicit declaration of function ‘___constant_swab32’; did you mean ‘__builtin_bswap32’? [-Wimplicit-function-declaration] #define __constant_cpu_to_be32(x) ((__force __be32)___constant_swab32((x))) Declare all ___constant_swabXX() macros. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-23include: import if_vlan.h from LinuxVladimir Oltean1-0/+26
This is needed for the VLAN header structure. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-10-23Merge https://source.denx.de/u-boot/custodians/u-boot-spiTom Rini1-11/+0
- Fix mtd erase with mtdpart (Marek Behún) - NXP fspi driver fixes (Kuldeep Singh)
2021-10-23mtd: Remove mtd_erase_callback() entirelyMarek Behún1-11/+0
The original purpose of mtd_erase_callback() in Linux at the time it was imported to U-Boot, was to inform the caller that erasing is done (since it was an asynchronous operation). All supplied callback methods in U-Boot do nothing, but the mtd_erase_callback() function was (until previous patch) grossly abused in U-Boot's mtdpart implementation for completely different purpose. Since we got rid of the abusement, remove the mtd_erase_callback() function and the .callback member from struct erase_info entirely, in order to avoid such problems in the future. Signed-off-by: Marek Behún <marek.behun@nic.cz>
2021-10-08kconfig: Add tools support to CONFIG_IS_ENABLED()Simon Glass1-3/+10
At present we must separately test for the host build for many options, since we force them to be enabled. For example, CONFIG_FIT is always enabled in the host tools, even if CONFIG_FIT is not enabled by the board itself. It would be more convenient if we could use, for example, CONFIG_IS_ENABLED(FIT) and get CONFIG_HOST_FIT, when building for the host. Add support for this. With this and the tools_build() function, we should be able to remove all the #ifdefs currently needed in code that is build by tools and targets. This will be even nicer when we move to using CONFIG(xxx) everywhere, since all the #ifdef and IS_ENABLED/CONFIG_IS_ENABLED stuff will go away. Signed-off-by: Simon Glass <sjg@chromium.org> Suggested-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> # b4f73886 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2021-10-08zstd: Create a function for use from U-BootSimon Glass1-0/+11
The existing zstd API requires the same sequence of calls to perform its task. Create a helper for U-Boot, to avoid code duplication, as is done with other compression algorithms. Make use of of this from the image code. Note that the zstd code lacks a test in test/compression.c and this should be added by the maintainer. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-10-08lib: Add memdup()Simon Glass1-0/+13
Add a function to duplicate a memory region, a little like strdup(). Signed-off-by: Simon Glass <sjg@chromium.org>
2021-10-06Convert CONFIG_SYS_NAND_MAX_CHIPS to KconfigTom Rini1-5/+0
This converts the following to Kconfig: CONFIG_SYS_NAND_MAX_CHIPS Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-30Merge tag 'xilinx-for-v2022.01-rc1' of ↵Tom Rini1-0/+2
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.01-rc1 zynq: - Enable capsule update for qspi and mmc - Update zed DT qspi compatible string zynqmp: - Add missing modeboot for EMMC - Add missing nand DT properties - List all eeproms for SC on vck190 - Add vck190 SC psu_init clk: - Handle only GATE type clock for Versal watchdog: - Update versal driver to handle system reset
2021-09-30WS cleanup: remove SPACE(s) followed by TABWolfgang Denk9-19/+19
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30WS cleanup: remove trailing white spaceWolfgang Denk2-3/+3
Signed-off-by: Wolfgang Denk <wd@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-09-30WS cleanup: remove excessive empty linesWolfgang Denk2-2/+0
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30WS cleanup: remove trailing empty linesWolfgang Denk1-1/+0
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-28mtd: nand: raw: convert nand_dt_init() to ofnode_xx() interfacePatrice Chotard1-3/+3
nand_dt_init() is still using fdtdec_xx() interface. If OF_LIVE flag is enabled, dt property can't be get anymore. Updating all fdtdec_xx() interface to ofnode_xx() to solve this issue. For doing this, node parameter type must be ofnode. First idea was to convert "node" parameter to ofnode type inside nand_dt_init() using offset_to_ofnode(node). But offset_to_ofnode() is not bijective, in case OF_LIVE flag is enabled, it performs an assert(). So, this leads to update nand_chip struct flash_node field from int to ofnode and to update all nand_dt_init() callers. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-09-28mtd: spi: nor: force mtd name to "nor%d"Patrick Delaunay1-0/+2
Force the mtd name of spi-nor to "nor" + the driver sequence number: "nor0", "nor1"... beginning after the existing nor devices. This patch is coherent with existing "nand" and "spi-nand" mtd device names. When CFI MTD NOR device are supported, the spi-nor index is chosen after the last CFI device defined by CONFIG_SYS_MAX_FLASH_BANKS. When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is activated, this config is replaced by to cfi_flash_num_flash_banks in the include file mtd/cfi_flash.h. This generic name "nor%d" can be use to identify the mtd spi-nor device without knowing the real device name or the DT path of the device, used with API get_mtd_device_nm() and is used in mtdparts command. This patch also avoids issue when the same NOR device is present 2 times, for example on STM32MP15F-EV1: STM32MP> mtd list SF: Detected mx66l51235l with page size 256 Bytes, erase size 64 KiB, \ total 64 MiB List of MTD devices: * nand0 - type: NAND flash - block size: 0x40000 bytes - min I/O: 0x1000 bytes - OOB size: 224 bytes - OOB available: 118 bytes - ECC strength: 8 bits - ECC step size: 512 bytes - bitflip threshold: 6 bits - 0x000000000000-0x000040000000 : "nand0" * mx66l51235l - device: mx66l51235l@0 - parent: spi@58003000 - driver: jedec_spi_nor - path: /soc/spi@58003000/mx66l51235l@0 - type: NOR flash - block size: 0x10000 bytes - min I/O: 0x1 bytes - 0x000000000000-0x000004000000 : "mx66l51235l" * mx66l51235l - device: mx66l51235l@1 - parent: spi@58003000 - driver: jedec_spi_nor - path: /soc/spi@58003000/mx66l51235l@1 - type: NOR flash - block size: 0x10000 bytes - min I/O: 0x1 bytes - 0x000000000000-0x000004000000 : "mx66l51235l" The same mtd name "mx66l51235l" identify the 2 instances mx66l51235l@0 and mx66l51235l@1. This patch fixes a ST32CubeProgrammer / stm32prog command issue with nor0 target on STM32MP157C-EV1 board introduced by commit b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when DM is enabled"). Fixes: b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when DM is enabled") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> [trini: Add <dm/device.h> to <mtd.h> for DM_MAX_SEQ_STR] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-28mtd: nand: raw: convert nand_dt_init() to ofnode_xx() interfacePatrice Chotard1-3/+3
nand_dt_init() is still using fdtdec_xx() interface. If OF_LIVE flag is enabled, dt property can't be get anymore. Updating all fdtdec_xx() interface to ofnode_xx() to solve this issue. For doing this, node parameter type must be ofnode. First idea was to convert "node" parameter to ofnode type inside nand_dt_init() using offset_to_ofnode(node). But offset_to_ofnode() is not bijective, in case OF_LIVE flag is enabled, it performs an assert(). So, this leads to update nand_chip struct flash_node field from int to ofnode and to update all nand_dt_init() callers. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-09-24mtd: remove SPEAr flash driver st_smiPatrick Delaunay1-100/+0
Remove the driver st_smic.c used in SPEAr products and the associated config CONFIG_ST_SMI; this driver is no more used in U-Boot after the commit 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support"). Fixes: 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2021-09-22usb: add support for ULPI/SERIAL/HSIC PHY modesMatthias Schiffer1-0/+3
Import usb_phy_interface enum values and DT match strings from the Linux kernel. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
2021-09-17firmware: ti_sci: Include linux/err.h in ti_sci_protocol.hSuman Anna1-1/+3
The common TI SCI header file uses some macros from err.h and these get exercised when CONFIG_TI_SCI_PROTOCOL is not defined. Include the linux/err.h header file in this header file directly rather than relying on source files to include it to eliminate any potential build errors. While at this, reorder the existing header file include to the beginning of the file. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
2021-07-26net: ethtool: Add ethernet speed macros for higher speedsAshok Reddy Soma1-0/+8
Add speed macro's for higher ethernet speeds to be used in u-boot networking drivers. Added Macros for speeds 14G, 20G, 25G, 40G, 50G, 56G, 100G and 200G inline with linux. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-15soc: ti: pruss: Add a platform driver for PRUSS in TI SoCsKeerthy1-0/+227
The Programmable Real-Time Unit - Industrial Communication Subsystem (PRU-ICSS) is present of various TI SoCs such as AM335x or AM437x or the AM654x family. Each SoC can have one or more PRUSS instances that may or may not be identical. The PRUSS consists of dual 32-bit RISC cores called the Programmable Real-Time Units (PRUs), some shared, data and instruction memories, some internal peripheral modules, and an interrupt controller. The programmable nature of the PRUs provide flexibility to implement custom peripheral interfaces, fast real-time responses, or specialized data handling. Add support for pruss driver. Currently am654x family is supported. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210622063431.3151-2-lokeshvutla@ti.com
2021-07-01build_bug.h: add wrapper for _Static_assertRasmus Villemoes1-0/+19
[Linux commit 6bab69c65013bed5fce9f101a64a84d0385b3946] BUILD_BUG_ON() is a little annoying, since it cannot be used outside function scope. So one cannot put assertions about the sizeof() a struct next to the struct definition, but has to hide that in some more or less arbitrary function. Since gcc 4.6 (which is now also the required minimum), there is support for the C11 _Static_assert in all C modes, including gnu89. So add a simple wrapper for that. _Static_assert() requires a message argument, which is usually quite redundant (and I believe that bug got fixed at least in newer C++ standards), but we can easily work around that with a little macro magic, making it optional. For example, adding static_assert(sizeof(struct printf_spec) == 8); in vsprintf.c and modifying that struct to violate it, one gets ./include/linux/build_bug.h:78:41: error: static assertion failed: "sizeof(struct printf_spec) == 8" #define __static_assert(expr, msg, ...) _Static_assert(expr, "" msg "") godbolt.org suggests that _Static_assert() has been support by clang since at least 3.0.0. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-29mtd: spi-nor-core: Add fixups for Cypress s25hl-t/s25hs-tTakahiro Kuwano1-0/+3
The nor->ready() and spansion_sr_ready() introduced earlier in this series are used for multi-die package parts. The nor->quad_enable() sets the volatile QE bit on each die. The nor->erase() is hooked if the device is not configured to uniform sectors, assuming it has 32 x 4KB sectors overlaid on bottom address. Other configurations, top and split, are not supported at this point. Will submit additional patches to support it as needed. The post_bfpt/sfdp() fixes the params wrongly advertised in SFDP. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29mtd: spi-nor-core: Add Cypress manufacturer ID in set_4byteTakahiro Kuwano1-0/+1
Cypress chips support SPINOR_OP_EN4B(B7h) to enable 4-byte addressing mode. Cypress chips support B8h to disable 4-byte addressing mode instead of SPINOR_OP_EX4B(E9h). This patch defines new opcode and updates set_4byte() to support enable/disable 4-byte addressing mode for Cypress chips. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29mtd: spi-nor-core: Read status by Read Any RegisterTakahiro Kuwano1-0/+1
The spansion_sr_ready() reads status register 1 by Read Any Register commnad. This function is called from Flash specific hook with die address and dummy cycles to support multi-die package parts from Spansion/Cypress. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29mtd: spi-nor-core: Add the ->ready() hookTakahiro Kuwano1-0/+2
For dual/quad die package devices from Spansion/Cypress, the device's status needs to be checked by reading status registers in all dies, by using Read Any Register command. To support this, a Flash specific hook that can overwrite the legacy status check is needed. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29mtd: spi-nor-core: Add support for volatile QE bitTakahiro Kuwano1-0/+1
Some of Spansion/Cypress chips support volatile version of configuration registers and it is recommended to update volatile registers in the field application due to a risk of the non-volatile registers corruption by power interrupt. This patch adds a function to set Quad Enable bit in CFR1 volatile. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29mtd: spi-nor-core: Add support for Read/Write Any RegisterTakahiro Kuwano1-0/+2
Some of Spansion/Cypress chips support Read/Write Any Register commands. These commands are mainly used to write volatile registers and access to the registers in second and subsequent die for multi-die package parts. The Read Any Register instruction (65h) is followed by register address and dummy cycles, then the selected register byte is returned. The Write Any Register instruction (71h) is followed by register address and register byte to write. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-29mtd: spi-nor: Add Cypress manufacturer IDTakahiro Kuwano1-0/+1
This patch adds Cypress manufacturer ID (34h) definition. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Allow using Micron mt35xu512aba in Octal DTR modePratyush Yadav1-0/+6
Since this flash doesn't have a Profile 1.0 table, the Octal DTR capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D fast read settings. Enable Octal DTR mode with 20 dummy cycles to allow running at the maximum supported frequency of 200Mhz. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Add support for Cypress Semper flashPratyush Yadav1-0/+13
The Cypress Semper flash is an xSPI compliant octal DTR flash. Add support for using it in octal DTR mode. The flash by default boots in a hybrid sector mode. Switch to uniform sector mode on boot. Use the default 20 dummy cycles for a read fast command. The SFDP programming on some older versions of the flash was incorrect. Fixes for that are included in the fixup hooks. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Perform a Soft Reset on shutdownPratyush Yadav1-0/+17
On probe, the SPI NOR core will put a flash in 8D-8D-8D mode if it supports it. But Linux as of now expects to get the flash in 1S-1S-1S mode. Handing the flash to Linux in Octal DTR mode means the kernel will fail to detect the flash. So, we need to reset to Power-on-Reset (POR) state before handing off the flash. A Software Reset command can be used to do this. One limitation of the soft reset is that it will restore state from non-volatile registers in some flashes. This means that if the flash was set to 8D mode in a non-volatile configuration, a soft reset won't help. This commit assumes that we don't set any non-volatile bits anywhere, and the flash doesn't have any non-volatile Octal DTR mode configuration. Since spi-nor-tiny doesn't (and likely shouldn't) have spi_nor_soft_reset(), add a dummy spi_nor_remove() for it that does nothing. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Detect Soft Reset sequence support from BFPTPratyush Yadav1-0/+1
A Soft Reset sequence will return the flash to Power-on-Reset (POR) state. It consists of two commands: Soft Reset Enable and Soft Reset. Find out if the sequence is supported from BFPT DWORD 16. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Enable octal DTR mode when possiblePratyush Yadav1-0/+2
Allow flashes to specify a hook to enable octal DTR mode. Use this hook whenever possible to get optimal transfer speeds. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Parse xSPI Profile 1.0 tablePratyush Yadav1-0/+7
This table is indication that the flash is xSPI compliant and hence supports octal DTR mode. Extract information like the fast read opcode, the number of dummy cycles needed for a Read Status Register command, and the number of address bytes needed for a Read Status Register command. The default dummy cycles for a fast octal DTR read are set to 20. Since there is no simple way of determining the dummy cycles needed for the fast read command, flashes that use a different value should update it in their flash-specific hooks. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Add support for DTR protocolPratyush Yadav1-12/+38
Double Transfer Rate (DTR) is SPI protocol in which data is transferred on each clock edge as opposed to on each clock cycle. Make framework-level changes to allow supporting flashes in DTR mode. Right now, mixed DTR modes are not supported. So, for example a mode like 4S-4D-4D will not work. All phases need to be either DTR or STR. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Rework hwcaps selectionPratyush Yadav1-2/+15
The spi-mem layer provides a spi_mem_supports_op() function to check whether a specific operation is supported by the controller or not. This is much more accurate than the hwcaps selection logic based on SPI_{RX,TX}_ flags. Rework the hwcaps selection logic to use spi_mem_supports_op(). To make sure the build doesn't break for boards not using CONFIG_DM_SPI, add a simple SPI_{RX,TX}_ based hwcaps selection logic in spi-mem-nodm similar to spi_mem_default_supports_op(). This change is only compile-tested. To avoid SPL size problems on the x530 board, the old hwcaps selection is still kept around. Leaving the code in-place was getting difficult to read and understand, so the code is restructured to have it all in one isolated function. As a result of this, the parameter hwcaps to spi_nor_setup() is no longer needed. Remove it. Based on the Linux commit c76f5089796a (mtd: spi-nor: Rework hwcaps selection for the spi-mem case, 2019-08-06) Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Introduce flash-specific fixup hooksPratyush Yadav1-0/+2
Sometimes the information in a flash's SFDP tables is wrong. Sometimes some information just can't be expressed in the SFDP table. So, introduce the fixup hooks to allow tailoring settings for a specific flash. Three hooks are added: default_init, post_sfdp, and post_bfpt. These allow tweaking the flash settings at different point in the probe sequence. Since the hooks reside in nor->info, set that value just before the call to spi_nor_init_params(). The hooks and at what points they are executed mimics Linux's spi-nor framework. One major difference is that Linux puts the struct spi_nor_fixups in nor->info. This is not possible in U-Boot because the spi-nor-ids list is shared between spi-nor-core.c and spi-nor-tiny.c. Since spi-nor-tiny shouldn't have those fixup hooks populated, add a separate function that lets flashes populate their fixup hooks. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-28mtd: spi-nor-core: Add a ->setup() hookPratyush Yadav1-61/+131
nor->setup() can be used by flashes to configure settings in case they have any peculiarities that can't be easily expressed by the generic spi-nor framework. This includes things like different opcodes, dummy cycles, page size, uniform/non-uniform sector sizes, etc. Move related declarations to avoid forward declarations. Inspired by the Linux kernel's setup() hook. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2021-06-24mtd: add support for parsing partitions defined in OFMarek Behún1-0/+10
Add support for parsing partitions defined in device-trees via the `partitions` node with `fixed-partitions` compatible. The `mtdparts`/`mtdids` mechanism takes precedence. If some partitions are defined for a MTD device via this mechanism, the code won't register partitions for that MTD device from OF, even if they are defined. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com>
2021-06-11clk: fixed_rate: add API for directly registering fixed rate clocksTero Kristo1-0/+3
Current driver only supports registering fixed rate clocks from DT. Add new API which makes it possible to register fixed rate clocks directly from e.g. platform specific clock drivers. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11lib: rational: copy the rational fraction lib routines from LinuxTero Kristo1-0/+20
Copy the best rational approximation calculation routines from Linux. Typical usecase for these routines is to calculate the M/N divider values for PLLs to reach a specific clock rate. This is based on linux kernel commit: "lib/math/rational.c: fix possible incorrect result from rational fractions helper" (sha1: 323dd2c3ed0641f49e89b4e420f9eef5d3d5a881) Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-05-24compiler.h: align the __ADDRESSABLE macro with Linux' versionMarek Behún1-1/+1
Use UNIQUE_ID in the __ADDRESSABLE macro. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-24treewide: Convert macro and uses of __section(foo) to __section("foo")Marek Behún2-5/+5
This commit does the same thing as Linux commit 33def8498fdd. Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-12soc: ti: k3-navss-ringacc: Remove unused ring modesVignesh Raghavendra1-6/+1
With AM64x supporting only K3_NAV_RINGACC_RING_MODE_RING or the exposed ring mode, all other K3 SoCs have also been moved to this common baseline. Therefore drop other modes such as K3_NAV_RINGACC_RING_MODE_MESSAGE (and proxy) to save on SPL footprint. There is a saving of ~800 bytes with this change for am65x_evm_r5_defconfig. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2021-05-12soc: ti: k3-navss-ringacc: Add AM64 ringacc supportVignesh Raghavendra1-0/+15
AM64 dual mode rings are modeled as pair of Rings objects which has common configuration and memory buffer, but separate real-time control register sets for each direction mem2dev (forward) and dev2mem (reverse). AM64 rings must be requested only using k3_ringacc_request_rings_pair(), and forward ring must always be initialized/configured. After this any other Ringacc APIs can be used without any callers changes. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-05-12firmware: ti_sci: Update ti_sci_cmd_rm_udmap_tx_ch_cfg() API to the latestVignesh Raghavendra1-0/+14
Update struct ti_sci_msg_rm_udmap_tx_ch_cfg_req to latest ABI to support AM64x BCDMA Block copy channels. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-04-20psci: add features/reset2 supportIgor Opaniuk1-0/+3
Adds support for: * PSCI_FEATURES, which was introduced in PSCI 1.0. This provides API that allows discovering whether a specific PSCI function is implemented and its features. * SYSTEM_RESET2, which was introduced in PSCI 1.1, which extends existing SYSTEM_RESET. It provides support for vendor-specific resets, providing reset_type as an additional param. For additional details visit [1]. Implementations of some functions were borrowed from Linux PSCI driver code [2]. [1] https://developer.arm.com/documentation/den0022/latest/ [2] drivers/firmware/psci/psci.c Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>