From 94256dc61067fee4d0687c018f592e62862ab6c1 Mon Sep 17 00:00:00 2001 From: Mihai Sain Date: Mon, 14 Nov 2022 17:10:35 +0200 Subject: ARM: dts: at91: sama7g5: fix signal name of pin PD8 The signal name of pin PD8 with function D is A22_NANDCLE as it is defined in the datasheet. Fixes: 558378a4cd ("ARM: mach-at91: add support for new SoC sama7g5") Signed-off-by: Mihai Sain --- arch/arm/dts/sama7g5-pinfunc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/sama7g5-pinfunc.h b/arch/arm/dts/sama7g5-pinfunc.h index b77185f8ed..a17707ba60 100644 --- a/arch/arm/dts/sama7g5-pinfunc.h +++ b/arch/arm/dts/sama7g5-pinfunc.h @@ -673,7 +673,7 @@ #define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) #define PIN_PD8__SDMMC2_DAT3 PINMUX_PIN(PIN_PD8, 1, 1) #define PIN_PD8__I2SMCC0_DIN0 PINMUX_PIN(PIN_PD8, 3, 1) -#define PIN_PD8__A11_NANDCLE PINMUX_PIN(PIN_PD8, 4, 2) +#define PIN_PD8__A22_NANDCLE PINMUX_PIN(PIN_PD8, 4, 2) #define PIN_PD8__TIOA2 PINMUX_PIN(PIN_PD8, 5, 2) #define PIN_PD8__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD8, 6, 5) #define PIN_PD9 105 -- cgit v1.2.3 From d0e8777beeb675b77d6b2bf679133106892eb8dd Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 4 Dec 2022 14:00:05 +0100 Subject: sound: avoid endless loop 'sound play 1 100000' results in an endless loop on the sandbox. If the frequency exceeds half the sampling rate, zero out the output buffer. Fixes: 511ed5fdd389 ("SOUND: SAMSUNG: Add I2S driver") Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- drivers/sound/sound.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/sound/sound.c b/drivers/sound/sound.c index 041dfdccfe..c0fc50c99d 100644 --- a/drivers/sound/sound.c +++ b/drivers/sound/sound.c @@ -15,7 +15,10 @@ void sound_create_square_wave(uint sample_rate, unsigned short *data, int size, const int period = freq ? sample_rate / freq : 0; const int half = period / 2; - assert(freq); + if (!half) { + memset(data, 0, size); + return; + } /* Make sure we don't overflow our buffer */ if (size % 2) -- cgit v1.2.3 From 968eaaeaa7a8cf0956e19e9217af9e81bc7fb2eb Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 4 Dec 2022 17:11:41 +0100 Subject: test: test sandbox sound driver more rigorously Consider unexpected values for frequency: * negative frequency * zero frequency * frequency exceeding sampling frequency As in these cases the sum of the samples is zero also check the count of the samples. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- arch/sandbox/include/asm/test.h | 10 ++++++++++ drivers/sound/sandbox.c | 9 +++++++++ test/dm/sound.c | 11 +++++++++++ 3 files changed, 30 insertions(+) diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index 0406085917..568738c16d 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -188,6 +188,16 @@ int sandbox_get_setup_called(struct udevice *dev); */ int sandbox_get_sound_active(struct udevice *dev); +/** + * sandbox_get_sound_count() - Read back the count of the sound data so far + * + * This data is provided to the sandbox driver by the sound play() method. + * + * @dev: Device to check + * Return: count of audio data + */ +int sandbox_get_sound_count(struct udevice *dev); + /** * sandbox_get_sound_sum() - Read back the sum of the sound data so far * diff --git a/drivers/sound/sandbox.c b/drivers/sound/sandbox.c index 4a2c87a84c..c6cbd81fdb 100644 --- a/drivers/sound/sandbox.c +++ b/drivers/sound/sandbox.c @@ -29,6 +29,7 @@ struct sandbox_i2s_priv { struct sandbox_sound_priv { int setup_called; /* Incremented when setup() method is called */ bool active; /* TX data is being sent */ + int count; /* Use to count the provided audio data */ int sum; /* Use to sum the provided audio data */ bool allow_beep; /* true to allow the start_beep() interface */ int frequency_hz; /* Beep frequency if active, else 0 */ @@ -68,6 +69,13 @@ int sandbox_get_sound_active(struct udevice *dev) return priv->active; } +int sandbox_get_sound_count(struct udevice *dev) +{ + struct sandbox_sound_priv *priv = dev_get_priv(dev); + + return priv->count; +} + int sandbox_get_sound_sum(struct udevice *dev) { struct sandbox_sound_priv *priv = dev_get_priv(dev); @@ -168,6 +176,7 @@ static int sandbox_sound_play(struct udevice *dev, void *data, uint data_size) for (i = 0; i < data_size; i++) priv->sum += ((uint8_t *)data)[i]; + priv->count += data_size; return i2s_tx_data(uc_priv->i2s, data, data_size); } diff --git a/test/dm/sound.c b/test/dm/sound.c index b73f6ab111..15d545ab5a 100644 --- a/test/dm/sound.c +++ b/test/dm/sound.c @@ -26,8 +26,19 @@ static int dm_test_sound(struct unit_test_state *uts) ut_asserteq(0, sandbox_get_setup_called(dev)); ut_assertok(sound_beep(dev, 1, 100)); + ut_asserteq(48, sandbox_get_sound_count(dev)); ut_asserteq(4560, sandbox_get_sound_sum(dev)); ut_assertok(sound_beep(dev, 1, 100)); + ut_asserteq(96, sandbox_get_sound_count(dev)); + ut_asserteq(9120, sandbox_get_sound_sum(dev)); + ut_assertok(sound_beep(dev, 1, -100)); + ut_asserteq(144, sandbox_get_sound_count(dev)); + ut_asserteq(9120, sandbox_get_sound_sum(dev)); + ut_assertok(sound_beep(dev, 1, 0)); + ut_asserteq(192, sandbox_get_sound_count(dev)); + ut_asserteq(9120, sandbox_get_sound_sum(dev)); + ut_assertok(sound_beep(dev, 1, INT_MAX)); + ut_asserteq(240, sandbox_get_sound_count(dev)); ut_asserteq(9120, sandbox_get_sound_sum(dev)); ut_asserteq(false, sandbox_get_sound_active(dev)); -- cgit v1.2.3 From ff414fcc44b8b385600df54f5a7dc0719cec106f Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 4 Dec 2022 16:33:07 +0100 Subject: cmd: fix long text for sound command Make it clear that if only 1 parameter is provided this is the duration. The ISO symbol for hertz is Hz. Fixes: c0c88533fffd ("Sound: Add command for audio playback") Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- cmd/sound.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/sound.c b/cmd/sound.c index f82f2aa670..20ac3f758e 100644 --- a/cmd/sound.c +++ b/cmd/sound.c @@ -86,5 +86,5 @@ U_BOOT_CMD( sound, 4, 1, do_sound, "sound sub-system", "init - initialise the sound driver\n" - "sound play [len] [freq] - play a sound for len ms at freq hz\n" + "sound play [len [freq]] - play a sound for len ms at freq Hz\n" ); -- cgit v1.2.3 From 3f01307ced9af0c20b48217c2c58b63f824451c5 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 4 Dec 2022 16:16:12 +0100 Subject: doc: man-page for the sound command Provide a man-page for the sound command. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- doc/usage/cmd/sound.rst | 41 +++++++++++++++++++++++++++++++++++++++++ doc/usage/index.rst | 1 + 2 files changed, 42 insertions(+) create mode 100644 doc/usage/cmd/sound.rst diff --git a/doc/usage/cmd/sound.rst b/doc/usage/cmd/sound.rst new file mode 100644 index 0000000000..d3fac243b1 --- /dev/null +++ b/doc/usage/cmd/sound.rst @@ -0,0 +1,41 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright 2022, Heinrich Schuchardt + +sound command +============= + +Synopsis +-------- + +:: + + sound init + sound play [len [freq]] + +Description +----------- + +The *sound* command is used to play a beep sound. + +sound init + initializes the sound driver. + +sound play + plays a square wave sound. It does not depend on previously calling + *sound init*. + +len + duration of the sound in ms, defaults to 1000 ms + +freq + frequency of the sound in Hz, defaults to 400 Hz + +Configuration +------------- + +The sound command is enabled by CONFIG_CMD_SOUND=y. + +Return value +------------ + +The return value $? is 0 (true) if the command succeeds, 1 (false) otherwise. diff --git a/doc/usage/index.rst b/doc/usage/index.rst index 0bc82887e9..bbd40a6e18 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -73,6 +73,7 @@ Shell commands cmd/scp03 cmd/setexpr cmd/size + cmd/sound cmd/temperature cmd/tftpput cmd/true -- cgit v1.2.3 From 304bc9f437df51b4d982fe25fd0988350c8f5fc9 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 4 Dec 2022 20:48:57 +0100 Subject: sandbox: fix sound driver In the callback function we have to use memcpy(). Otherwise we add the new samples on top of what is stored in the stream buffer. If we don't have enough data, zero out the rest of the stream buffer. Our sampling frequency is 48000. Let the batch size for the callback function be 960. If we play a multiple of 20 ms, this will always be a full batch. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- arch/sandbox/cpu/sdl.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/sandbox/cpu/sdl.c b/arch/sandbox/cpu/sdl.c index f4ca36b35c..2c570ed8d1 100644 --- a/arch/sandbox/cpu/sdl.c +++ b/arch/sandbox/cpu/sdl.c @@ -441,7 +441,6 @@ void sandbox_sdl_fill_audio(void *udata, Uint8 *stream, int len) { struct buf_info *buf; int avail; - bool have_data = false; int i; for (i = 0; i < 2; i++) { @@ -453,10 +452,9 @@ void sandbox_sdl_fill_audio(void *udata, Uint8 *stream, int len) } if (avail > len) avail = len; - have_data = true; - SDL_MixAudio(stream, buf->data + buf->pos, avail, - SDL_MIX_MAXVOLUME); + memcpy(stream, buf->data + buf->pos, avail); + stream += avail; buf->pos += avail; len -= avail; @@ -466,7 +464,8 @@ void sandbox_sdl_fill_audio(void *udata, Uint8 *stream, int len) else break; } - sdl.stopping = !have_data; + memset(stream, 0, len); + sdl.stopping = !!len; } int sandbox_sdl_sound_init(int rate, int channels) @@ -484,7 +483,7 @@ int sandbox_sdl_sound_init(int rate, int channels) wanted.freq = rate; wanted.format = AUDIO_S16; wanted.channels = channels; - wanted.samples = 1024; /* Good low-latency value for callback */ + wanted.samples = 960; /* Good low-latency value for callback */ wanted.callback = sandbox_sdl_fill_audio; wanted.userdata = NULL; -- cgit v1.2.3 From 01c8b664d23829b254e6745a75123c5b9d512520 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Thu, 24 Nov 2022 11:36:03 +0100 Subject: dt-bindings: stm32mp13: add clock & reset support for STM32MP13 Add support of stm32mp13 DT bindings of clock and reset. Signed-off-by: Gabriel Fernandez Reviewed-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- MAINTAINERS | 5 +- include/dt-bindings/clock/stm32mp13-clks.h | 229 +++++++++++++++++++++++++++ include/dt-bindings/reset/stm32mp13-resets.h | 100 ++++++++++++ 3 files changed, 331 insertions(+), 3 deletions(-) create mode 100644 include/dt-bindings/clock/stm32mp13-clks.h create mode 100644 include/dt-bindings/reset/stm32mp13-resets.h diff --git a/MAINTAINERS b/MAINTAINERS index 75b27bc1cc..3fc4cd0f12 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -568,10 +568,9 @@ F: drivers/spi/stm32_spi.c F: drivers/video/stm32/stm32_ltdc.c F: drivers/watchdog/stm32mp_wdt.c F: include/dt-bindings/clock/stm32fx-clock.h -F: include/dt-bindings/clock/stm32mp1-clks.h -F: include/dt-bindings/clock/stm32mp1-clksrc.h +F: include/dt-bindings/clock/stm32mp* F: include/dt-bindings/pinctrl/stm32-pinfunc.h -F: include/dt-bindings/reset/stm32mp1-resets.h +F: include/dt-bindings/reset/stm32mp* F: include/stm32_rcc.h F: tools/stm32image.c N: stm diff --git a/include/dt-bindings/clock/stm32mp13-clks.h b/include/dt-bindings/clock/stm32mp13-clks.h new file mode 100644 index 0000000000..799dee5b80 --- /dev/null +++ b/include/dt-bindings/clock/stm32mp13-clks.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP13_CLKS_H_ +#define _DT_BINDINGS_STM32MP13_CLKS_H_ + +/* OSCILLATOR clocks */ +#define CK_HSE 0 +#define CK_CSI 1 +#define CK_LSI 2 +#define CK_LSE 3 +#define CK_HSI 4 +#define CK_HSE_DIV2 5 + +/* PLL */ +#define PLL1 6 +#define PLL2 7 +#define PLL3 8 +#define PLL4 9 + +/* ODF */ +#define PLL1_P 10 +#define PLL1_Q 11 +#define PLL1_R 12 +#define PLL2_P 13 +#define PLL2_Q 14 +#define PLL2_R 15 +#define PLL3_P 16 +#define PLL3_Q 17 +#define PLL3_R 18 +#define PLL4_P 19 +#define PLL4_Q 20 +#define PLL4_R 21 + +#define PCLK1 22 +#define PCLK2 23 +#define PCLK3 24 +#define PCLK4 25 +#define PCLK5 26 +#define PCLK6 27 + +/* SYSTEM CLOCK */ +#define CK_PER 28 +#define CK_MPU 29 +#define CK_AXI 30 +#define CK_MLAHB 31 + +/* BASE TIMER */ +#define CK_TIMG1 32 +#define CK_TIMG2 33 +#define CK_TIMG3 34 + +/* AUX */ +#define RTC 35 + +/* TRACE & DEBUG clocks */ +#define CK_DBG 36 +#define CK_TRACE 37 + +/* MCO clocks */ +#define CK_MCO1 38 +#define CK_MCO2 39 + +/* IP clocks */ +#define SYSCFG 40 +#define VREF 41 +#define DTS 42 +#define PMBCTRL 43 +#define HDP 44 +#define IWDG2 45 +#define STGENRO 46 +#define USART1 47 +#define RTCAPB 48 +#define TZC 49 +#define TZPC 50 +#define IWDG1 51 +#define BSEC 52 +#define DMA1 53 +#define DMA2 54 +#define DMAMUX1 55 +#define DMAMUX2 56 +#define GPIOA 57 +#define GPIOB 58 +#define GPIOC 59 +#define GPIOD 60 +#define GPIOE 61 +#define GPIOF 62 +#define GPIOG 63 +#define GPIOH 64 +#define GPIOI 65 +#define CRYP1 66 +#define HASH1 67 +#define BKPSRAM 68 +#define MDMA 69 +#define CRC1 70 +#define USBH 71 +#define DMA3 72 +#define TSC 73 +#define PKA 74 +#define AXIMC 75 +#define MCE 76 +#define ETH1TX 77 +#define ETH2TX 78 +#define ETH1RX 79 +#define ETH2RX 80 +#define ETH1MAC 81 +#define ETH2MAC 82 +#define ETH1STP 83 +#define ETH2STP 84 + +/* IP clocks with parents */ +#define SDMMC1_K 85 +#define SDMMC2_K 86 +#define ADC1_K 87 +#define ADC2_K 88 +#define FMC_K 89 +#define QSPI_K 90 +#define RNG1_K 91 +#define USBPHY_K 92 +#define STGEN_K 93 +#define SPDIF_K 94 +#define SPI1_K 95 +#define SPI2_K 96 +#define SPI3_K 97 +#define SPI4_K 98 +#define SPI5_K 99 +#define I2C1_K 100 +#define I2C2_K 101 +#define I2C3_K 102 +#define I2C4_K 103 +#define I2C5_K 104 +#define TIM2_K 105 +#define TIM3_K 106 +#define TIM4_K 107 +#define TIM5_K 108 +#define TIM6_K 109 +#define TIM7_K 110 +#define TIM12_K 111 +#define TIM13_K 112 +#define TIM14_K 113 +#define TIM1_K 114 +#define TIM8_K 115 +#define TIM15_K 116 +#define TIM16_K 117 +#define TIM17_K 118 +#define LPTIM1_K 119 +#define LPTIM2_K 120 +#define LPTIM3_K 121 +#define LPTIM4_K 122 +#define LPTIM5_K 123 +#define USART1_K 124 +#define USART2_K 125 +#define USART3_K 126 +#define UART4_K 127 +#define UART5_K 128 +#define USART6_K 129 +#define UART7_K 130 +#define UART8_K 131 +#define DFSDM_K 132 +#define FDCAN_K 133 +#define SAI1_K 134 +#define SAI2_K 135 +#define ADFSDM_K 136 +#define USBO_K 137 +#define LTDC_PX 138 +#define ETH1CK_K 139 +#define ETH1PTP_K 140 +#define ETH2CK_K 141 +#define ETH2PTP_K 142 +#define DCMIPP_K 143 +#define SAES_K 144 +#define DTS_K 145 + +/* DDR */ +#define DDRC1 146 +#define DDRC1LP 147 +#define DDRC2 148 +#define DDRC2LP 149 +#define DDRPHYC 150 +#define DDRPHYCLP 151 +#define DDRCAPB 152 +#define DDRCAPBLP 153 +#define AXIDCG 154 +#define DDRPHYCAPB 155 +#define DDRPHYCAPBLP 156 +#define DDRPERFM 157 + +#define ADC1 158 +#define ADC2 159 +#define SAI1 160 +#define SAI2 161 + +#define STM32MP1_LAST_CLK 162 + +/* SCMI clock identifiers */ +#define CK_SCMI_HSE 0 +#define CK_SCMI_HSI 1 +#define CK_SCMI_CSI 2 +#define CK_SCMI_LSE 3 +#define CK_SCMI_LSI 4 +#define CK_SCMI_HSE_DIV2 5 +#define CK_SCMI_PLL2_Q 6 +#define CK_SCMI_PLL2_R 7 +#define CK_SCMI_PLL3_P 8 +#define CK_SCMI_PLL3_Q 9 +#define CK_SCMI_PLL3_R 10 +#define CK_SCMI_PLL4_P 11 +#define CK_SCMI_PLL4_Q 12 +#define CK_SCMI_PLL4_R 13 +#define CK_SCMI_MPU 14 +#define CK_SCMI_AXI 15 +#define CK_SCMI_MLAHB 16 +#define CK_SCMI_CKPER 17 +#define CK_SCMI_PCLK1 18 +#define CK_SCMI_PCLK2 19 +#define CK_SCMI_PCLK3 20 +#define CK_SCMI_PCLK4 21 +#define CK_SCMI_PCLK5 22 +#define CK_SCMI_PCLK6 23 +#define CK_SCMI_CKTIMG1 24 +#define CK_SCMI_CKTIMG2 25 +#define CK_SCMI_CKTIMG3 26 +#define CK_SCMI_RTC 27 +#define CK_SCMI_RTCAPB 28 + +#endif /* _DT_BINDINGS_STM32MP13_CLKS_H_ */ diff --git a/include/dt-bindings/reset/stm32mp13-resets.h b/include/dt-bindings/reset/stm32mp13-resets.h new file mode 100644 index 0000000000..18ccb05db6 --- /dev/null +++ b/include/dt-bindings/reset/stm32mp13-resets.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP13_RESET_H_ +#define _DT_BINDINGS_STM32MP13_RESET_H_ + +#define TIM2_R 13568 +#define TIM3_R 13569 +#define TIM4_R 13570 +#define TIM5_R 13571 +#define TIM6_R 13572 +#define TIM7_R 13573 +#define LPTIM1_R 13577 +#define SPI2_R 13579 +#define SPI3_R 13580 +#define USART3_R 13583 +#define UART4_R 13584 +#define UART5_R 13585 +#define UART7_R 13586 +#define UART8_R 13587 +#define I2C1_R 13589 +#define I2C2_R 13590 +#define SPDIF_R 13594 +#define TIM1_R 13632 +#define TIM8_R 13633 +#define SPI1_R 13640 +#define USART6_R 13645 +#define SAI1_R 13648 +#define SAI2_R 13649 +#define DFSDM_R 13652 +#define FDCAN_R 13656 +#define LPTIM2_R 13696 +#define LPTIM3_R 13697 +#define LPTIM4_R 13698 +#define LPTIM5_R 13699 +#define SYSCFG_R 13707 +#define VREF_R 13709 +#define DTS_R 13712 +#define PMBCTRL_R 13713 +#define LTDC_R 13760 +#define DCMIPP_R 13761 +#define DDRPERFM_R 13768 +#define USBPHY_R 13776 +#define STGEN_R 13844 +#define USART1_R 13888 +#define USART2_R 13889 +#define SPI4_R 13890 +#define SPI5_R 13891 +#define I2C3_R 13892 +#define I2C4_R 13893 +#define I2C5_R 13894 +#define TIM12_R 13895 +#define TIM13_R 13896 +#define TIM14_R 13897 +#define TIM15_R 13898 +#define TIM16_R 13899 +#define TIM17_R 13900 +#define DMA1_R 13952 +#define DMA2_R 13953 +#define DMAMUX1_R 13954 +#define DMA3_R 13955 +#define DMAMUX2_R 13956 +#define ADC1_R 13957 +#define ADC2_R 13958 +#define USBO_R 13960 +#define GPIOA_R 14080 +#define GPIOB_R 14081 +#define GPIOC_R 14082 +#define GPIOD_R 14083 +#define GPIOE_R 14084 +#define GPIOF_R 14085 +#define GPIOG_R 14086 +#define GPIOH_R 14087 +#define GPIOI_R 14088 +#define TSC_R 14095 +#define PKA_R 14146 +#define SAES_R 14147 +#define CRYP1_R 14148 +#define HASH1_R 14149 +#define RNG1_R 14150 +#define AXIMC_R 14160 +#define MDMA_R 14208 +#define MCE_R 14209 +#define ETH1MAC_R 14218 +#define FMC_R 14220 +#define QSPI_R 14222 +#define SDMMC1_R 14224 +#define SDMMC2_R 14225 +#define CRC1_R 14228 +#define USBH_R 14232 +#define ETH2MAC_R 14238 + +/* SCMI reset domain identifiers */ +#define RST_SCMI_LTDC 0 +#define RST_SCMI_MDMA 1 + +#endif /* _DT_BINDINGS_STM32MP13_RESET_H_ */ -- cgit v1.2.3 From c8df960c8d8c947ecb6c02bdecf315fc63fb3da6 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Thu, 24 Nov 2022 11:36:04 +0100 Subject: clk: stm32mp13: introduce STM32MP13 RCC driver STM32MP13 RCC driver uses Common Clock Framework and also a 'clk-stm32-core' API. Then STM32MPx RCC driver will contain only data configuration (gates, mux, dividers and the way to check security) or some specific clocks. This API will be used by all new other generations of ST Socs. Signed-off-by: Gabriel Fernandez Reviewed-by: Patrick Delaunay Reviewed-by: Sean Anderson Tested-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/clk/stm32/Kconfig | 15 + drivers/clk/stm32/Makefile | 2 + drivers/clk/stm32/clk-stm32-core.c | 268 ++++++++++++ drivers/clk/stm32/clk-stm32-core.h | 276 ++++++++++++ drivers/clk/stm32/clk-stm32mp13.c | 841 +++++++++++++++++++++++++++++++++++++ drivers/clk/stm32/stm32mp13_rcc.h | 288 +++++++++++++ 6 files changed, 1690 insertions(+) create mode 100644 drivers/clk/stm32/clk-stm32-core.c create mode 100644 drivers/clk/stm32/clk-stm32-core.h create mode 100644 drivers/clk/stm32/clk-stm32mp13.c create mode 100644 drivers/clk/stm32/stm32mp13_rcc.h diff --git a/drivers/clk/stm32/Kconfig b/drivers/clk/stm32/Kconfig index eac3fc1e9d..7a34ea23c3 100644 --- a/drivers/clk/stm32/Kconfig +++ b/drivers/clk/stm32/Kconfig @@ -14,6 +14,12 @@ config CLK_STM32H7 This clock driver adds support for RCC clock management for STM32H7 SoCs. +config CLK_STM32_CORE + bool "Enable RCC clock core driver for STM32MP" + depends on ARCH_STM32MP && CLK + select CLK_CCF + select CLK_COMPOSITE_CCF + config CLK_STM32MP1 bool "Enable RCC clock driver for STM32MP15" depends on ARCH_STM32MP && CLK @@ -21,3 +27,12 @@ config CLK_STM32MP1 help Enable the STM32 clock (RCC) driver. Enable support for manipulating STM32MP15's on-SoC clocks. + +config CLK_STM32MP13 + bool "Enable RCC clock driver for STM32MP13" + depends on ARCH_STM32MP && CLK + default y if STM32MP13x + select CLK_STM32_CORE + help + Enable the STM32 clock (RCC) driver. Enable support for + manipulating STM32MP13's on-SoC clocks. diff --git a/drivers/clk/stm32/Makefile b/drivers/clk/stm32/Makefile index f66f295403..20afbc3cfc 100644 --- a/drivers/clk/stm32/Makefile +++ b/drivers/clk/stm32/Makefile @@ -2,6 +2,8 @@ # # Copyright (C) 2022, STMicroelectronics - All Rights Reserved +obj-$(CONFIG_CLK_STM32_CORE) += clk-stm32-core.o obj-$(CONFIG_CLK_STM32F) += clk-stm32f.o obj-$(CONFIG_CLK_STM32H7) += clk-stm32h7.o obj-$(CONFIG_CLK_STM32MP1) += clk-stm32mp1.o +obj-$(CONFIG_CLK_STM32MP13) += clk-stm32mp13.o diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c new file mode 100644 index 0000000000..37e996e78f --- /dev/null +++ b/drivers/clk/stm32/clk-stm32-core.c @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +#define LOG_CATEGORY UCLASS_CLK + +#include +#include +#include +#include +#include +#include +#include +#include "clk-stm32-core.h" + +int stm32_rcc_init(struct udevice *dev, + const struct stm32_clock_match_data *data) +{ + int i; + u8 *cpt; + struct stm32mp_rcc_priv *priv = dev_get_priv(dev); + fdt_addr_t base = dev_read_addr(dev->parent); + const struct clk_stm32_clock_data *clock_data = data->clock_data; + + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = (void __iomem *)base; + + /* allocate the counter of user for internal RCC gates, common for several user */ + cpt = kzalloc(clock_data->num_gates, GFP_KERNEL); + if (!cpt) + return -ENOMEM; + + priv->gate_cpt = cpt; + + priv->data = clock_data; + + for (i = 0; i < data->num_clocks; i++) { + const struct clock_config *cfg = &data->tab_clocks[i]; + struct clk *clk = ERR_PTR(-ENOENT); + + if (data->check_security && data->check_security(priv->base, cfg)) + continue; + + if (cfg->setup) { + clk = cfg->setup(dev, cfg); + clk->id = cfg->id; + } else { + dev_err(dev, "failed to register clock %s\n", cfg->name); + return -ENOENT; + } + } + + return 0; +} + +ulong clk_stm32_get_rate_by_name(const char *name) +{ + struct udevice *dev; + + if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) { + struct clk *clk = dev_get_clk_ptr(dev); + + return clk_get_rate(clk); + } + + return 0; +} + +const struct clk_ops stm32_clk_ops = { + .enable = ccf_clk_enable, + .disable = ccf_clk_disable, + .get_rate = ccf_clk_get_rate, + .set_rate = ccf_clk_set_rate, +}; + +#define RCC_MP_ENCLRR_OFFSET 4 + +static void clk_stm32_gate_set_state(void __iomem *base, + const struct clk_stm32_clock_data *data, + u8 *cpt, u16 gate_id, int enable) +{ + const struct stm32_gate_cfg *gate_cfg = &data->gates[gate_id]; + void __iomem *addr = base + gate_cfg->reg_off; + u8 set_clr = gate_cfg->set_clr ? RCC_MP_ENCLRR_OFFSET : 0; + + if (enable) { + if (cpt[gate_id]++ > 0) + return; + + if (set_clr) + writel(BIT(gate_cfg->bit_idx), addr); + else + writel(readl(addr) | BIT(gate_cfg->bit_idx), addr); + } else { + if (--cpt[gate_id] > 0) + return; + + if (set_clr) + writel(BIT(gate_cfg->bit_idx), addr + set_clr); + else + writel(readl(addr) & ~BIT(gate_cfg->bit_idx), addr); + } +} + +static int clk_stm32_gate_enable(struct clk *clk) +{ + struct clk_stm32_gate *stm32_gate = to_clk_stm32_gate(clk); + struct stm32mp_rcc_priv *priv = stm32_gate->priv; + + clk_stm32_gate_set_state(priv->base, priv->data, priv->gate_cpt, + stm32_gate->gate_id, 1); + + return 0; +} + +static int clk_stm32_gate_disable(struct clk *clk) +{ + struct clk_stm32_gate *stm32_gate = to_clk_stm32_gate(clk); + struct stm32mp_rcc_priv *priv = stm32_gate->priv; + + clk_stm32_gate_set_state(priv->base, priv->data, priv->gate_cpt, + stm32_gate->gate_id, 0); + + return 0; +} + +static const struct clk_ops clk_stm32_gate_ops = { + .enable = clk_stm32_gate_enable, + .disable = clk_stm32_gate_disable, + .get_rate = clk_generic_get_rate, +}; + +#define UBOOT_DM_CLK_STM32_GATE "clk_stm32_gate" + +U_BOOT_DRIVER(clk_stm32_gate) = { + .name = UBOOT_DM_CLK_STM32_GATE, + .id = UCLASS_CLK, + .ops = &clk_stm32_gate_ops, +}; + +struct clk *clk_stm32_gate_register(struct udevice *dev, + const struct clock_config *cfg) +{ + struct stm32mp_rcc_priv *priv = dev_get_priv(dev); + struct stm32_clk_gate_cfg *clk_cfg = cfg->clock_cfg; + struct clk_stm32_gate *stm32_gate; + struct clk *clk; + int ret; + + stm32_gate = kzalloc(sizeof(*stm32_gate), GFP_KERNEL); + if (!stm32_gate) + return ERR_PTR(-ENOMEM); + + stm32_gate->priv = priv; + stm32_gate->gate_id = clk_cfg->gate_id; + + clk = &stm32_gate->clk; + clk->flags = cfg->flags; + + ret = clk_register(clk, UBOOT_DM_CLK_STM32_GATE, + cfg->name, cfg->parent_name); + if (ret) { + kfree(stm32_gate); + return ERR_PTR(ret); + } + + return clk; +} + +struct clk * +clk_stm32_register_composite(struct udevice *dev, + const struct clock_config *cfg) +{ + struct stm32_clk_composite_cfg *composite = cfg->clock_cfg; + const char *const *parent_names; + int num_parents; + struct clk *clk = ERR_PTR(-ENOMEM); + struct clk_mux *mux = NULL; + struct clk_stm32_gate *gate = NULL; + struct clk_divider *div = NULL; + struct clk *mux_clk = NULL; + const struct clk_ops *mux_ops = NULL; + struct clk *gate_clk = NULL; + const struct clk_ops *gate_ops = NULL; + struct clk *div_clk = NULL; + const struct clk_ops *div_ops = NULL; + struct stm32mp_rcc_priv *priv = dev_get_priv(dev); + const struct clk_stm32_clock_data *data = priv->data; + + if (composite->mux_id != NO_STM32_MUX) { + const struct stm32_mux_cfg *mux_cfg; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + goto fail; + + mux_cfg = &data->muxes[composite->mux_id]; + + mux->reg = priv->base + mux_cfg->reg_off; + mux->shift = mux_cfg->shift; + mux->mask = BIT(mux_cfg->width) - 1; + mux->num_parents = mux_cfg->num_parents; + mux->flags = 0; + mux->parent_names = mux_cfg->parent_names; + + mux_clk = &mux->clk; + mux_ops = &clk_mux_ops; + + parent_names = mux_cfg->parent_names; + num_parents = mux_cfg->num_parents; + } else { + parent_names = &cfg->parent_name; + num_parents = 1; + } + + if (composite->div_id != NO_STM32_DIV) { + const struct stm32_div_cfg *div_cfg; + + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + goto fail; + + div_cfg = &data->dividers[composite->div_id]; + + div->reg = priv->base + div_cfg->reg_off; + div->shift = div_cfg->shift; + div->width = div_cfg->width; + div->width = div_cfg->width; + div->flags = div_cfg->div_flags; + div->table = div_cfg->table; + + div_clk = &div->clk; + div_ops = &clk_divider_ops; + } + + if (composite->gate_id != NO_STM32_GATE) { + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + goto fail; + + gate->priv = priv; + gate->gate_id = composite->gate_id; + + gate_clk = &gate->clk; + gate_ops = &clk_stm32_gate_ops; + } + + clk = clk_register_composite(NULL, cfg->name, + parent_names, num_parents, + mux_clk, mux_ops, + div_clk, div_ops, + gate_clk, gate_ops, + cfg->flags); + if (IS_ERR(clk)) + goto fail; + + return clk; + +fail: + kfree(gate); + kfree(div); + kfree(mux); + return ERR_CAST(clk); +} diff --git a/drivers/clk/stm32/clk-stm32-core.h b/drivers/clk/stm32/clk-stm32-core.h new file mode 100644 index 0000000000..53c2b467ab --- /dev/null +++ b/drivers/clk/stm32/clk-stm32-core.h @@ -0,0 +1,276 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +struct stm32_clock_match_data; + +/** + * struct stm32_mux_cfg - multiplexer configuration + * + * @parent_names: array of string names for all possible parents + * @num_parents: number of possible parents + * @reg_off: register controlling multiplexer + * @shift: shift to multiplexer bit field + * @width: width of the multiplexer bit field + * @mux_flags: hardware-specific flags + * @table: array of register values corresponding to the parent + * index + */ +struct stm32_mux_cfg { + const char * const *parent_names; + u8 num_parents; + u32 reg_off; + u8 shift; + u8 width; + u8 mux_flags; + u32 *table; +}; + +/** + * struct stm32_gate_cfg - gating configuration + * + * @reg_off: register controlling gate + * @bit_idx: single bit controlling gate + * @gate_flags: hardware-specific flags + * @set_clr: 0 : normal gate, 1 : has a register to clear the gate + */ +struct stm32_gate_cfg { + u32 reg_off; + u8 bit_idx; + u8 gate_flags; + u8 set_clr; +}; + +/** + * struct stm32_div_cfg - divider configuration + * + * @reg_off: register containing the divider + * @shift: shift to the divider bit field + * @width: width of the divider bit field + * @table: array of value/divider pairs, last entry should have div = 0 + */ +struct stm32_div_cfg { + u32 reg_off; + u8 shift; + u8 width; + u8 div_flags; + const struct clk_div_table *table; +}; + +#define NO_STM32_MUX -1 +#define NO_STM32_DIV -1 +#define NO_STM32_GATE -1 + +/** + * struct stm32_composite_cfg - composite configuration + * + * @mux: index of a multiplexer + * @gate: index of a gate + * @div: index of a divider + */ +struct stm32_composite_cfg { + int mux; + int gate; + int div; +}; + +/** + * struct clock_config - clock configuration + * + * @id: binding id of the clock + * @name: clock name + * @parent_name: name of the clock parent + * @flags: framework-specific flags + * @sec_id: secure id (use to known if the clock is secured or not) + * @clock_cfg: specific clock data configuration + * @setup: specific call back to reister the clock (will use + * clock_cfg data as input) + */ +struct clock_config { + unsigned long id; + const char *name; + const char *parent_name; + unsigned long flags; + int sec_id; + void *clock_cfg; + + struct clk *(*setup)(struct udevice *dev, + const struct clock_config *cfg); +}; + +/** + * struct clk_stm32_clock_data - clock data + * + * @num_gates: number of defined gates + * @gates: array of gate configuration + * @muxes: array of multiplexer configuration + * @dividers: array of divider configuration + */ +struct clk_stm32_clock_data { + unsigned int num_gates; + const struct stm32_gate_cfg *gates; + const struct stm32_mux_cfg *muxes; + const struct stm32_div_cfg *dividers; +}; + +/** + * struct stm32_clock_match_data - clock match data + * + * @num_gates: number of clocks + * @tab_clocks: array of clock configuration + * @clock_data: definition of all gates / dividers / multiplexers + * @check_security: call back to check if clock is secured or not + */ +struct stm32_clock_match_data { + unsigned int num_clocks; + const struct clock_config *tab_clocks; + const struct clk_stm32_clock_data *clock_data; + int (*check_security)(void __iomem *base, + const struct clock_config *cfg); +}; + +/** + * struct stm32mp_rcc_priv - private struct for stm32mp clocks + * + * @base: base register of RCC driver + * @gate_cpt: array of refcounting for gate with more than one + * clocks as input. See explanation of Peripheral clock enabling + * below. + * @data: data for gate / divider / multiplexer configuration + */ +struct stm32mp_rcc_priv { + void __iomem *base; + u8 *gate_cpt; + const struct clk_stm32_clock_data *data; +}; + +int stm32_rcc_init(struct udevice *dev, + const struct stm32_clock_match_data *data); + +/** + * STM32 Gate + * + * PCE (Peripheral Clock Enabling) Peripheral + * + * ------------------------------ ---------- + * | | | | + * | | | PERx | + * bus_ck | ----- | | | + * ------------->|------------------| | | ckg_bus_perx | | + * | | AND |-----|---------------->| | + * | -----------| | | | | + * | | ----- | | | + * | | | | | + * | ----- | | | + * Perx_EN |-----|---| GCL | Gating | | | + * | ----- Control | | | + * | | Logic | | | + * | | | | | + * | | ----- | | | + * | -----------| | | ckg_ker_perx | | + * perx_ker_ck | | AND |-----|---------------->| | + * ------------->|------------------| | | | | + * | ----- | | | + * | | | | + * | | | | + * ------------------------------ ---------- + + * Each peripheral requires a bus interface clock, named ckg_bus_perx + * (for peripheral ‘x’). + * Some peripherals (SAI, UART...) need also a dedicated clock for their + * communication interface, this clock is generally asynchronous with respect to + * the bus interface clock, and is named kernel clock (ckg_ker_perx). + + * Both clocks can be gated by one Perx_EN enable bit. + * Then we have to manage a refcounting on gate level to avoid gate if one + * the bus or the Kernel was enable. + * + * Example: + * 1) enable the bus clock + * --> bus_clk ref_counting = 1, gate_ref_count = 1 + * 2) enable the kernel clock + * --> perx_ker_ck ref_counting = 1, gate_ref_count = 2 + * 3) disable kernel clock + *  ---> perx_ker_ck ref_counting = 0, gate_ref_count = 1 + *  ==> then i will not gate because gate_ref_count > 0 + * 4) disable bus clock + * --> bus_clk ref_counting = 0, gate_ref_count = 0 + * ==> then i can gate (write in the register) because + * gate_ref_count = 0 + */ + +struct clk_stm32_gate { + struct clk clk; + struct stm32mp_rcc_priv *priv; + int gate_id; +}; + +#define to_clk_stm32_gate(_clk) container_of(_clk, struct clk_stm32_gate, clk) + +struct clk * +clk_stm32_gate_register(struct udevice *dev, + const struct clock_config *cfg); + +struct clk * +clk_stm32_register_composite(struct udevice *dev, + const struct clock_config *cfg); + +struct stm32_clk_gate_cfg { + int gate_id; +}; + +#define STM32_GATE(_id, _name, _parent, _flags, _gate_id, _sec_id) \ +{ \ + .id = _id, \ + .sec_id = _sec_id, \ + .name = _name, \ + .parent_name = _parent, \ + .flags = _flags, \ + .clock_cfg = &(struct stm32_clk_gate_cfg) { \ + .gate_id = _gate_id, \ + }, \ + .setup = clk_stm32_gate_register, \ +} + +struct stm32_clk_composite_cfg { + int gate_id; + int mux_id; + int div_id; +}; + +#define STM32_COMPOSITE(_id, _name, _flags, _sec_id, \ + _gate_id, _mux_id, _div_id) \ +{ \ + .id = _id, \ + .name = _name, \ + .sec_id = _sec_id, \ + .flags = _flags, \ + .clock_cfg = &(struct stm32_clk_composite_cfg) { \ + .gate_id = _gate_id, \ + .mux_id = _mux_id, \ + .div_id = _div_id, \ + }, \ + .setup = clk_stm32_register_composite, \ +} + +#define STM32_COMPOSITE_NOMUX(_id, _name, _parent, _flags, _sec_id, \ + _gate_id, _div_id) \ +{ \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .sec_id = _sec_id, \ + .flags = _flags, \ + .clock_cfg = &(struct stm32_clk_composite_cfg) { \ + .gate_id = _gate_id, \ + .mux_id = NO_STM32_MUX, \ + .div_id = _div_id, \ + }, \ + .setup = clk_stm32_register_composite, \ +} + +extern const struct clk_ops stm32_clk_ops; + +ulong clk_stm32_get_rate_by_name(const char *name); diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c new file mode 100644 index 0000000000..5174ae53a1 --- /dev/null +++ b/drivers/clk/stm32/clk-stm32mp13.c @@ -0,0 +1,841 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +#define LOG_CATEGORY UCLASS_CLK + +#include +#include +#include +#include +#include +#include +#include + +#include "clk-stm32-core.h" +#include "stm32mp13_rcc.h" + +DECLARE_GLOBAL_DATA_PTR; + +static const char * const adc12_src[] = { + "pll4_r", "ck_per", "pll3_q" +}; + +static const char * const dcmipp_src[] = { + "ck_axi", "pll2_q", "pll4_p", "ck_per", +}; + +static const char * const eth12_src[] = { + "pll4_p", "pll3_q" +}; + +static const char * const fdcan_src[] = { + "ck_hse", "pll3_q", "pll4_q", "pll4_r" +}; + +static const char * const fmc_src[] = { + "ck_axi", "pll3_r", "pll4_p", "ck_per" +}; + +static const char * const i2c12_src[] = { + "pclk1", "pll4_r", "ck_hsi", "ck_csi" +}; + +static const char * const i2c345_src[] = { + "pclk6", "pll4_r", "ck_hsi", "ck_csi" +}; + +static const char * const lptim1_src[] = { + "pclk1", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per" +}; + +static const char * const lptim23_src[] = { + "pclk3", "pll4_q", "ck_per", "ck_lse", "ck_lsi" +}; + +static const char * const lptim45_src[] = { + "pclk3", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per" +}; + +static const char * const mco1_src[] = { + "ck_hsi", "ck_hse", "ck_csi", "ck_lsi", "ck_lse" +}; + +static const char * const mco2_src[] = { + "ck_mpu", "ck_axi", "ck_mlahb", "pll4_p", "ck_hse", "ck_hsi" +}; + +static const char * const qspi_src[] = { + "ck_axi", "pll3_r", "pll4_p", "ck_per" +}; + +static const char * const rng1_src[] = { + "ck_csi", "pll4_r", "reserved", "ck_lsi" +}; + +static const char * const saes_src[] = { + "ck_axi", "ck_per", "pll4_r", "ck_lsi" +}; + +static const char * const sai1_src[] = { + "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "pll3_r" +}; + +static const char * const sai2_src[] = { + "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb", "pll3_r" +}; + +static const char * const sdmmc12_src[] = { + "ck_axi", "pll3_r", "pll4_p", "ck_hsi" +}; + +static const char * const spdif_src[] = { + "pll4_p", "pll3_q", "ck_hsi" +}; + +static const char * const spi123_src[] = { + "pll4_p", "pll3_q", "i2s_ckin", "ck_per", "pll3_r" +}; + +static const char * const spi4_src[] = { + "pclk6", "pll4_q", "ck_hsi", "ck_csi", "ck_hse", "i2s_ckin" +}; + +static const char * const spi5_src[] = { + "pclk6", "pll4_q", "ck_hsi", "ck_csi", "ck_hse" +}; + +static const char * const stgen_src[] = { + "ck_hsi", "ck_hse" +}; + +static const char * const usart12_src[] = { + "pclk6", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse" +}; + +static const char * const usart34578_src[] = { + "pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse" +}; + +static const char * const usart6_src[] = { + "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse" +}; + +static const char * const usbo_src[] = { + "pll4_r", "ck_usbo_48m" +}; + +static const char * const usbphy_src[] = { + "ck_hse", "pll4_r", "clk-hse-div2" +}; + +enum enum_mux_cfg { + MUX_I2C12, + MUX_LPTIM45, + MUX_SPI23, + MUX_UART35, + MUX_UART78, + MUX_ADC1, + MUX_ADC2, + MUX_DCMIPP, + MUX_ETH1, + MUX_ETH2, + MUX_FDCAN, + MUX_FMC, + MUX_I2C3, + MUX_I2C4, + MUX_I2C5, + MUX_LPTIM1, + MUX_LPTIM2, + MUX_LPTIM3, + MUX_QSPI, + MUX_RNG1, + MUX_SAES, + MUX_SAI1, + MUX_SAI2, + MUX_SDMMC1, + MUX_SDMMC2, + MUX_SPDIF, + MUX_SPI1, + MUX_SPI4, + MUX_SPI5, + MUX_STGEN, + MUX_UART1, + MUX_UART2, + MUX_UART4, + MUX_UART6, + MUX_USBO, + MUX_USBPHY, + MUX_MCO1, + MUX_MCO2 +}; + +#define MUX_CFG(id, src, _offset, _shift, _witdh) \ + [id] = { \ + .num_parents = ARRAY_SIZE(src), \ + .parent_names = (src), \ + .reg_off = (_offset), \ + .shift = (_shift), \ + .width = (_witdh), \ + } + +static const struct stm32_mux_cfg stm32mp13_muxes[] = { + MUX_CFG(MUX_I2C12, i2c12_src, RCC_I2C12CKSELR, 0, 3), + MUX_CFG(MUX_LPTIM45, lptim45_src, RCC_LPTIM45CKSELR, 0, 3), + MUX_CFG(MUX_SPI23, spi123_src, RCC_SPI2S23CKSELR, 0, 3), + MUX_CFG(MUX_UART35, usart34578_src, RCC_UART35CKSELR, 0, 3), + MUX_CFG(MUX_UART78, usart34578_src, RCC_UART78CKSELR, 0, 3), + MUX_CFG(MUX_ADC1, adc12_src, RCC_ADC12CKSELR, 0, 2), + MUX_CFG(MUX_ADC2, adc12_src, RCC_ADC12CKSELR, 2, 2), + MUX_CFG(MUX_DCMIPP, dcmipp_src, RCC_DCMIPPCKSELR, 0, 2), + MUX_CFG(MUX_ETH1, eth12_src, RCC_ETH12CKSELR, 0, 2), + MUX_CFG(MUX_ETH2, eth12_src, RCC_ETH12CKSELR, 8, 2), + MUX_CFG(MUX_FDCAN, fdcan_src, RCC_FDCANCKSELR, 0, 2), + MUX_CFG(MUX_FMC, fmc_src, RCC_FMCCKSELR, 0, 2), + MUX_CFG(MUX_I2C3, i2c345_src, RCC_I2C345CKSELR, 0, 3), + MUX_CFG(MUX_I2C4, i2c345_src, RCC_I2C345CKSELR, 3, 3), + MUX_CFG(MUX_I2C5, i2c345_src, RCC_I2C345CKSELR, 6, 3), + MUX_CFG(MUX_LPTIM1, lptim1_src, RCC_LPTIM1CKSELR, 0, 3), + MUX_CFG(MUX_LPTIM2, lptim23_src, RCC_LPTIM23CKSELR, 0, 3), + MUX_CFG(MUX_LPTIM3, lptim23_src, RCC_LPTIM23CKSELR, 3, 3), + MUX_CFG(MUX_MCO1, mco1_src, RCC_MCO1CFGR, 0, 3), + MUX_CFG(MUX_MCO2, mco2_src, RCC_MCO2CFGR, 0, 3), + MUX_CFG(MUX_QSPI, qspi_src, RCC_QSPICKSELR, 0, 2), + MUX_CFG(MUX_RNG1, rng1_src, RCC_RNG1CKSELR, 0, 2), + MUX_CFG(MUX_SAES, saes_src, RCC_SAESCKSELR, 0, 2), + MUX_CFG(MUX_SAI1, sai1_src, RCC_SAI1CKSELR, 0, 3), + MUX_CFG(MUX_SAI2, sai2_src, RCC_SAI2CKSELR, 0, 3), + MUX_CFG(MUX_SDMMC1, sdmmc12_src, RCC_SDMMC12CKSELR, 0, 3), + MUX_CFG(MUX_SDMMC2, sdmmc12_src, RCC_SDMMC12CKSELR, 3, 3), + MUX_CFG(MUX_SPDIF, spdif_src, RCC_SPDIFCKSELR, 0, 2), + MUX_CFG(MUX_SPI1, spi123_src, RCC_SPI2S1CKSELR, 0, 3), + MUX_CFG(MUX_SPI4, spi4_src, RCC_SPI45CKSELR, 0, 3), + MUX_CFG(MUX_SPI5, spi5_src, RCC_SPI45CKSELR, 3, 3), + MUX_CFG(MUX_STGEN, stgen_src, RCC_STGENCKSELR, 0, 2), + MUX_CFG(MUX_UART1, usart12_src, RCC_UART12CKSELR, 0, 3), + MUX_CFG(MUX_UART2, usart12_src, RCC_UART12CKSELR, 3, 3), + MUX_CFG(MUX_UART4, usart34578_src, RCC_UART4CKSELR, 0, 3), + MUX_CFG(MUX_UART6, usart6_src, RCC_UART6CKSELR, 0, 3), + MUX_CFG(MUX_USBO, usbo_src, RCC_USBCKSELR, 4, 1), + MUX_CFG(MUX_USBPHY, usbphy_src, RCC_USBCKSELR, 0, 2), +}; + +enum enum_gate_cfg { + GATE_ZERO, /* reserved for no gate */ + GATE_MCO1, + GATE_MCO2, + GATE_DBGCK, + GATE_TRACECK, + GATE_DDRC1, + GATE_DDRC1LP, + GATE_DDRPHYC, + GATE_DDRPHYCLP, + GATE_DDRCAPB, + GATE_DDRCAPBLP, + GATE_AXIDCG, + GATE_DDRPHYCAPB, + GATE_DDRPHYCAPBLP, + GATE_TIM2, + GATE_TIM3, + GATE_TIM4, + GATE_TIM5, + GATE_TIM6, + GATE_TIM7, + GATE_LPTIM1, + GATE_SPI2, + GATE_SPI3, + GATE_USART3, + GATE_UART4, + GATE_UART5, + GATE_UART7, + GATE_UART8, + GATE_I2C1, + GATE_I2C2, + GATE_SPDIF, + GATE_TIM1, + GATE_TIM8, + GATE_SPI1, + GATE_USART6, + GATE_SAI1, + GATE_SAI2, + GATE_DFSDM, + GATE_ADFSDM, + GATE_FDCAN, + GATE_LPTIM2, + GATE_LPTIM3, + GATE_LPTIM4, + GATE_LPTIM5, + GATE_VREF, + GATE_DTS, + GATE_PMBCTRL, + GATE_HDP, + GATE_SYSCFG, + GATE_DCMIPP, + GATE_DDRPERFM, + GATE_IWDG2APB, + GATE_USBPHY, + GATE_STGENRO, + GATE_LTDC, + GATE_TZC, + GATE_ETZPC, + GATE_IWDG1APB, + GATE_BSEC, + GATE_STGENC, + GATE_USART1, + GATE_USART2, + GATE_SPI4, + GATE_SPI5, + GATE_I2C3, + GATE_I2C4, + GATE_I2C5, + GATE_TIM12, + GATE_TIM13, + GATE_TIM14, + GATE_TIM15, + GATE_TIM16, + GATE_TIM17, + GATE_DMA1, + GATE_DMA2, + GATE_DMAMUX1, + GATE_DMA3, + GATE_DMAMUX2, + GATE_ADC1, + GATE_ADC2, + GATE_USBO, + GATE_TSC, + GATE_GPIOA, + GATE_GPIOB, + GATE_GPIOC, + GATE_GPIOD, + GATE_GPIOE, + GATE_GPIOF, + GATE_GPIOG, + GATE_GPIOH, + GATE_GPIOI, + GATE_PKA, + GATE_SAES, + GATE_CRYP1, + GATE_HASH1, + GATE_RNG1, + GATE_BKPSRAM, + GATE_AXIMC, + GATE_MCE, + GATE_ETH1CK, + GATE_ETH1TX, + GATE_ETH1RX, + GATE_ETH1MAC, + GATE_FMC, + GATE_QSPI, + GATE_SDMMC1, + GATE_SDMMC2, + GATE_CRC1, + GATE_USBH, + GATE_ETH2CK, + GATE_ETH2TX, + GATE_ETH2RX, + GATE_ETH2MAC, + GATE_ETH1STP, + GATE_ETH2STP, + GATE_MDMA +}; + +#define GATE_CFG(id, _offset, _bit_idx, _offset_clr) \ + [id] = { \ + .reg_off = (_offset), \ + .bit_idx = (_bit_idx), \ + .set_clr = (_offset_clr), \ + } + +static const struct stm32_gate_cfg stm32mp13_gates[] = { + GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 12, 0), + GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 12, 0), + GATE_CFG(GATE_DBGCK, RCC_DBGCFGR, 8, 0), + GATE_CFG(GATE_TRACECK, RCC_DBGCFGR, 9, 0), + GATE_CFG(GATE_DDRC1, RCC_DDRITFCR, 0, 0), + GATE_CFG(GATE_DDRC1LP, RCC_DDRITFCR, 1, 0), + GATE_CFG(GATE_DDRPHYC, RCC_DDRITFCR, 4, 0), + GATE_CFG(GATE_DDRPHYCLP, RCC_DDRITFCR, 5, 0), + GATE_CFG(GATE_DDRCAPB, RCC_DDRITFCR, 6, 0), + GATE_CFG(GATE_DDRCAPBLP, RCC_DDRITFCR, 7, 0), + GATE_CFG(GATE_AXIDCG, RCC_DDRITFCR, 8, 0), + GATE_CFG(GATE_DDRPHYCAPB, RCC_DDRITFCR, 9, 0), + GATE_CFG(GATE_DDRPHYCAPBLP, RCC_DDRITFCR, 10, 0), + GATE_CFG(GATE_TIM2, RCC_MP_APB1ENSETR, 0, 1), + GATE_CFG(GATE_TIM3, RCC_MP_APB1ENSETR, 1, 1), + GATE_CFG(GATE_TIM4, RCC_MP_APB1ENSETR, 2, 1), + GATE_CFG(GATE_TIM5, RCC_MP_APB1ENSETR, 3, 1), + GATE_CFG(GATE_TIM6, RCC_MP_APB1ENSETR, 4, 1), + GATE_CFG(GATE_TIM7, RCC_MP_APB1ENSETR, 5, 1), + GATE_CFG(GATE_LPTIM1, RCC_MP_APB1ENSETR, 9, 1), + GATE_CFG(GATE_SPI2, RCC_MP_APB1ENSETR, 11, 1), + GATE_CFG(GATE_SPI3, RCC_MP_APB1ENSETR, 12, 1), + GATE_CFG(GATE_USART3, RCC_MP_APB1ENSETR, 15, 1), + GATE_CFG(GATE_UART4, RCC_MP_APB1ENSETR, 16, 1), + GATE_CFG(GATE_UART5, RCC_MP_APB1ENSETR, 17, 1), + GATE_CFG(GATE_UART7, RCC_MP_APB1ENSETR, 18, 1), + GATE_CFG(GATE_UART8, RCC_MP_APB1ENSETR, 19, 1), + GATE_CFG(GATE_I2C1, RCC_MP_APB1ENSETR, 21, 1), + GATE_CFG(GATE_I2C2, RCC_MP_APB1ENSETR, 22, 1), + GATE_CFG(GATE_SPDIF, RCC_MP_APB1ENSETR, 26, 1), + GATE_CFG(GATE_TIM1, RCC_MP_APB2ENSETR, 0, 1), + GATE_CFG(GATE_TIM8, RCC_MP_APB2ENSETR, 1, 1), + GATE_CFG(GATE_SPI1, RCC_MP_APB2ENSETR, 8, 1), + GATE_CFG(GATE_USART6, RCC_MP_APB2ENSETR, 13, 1), + GATE_CFG(GATE_SAI1, RCC_MP_APB2ENSETR, 16, 1), + GATE_CFG(GATE_SAI2, RCC_MP_APB2ENSETR, 17, 1), + GATE_CFG(GATE_DFSDM, RCC_MP_APB2ENSETR, 20, 1), + GATE_CFG(GATE_ADFSDM, RCC_MP_APB2ENSETR, 21, 1), + GATE_CFG(GATE_FDCAN, RCC_MP_APB2ENSETR, 24, 1), + GATE_CFG(GATE_LPTIM2, RCC_MP_APB3ENSETR, 0, 1), + GATE_CFG(GATE_LPTIM3, RCC_MP_APB3ENSETR, 1, 1), + GATE_CFG(GATE_LPTIM4, RCC_MP_APB3ENSETR, 2, 1), + GATE_CFG(GATE_LPTIM5, RCC_MP_APB3ENSETR, 3, 1), + GATE_CFG(GATE_VREF, RCC_MP_APB3ENSETR, 13, 1), + GATE_CFG(GATE_DTS, RCC_MP_APB3ENSETR, 16, 1), + GATE_CFG(GATE_PMBCTRL, RCC_MP_APB3ENSETR, 17, 1), + GATE_CFG(GATE_HDP, RCC_MP_APB3ENSETR, 20, 1), + GATE_CFG(GATE_SYSCFG, RCC_MP_NS_APB3ENSETR, 0, 1), + GATE_CFG(GATE_DCMIPP, RCC_MP_APB4ENSETR, 1, 1), + GATE_CFG(GATE_DDRPERFM, RCC_MP_APB4ENSETR, 8, 1), + GATE_CFG(GATE_IWDG2APB, RCC_MP_APB4ENSETR, 15, 1), + GATE_CFG(GATE_USBPHY, RCC_MP_APB4ENSETR, 16, 1), + GATE_CFG(GATE_STGENRO, RCC_MP_APB4ENSETR, 20, 1), + GATE_CFG(GATE_LTDC, RCC_MP_NS_APB4ENSETR, 0, 1), + GATE_CFG(GATE_TZC, RCC_MP_APB5ENSETR, 11, 1), + GATE_CFG(GATE_ETZPC, RCC_MP_APB5ENSETR, 13, 1), + GATE_CFG(GATE_IWDG1APB, RCC_MP_APB5ENSETR, 15, 1), + GATE_CFG(GATE_BSEC, RCC_MP_APB5ENSETR, 16, 1), + GATE_CFG(GATE_STGENC, RCC_MP_APB5ENSETR, 20, 1), + GATE_CFG(GATE_USART1, RCC_MP_APB6ENSETR, 0, 1), + GATE_CFG(GATE_USART2, RCC_MP_APB6ENSETR, 1, 1), + GATE_CFG(GATE_SPI4, RCC_MP_APB6ENSETR, 2, 1), + GATE_CFG(GATE_SPI5, RCC_MP_APB6ENSETR, 3, 1), + GATE_CFG(GATE_I2C3, RCC_MP_APB6ENSETR, 4, 1), + GATE_CFG(GATE_I2C4, RCC_MP_APB6ENSETR, 5, 1), + GATE_CFG(GATE_I2C5, RCC_MP_APB6ENSETR, 6, 1), + GATE_CFG(GATE_TIM12, RCC_MP_APB6ENSETR, 7, 1), + GATE_CFG(GATE_TIM13, RCC_MP_APB6ENSETR, 8, 1), + GATE_CFG(GATE_TIM14, RCC_MP_APB6ENSETR, 9, 1), + GATE_CFG(GATE_TIM15, RCC_MP_APB6ENSETR, 10, 1), + GATE_CFG(GATE_TIM16, RCC_MP_APB6ENSETR, 11, 1), + GATE_CFG(GATE_TIM17, RCC_MP_APB6ENSETR, 12, 1), + GATE_CFG(GATE_DMA1, RCC_MP_AHB2ENSETR, 0, 1), + GATE_CFG(GATE_DMA2, RCC_MP_AHB2ENSETR, 1, 1), + GATE_CFG(GATE_DMAMUX1, RCC_MP_AHB2ENSETR, 2, 1), + GATE_CFG(GATE_DMA3, RCC_MP_AHB2ENSETR, 3, 1), + GATE_CFG(GATE_DMAMUX2, RCC_MP_AHB2ENSETR, 4, 1), + GATE_CFG(GATE_ADC1, RCC_MP_AHB2ENSETR, 5, 1), + GATE_CFG(GATE_ADC2, RCC_MP_AHB2ENSETR, 6, 1), + GATE_CFG(GATE_USBO, RCC_MP_AHB2ENSETR, 8, 1), + GATE_CFG(GATE_TSC, RCC_MP_AHB4ENSETR, 15, 1), + GATE_CFG(GATE_GPIOA, RCC_MP_NS_AHB4ENSETR, 0, 1), + GATE_CFG(GATE_GPIOB, RCC_MP_NS_AHB4ENSETR, 1, 1), + GATE_CFG(GATE_GPIOC, RCC_MP_NS_AHB4ENSETR, 2, 1), + GATE_CFG(GATE_GPIOD, RCC_MP_NS_AHB4ENSETR, 3, 1), + GATE_CFG(GATE_GPIOE, RCC_MP_NS_AHB4ENSETR, 4, 1), + GATE_CFG(GATE_GPIOF, RCC_MP_NS_AHB4ENSETR, 5, 1), + GATE_CFG(GATE_GPIOG, RCC_MP_NS_AHB4ENSETR, 6, 1), + GATE_CFG(GATE_GPIOH, RCC_MP_NS_AHB4ENSETR, 7, 1), + GATE_CFG(GATE_GPIOI, RCC_MP_NS_AHB4ENSETR, 8, 1), + GATE_CFG(GATE_PKA, RCC_MP_AHB5ENSETR, 2, 1), + GATE_CFG(GATE_SAES, RCC_MP_AHB5ENSETR, 3, 1), + GATE_CFG(GATE_CRYP1, RCC_MP_AHB5ENSETR, 4, 1), + GATE_CFG(GATE_HASH1, RCC_MP_AHB5ENSETR, 5, 1), + GATE_CFG(GATE_RNG1, RCC_MP_AHB5ENSETR, 6, 1), + GATE_CFG(GATE_BKPSRAM, RCC_MP_AHB5ENSETR, 8, 1), + GATE_CFG(GATE_AXIMC, RCC_MP_AHB5ENSETR, 16, 1), + GATE_CFG(GATE_MCE, RCC_MP_AHB6ENSETR, 1, 1), + GATE_CFG(GATE_ETH1CK, RCC_MP_AHB6ENSETR, 7, 1), + GATE_CFG(GATE_ETH1TX, RCC_MP_AHB6ENSETR, 8, 1), + GATE_CFG(GATE_ETH1RX, RCC_MP_AHB6ENSETR, 9, 1), + GATE_CFG(GATE_ETH1MAC, RCC_MP_AHB6ENSETR, 10, 1), + GATE_CFG(GATE_FMC, RCC_MP_AHB6ENSETR, 12, 1), + GATE_CFG(GATE_QSPI, RCC_MP_AHB6ENSETR, 14, 1), + GATE_CFG(GATE_SDMMC1, RCC_MP_AHB6ENSETR, 16, 1), + GATE_CFG(GATE_SDMMC2, RCC_MP_AHB6ENSETR, 17, 1), + GATE_CFG(GATE_CRC1, RCC_MP_AHB6ENSETR, 20, 1), + GATE_CFG(GATE_USBH, RCC_MP_AHB6ENSETR, 24, 1), + GATE_CFG(GATE_ETH2CK, RCC_MP_AHB6ENSETR, 27, 1), + GATE_CFG(GATE_ETH2TX, RCC_MP_AHB6ENSETR, 28, 1), + GATE_CFG(GATE_ETH2RX, RCC_MP_AHB6ENSETR, 29, 1), + GATE_CFG(GATE_ETH2MAC, RCC_MP_AHB6ENSETR, 30, 1), + GATE_CFG(GATE_ETH1STP, RCC_MP_AHB6LPENSETR, 11, 1), + GATE_CFG(GATE_ETH2STP, RCC_MP_AHB6LPENSETR, 31, 1), + GATE_CFG(GATE_MDMA, RCC_MP_NS_AHB6ENSETR, 0, 1), +}; + +static const struct clk_div_table ck_trace_div_table[] = { + { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, + { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 }, + { 0 }, +}; + +enum enum_div_cfg { + DIV_MCO1, + DIV_MCO2, + DIV_TRACE, + DIV_ETH1PTP, + DIV_ETH2PTP, + LAST_DIV +}; + +#define DIV_CFG(id, _offset, _shift, _width, _flags, _table) \ + [id] = { \ + .reg_off = _offset, \ + .shift = _shift, \ + .width = _width, \ + .div_flags = _flags, \ + .table = _table, \ + } + +static const struct stm32_div_cfg stm32mp13_dividers[LAST_DIV] = { + DIV_CFG(DIV_MCO1, RCC_MCO1CFGR, 4, 4, 0, NULL), + DIV_CFG(DIV_MCO2, RCC_MCO2CFGR, 4, 4, 0, NULL), + DIV_CFG(DIV_TRACE, RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table), + DIV_CFG(DIV_ETH1PTP, RCC_ETH12CKSELR, 4, 4, 0, NULL), + DIV_CFG(DIV_ETH2PTP, RCC_ETH12CKSELR, 12, 4, 0, NULL), +}; + +struct clk_stm32_securiy { + u16 offset; + u8 bit_idx; +}; + +enum securit_clk { + SECF_NONE, + SECF_LPTIM2, + SECF_LPTIM3, + SECF_VREF, + SECF_DCMIPP, + SECF_USBPHY, + SECF_RTC, + SECF_TZC, + SECF_ETZPC, + SECF_IWDG1, + SECF_BSEC, + SECF_STGENC, + SECF_STGENRO, + SECF_USART1, + SECF_USART2, + SECF_SPI4, + SECF_SPI5, + SECF_I2C3, + SECF_I2C4, + SECF_I2C5, + SECF_TIM12, + SECF_TIM13, + SECF_TIM14, + SECF_TIM15, + SECF_TIM16, + SECF_TIM17, + SECF_DMA3, + SECF_DMAMUX2, + SECF_ADC1, + SECF_ADC2, + SECF_USBO, + SECF_TSC, + SECF_PKA, + SECF_SAES, + SECF_CRYP1, + SECF_HASH1, + SECF_RNG1, + SECF_BKPSRAM, + SECF_MCE, + SECF_FMC, + SECF_QSPI, + SECF_SDMMC1, + SECF_SDMMC2, + SECF_ETH1CK, + SECF_ETH1TX, + SECF_ETH1RX, + SECF_ETH1MAC, + SECF_ETH1STP, + SECF_ETH2CK, + SECF_ETH2TX, + SECF_ETH2RX, + SECF_ETH2MAC, + SECF_ETH2STP, + SECF_MCO1, + SECF_MCO2 +}; + +#define SECF(_sec_id, _offset, _bit_idx) \ + [_sec_id] = { \ + .offset = _offset, \ + .bit_idx = _bit_idx, \ + } + +static const struct clk_stm32_securiy stm32mp13_security[] = { + SECF(SECF_LPTIM2, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM2SECF), + SECF(SECF_LPTIM3, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM3SECF), + SECF(SECF_VREF, RCC_APB3SECSR, RCC_APB3SECSR_VREFSECF), + SECF(SECF_DCMIPP, RCC_APB4SECSR, RCC_APB4SECSR_DCMIPPSECF), + SECF(SECF_USBPHY, RCC_APB4SECSR, RCC_APB4SECSR_USBPHYSECF), + SECF(SECF_RTC, RCC_APB5SECSR, RCC_APB5SECSR_RTCSECF), + SECF(SECF_TZC, RCC_APB5SECSR, RCC_APB5SECSR_TZCSECF), + SECF(SECF_ETZPC, RCC_APB5SECSR, RCC_APB5SECSR_ETZPCSECF), + SECF(SECF_IWDG1, RCC_APB5SECSR, RCC_APB5SECSR_IWDG1SECF), + SECF(SECF_BSEC, RCC_APB5SECSR, RCC_APB5SECSR_BSECSECF), + SECF(SECF_STGENC, RCC_APB5SECSR, RCC_APB5SECSR_STGENCSECF), + SECF(SECF_STGENRO, RCC_APB5SECSR, RCC_APB5SECSR_STGENROSECF), + SECF(SECF_USART1, RCC_APB6SECSR, RCC_APB6SECSR_USART1SECF), + SECF(SECF_USART2, RCC_APB6SECSR, RCC_APB6SECSR_USART2SECF), + SECF(SECF_SPI4, RCC_APB6SECSR, RCC_APB6SECSR_SPI4SECF), + SECF(SECF_SPI5, RCC_APB6SECSR, RCC_APB6SECSR_SPI5SECF), + SECF(SECF_I2C3, RCC_APB6SECSR, RCC_APB6SECSR_I2C3SECF), + SECF(SECF_I2C4, RCC_APB6SECSR, RCC_APB6SECSR_I2C4SECF), + SECF(SECF_I2C5, RCC_APB6SECSR, RCC_APB6SECSR_I2C5SECF), + SECF(SECF_TIM12, RCC_APB6SECSR, RCC_APB6SECSR_TIM12SECF), + SECF(SECF_TIM13, RCC_APB6SECSR, RCC_APB6SECSR_TIM13SECF), + SECF(SECF_TIM14, RCC_APB6SECSR, RCC_APB6SECSR_TIM14SECF), + SECF(SECF_TIM15, RCC_APB6SECSR, RCC_APB6SECSR_TIM15SECF), + SECF(SECF_TIM16, RCC_APB6SECSR, RCC_APB6SECSR_TIM16SECF), + SECF(SECF_TIM17, RCC_APB6SECSR, RCC_APB6SECSR_TIM17SECF), + SECF(SECF_DMA3, RCC_AHB2SECSR, RCC_AHB2SECSR_DMA3SECF), + SECF(SECF_DMAMUX2, RCC_AHB2SECSR, RCC_AHB2SECSR_DMAMUX2SECF), + SECF(SECF_ADC1, RCC_AHB2SECSR, RCC_AHB2SECSR_ADC1SECF), + SECF(SECF_ADC2, RCC_AHB2SECSR, RCC_AHB2SECSR_ADC2SECF), + SECF(SECF_USBO, RCC_AHB2SECSR, RCC_AHB2SECSR_USBOSECF), + SECF(SECF_TSC, RCC_AHB4SECSR, RCC_AHB4SECSR_TSCSECF), + SECF(SECF_PKA, RCC_AHB5SECSR, RCC_AHB5SECSR_PKASECF), + SECF(SECF_SAES, RCC_AHB5SECSR, RCC_AHB5SECSR_SAESSECF), + SECF(SECF_CRYP1, RCC_AHB5SECSR, RCC_AHB5SECSR_CRYP1SECF), + SECF(SECF_HASH1, RCC_AHB5SECSR, RCC_AHB5SECSR_HASH1SECF), + SECF(SECF_RNG1, RCC_AHB5SECSR, RCC_AHB5SECSR_RNG1SECF), + SECF(SECF_BKPSRAM, RCC_AHB5SECSR, RCC_AHB5SECSR_BKPSRAMSECF), + SECF(SECF_MCE, RCC_AHB6SECSR, RCC_AHB6SECSR_MCESECF), + SECF(SECF_FMC, RCC_AHB6SECSR, RCC_AHB6SECSR_FMCSECF), + SECF(SECF_QSPI, RCC_AHB6SECSR, RCC_AHB6SECSR_QSPISECF), + SECF(SECF_SDMMC1, RCC_AHB6SECSR, RCC_AHB6SECSR_SDMMC1SECF), + SECF(SECF_SDMMC2, RCC_AHB6SECSR, RCC_AHB6SECSR_SDMMC2SECF), + SECF(SECF_ETH1CK, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1CKSECF), + SECF(SECF_ETH1TX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1TXSECF), + SECF(SECF_ETH1RX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1RXSECF), + SECF(SECF_ETH1MAC, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1MACSECF), + SECF(SECF_ETH1STP, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1STPSECF), + SECF(SECF_ETH2CK, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2CKSECF), + SECF(SECF_ETH2TX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2TXSECF), + SECF(SECF_ETH2RX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2RXSECF), + SECF(SECF_ETH2MAC, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2MACSECF), + SECF(SECF_ETH2STP, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2STPSECF), + SECF(SECF_MCO1, RCC_SECCFGR, RCC_SECCFGR_MCO1SECF), + SECF(SECF_MCO2, RCC_SECCFGR, RCC_SECCFGR_MCO2SECF), +}; + +#define PCLK(_id, _name, _parent, _flags, _gate_id, _sec_id) \ + STM32_GATE(_id, _name, _parent, _flags, _gate_id, _sec_id) + +#define TIMER(_id, _name, _parent, _flags, _gate_id, _sec_id) \ + STM32_GATE(_id, _name, _parent, ((_flags) | CLK_SET_RATE_PARENT), \ + _gate_id, _sec_id) + +#define KCLK(_id, _name, _flags, _gate_id, _mux_id, _sec_id) \ + STM32_COMPOSITE(_id, _name, _flags, _sec_id, \ + _gate_id, _mux_id, NO_STM32_DIV) + +static const struct clock_config stm32mp13_clock_cfg[] = { + TIMER(TIM2_K, "tim2_k", "timg1_ck", 0, GATE_TIM2, SECF_NONE), + TIMER(TIM3_K, "tim3_k", "timg1_ck", 0, GATE_TIM3, SECF_NONE), + TIMER(TIM4_K, "tim4_k", "timg1_ck", 0, GATE_TIM4, SECF_NONE), + TIMER(TIM5_K, "tim5_k", "timg1_ck", 0, GATE_TIM5, SECF_NONE), + TIMER(TIM6_K, "tim6_k", "timg1_ck", 0, GATE_TIM6, SECF_NONE), + TIMER(TIM7_K, "tim7_k", "timg1_ck", 0, GATE_TIM7, SECF_NONE), + TIMER(TIM1_K, "tim1_k", "timg2_ck", 0, GATE_TIM1, SECF_NONE), + TIMER(TIM8_K, "tim8_k", "timg2_ck", 0, GATE_TIM8, SECF_NONE), + TIMER(TIM12_K, "tim12_k", "timg3_ck", 0, GATE_TIM12, SECF_TIM12), + TIMER(TIM13_K, "tim13_k", "timg3_ck", 0, GATE_TIM13, SECF_TIM13), + TIMER(TIM14_K, "tim14_k", "timg3_ck", 0, GATE_TIM14, SECF_TIM14), + TIMER(TIM15_K, "tim15_k", "timg3_ck", 0, GATE_TIM15, SECF_TIM15), + TIMER(TIM16_K, "tim16_k", "timg3_ck", 0, GATE_TIM16, SECF_TIM16), + TIMER(TIM17_K, "tim17_k", "timg3_ck", 0, GATE_TIM17, SECF_TIM17), + + /* Peripheral clocks */ + PCLK(SYSCFG, "syscfg", "pclk3", 0, GATE_SYSCFG, SECF_NONE), + PCLK(VREF, "vref", "pclk3", 0, GATE_VREF, SECF_VREF), + PCLK(PMBCTRL, "pmbctrl", "pclk3", 0, GATE_PMBCTRL, SECF_NONE), + PCLK(HDP, "hdp", "pclk3", 0, GATE_HDP, SECF_NONE), + PCLK(IWDG2, "iwdg2", "pclk4", 0, GATE_IWDG2APB, SECF_NONE), + PCLK(STGENRO, "stgenro", "pclk4", 0, GATE_STGENRO, SECF_STGENRO), + PCLK(TZPC, "tzpc", "pclk5", 0, GATE_TZC, SECF_TZC), + PCLK(IWDG1, "iwdg1", "pclk5", 0, GATE_IWDG1APB, SECF_IWDG1), + PCLK(BSEC, "bsec", "pclk5", 0, GATE_BSEC, SECF_BSEC), + PCLK(DMA1, "dma1", "ck_mlahb", 0, GATE_DMA1, SECF_NONE), + PCLK(DMA2, "dma2", "ck_mlahb", 0, GATE_DMA2, SECF_NONE), + PCLK(DMAMUX1, "dmamux1", "ck_mlahb", 0, GATE_DMAMUX1, SECF_NONE), + PCLK(DMAMUX2, "dmamux2", "ck_mlahb", 0, GATE_DMAMUX2, SECF_DMAMUX2), + PCLK(ADC1, "adc1", "ck_mlahb", 0, GATE_ADC1, SECF_ADC1), + PCLK(ADC2, "adc2", "ck_mlahb", 0, GATE_ADC2, SECF_ADC2), + PCLK(GPIOA, "gpioa", "pclk4", 0, GATE_GPIOA, SECF_NONE), + PCLK(GPIOB, "gpiob", "pclk4", 0, GATE_GPIOB, SECF_NONE), + PCLK(GPIOC, "gpioc", "pclk4", 0, GATE_GPIOC, SECF_NONE), + PCLK(GPIOD, "gpiod", "pclk4", 0, GATE_GPIOD, SECF_NONE), + PCLK(GPIOE, "gpioe", "pclk4", 0, GATE_GPIOE, SECF_NONE), + PCLK(GPIOF, "gpiof", "pclk4", 0, GATE_GPIOF, SECF_NONE), + PCLK(GPIOG, "gpiog", "pclk4", 0, GATE_GPIOG, SECF_NONE), + PCLK(GPIOH, "gpioh", "pclk4", 0, GATE_GPIOH, SECF_NONE), + PCLK(GPIOI, "gpioi", "pclk4", 0, GATE_GPIOI, SECF_NONE), + PCLK(TSC, "tsc", "pclk4", 0, GATE_TSC, SECF_TZC), + PCLK(PKA, "pka", "ck_axi", 0, GATE_PKA, SECF_PKA), + PCLK(CRYP1, "cryp1", "ck_axi", 0, GATE_CRYP1, SECF_CRYP1), + PCLK(HASH1, "hash1", "ck_axi", 0, GATE_HASH1, SECF_HASH1), + PCLK(BKPSRAM, "bkpsram", "ck_axi", 0, GATE_BKPSRAM, SECF_BKPSRAM), + PCLK(MDMA, "mdma", "ck_axi", 0, GATE_MDMA, SECF_NONE), + PCLK(ETH1TX, "eth1tx", "ck_axi", 0, GATE_ETH1TX, SECF_ETH1TX), + PCLK(ETH1RX, "eth1rx", "ck_axi", 0, GATE_ETH1RX, SECF_ETH1RX), + PCLK(ETH1MAC, "eth1mac", "ck_axi", 0, GATE_ETH1MAC, SECF_ETH1MAC), + PCLK(ETH2TX, "eth2tx", "ck_axi", 0, GATE_ETH2TX, SECF_ETH2TX), + PCLK(ETH2RX, "eth2rx", "ck_axi", 0, GATE_ETH2RX, SECF_ETH2RX), + PCLK(ETH2MAC, "eth2mac", "ck_axi", 0, GATE_ETH2MAC, SECF_ETH2MAC), + PCLK(CRC1, "crc1", "ck_axi", 0, GATE_CRC1, SECF_NONE), + PCLK(USBH, "usbh", "ck_axi", 0, GATE_USBH, SECF_NONE), + PCLK(DDRPERFM, "ddrperfm", "pclk4", 0, GATE_DDRPERFM, SECF_NONE), + PCLK(ETH1STP, "eth1stp", "ck_axi", 0, GATE_ETH1STP, SECF_ETH1STP), + PCLK(ETH2STP, "eth2stp", "ck_axi", 0, GATE_ETH2STP, SECF_ETH2STP), + + /* Kernel clocks */ + KCLK(SDMMC1_K, "sdmmc1_k", 0, GATE_SDMMC1, MUX_SDMMC1, SECF_SDMMC1), + KCLK(SDMMC2_K, "sdmmc2_k", 0, GATE_SDMMC2, MUX_SDMMC2, SECF_SDMMC2), + KCLK(FMC_K, "fmc_k", 0, GATE_FMC, MUX_FMC, SECF_FMC), + KCLK(QSPI_K, "qspi_k", 0, GATE_QSPI, MUX_QSPI, SECF_QSPI), + KCLK(SPI2_K, "spi2_k", 0, GATE_SPI2, MUX_SPI23, SECF_NONE), + KCLK(SPI3_K, "spi3_k", 0, GATE_SPI3, MUX_SPI23, SECF_NONE), + KCLK(I2C1_K, "i2c1_k", 0, GATE_I2C1, MUX_I2C12, SECF_NONE), + KCLK(I2C2_K, "i2c2_k", 0, GATE_I2C2, MUX_I2C12, SECF_NONE), + KCLK(LPTIM4_K, "lptim4_k", 0, GATE_LPTIM4, MUX_LPTIM45, SECF_NONE), + KCLK(LPTIM5_K, "lptim5_k", 0, GATE_LPTIM5, MUX_LPTIM45, SECF_NONE), + KCLK(USART3_K, "usart3_k", 0, GATE_USART3, MUX_UART35, SECF_NONE), + KCLK(UART5_K, "uart5_k", 0, GATE_UART5, MUX_UART35, SECF_NONE), + KCLK(UART7_K, "uart7_k", 0, GATE_UART7, MUX_UART78, SECF_NONE), + KCLK(UART8_K, "uart8_k", 0, GATE_UART8, MUX_UART78, SECF_NONE), + KCLK(RNG1_K, "rng1_k", 0, GATE_RNG1, MUX_RNG1, SECF_RNG1), + KCLK(USBPHY_K, "usbphy_k", 0, GATE_USBPHY, MUX_USBPHY, SECF_USBPHY), + KCLK(STGEN_K, "stgen_k", 0, GATE_STGENC, MUX_STGEN, SECF_STGENC), + KCLK(SPDIF_K, "spdif_k", 0, GATE_SPDIF, MUX_SPDIF, SECF_NONE), + KCLK(SPI1_K, "spi1_k", 0, GATE_SPI1, MUX_SPI1, SECF_NONE), + KCLK(SPI4_K, "spi4_k", 0, GATE_SPI4, MUX_SPI4, SECF_SPI4), + KCLK(SPI5_K, "spi5_k", 0, GATE_SPI5, MUX_SPI5, SECF_SPI5), + KCLK(I2C3_K, "i2c3_k", 0, GATE_I2C3, MUX_I2C3, SECF_I2C3), + KCLK(I2C4_K, "i2c4_k", 0, GATE_I2C4, MUX_I2C4, SECF_I2C4), + KCLK(I2C5_K, "i2c5_k", 0, GATE_I2C5, MUX_I2C5, SECF_I2C5), + KCLK(LPTIM1_K, "lptim1_k", 0, GATE_LPTIM1, MUX_LPTIM1, SECF_NONE), + KCLK(LPTIM2_K, "lptim2_k", 0, GATE_LPTIM2, MUX_LPTIM2, SECF_LPTIM2), + KCLK(LPTIM3_K, "lptim3_k", 0, GATE_LPTIM3, MUX_LPTIM3, SECF_LPTIM3), + KCLK(USART1_K, "usart1_k", 0, GATE_USART1, MUX_UART1, SECF_USART1), + KCLK(USART2_K, "usart2_k", 0, GATE_USART2, MUX_UART2, SECF_USART2), + KCLK(UART4_K, "uart4_k", 0, GATE_UART4, MUX_UART4, SECF_NONE), + KCLK(USART6_K, "uart6_k", 0, GATE_USART6, MUX_UART6, SECF_NONE), + KCLK(FDCAN_K, "fdcan_k", 0, GATE_FDCAN, MUX_FDCAN, SECF_NONE), + KCLK(SAI1_K, "sai1_k", 0, GATE_SAI1, MUX_SAI1, SECF_NONE), + KCLK(SAI2_K, "sai2_k", 0, GATE_SAI2, MUX_SAI2, SECF_NONE), + KCLK(ADC1_K, "adc1_k", 0, GATE_ADC1, MUX_ADC1, SECF_ADC1), + KCLK(ADC2_K, "adc2_k", 0, GATE_ADC2, MUX_ADC2, SECF_ADC2), + KCLK(DCMIPP_K, "dcmipp_k", 0, GATE_DCMIPP, MUX_DCMIPP, SECF_DCMIPP), + KCLK(ADFSDM_K, "adfsdm_k", 0, GATE_ADFSDM, MUX_SAI1, SECF_NONE), + KCLK(USBO_K, "usbo_k", 0, GATE_USBO, MUX_USBO, SECF_USBO), + KCLK(ETH1CK_K, "eth1ck_k", 0, GATE_ETH1CK, MUX_ETH1, SECF_ETH1CK), + KCLK(ETH2CK_K, "eth2ck_k", 0, GATE_ETH2CK, MUX_ETH2, SECF_ETH2CK), + KCLK(SAES_K, "saes_k", 0, GATE_SAES, MUX_SAES, SECF_SAES), + + STM32_GATE(DFSDM_K, "dfsdm_k", "ck_mlahb", 0, GATE_DFSDM, SECF_NONE), + STM32_GATE(LTDC_PX, "ltdc_px", "pll4_q", CLK_SET_RATE_PARENT, + GATE_LTDC, SECF_NONE), + + STM32_GATE(DTS_K, "dts_k", "ck_lse", 0, GATE_DTS, SECF_NONE), + + STM32_COMPOSITE(ETH1PTP_K, "eth1ptp_k", CLK_OPS_PARENT_ENABLE | + CLK_SET_RATE_NO_REPARENT, SECF_ETH1CK, + NO_STM32_GATE, MUX_ETH1, DIV_ETH1PTP), + + STM32_COMPOSITE(ETH2PTP_K, "eth2ptp_k", CLK_OPS_PARENT_ENABLE | + CLK_SET_RATE_NO_REPARENT, SECF_ETH2CK, + NO_STM32_GATE, MUX_ETH2, DIV_ETH2PTP), + + /* MCO clocks */ + STM32_COMPOSITE(CK_MCO1, "ck_mco1", CLK_OPS_PARENT_ENABLE | + CLK_SET_RATE_NO_REPARENT, SECF_MCO1, + GATE_MCO1, MUX_MCO1, DIV_MCO1), + + STM32_COMPOSITE(CK_MCO2, "ck_mco2", CLK_OPS_PARENT_ENABLE | + CLK_SET_RATE_NO_REPARENT, SECF_MCO2, + GATE_MCO2, MUX_MCO2, DIV_MCO2), + + /* Debug clocks */ + STM32_GATE(CK_DBG, "ck_sys_dbg", "ck_axi", CLK_IGNORE_UNUSED, + GATE_DBGCK, SECF_NONE), + + STM32_COMPOSITE_NOMUX(CK_TRACE, "ck_trace", "ck_axi", + CLK_OPS_PARENT_ENABLE, SECF_NONE, + GATE_TRACECK, DIV_TRACE), +}; + +static int stm32mp13_check_security(void __iomem *base, + const struct clock_config *cfg) +{ + int sec_id = cfg->sec_id; + int secured = 0; + + if (sec_id != SECF_NONE) { + const struct clk_stm32_securiy *secf; + + secf = &stm32mp13_security[sec_id]; + secured = !!(readl(base + secf->offset) & BIT(secf->bit_idx)); + } + + return secured; +} + +static const struct stm32_clock_match_data stm32mp13_data = { + .tab_clocks = stm32mp13_clock_cfg, + .num_clocks = ARRAY_SIZE(stm32mp13_clock_cfg), + .clock_data = &(const struct clk_stm32_clock_data) { + .num_gates = ARRAY_SIZE(stm32mp13_gates), + .gates = stm32mp13_gates, + .muxes = stm32mp13_muxes, + .dividers = stm32mp13_dividers, + }, + .check_security = stm32mp13_check_security, +}; + +static int stm32mp1_clk_probe(struct udevice *dev) +{ + struct udevice *scmi; + int err; + + /* force SCMI probe to register all SCMI clocks */ + uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(scmi_clock), &scmi); + + err = stm32_rcc_init(dev, &stm32mp13_data); + if (err) + return err; + + gd->cpu_clk = clk_stm32_get_rate_by_name("ck_mpu"); + gd->bus_clk = clk_stm32_get_rate_by_name("ck_axi"); + + /* DDRPHYC father */ + gd->mem_clk = clk_stm32_get_rate_by_name("pll2_r"); + + if (IS_ENABLED(CONFIG_DISPLAY_CPUINFO)) { + if (gd->flags & GD_FLG_RELOC) { + char buf[32]; + + log_info("Clocks:\n"); + log_info("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk)); + log_info("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk)); + log_info("- PER : %s MHz\n", + strmhz(buf, clk_stm32_get_rate_by_name("ck_per"))); + log_info("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk)); + } + } + + return 0; +} + +U_BOOT_DRIVER(stm32mp1_clock) = { + .name = "stm32mp13_clk", + .id = UCLASS_CLK, + .ops = &stm32_clk_ops, + .priv_auto = sizeof(struct stm32mp_rcc_priv), + .probe = stm32mp1_clk_probe, +}; diff --git a/drivers/clk/stm32/stm32mp13_rcc.h b/drivers/clk/stm32/stm32mp13_rcc.h new file mode 100644 index 0000000000..e7191b428a --- /dev/null +++ b/drivers/clk/stm32/stm32mp13_rcc.h @@ -0,0 +1,288 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * Configuration settings for the STM32MP13x CPU + */ + +#ifndef STM32MP13_RCC_H +#define STM32MP13_RCC_H + +/* RCC registers */ +#define RCC_SECCFGR 0x0 +#define RCC_MP_SREQSETR 0x100 +#define RCC_MP_SREQCLRR 0x104 +#define RCC_MP_APRSTCR 0x108 +#define RCC_MP_APRSTSR 0x10c +#define RCC_PWRLPDLYCR 0x110 +#define RCC_MP_GRSTCSETR 0x114 +#define RCC_BR_RSTSCLRR 0x118 +#define RCC_MP_RSTSSETR 0x11c +#define RCC_MP_RSTSCLRR 0x120 +#define RCC_MP_IWDGFZSETR 0x124 +#define RCC_MP_IWDGFZCLRR 0x128 +#define RCC_MP_CIER 0x200 +#define RCC_MP_CIFR 0x204 +#define RCC_BDCR 0x400 +#define RCC_RDLSICR 0x404 +#define RCC_OCENSETR 0x420 +#define RCC_OCENCLRR 0x424 +#define RCC_OCRDYR 0x428 +#define RCC_HSICFGR 0x440 +#define RCC_CSICFGR 0x444 +#define RCC_MCO1CFGR 0x460 +#define RCC_MCO2CFGR 0x464 +#define RCC_DBGCFGR 0x468 +#define RCC_RCK12SELR 0x480 +#define RCC_RCK3SELR 0x484 +#define RCC_RCK4SELR 0x488 +#define RCC_PLL1CR 0x4a0 +#define RCC_PLL1CFGR1 0x4a4 +#define RCC_PLL1CFGR2 0x4a8 +#define RCC_PLL1FRACR 0x4ac +#define RCC_PLL1CSGR 0x4b0 +#define RCC_PLL2CR 0x4d0 +#define RCC_PLL2CFGR1 0x4d4 +#define RCC_PLL2CFGR2 0x4d8 +#define RCC_PLL2FRACR 0x4dc +#define RCC_PLL2CSGR 0x4e0 +#define RCC_PLL3CR 0x500 +#define RCC_PLL3CFGR1 0x504 +#define RCC_PLL3CFGR2 0x508 +#define RCC_PLL3FRACR 0x50c +#define RCC_PLL3CSGR 0x510 +#define RCC_PLL4CR 0x520 +#define RCC_PLL4CFGR1 0x524 +#define RCC_PLL4CFGR2 0x528 +#define RCC_PLL4FRACR 0x52c +#define RCC_PLL4CSGR 0x530 +#define RCC_MPCKSELR 0x540 +#define RCC_ASSCKSELR 0x544 +#define RCC_MSSCKSELR 0x548 +#define RCC_CPERCKSELR 0x54c +#define RCC_RTCDIVR 0x560 +#define RCC_MPCKDIVR 0x564 +#define RCC_AXIDIVR 0x568 +#define RCC_MLAHBDIVR 0x56c +#define RCC_APB1DIVR 0x570 +#define RCC_APB2DIVR 0x574 +#define RCC_APB3DIVR 0x578 +#define RCC_APB4DIVR 0x57c +#define RCC_APB5DIVR 0x580 +#define RCC_APB6DIVR 0x584 +#define RCC_TIMG1PRER 0x5a0 +#define RCC_TIMG2PRER 0x5a4 +#define RCC_TIMG3PRER 0x5a8 +#define RCC_DDRITFCR 0x5c0 +#define RCC_I2C12CKSELR 0x600 +#define RCC_I2C345CKSELR 0x604 +#define RCC_SPI2S1CKSELR 0x608 +#define RCC_SPI2S23CKSELR 0x60c +#define RCC_SPI45CKSELR 0x610 +#define RCC_UART12CKSELR 0x614 +#define RCC_UART35CKSELR 0x618 +#define RCC_UART4CKSELR 0x61c +#define RCC_UART6CKSELR 0x620 +#define RCC_UART78CKSELR 0x624 +#define RCC_LPTIM1CKSELR 0x628 +#define RCC_LPTIM23CKSELR 0x62c +#define RCC_LPTIM45CKSELR 0x630 +#define RCC_SAI1CKSELR 0x634 +#define RCC_SAI2CKSELR 0x638 +#define RCC_FDCANCKSELR 0x63c +#define RCC_SPDIFCKSELR 0x640 +#define RCC_ADC12CKSELR 0x644 +#define RCC_SDMMC12CKSELR 0x648 +#define RCC_ETH12CKSELR 0x64c +#define RCC_USBCKSELR 0x650 +#define RCC_QSPICKSELR 0x654 +#define RCC_FMCCKSELR 0x658 +#define RCC_RNG1CKSELR 0x65c +#define RCC_STGENCKSELR 0x660 +#define RCC_DCMIPPCKSELR 0x664 +#define RCC_SAESCKSELR 0x668 +#define RCC_APB1RSTSETR 0x6a0 +#define RCC_APB1RSTCLRR 0x6a4 +#define RCC_APB2RSTSETR 0x6a8 +#define RCC_APB2RSTCLRR 0x6ac +#define RCC_APB3RSTSETR 0x6b0 +#define RCC_APB3RSTCLRR 0x6b4 +#define RCC_APB4RSTSETR 0x6b8 +#define RCC_APB4RSTCLRR 0x6bc +#define RCC_APB5RSTSETR 0x6c0 +#define RCC_APB5RSTCLRR 0x6c4 +#define RCC_APB6RSTSETR 0x6c8 +#define RCC_APB6RSTCLRR 0x6cc +#define RCC_AHB2RSTSETR 0x6d0 +#define RCC_AHB2RSTCLRR 0x6d4 +#define RCC_AHB4RSTSETR 0x6e0 +#define RCC_AHB4RSTCLRR 0x6e4 +#define RCC_AHB5RSTSETR 0x6e8 +#define RCC_AHB5RSTCLRR 0x6ec +#define RCC_AHB6RSTSETR 0x6f0 +#define RCC_AHB6RSTCLRR 0x6f4 +#define RCC_MP_APB1ENSETR 0x700 +#define RCC_MP_APB1ENCLRR 0x704 +#define RCC_MP_APB2ENSETR 0x708 +#define RCC_MP_APB2ENCLRR 0x70c +#define RCC_MP_APB3ENSETR 0x710 +#define RCC_MP_APB3ENCLRR 0x714 +#define RCC_MP_S_APB3ENSETR 0x718 +#define RCC_MP_S_APB3ENCLRR 0x71c +#define RCC_MP_NS_APB3ENSETR 0x720 +#define RCC_MP_NS_APB3ENCLRR 0x724 +#define RCC_MP_APB4ENSETR 0x728 +#define RCC_MP_APB4ENCLRR 0x72c +#define RCC_MP_S_APB4ENSETR 0x730 +#define RCC_MP_S_APB4ENCLRR 0x734 +#define RCC_MP_NS_APB4ENSETR 0x738 +#define RCC_MP_NS_APB4ENCLRR 0x73c +#define RCC_MP_APB5ENSETR 0x740 +#define RCC_MP_APB5ENCLRR 0x744 +#define RCC_MP_APB6ENSETR 0x748 +#define RCC_MP_APB6ENCLRR 0x74c +#define RCC_MP_AHB2ENSETR 0x750 +#define RCC_MP_AHB2ENCLRR 0x754 +#define RCC_MP_AHB4ENSETR 0x760 +#define RCC_MP_AHB4ENCLRR 0x764 +#define RCC_MP_S_AHB4ENSETR 0x768 +#define RCC_MP_S_AHB4ENCLRR 0x76c +#define RCC_MP_NS_AHB4ENSETR 0x770 +#define RCC_MP_NS_AHB4ENCLRR 0x774 +#define RCC_MP_AHB5ENSETR 0x778 +#define RCC_MP_AHB5ENCLRR 0x77c +#define RCC_MP_AHB6ENSETR 0x780 +#define RCC_MP_AHB6ENCLRR 0x784 +#define RCC_MP_S_AHB6ENSETR 0x788 +#define RCC_MP_S_AHB6ENCLRR 0x78c +#define RCC_MP_NS_AHB6ENSETR 0x790 +#define RCC_MP_NS_AHB6ENCLRR 0x794 +#define RCC_MP_APB1LPENSETR 0x800 +#define RCC_MP_APB1LPENCLRR 0x804 +#define RCC_MP_APB2LPENSETR 0x808 +#define RCC_MP_APB2LPENCLRR 0x80c +#define RCC_MP_APB3LPENSETR 0x810 +#define RCC_MP_APB3LPENCLRR 0x814 +#define RCC_MP_S_APB3LPENSETR 0x818 +#define RCC_MP_S_APB3LPENCLRR 0x81c +#define RCC_MP_NS_APB3LPENSETR 0x820 +#define RCC_MP_NS_APB3LPENCLRR 0x824 +#define RCC_MP_APB4LPENSETR 0x828 +#define RCC_MP_APB4LPENCLRR 0x82c +#define RCC_MP_S_APB4LPENSETR 0x830 +#define RCC_MP_S_APB4LPENCLRR 0x834 +#define RCC_MP_NS_APB4LPENSETR 0x838 +#define RCC_MP_NS_APB4LPENCLRR 0x83c +#define RCC_MP_APB5LPENSETR 0x840 +#define RCC_MP_APB5LPENCLRR 0x844 +#define RCC_MP_APB6LPENSETR 0x848 +#define RCC_MP_APB6LPENCLRR 0x84c +#define RCC_MP_AHB2LPENSETR 0x850 +#define RCC_MP_AHB2LPENCLRR 0x854 +#define RCC_MP_AHB4LPENSETR 0x858 +#define RCC_MP_AHB4LPENCLRR 0x85c +#define RCC_MP_S_AHB4LPENSETR 0x868 +#define RCC_MP_S_AHB4LPENCLRR 0x86c +#define RCC_MP_NS_AHB4LPENSETR 0x870 +#define RCC_MP_NS_AHB4LPENCLRR 0x874 +#define RCC_MP_AHB5LPENSETR 0x878 +#define RCC_MP_AHB5LPENCLRR 0x87c +#define RCC_MP_AHB6LPENSETR 0x880 +#define RCC_MP_AHB6LPENCLRR 0x884 +#define RCC_MP_S_AHB6LPENSETR 0x888 +#define RCC_MP_S_AHB6LPENCLRR 0x88c +#define RCC_MP_NS_AHB6LPENSETR 0x890 +#define RCC_MP_NS_AHB6LPENCLRR 0x894 +#define RCC_MP_S_AXIMLPENSETR 0x898 +#define RCC_MP_S_AXIMLPENCLRR 0x89c +#define RCC_MP_NS_AXIMLPENSETR 0x8a0 +#define RCC_MP_NS_AXIMLPENCLRR 0x8a4 +#define RCC_MP_MLAHBLPENSETR 0x8a8 +#define RCC_MP_MLAHBLPENCLRR 0x8ac +#define RCC_APB3SECSR 0x8c0 +#define RCC_APB4SECSR 0x8c4 +#define RCC_APB5SECSR 0x8c8 +#define RCC_APB6SECSR 0x8cc +#define RCC_AHB2SECSR 0x8d0 +#define RCC_AHB4SECSR 0x8d4 +#define RCC_AHB5SECSR 0x8d8 +#define RCC_AHB6SECSR 0x8dc +#define RCC_VERR 0xff4 +#define RCC_IDR 0xff8 +#define RCC_SIDR 0xffc + +/* RCC_SECCFGR register fields */ +#define RCC_SECCFGR_MCO1SECF 22 +#define RCC_SECCFGR_MCO2SECF 23 + +/* RCC_APB3SECSR register fields */ +#define RCC_APB3SECSR_LPTIM2SECF 0 +#define RCC_APB3SECSR_LPTIM3SECF 1 +#define RCC_APB3SECSR_VREFSECF 13 + +/* RCC_APB4SECSR register fields */ +#define RCC_APB4SECSR_DCMIPPSECF 1 +#define RCC_APB4SECSR_USBPHYSECF 16 + +/* RCC_APB5SECSR register fields */ +#define RCC_APB5SECSR_RTCSECF 8 +#define RCC_APB5SECSR_TZCSECF 11 +#define RCC_APB5SECSR_ETZPCSECF 13 +#define RCC_APB5SECSR_IWDG1SECF 15 +#define RCC_APB5SECSR_BSECSECF 16 +#define RCC_APB5SECSR_STGENCSECF 20 +#define RCC_APB5SECSR_STGENROSECF 21 + +/* RCC_APB6SECSR register fields */ +#define RCC_APB6SECSR_USART1SECF 0 +#define RCC_APB6SECSR_USART2SECF 1 +#define RCC_APB6SECSR_SPI4SECF 2 +#define RCC_APB6SECSR_SPI5SECF 3 +#define RCC_APB6SECSR_I2C3SECF 4 +#define RCC_APB6SECSR_I2C4SECF 5 +#define RCC_APB6SECSR_I2C5SECF 6 +#define RCC_APB6SECSR_TIM12SECF 7 +#define RCC_APB6SECSR_TIM13SECF 8 +#define RCC_APB6SECSR_TIM14SECF 9 +#define RCC_APB6SECSR_TIM15SECF 10 +#define RCC_APB6SECSR_TIM16SECF 11 +#define RCC_APB6SECSR_TIM17SECF 12 + +/* RCC_AHB2SECSR register fields */ +#define RCC_AHB2SECSR_DMA3SECF 3 +#define RCC_AHB2SECSR_DMAMUX2SECF 4 +#define RCC_AHB2SECSR_ADC1SECF 5 +#define RCC_AHB2SECSR_ADC2SECF 6 +#define RCC_AHB2SECSR_USBOSECF 8 + +/* RCC_AHB4SECSR register fields */ +#define RCC_AHB4SECSR_TSCSECF 15 + +/* RCC_AHB5SECSR register fields */ +#define RCC_AHB5SECSR_PKASECF 2 +#define RCC_AHB5SECSR_SAESSECF 3 +#define RCC_AHB5SECSR_CRYP1SECF 4 +#define RCC_AHB5SECSR_HASH1SECF 5 +#define RCC_AHB5SECSR_RNG1SECF 6 +#define RCC_AHB5SECSR_BKPSRAMSECF 8 + +/* RCC_AHB6SECSR register fields */ +#define RCC_AHB6SECSR_MCESECF 1 +#define RCC_AHB6SECSR_FMCSECF 12 +#define RCC_AHB6SECSR_QSPISECF 14 +#define RCC_AHB6SECSR_SDMMC1SECF 16 +#define RCC_AHB6SECSR_SDMMC2SECF 17 + +#define RCC_AHB6SECSR_ETH1CKSECF 7 +#define RCC_AHB6SECSR_ETH1TXSECF 8 +#define RCC_AHB6SECSR_ETH1RXSECF 9 +#define RCC_AHB6SECSR_ETH1MACSECF 10 +#define RCC_AHB6SECSR_ETH1STPSECF 11 + +#define RCC_AHB6SECSR_ETH2CKSECF 27 +#define RCC_AHB6SECSR_ETH2TXSECF 28 +#define RCC_AHB6SECSR_ETH2RXSECF 29 +#define RCC_AHB6SECSR_ETH2MACSECF 30 +#define RCC_AHB6SECSR_ETH2STPSECF 31 + +#endif /* STM32MP13_RCC_H */ -- cgit v1.2.3 From 2c8d548f4ea83aabf15c414537269c83d8a91381 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Thu, 24 Nov 2022 11:36:05 +0100 Subject: arm: dts: stm32mp13: add support of RCC driver Adds support of Clock and Reset drivers for STM32MP13 platform. Signed-off-by: Gabriel Fernandez Reviewed-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp13-u-boot.dtsi | 4 ++ arch/arm/dts/stm32mp131.dtsi | 119 ++++++++++++++----------------------- arch/arm/dts/stm32mp133.dtsi | 4 +- arch/arm/dts/stm32mp13xc.dtsi | 3 +- arch/arm/dts/stm32mp13xf.dtsi | 3 +- 5 files changed, 54 insertions(+), 79 deletions(-) diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi index 47a43649bb..3730f474b2 100644 --- a/arch/arm/dts/stm32mp13-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13-u-boot.dtsi @@ -92,6 +92,10 @@ u-boot,dm-pre-reloc; }; +&rcc { + u-boot,dm-pre-reloc; +}; + &scmi { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index a1c6d0d00b..d893bc24b4 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -4,6 +4,8 @@ * Author: Alexandre Torgue for STMicroelectronics. */ #include +#include +#include / { #address-cells = <1>; @@ -52,62 +54,6 @@ }; }; - clocks { - clk_axi: clk-axi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <266500000>; - }; - - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - clk_hsi: clk-hsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <64000000>; - }; - - clk_lsi: clk-lsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - clk_pclk3: clk-pclk3 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104438965>; - }; - - clk_pclk4: clk-pclk4 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <133250000>; - }; - - clk_pll4_p: clk-pll4_p { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - clk_pll4_r: clk-pll4_r { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <99000000>; - }; - - clk_rtc_k: clk-rtc-k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - }; - intc: interrupt-controller@a0021000 { compatible = "arm,cortex-a7-gic"; #interrupt-cells = <3>; @@ -155,7 +101,8 @@ compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; interrupts = ; - clocks = <&clk_hsi>; + clocks = <&rcc UART4_K>; + resets = <&rcc UART4_R>; status = "disabled"; }; @@ -170,7 +117,8 @@ , , ; - clocks = <&clk_pclk4>; + clocks = <&rcc DMA1>; + resets = <&rcc DMA1_R>; #dma-cells = <4>; st,mem2mem; dma-requests = <8>; @@ -187,7 +135,8 @@ , , ; - clocks = <&clk_pclk4>; + clocks = <&rcc DMA2>; + resets = <&rcc DMA2_R>; #dma-cells = <4>; st,mem2mem; dma-requests = <8>; @@ -196,13 +145,29 @@ dmamux1: dma-router@48002000 { compatible = "st,stm32h7-dmamux"; reg = <0x48002000 0x40>; - clocks = <&clk_pclk4>; + clocks = <&rcc DMAMUX1>; + resets = <&rcc DMAMUX1_R>; #dma-cells = <3>; dma-masters = <&dma1 &dma2>; dma-requests = <128>; dma-channels = <16>; }; + rcc: rcc@50000000 { + compatible = "st,stm32mp13-rcc", "syscon"; + reg = <0x50000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + interrupts = ; + + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; + }; + exti: interrupt-controller@5000d000 { compatible = "st,stm32mp13-exti", "syscon"; interrupt-controller; @@ -213,14 +178,14 @@ syscfg: syscon@50020000 { compatible = "st,stm32mp157-syscfg", "syscon"; reg = <0x50020000 0x400>; - clocks = <&clk_pclk3>; + clocks = <&rcc SYSCFG>; }; mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; interrupts = ; - clocks = <&clk_pclk4>; + clocks = <&rcc MDMA>; #dma-cells = <5>; dma-channels = <32>; dma-requests = <48>; @@ -232,8 +197,9 @@ reg = <0x58005000 0x1000>, <0x58006000 0x1000>; interrupts = ; interrupt-names = "cmd_irq"; - clocks = <&clk_pll4_p>; + clocks = <&rcc SDMMC1_K>; clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <130000000>; @@ -246,8 +212,10 @@ reg = <0x58007000 0x1000>, <0x58008000 0x1000>; interrupts = ; interrupt-names = "cmd_irq"; - clocks = <&clk_pll4_p>; + clocks = <&rcc SDMMC2_K>; clock-names = "apb_pclk"; + resets = <&rcc SDMMC2_R>; + cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <130000000>; @@ -257,7 +225,7 @@ iwdg2: watchdog@5a002000 { compatible = "st,stm32mp1-iwdg"; reg = <0x5a002000 0x400>; - clocks = <&clk_pclk4>, <&clk_lsi>; + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; clock-names = "pclk", "lsi"; status = "disabled"; }; @@ -266,7 +234,8 @@ compatible = "st,stm32mp1-rtc"; reg = <0x5c004000 0x400>; interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_pclk4>, <&clk_rtc_k>; + clocks = <&scmi_clk CK_SCMI_RTCAPB>, + <&scmi_clk CK_SCMI_RTC>; clock-names = "pclk", "rtc_ck"; status = "disabled"; }; @@ -307,7 +276,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOA>; st,bank-name = "GPIOA"; ngpios = <16>; gpio-ranges = <&pinctrl 0 0 16>; @@ -319,7 +288,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOB>; st,bank-name = "GPIOB"; ngpios = <16>; gpio-ranges = <&pinctrl 0 16 16>; @@ -331,7 +300,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOC>; st,bank-name = "GPIOC"; ngpios = <16>; gpio-ranges = <&pinctrl 0 32 16>; @@ -343,7 +312,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOD>; st,bank-name = "GPIOD"; ngpios = <16>; gpio-ranges = <&pinctrl 0 48 16>; @@ -355,7 +324,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOE>; st,bank-name = "GPIOE"; ngpios = <16>; gpio-ranges = <&pinctrl 0 64 16>; @@ -367,7 +336,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOF>; st,bank-name = "GPIOF"; ngpios = <16>; gpio-ranges = <&pinctrl 0 80 16>; @@ -379,7 +348,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x6000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOG>; st,bank-name = "GPIOG"; ngpios = <16>; gpio-ranges = <&pinctrl 0 96 16>; @@ -391,7 +360,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x7000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOH>; st,bank-name = "GPIOH"; ngpios = <15>; gpio-ranges = <&pinctrl 0 112 15>; @@ -403,7 +372,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x8000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOI>; st,bank-name = "GPIOI"; ngpios = <8>; gpio-ranges = <&pinctrl 0 128 8>; diff --git a/arch/arm/dts/stm32mp133.dtsi b/arch/arm/dts/stm32mp133.dtsi index 0fb1386257..531c263c9f 100644 --- a/arch/arm/dts/stm32mp133.dtsi +++ b/arch/arm/dts/stm32mp133.dtsi @@ -15,7 +15,7 @@ interrupts = , ; interrupt-names = "int0", "int1"; - clocks = <&clk_hse>, <&clk_pll4_r>; + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; status = "disabled"; @@ -28,7 +28,7 @@ interrupts = , ; interrupt-names = "int0", "int1"; - clocks = <&clk_hse>, <&clk_pll4_r>; + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; diff --git a/arch/arm/dts/stm32mp13xc.dtsi b/arch/arm/dts/stm32mp13xc.dtsi index fa6889e305..4d00e75928 100644 --- a/arch/arm/dts/stm32mp13xc.dtsi +++ b/arch/arm/dts/stm32mp13xc.dtsi @@ -10,7 +10,8 @@ compatible = "st,stm32mp1-cryp"; reg = <0x54002000 0x400>; interrupts = ; - clocks = <&clk_axi>; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; status = "disabled"; }; }; diff --git a/arch/arm/dts/stm32mp13xf.dtsi b/arch/arm/dts/stm32mp13xf.dtsi index fa6889e305..4d00e75928 100644 --- a/arch/arm/dts/stm32mp13xf.dtsi +++ b/arch/arm/dts/stm32mp13xf.dtsi @@ -10,7 +10,8 @@ compatible = "st,stm32mp1-cryp"; reg = <0x54002000 0x400>; interrupts = ; - clocks = <&clk_axi>; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; status = "disabled"; }; }; -- cgit v1.2.3 From 1727d46bf9b75722e08e7de98fca74ebd6b05cc4 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Wed, 23 Nov 2022 16:20:15 +0100 Subject: adc: stm32mp15: split channel init into several routines Split stm32_adc_chan_of_init channel initialization function into several routines to increase readability and prepare channel generic binding handling. Signed-off-by: Olivier Moysan Reviewed-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/adc/stm32-adc.c | 44 ++++++++++++++++++++++++++++++++++---------- 1 file changed, 34 insertions(+), 10 deletions(-) diff --git a/drivers/adc/stm32-adc.c b/drivers/adc/stm32-adc.c index ad8d1a32cd..1250385fbb 100644 --- a/drivers/adc/stm32-adc.c +++ b/drivers/adc/stm32-adc.c @@ -162,12 +162,8 @@ static int stm32_adc_channel_data(struct udevice *dev, int channel, return 0; } -static int stm32_adc_chan_of_init(struct udevice *dev) +static int stm32_adc_get_legacy_chan_count(struct udevice *dev) { - struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev); - struct stm32_adc *adc = dev_get_priv(dev); - u32 chans[STM32_ADC_CH_MAX]; - unsigned int i, num_channels; int ret; /* Retrieve single ended channels listed in device tree */ @@ -176,12 +172,16 @@ static int stm32_adc_chan_of_init(struct udevice *dev) dev_err(dev, "can't get st,adc-channels: %d\n", ret); return ret; } - num_channels = ret / sizeof(u32); - if (num_channels > adc->cfg->max_channels) { - dev_err(dev, "too many st,adc-channels: %d\n", num_channels); - return -EINVAL; - } + return (ret / sizeof(u32)); +} + +static int stm32_adc_legacy_chan_init(struct udevice *dev, unsigned int num_channels) +{ + struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev); + struct stm32_adc *adc = dev_get_priv(dev); + u32 chans[STM32_ADC_CH_MAX]; + int i, ret; ret = dev_read_u32_array(dev, "st,adc-channels", chans, num_channels); if (ret < 0) { @@ -197,6 +197,30 @@ static int stm32_adc_chan_of_init(struct udevice *dev) uc_pdata->channel_mask |= 1 << chans[i]; } + return ret; +} + +static int stm32_adc_chan_of_init(struct udevice *dev) +{ + struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev); + struct stm32_adc *adc = dev_get_priv(dev); + unsigned int num_channels; + int ret; + + ret = stm32_adc_get_legacy_chan_count(dev); + if (ret < 0) + return ret; + num_channels = ret; + + if (num_channels > adc->cfg->max_channels) { + dev_err(dev, "too many st,adc-channels: %d\n", num_channels); + return -EINVAL; + } + + ret = stm32_adc_legacy_chan_init(dev, num_channels); + if (ret < 0) + return ret; + uc_pdata->data_mask = (1 << adc->cfg->num_bits) - 1; uc_pdata->data_format = ADC_DATA_FORMAT_BIN; uc_pdata->data_timeout_us = 100000; -- cgit v1.2.3 From a9aa2aef5fbe9cbab61fbcc6e61cbabb7176f4f7 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Wed, 23 Nov 2022 16:20:16 +0100 Subject: adc: stm32mp15: add support of generic channels binding Add support of generic IIO channels binding: ./devicetree/bindings/iio/adc/adc.yaml Keep support of st,adc-channels for backward compatibility. Signed-off-by: Olivier Moysan Reviewed-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/adc/stm32-adc.c | 51 +++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 45 insertions(+), 6 deletions(-) diff --git a/drivers/adc/stm32-adc.c b/drivers/adc/stm32-adc.c index 1250385fbb..85efc119db 100644 --- a/drivers/adc/stm32-adc.c +++ b/drivers/adc/stm32-adc.c @@ -200,24 +200,63 @@ static int stm32_adc_legacy_chan_init(struct udevice *dev, unsigned int num_chan return ret; } +static int stm32_adc_generic_chan_init(struct udevice *dev, unsigned int num_channels) +{ + struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev); + struct stm32_adc *adc = dev_get_priv(dev); + ofnode child; + int val, ret; + + ofnode_for_each_subnode(child, dev_ofnode(dev)) { + ret = ofnode_read_u32(child, "reg", &val); + if (ret) { + dev_err(dev, "Missing channel index %d\n", ret); + return ret; + } + + if (val >= adc->cfg->max_channels) { + dev_err(dev, "Invalid channel %d\n", val); + return -EINVAL; + } + + uc_pdata->channel_mask |= 1 << val; + } + + return 0; +} + static int stm32_adc_chan_of_init(struct udevice *dev) { struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev); struct stm32_adc *adc = dev_get_priv(dev); unsigned int num_channels; int ret; - - ret = stm32_adc_get_legacy_chan_count(dev); - if (ret < 0) - return ret; - num_channels = ret; + bool legacy = false; + + num_channels = dev_get_child_count(dev); + /* If no channels have been found, fallback to channels legacy properties. */ + if (!num_channels) { + legacy = true; + + ret = stm32_adc_get_legacy_chan_count(dev); + if (!ret) { + dev_err(dev, "No channel found\n"); + return -ENODATA; + } else if (ret < 0) { + return ret; + } + num_channels = ret; + } if (num_channels > adc->cfg->max_channels) { dev_err(dev, "too many st,adc-channels: %d\n", num_channels); return -EINVAL; } - ret = stm32_adc_legacy_chan_init(dev, num_channels); + if (legacy) + ret = stm32_adc_legacy_chan_init(dev, num_channels); + else + ret = stm32_adc_generic_chan_init(dev, num_channels); if (ret < 0) return ret; -- cgit v1.2.3 From 3068bb60c6f7a635f5bead600b5715b60f1fe43a Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Wed, 2 Nov 2022 14:53:48 +0100 Subject: ARM: dts: stm32: add sdmmc cd-gpios for STM32MP135F-DK On STM32MP135F-DK, the SD card detect GPIO is GPIOH4. Backport of the Linux patch: https://lore.kernel.org/linux-arm-kernel/20220921160334.3227138-1-yann.gautier@foss.st.com/ Signed-off-by: Yann Gautier Signed-off-by: Alexandre Torgue Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp135f-dk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts index e6b8ffd332..52f86596ce 100644 --- a/arch/arm/dts/stm32mp135f-dk.dts +++ b/arch/arm/dts/stm32mp135f-dk.dts @@ -82,7 +82,7 @@ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - broken-cd; + cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; disable-wp; st,neg-edge; bus-width = <4>; -- cgit v1.2.3 From 666b1a712d81560c8081bd7704f1252130bf72f1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 2 Nov 2022 14:53:49 +0100 Subject: ARM: dts: stm32: Drop MMCI interrupt-names The pl18x MMCI driver does not use the interrupt-names property, the binding document has been updated to recommend this property be unused, remove it. Backport of Marek's Linux patch: https://lore.kernel.org/linux-arm-kernel/20221013221242.218808-3-marex@denx.de/ Reviewed-by: Linus Walleij Reviewed-by: Yann Gautier Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue Signed-off-by: Yann Gautier Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32h743.dtsi | 2 -- arch/arm/dts/stm32mp131.dtsi | 2 -- arch/arm/dts/stm32mp151.dtsi | 3 --- 3 files changed, 7 deletions(-) diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi index ceb629c4fa..c490d0a571 100644 --- a/arch/arm/dts/stm32h743.dtsi +++ b/arch/arm/dts/stm32h743.dtsi @@ -339,7 +339,6 @@ arm,primecell-periphid = <0x10153180>; reg = <0x52007000 0x1000>; interrupts = <49>; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC1_CK>; clock-names = "apb_pclk"; resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; @@ -353,7 +352,6 @@ arm,primecell-periphid = <0x10153180>; reg = <0x48022400 0x400>; interrupts = <124>; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC2_CK>; clock-names = "apb_pclk"; resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>; diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index d893bc24b4..3cf51f09bc 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -196,7 +196,6 @@ arm,primecell-periphid = <0x20253180>; reg = <0x58005000 0x1000>, <0x58006000 0x1000>; interrupts = ; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC1_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC1_R>; @@ -211,7 +210,6 @@ arm,primecell-periphid = <0x20253180>; reg = <0x58007000 0x1000>, <0x58008000 0x1000>; interrupts = ; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC2_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC2_R>; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index f0fb022fc6..8bbb1aef2e 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -1102,7 +1102,6 @@ arm,primecell-periphid = <0x00253180>; reg = <0x48004000 0x400>; interrupts = ; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC3_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC3_R>; @@ -1435,7 +1434,6 @@ arm,primecell-periphid = <0x00253180>; reg = <0x58005000 0x1000>; interrupts = ; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC1_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC1_R>; @@ -1450,7 +1448,6 @@ arm,primecell-periphid = <0x00253180>; reg = <0x58007000 0x1000>; interrupts = ; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC2_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC2_R>; -- cgit v1.2.3 From ac803d9cae483d309ce1b0441cb4495a7cc9daba Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 27 Oct 2022 23:17:55 +0200 Subject: ARM: stm32: Add boot counter to DHSOM Add boot counter to STM32MP15xx DHSOM. This aligns the software with other upstream DHSOM products which already do enable boot counter. The boot counter on STM32MP15xx is placed in the TAMP block TAMP_BKPxR register 19, right past register 17 and 18 used for CM4 resource table and state by the Linux kernel. The TAMP_BKPxR register block is used because its contents survives warm reset, but not cold reset. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard --- configs/stm32mp15_dhcom_basic_defconfig | 5 +++++ configs/stm32mp15_dhcor_basic_defconfig | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index 3ba396b967..c8093c4e15 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcom-pdk2" CONFIG_SPL_TEXT_BASE=0x2FFC2500 CONFIG_SYS_PROMPT="STM32MP> " CONFIG_SPL_MMC=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SYS_BOOTCOUNT_ADDR=0x5C00A14C CONFIG_SPL=y CONFIG_TARGET_DH_STM32MP1_PDK2=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -74,6 +76,7 @@ CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_SYS_DISABLE_AUTOLOAD=y +CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y @@ -99,6 +102,8 @@ CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y CONFIG_STM32_ADC=y CONFIG_SPL_BLOCK_CACHE=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000 CONFIG_DFU_MMC=y CONFIG_DFU_MTD=y CONFIG_DFU_RAM=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index ddd96ac4d2..7b2b92e15e 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcor-avenger96" CONFIG_SPL_TEXT_BASE=0x2FFC2500 CONFIG_SYS_PROMPT="STM32MP> " CONFIG_SPL_MMC=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SYS_BOOTCOUNT_ADDR=0x5C00A14C CONFIG_SPL=y CONFIG_TARGET_DH_STM32MP1_PDK2=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -72,6 +74,7 @@ CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_SYS_DISABLE_AUTOLOAD=y +CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y @@ -96,6 +99,8 @@ CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y CONFIG_STM32_ADC=y CONFIG_SPL_BLOCK_CACHE=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000 CONFIG_DFU_MMC=y CONFIG_DFU_MTD=y CONFIG_DFU_RAM=y -- cgit v1.2.3 From bf98da5feb970bea3d07976d86fb077727d448e4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 1 Nov 2022 23:35:31 +0100 Subject: ARM: stm32: Add version variable to DHSOM Enable insertion of version variable into U-Boot environment on DHSOM, to make it possible to check U-Boot version e.g. in U-Boot scripts. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- configs/stm32mp15_dhcom_basic_defconfig | 1 + configs/stm32mp15_dhcor_basic_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index c8093c4e15..fd261d9610 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -97,6 +97,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_ENV_IS_NOWHERE=y +CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 7b2b92e15e..947bc6b502 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -94,6 +94,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_ENV_IS_NOWHERE=y +CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y -- cgit v1.2.3 From 0eca0b1075a4040dd37291bf3fe9506a7fe98a6d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Dec 2022 03:35:13 +0100 Subject: ARM: stm32: Enable assorted ST specific commands on DHSOM Enable the stm32prog, stm32key, stboard commands on DHSOM. Those can be used e.g. to implement verified boot. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- configs/stm32mp15_dhcom_basic_defconfig | 4 ++++ configs/stm32mp15_dhcor_basic_defconfig | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index fd261d9610..92ccbb7093 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -11,7 +11,11 @@ CONFIG_SPL_MMC=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0x5C00A14C CONFIG_SPL=y +CONFIG_CMD_STM32KEY=y +CONFIG_CMD_STBOARD=y CONFIG_TARGET_DH_STM32MP1_PDK2=y +CONFIG_CMD_STM32PROG=y +CONFIG_CMD_STM32PROG_OTP=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y # CONFIG_ARMV7_VIRT is not set diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 947bc6b502..306221404d 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -11,7 +11,11 @@ CONFIG_SPL_MMC=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0x5C00A14C CONFIG_SPL=y +CONFIG_CMD_STM32KEY=y +CONFIG_CMD_STBOARD=y CONFIG_TARGET_DH_STM32MP1_PDK2=y +CONFIG_CMD_STM32PROG=y +CONFIG_CMD_STM32PROG_OTP=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y # CONFIG_ARMV7_VIRT is not set -- cgit v1.2.3 From 1ca617f5fd5bb5a0a6e3fad5fbab60493ab14f26 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Dec 2022 03:35:14 +0100 Subject: ARM: stm32: Increment boot counter in SPL on DHSOM Increment the boot counter already in U-Boot SPL instead of incrementing it only later in U-Boot proper. This can be used by SPL to boot either of two U-Boot copies and improve redundancy of software on the platform, e.g. in case of full A/B update strategy. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- configs/stm32mp15_dhcom_basic_defconfig | 1 + configs/stm32mp15_dhcor_basic_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index 92ccbb7093..f1eb022bc6 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -36,6 +36,7 @@ CONFIG_CONSOLE_MUX=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x3db00 +CONFIG_SPL_BOOTCOUNT_LIMIT=y CONFIG_SPL_LEGACY_IMAGE_FORMAT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK=0x30000000 diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 306221404d..2e9f204978 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -34,6 +34,7 @@ CONFIG_CONSOLE_MUX=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x3db00 +CONFIG_SPL_BOOTCOUNT_LIMIT=y CONFIG_SPL_LEGACY_IMAGE_FORMAT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK=0x30000000 -- cgit v1.2.3 From f708283ab9d984c025f10dbd22f619d1d6cf0175 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Dec 2022 03:35:15 +0100 Subject: ARM: stm32: Increment WDT by default on DHSOM Enable watchdog timer on the DHSOM by default, both in U-Boot proper and in SPL. This can be used in combination with boot counter by either SPL or U-Boot proper to boot either copy of system software, e.g. in case of full A/B update strategy. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- configs/stm32mp15_dhcom_basic_defconfig | 2 ++ configs/stm32mp15_dhcor_basic_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index f1eb022bc6..26c2e73aa0 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -175,6 +175,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_WDT=y +CONFIG_WDT_STM32MP=y CONFIG_FAT_WRITE=y # CONFIG_BINMAN_FDT is not set CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 2e9f204978..f76e13eafd 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -174,6 +174,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_WDT=y +CONFIG_WDT_STM32MP=y CONFIG_FAT_WRITE=y # CONFIG_BINMAN_FDT is not set CONFIG_FDT_FIXUP_PARTITIONS=y -- cgit v1.2.3 From 1c03ab9f4bdf19d1ac7afc157788bd0102ccd969 Mon Sep 17 00:00:00 2001 From: Kautuk Consul Date: Wed, 7 Dec 2022 17:12:34 +0530 Subject: lib: Add common semihosting library We factor out the arch-independent parts of the ARM semihosting implementation as a common library so that it can be shared with RISC-V. Signed-off-by: Kautuk Consul Reviewed-by: Leo Yu-Chi Liang --- arch/arm/Kconfig | 46 ----------- arch/arm/lib/semihosting.c | 181 +------------------------------------------ include/semihosting.h | 11 +++ lib/Kconfig | 47 ++++++++++++ lib/Makefile | 2 + lib/semihosting.c | 186 +++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 247 insertions(+), 226 deletions(-) create mode 100644 lib/semihosting.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3f68d0988b..cac4fa09fd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -413,52 +413,6 @@ config ARM_SMCCC This should be enabled if U-Boot needs to communicate with system firmware (for example, PSCI) according to SMCCC. -config SEMIHOSTING - bool "Support ARM semihosting" - help - Semihosting is a method for a target to communicate with a host - debugger. It uses special instructions which the debugger will trap - on and interpret. This allows U-Boot to read/write files, print to - the console, and execute arbitrary commands on the host system. - - Enabling this option will add support for reading and writing files - on the host system. If you don't have a debugger attached then trying - to do this will likely cause U-Boot to hang. Say 'n' if you are unsure. - -config SEMIHOSTING_FALLBACK - bool "Recover gracefully when semihosting fails" - depends on SEMIHOSTING && ARM64 - default y - help - Normally, if U-Boot makes a semihosting call and no debugger is - attached, then it will panic due to a synchronous abort - exception. This config adds an exception handler which will allow - U-Boot to recover. Say 'y' if unsure. - -config SPL_SEMIHOSTING - bool "Support ARM semihosting in SPL" - depends on SPL - help - Semihosting is a method for a target to communicate with a host - debugger. It uses special instructions which the debugger will trap - on and interpret. This allows U-Boot to read/write files, print to - the console, and execute arbitrary commands on the host system. - - Enabling this option will add support for reading and writing files - on the host system. If you don't have a debugger attached then trying - to do this will likely cause U-Boot to hang. Say 'n' if you are unsure. - -config SPL_SEMIHOSTING_FALLBACK - bool "Recover gracefully when semihosting fails in SPL" - depends on SPL_SEMIHOSTING && ARM64 - select ARMV8_SPL_EXCEPTION_VECTORS - default y - help - Normally, if U-Boot makes a semihosting call and no debugger is - attached, then it will panic due to a synchronous abort - exception. This config adds an exception handler which will allow - U-Boot to recover. Say 'y' if unsure. - config SYS_THUMB_BUILD bool "Build U-Boot using the Thumb instruction set" depends on !ARM64 diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index 939c0f7513..7b7669bed0 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -5,20 +5,6 @@ */ #include -#include -#include - -#define SYSOPEN 0x01 -#define SYSCLOSE 0x02 -#define SYSWRITEC 0x03 -#define SYSWRITE0 0x04 -#define SYSWRITE 0x05 -#define SYSREAD 0x06 -#define SYSREADC 0x07 -#define SYSISERROR 0x08 -#define SYSSEEK 0x0A -#define SYSFLEN 0x0C -#define SYSERRNO 0x13 /* * Macro to force the compiler to *populate* memory (for an array or struct) @@ -39,7 +25,7 @@ /* * Call the handler */ -static long smh_trap(unsigned int sysnum, void *addr) +long smh_trap(unsigned int sysnum, void *addr) { register long result asm("r0"); register void *_addr asm("r1") = addr; @@ -59,168 +45,3 @@ static long smh_trap(unsigned int sysnum, void *addr) return result; } - -#if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK) -static bool _semihosting_enabled = true; -static bool try_semihosting = true; - -bool semihosting_enabled(void) -{ - if (try_semihosting) { - smh_trap(SYSERRNO, NULL); - try_semihosting = false; - } - - return _semihosting_enabled; -} - -void disable_semihosting(void) -{ - _semihosting_enabled = false; -} -#endif - -/** - * smh_errno() - Read the host's errno - * - * This gets the value of the host's errno and negates it. The host's errno may - * or may not be set, so only call this function if a previous semihosting call - * has failed. - * - * Return: a negative error value - */ -static int smh_errno(void) -{ - long ret = smh_trap(SYSERRNO, NULL); - - if (ret > 0 && ret < INT_MAX) - return -ret; - return -EIO; -} - -long smh_open(const char *fname, enum smh_open_mode mode) -{ - long fd; - struct smh_open_s { - const char *fname; - unsigned long mode; - size_t len; - } open; - - debug("%s: file \'%s\', mode \'%u\'\n", __func__, fname, mode); - - open.fname = fname; - open.len = strlen(fname); - open.mode = mode; - - /* Open the file on the host */ - fd = smh_trap(SYSOPEN, &open); - if (fd == -1) - return smh_errno(); - return fd; -} - -/** - * struct smg_rdwr_s - Arguments for read and write - * @fd: A file descriptor returned from smh_open() - * @memp: Pointer to a buffer of memory of at least @len bytes - * @len: The number of bytes to read or write - */ -struct smh_rdwr_s { - long fd; - void *memp; - size_t len; -}; - -long smh_read(long fd, void *memp, size_t len) -{ - long ret; - struct smh_rdwr_s read; - - debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len); - - read.fd = fd; - read.memp = memp; - read.len = len; - - ret = smh_trap(SYSREAD, &read); - if (ret < 0) - return smh_errno(); - return len - ret; -} - -long smh_write(long fd, const void *memp, size_t len, ulong *written) -{ - long ret; - struct smh_rdwr_s write; - - debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len); - - write.fd = fd; - write.memp = (void *)memp; - write.len = len; - - ret = smh_trap(SYSWRITE, &write); - *written = len - ret; - if (ret) - return smh_errno(); - return 0; -} - -long smh_close(long fd) -{ - long ret; - - debug("%s: fd %ld\n", __func__, fd); - - ret = smh_trap(SYSCLOSE, &fd); - if (ret == -1) - return smh_errno(); - return 0; -} - -long smh_flen(long fd) -{ - long ret; - - debug("%s: fd %ld\n", __func__, fd); - - ret = smh_trap(SYSFLEN, &fd); - if (ret == -1) - return smh_errno(); - return ret; -} - -long smh_seek(long fd, long pos) -{ - long ret; - struct smh_seek_s { - long fd; - long pos; - } seek; - - debug("%s: fd %ld pos %ld\n", __func__, fd, pos); - - seek.fd = fd; - seek.pos = pos; - - ret = smh_trap(SYSSEEK, &seek); - if (ret) - return smh_errno(); - return 0; -} - -int smh_getc(void) -{ - return smh_trap(SYSREADC, NULL); -} - -void smh_putc(char ch) -{ - smh_trap(SYSWRITEC, &ch); -} - -void smh_puts(const char *s) -{ - smh_trap(SYSWRITE0, (char *)s); -} diff --git a/include/semihosting.h b/include/semihosting.h index f1f73464e4..4e844cbad8 100644 --- a/include/semihosting.h +++ b/include/semihosting.h @@ -17,6 +17,17 @@ #define SMH_T32_SVC 0xDFAB #define SMH_T32_HLT 0xBABC +/** + * smh_trap() - ARCH-specific semihosting call. + * + * Semihosting library/driver can use this function to do the + * actual semihosting calls. + * + * Return: Error code defined by semihosting spec. + */ + +long smh_trap(unsigned int sysnum, void *addr); + #if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK) /** * semihosting_enabled() - Determine whether semihosting is supported diff --git a/lib/Kconfig b/lib/Kconfig index 6abe1d0a86..b8833e0183 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -71,6 +71,53 @@ config HAVE_PRIVATE_LIBGCC config LIB_UUID bool +config SEMIHOSTING + bool "Support semihosting" + depends on ARM + help + Semihosting is a method for a target to communicate with a host + debugger. It uses special instructions which the debugger will trap + on and interpret. This allows U-Boot to read/write files, print to + the console, and execute arbitrary commands on the host system. + + Enabling this option will add support for reading and writing files + on the host system. If you don't have a debugger attached then trying + to do this will likely cause U-Boot to hang. Say 'n' if you are unsure. + +config SEMIHOSTING_FALLBACK + bool "Recover gracefully when semihosting fails" + depends on SEMIHOSTING && ARM64 + default y + help + Normally, if U-Boot makes a semihosting call and no debugger is + attached, then it will panic due to a synchronous abort + exception. This config adds an exception handler which will allow + U-Boot to recover. Say 'y' if unsure. + +config SPL_SEMIHOSTING + bool "Support semihosting in SPL" + depends on SPL && ARM + help + Semihosting is a method for a target to communicate with a host + debugger. It uses special instructions which the debugger will trap + on and interpret. This allows U-Boot to read/write files, print to + the console, and execute arbitrary commands on the host system. + + Enabling this option will add support for reading and writing files + on the host system. If you don't have a debugger attached then trying + to do this will likely cause U-Boot to hang. Say 'n' if you are unsure. + +config SPL_SEMIHOSTING_FALLBACK + bool "Recover gracefully when semihosting fails in SPL" + depends on SPL_SEMIHOSTING && ARM64 + select ARMV8_SPL_EXCEPTION_VECTORS + default y + help + Normally, if U-Boot makes a semihosting call and no debugger is + attached, then it will panic due to a synchronous abort + exception. This config adds an exception handler which will allow + U-Boot to recover. Say 'y' if unsure. + config PRINTF bool default y diff --git a/lib/Makefile b/lib/Makefile index f2cfd1e428..d77b33e7f4 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -146,6 +146,8 @@ obj-y += date.o obj-y += rtc-lib.o obj-$(CONFIG_LIB_ELF) += elf.o +obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o + # # Build a fast OID lookup registry from include/linux/oid_registry.h # diff --git a/lib/semihosting.c b/lib/semihosting.c new file mode 100644 index 0000000000..831774e356 --- /dev/null +++ b/lib/semihosting.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Sean Anderson + * Copyright 2014 Broadcom Corporation + */ + +#include +#include +#include + +#define SYSOPEN 0x01 +#define SYSCLOSE 0x02 +#define SYSWRITEC 0x03 +#define SYSWRITE0 0x04 +#define SYSWRITE 0x05 +#define SYSREAD 0x06 +#define SYSREADC 0x07 +#define SYSISERROR 0x08 +#define SYSSEEK 0x0A +#define SYSFLEN 0x0C +#define SYSERRNO 0x13 + +#if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK) +static bool _semihosting_enabled = true; +static bool try_semihosting = true; + +bool semihosting_enabled(void) +{ + if (try_semihosting) { + smh_trap(SYSERRNO, NULL); + try_semihosting = false; + } + + return _semihosting_enabled; +} + +void disable_semihosting(void) +{ + _semihosting_enabled = false; +} +#endif + +/** + * smh_errno() - Read the host's errno + * + * This gets the value of the host's errno and negates it. The host's errno may + * or may not be set, so only call this function if a previous semihosting call + * has failed. + * + * Return: a negative error value + */ +static int smh_errno(void) +{ + long ret = smh_trap(SYSERRNO, NULL); + + if (ret > 0 && ret < INT_MAX) + return -ret; + return -EIO; +} + +long smh_open(const char *fname, enum smh_open_mode mode) +{ + long fd; + struct smh_open_s { + const char *fname; + unsigned long mode; + size_t len; + } open; + + debug("%s: file \'%s\', mode \'%u\'\n", __func__, fname, mode); + + open.fname = fname; + open.len = strlen(fname); + open.mode = mode; + + /* Open the file on the host */ + fd = smh_trap(SYSOPEN, &open); + if (fd == -1) + return smh_errno(); + return fd; +} + +/** + * struct smg_rdwr_s - Arguments for read and write + * @fd: A file descriptor returned from smh_open() + * @memp: Pointer to a buffer of memory of at least @len bytes + * @len: The number of bytes to read or write + */ +struct smh_rdwr_s { + long fd; + void *memp; + size_t len; +}; + +long smh_read(long fd, void *memp, size_t len) +{ + long ret; + struct smh_rdwr_s read; + + debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len); + + read.fd = fd; + read.memp = memp; + read.len = len; + + ret = smh_trap(SYSREAD, &read); + if (ret < 0) + return smh_errno(); + return len - ret; +} + +long smh_write(long fd, const void *memp, size_t len, ulong *written) +{ + long ret; + struct smh_rdwr_s write; + + debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len); + + write.fd = fd; + write.memp = (void *)memp; + write.len = len; + + ret = smh_trap(SYSWRITE, &write); + *written = len - ret; + if (ret) + return smh_errno(); + return 0; +} + +long smh_close(long fd) +{ + long ret; + + debug("%s: fd %ld\n", __func__, fd); + + ret = smh_trap(SYSCLOSE, &fd); + if (ret == -1) + return smh_errno(); + return 0; +} + +long smh_flen(long fd) +{ + long ret; + + debug("%s: fd %ld\n", __func__, fd); + + ret = smh_trap(SYSFLEN, &fd); + if (ret == -1) + return smh_errno(); + return ret; +} + +long smh_seek(long fd, long pos) +{ + long ret; + struct smh_seek_s { + long fd; + long pos; + } seek; + + debug("%s: fd %ld pos %ld\n", __func__, fd, pos); + + seek.fd = fd; + seek.pos = pos; + + ret = smh_trap(SYSSEEK, &seek); + if (ret) + return smh_errno(); + return 0; +} + +int smh_getc(void) +{ + return smh_trap(SYSREADC, NULL); +} + +void smh_putc(char ch) +{ + smh_trap(SYSWRITEC, &ch); +} + +void smh_puts(const char *s) +{ + smh_trap(SYSWRITE0, (char *)s); +} -- cgit v1.2.3 From ae3527f088062dc4e117b0c4d4319e068f5e44cd Mon Sep 17 00:00:00 2001 From: Kautuk Consul Date: Wed, 7 Dec 2022 17:12:35 +0530 Subject: arch/riscv: add semihosting support for RISC-V We add RISC-V semihosting based serial console for JTAG based early debugging. The RISC-V semihosting specification is available at: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc Signed-off-by: Anup Patel Signed-off-by: Kautuk Consul Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/include/asm/spl.h | 1 + arch/riscv/lib/Makefile | 2 ++ arch/riscv/lib/interrupts.c | 25 +++++++++++++++++++++++++ arch/riscv/lib/semihosting.c | 24 ++++++++++++++++++++++++ lib/Kconfig | 10 +++++----- 5 files changed, 57 insertions(+), 5 deletions(-) create mode 100644 arch/riscv/lib/semihosting.c diff --git a/arch/riscv/include/asm/spl.h b/arch/riscv/include/asm/spl.h index e8a94fcb1f..2898a770ee 100644 --- a/arch/riscv/include/asm/spl.h +++ b/arch/riscv/include/asm/spl.h @@ -25,6 +25,7 @@ enum { BOOT_DEVICE_DFU, BOOT_DEVICE_XIP, BOOT_DEVICE_BOOTROM, + BOOT_DEVICE_SMH, BOOT_DEVICE_NONE }; diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index d6a8ae9728..e5a81ba722 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -42,3 +42,5 @@ extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC) obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMMOVE) += memmove.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o + +obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 100be2e966..e966afa7e3 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -9,6 +9,7 @@ * Copyright (C) 2019 Sean Anderson */ +#include #include #include #include @@ -17,6 +18,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -149,6 +151,29 @@ ulong handle_trap(ulong cause, ulong epc, ulong tval, struct pt_regs *regs) /* An UEFI application may have changed gd. Restore U-Boot's gd. */ efi_restore_gd(); + if (cause == CAUSE_BREAKPOINT && + CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK)) { + ulong pre_addr = epc - 4, post_addr = epc + 4; + + /* Check for prior and post addresses to be in same page. */ + if ((pre_addr & ~(PAGE_SIZE - 1)) == + (post_addr & ~(PAGE_SIZE - 1))) { + u32 pre = *(u32 *)pre_addr; + u32 post = *(u32 *)post_addr; + + /* Check for semihosting, i.e.: + * slli zero,zero,0x1f + * ebreak + * srai zero,zero,0x7 + */ + if (pre == 0x01f01013 && post == 0x40705013) { + disable_semihosting(); + epc += 4; + return epc; + } + } + } + is_irq = (cause & MCAUSE_INT); irq = (cause & ~MCAUSE_INT); diff --git a/arch/riscv/lib/semihosting.c b/arch/riscv/lib/semihosting.c new file mode 100644 index 0000000000..d6593b02a6 --- /dev/null +++ b/arch/riscv/lib/semihosting.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#include + +long smh_trap(int sysnum, void *addr) +{ + register int ret asm ("a0") = sysnum; + register void *param0 asm ("a1") = addr; + + asm volatile (".align 4\n" + ".option push\n" + ".option norvc\n" + + "slli zero, zero, 0x1f\n" + "ebreak\n" + "srai zero, zero, 7\n" + ".option pop\n" + : "+r" (ret) : "r" (param0) : "memory"); + + return ret; +} diff --git a/lib/Kconfig b/lib/Kconfig index b8833e0183..3c5a4ab386 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -73,7 +73,7 @@ config LIB_UUID config SEMIHOSTING bool "Support semihosting" - depends on ARM + depends on ARM || RISCV help Semihosting is a method for a target to communicate with a host debugger. It uses special instructions which the debugger will trap @@ -86,7 +86,7 @@ config SEMIHOSTING config SEMIHOSTING_FALLBACK bool "Recover gracefully when semihosting fails" - depends on SEMIHOSTING && ARM64 + depends on SEMIHOSTING && (ARM64 || RISCV) default y help Normally, if U-Boot makes a semihosting call and no debugger is @@ -96,7 +96,7 @@ config SEMIHOSTING_FALLBACK config SPL_SEMIHOSTING bool "Support semihosting in SPL" - depends on SPL && ARM + depends on SPL && (ARM || RISCV) help Semihosting is a method for a target to communicate with a host debugger. It uses special instructions which the debugger will trap @@ -109,8 +109,8 @@ config SPL_SEMIHOSTING config SPL_SEMIHOSTING_FALLBACK bool "Recover gracefully when semihosting fails in SPL" - depends on SPL_SEMIHOSTING && ARM64 - select ARMV8_SPL_EXCEPTION_VECTORS + depends on SPL_SEMIHOSTING && (ARM64 || RISCV) + select ARMV8_SPL_EXCEPTION_VECTORS if ARM64 default y help Normally, if U-Boot makes a semihosting call and no debugger is -- cgit v1.2.3 From ac14155a2a73b7f517ef356c1bf823b9f0eaf88d Mon Sep 17 00:00:00 2001 From: Kautuk Consul Date: Wed, 7 Dec 2022 17:12:36 +0530 Subject: common/spl/Kconfig: add dependency on SPL_SEMIHOSTING for SPL payload When we enable CONFIG_SPL and CONFIG_SPL_SEMIHOSTING then the code in common/spl/spl_semihosting.c tries to use the CONFIG_SPL_FS_LOAD_PAYLOAD_NAME string which remains undeclared unless SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS are configured. Add a dependency of SPL_SEMIHOSTING in the depends for SPL_FS_LOAD_PAYLOAD_NAME so that the code compiles fine. Signed-off-by: Kautuk Consul Reviewed-by: Leo Yu-Chi Liang --- common/spl/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index fef01bdd7d..6c4848f3b9 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -691,7 +691,7 @@ config SPL_FS_FAT config SPL_FS_LOAD_PAYLOAD_NAME string "File to load for U-Boot from the filesystem" - depends on SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS + depends on SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS || SPL_SEMIHOSTING default "tispl.bin" if SYS_K3_SPL_ATF default "u-boot.itb" if SPL_LOAD_FIT default "u-boot.img" -- cgit v1.2.3 From 57b9900cd59ad492f74390515901788459f1e8aa Mon Sep 17 00:00:00 2001 From: Zong Li Date: Wed, 16 Nov 2022 07:08:39 +0000 Subject: riscv: use imply instead of select for SPL_SEPARATE_BSS Use imply instead of select, then it can still be disabled by board-specific defconfig, or be set to n manually. Signed-off-by: Zong Li Reviewed-by: Rick Chen Reviewed-by: Bin Meng --- arch/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/Kconfig b/arch/Kconfig index ae39716697..102956d24c 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -111,7 +111,7 @@ config RISCV select SUPPORT_OF_CONTROL select OF_CONTROL select DM - select SPL_SEPARATE_BSS if SPL + imply SPL_SEPARATE_BSS if SPL imply DM_SERIAL imply DM_ETH imply DM_EVENT -- cgit v1.2.3 From 14dc0ab138988a8e45ffa086444ec8db48b3f103 Mon Sep 17 00:00:00 2001 From: Hugo SIMELIERE Date: Wed, 30 Nov 2022 09:29:16 +0100 Subject: usb: gadget: dfu: Fix check of transfer direction Commit fbce985e28eaca3af82afecc11961aadaf971a7e to fix CVE-2022-2347 blocks DFU usb requests. The verification of the transfer direction was done by an equality but it is a bit mask. Signed-off-by: Hugo SIMELIERE Reviewed-by: Fabio Estevam Reviewed-by: Sultan Qasim Khan Reviewed-by: Marek Vasut Tested-by: Marek Vasut --- drivers/usb/gadget/f_dfu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c index 33ef62f8ba..44877df4ec 100644 --- a/drivers/usb/gadget/f_dfu.c +++ b/drivers/usb/gadget/f_dfu.c @@ -325,7 +325,7 @@ static int state_dfu_idle(struct f_dfu *f_dfu, switch (ctrl->bRequest) { case USB_REQ_DFU_DNLOAD: - if (ctrl->bRequestType == USB_DIR_OUT) { + if (!(ctrl->bRequestType & USB_DIR_IN)) { if (len == 0) { f_dfu->dfu_state = DFU_STATE_dfuERROR; value = RET_STALL; @@ -337,7 +337,7 @@ static int state_dfu_idle(struct f_dfu *f_dfu, } break; case USB_REQ_DFU_UPLOAD: - if (ctrl->bRequestType == USB_DIR_IN) { + if (ctrl->bRequestType & USB_DIR_IN) { f_dfu->dfu_state = DFU_STATE_dfuUPLOAD_IDLE; f_dfu->blk_seq_num = 0; value = handle_upload(req, len); @@ -436,7 +436,7 @@ static int state_dfu_dnload_idle(struct f_dfu *f_dfu, switch (ctrl->bRequest) { case USB_REQ_DFU_DNLOAD: - if (ctrl->bRequestType == USB_DIR_OUT) { + if (!(ctrl->bRequestType & USB_DIR_IN)) { f_dfu->dfu_state = DFU_STATE_dfuDNLOAD_SYNC; f_dfu->blk_seq_num = w_value; value = handle_dnload(gadget, len); @@ -527,7 +527,7 @@ static int state_dfu_upload_idle(struct f_dfu *f_dfu, switch (ctrl->bRequest) { case USB_REQ_DFU_UPLOAD: - if (ctrl->bRequestType == USB_DIR_IN) { + if (ctrl->bRequestType & USB_DIR_IN) { /* state transition if less data then requested */ f_dfu->blk_seq_num = w_value; value = handle_upload(req, len); -- cgit v1.2.3 From bcd4110702d38c5356c84da6dc286c565ec19db3 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 30 Nov 2022 11:42:02 +0100 Subject: dfu: Make DFU virtual backend SPL friendly Define stub for dfu_*_virt function in SPL, because CONFIG_SPL_DFU_VIRT is not defined. This patch avoids compilation issue in dfu_fill_entity() when CONFIG_SPL_DFU is activated because the dfu_fill_entity_virt() function is not available. Fixes: ec44cace4b8d2 ("dfu: add DFU virtual backend") Reported-by: Marek Vasut Signed-off-by: Patrick Delaunay Reviewed-by: Marek Vasut Tested-by: Marek Vasut --- include/dfu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/dfu.h b/include/dfu.h index dcb9cd9d79..07922224ef 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -495,7 +495,7 @@ static inline int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, } #endif -#ifdef CONFIG_DFU_VIRT +#if CONFIG_IS_ENABLED(DFU_VIRT) int dfu_fill_entity_virt(struct dfu_entity *dfu, char *devstr, char **argv, int argc); int dfu_write_medium_virt(struct dfu_entity *dfu, u64 offset, -- cgit v1.2.3 From 51a0e215ec8ce9cc88f928373e9ce8303db1829b Mon Sep 17 00:00:00 2001 From: Szymon Heidrich Date: Mon, 5 Dec 2022 10:28:23 +0100 Subject: usb: gadget: rndis: Prevent InformationBufferOffset manipulation Prevent access to arbitrary memory locations in gen_ndis_set_resp via manipulation of buf->InformationBufferOffset. Original implementation permits manipulation of InformationBufferOffset to exploit OID_GEN_CURRENT_PACKET_FILTER to set arbitrary memory contents within a 32byte offset as the devices packet filter. The packet filter value may be next retrieved using gen_ndis_query_resp so it is possible to extract specific memory regions two bytes a time. The rndis_query_response was not modified as neither the buffer offset nor length passed to gen_ndis_query_resp is used. Signed-off-by: Szymon Heidrich --- drivers/usb/gadget/rndis.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/usb/gadget/rndis.c b/drivers/usb/gadget/rndis.c index 13c327ea38..3948f2cc9a 100644 --- a/drivers/usb/gadget/rndis.c +++ b/drivers/usb/gadget/rndis.c @@ -855,14 +855,17 @@ static int rndis_set_response(int configNr, rndis_set_msg_type *buf) rndis_set_cmplt_type *resp; rndis_resp_t *r; + BufLength = get_unaligned_le32(&buf->InformationBufferLength); + BufOffset = get_unaligned_le32(&buf->InformationBufferOffset); + if ((BufOffset > RNDIS_MAX_TOTAL_SIZE - 8) || + (BufLength > RNDIS_MAX_TOTAL_SIZE - 8 - BufOffset)) + return -EINVAL; + r = rndis_add_response(configNr, sizeof(rndis_set_cmplt_type)); if (!r) return -ENOMEM; resp = (rndis_set_cmplt_type *) r->buf; - BufLength = get_unaligned_le32(&buf->InformationBufferLength); - BufOffset = get_unaligned_le32(&buf->InformationBufferOffset); - #ifdef VERBOSE debug("%s: Length: %d\n", __func__, BufLength); debug("%s: Offset: %d\n", __func__, BufOffset); -- cgit v1.2.3 From 308bd746639a7d144a9cf563ac7449312841386d Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Thu, 22 Sep 2022 15:39:37 +0200 Subject: cmd: nand: Extend nand info to print ecc information Extract the information about ecc strength and ecc step size from mtd controller. This information is usefull to check if what we think as ecc is what we really configured. Signed-off-by: Michael Trimarchi Reviewed-by: Dario Binacchi Link: https://lore.kernel.org/all/20220922133937.277463-1-michael@amarulasolutions.com Signed-off-by: Dario Binacchi --- cmd/nand.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/cmd/nand.c b/cmd/nand.c index 5bb43794e9..9a723f5757 100644 --- a/cmd/nand.c +++ b/cmd/nand.c @@ -417,12 +417,14 @@ static void nand_print_and_set_info(int idx) printf("%dx ", chip->numchips); printf("%s, sector size %u KiB\n", mtd->name, mtd->erasesize >> 10); - printf(" Page size %8d b\n", mtd->writesize); - printf(" OOB size %8d b\n", mtd->oobsize); - printf(" Erase size %8d b\n", mtd->erasesize); - printf(" subpagesize %8d b\n", chip->subpagesize); - printf(" options 0x%08x\n", chip->options); - printf(" bbt options 0x%08x\n", chip->bbt_options); + printf(" Page size %8d b\n", mtd->writesize); + printf(" OOB size %8d b\n", mtd->oobsize); + printf(" Erase size %8d b\n", mtd->erasesize); + printf(" ecc strength %8d bits\n", mtd->ecc_strength); + printf(" ecc step size %8d b\n", mtd->ecc_step_size); + printf(" subpagesize %8d b\n", chip->subpagesize); + printf(" options 0x%08x\n", chip->options); + printf(" bbt options 0x%08x\n", chip->bbt_options); /* Set geometry info */ env_set_hex("nand_writesize", mtd->writesize); -- cgit v1.2.3 From c6bafdae50f2f55fd09dd46375c918a5b96328c5 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 11 Oct 2022 14:49:59 +0300 Subject: mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h We want to get rid of so don't enforce it for new platforms. This also means GPMC_MAX CS doesn't have to be defined by platform code. Define it locally here for now. Signed-off-by: Roger Quadros Reviewed-by: Michael Trimarchi Link: https://lore.kernel.org/all/20221011115012.6181-2-rogerq@kernel.org Signed-off-by: Dario Binacchi --- drivers/mtd/nand/raw/omap_gpmc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 8b9ff4de18..7e9ccf7878 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -8,7 +8,11 @@ #include #include #include + +#ifdef CONFIG_ARCH_OMAP2PLUS #include +#endif + #include #include #include @@ -17,6 +21,10 @@ #include #include +#ifndef GPMC_MAX_CS +#define GPMC_MAX_CS 4 +#endif + #define BADBLOCK_MARKER_LENGTH 2 #define SECTOR_BYTES 512 #define ECCCLEAR (0x1 << 8) -- cgit v1.2.3 From 472229fcfc84e850b78c39f86638c194f78ab89d Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 11 Oct 2022 14:50:00 +0300 Subject: mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms The GPMC module is present on some K2 and K3 SoCs. Enable building GPMC NAND driver for K2/K3 platforms. Signed-off-by: Roger Quadros Reviewed-By: Michael Trimarchi Link: https://lore.kernel.org/all/20221011115012.6181-3-rogerq@kernel.org Signed-off-by: Dario Binacchi --- drivers/mtd/nand/raw/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index da2c5795bc..8aaba8b1a2 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -197,7 +197,7 @@ config NAND_LPC32XX_SLC config NAND_OMAP_GPMC bool "Support OMAP GPMC NAND controller" - depends on ARCH_OMAP2PLUS + depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 help Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. GPMC controller is used for parallel NAND flash devices, and can -- cgit v1.2.3 From 7e4a494c5f676c7a16a28ac36b9fdbd84022a400 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 11 Oct 2022 14:50:01 +0300 Subject: mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms Pointer size cannot be assumed to be 32-bit, so use use uintptr_t instead of uint32_t. Fixes the below build warning on 64-bit builds. drivers/mtd/nand/raw/omap_gpmc.c:439:10: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] head = ((uint32_t) buf) % 4; Signed-off-by: Roger Quadros Reviewed-by: Michael Trimarchi Link: https://lore.kernel.org/all/20221011115012.6181-4-rogerq@kernel.org Signed-off-by: Dario Binacchi --- drivers/mtd/nand/raw/omap_gpmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 7e9ccf7878..d62c3e6fce 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -438,14 +438,14 @@ static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len) static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) { int ret; - uint32_t head, tail; + uintptr_t head, tail; struct nand_chip *chip = mtd_to_nand(mtd); /* * If the destination buffer is unaligned, start with reading * the overlap byte-wise. */ - head = ((uint32_t) buf) % 4; + head = ((uintptr_t)buf) % 4; if (head) { omap_nand_read(mtd, buf, head); buf += head; -- cgit v1.2.3 From cd72a950e0aaba0ea7e9cb1d03ff2f1ca0ca037a Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 11 Oct 2022 14:50:02 +0300 Subject: mtd: rawnand: omap_gpmc: Optimize NAND reads Rename omap_nand_read() to omap_nand_read_buf() to reflect actual behaviour. Use FIFO read address instead of raw read address for reads. The GPMC automatically converts 32-bit/16-bit reads to NAND device specific reads (8/16 bit). Use the largest possible read granularity size for more efficient reads. Signed-off-by: Roger Quadros Reviewed-by: Michael Trimarchi Link: https://lore.kernel.org/all/20221011115012.6181-5-rogerq@kernel.org Signed-off-by: Dario Binacchi --- drivers/mtd/nand/raw/omap_gpmc.c | 49 +++++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index d62c3e6fce..b36fe762b3 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -55,6 +55,7 @@ struct omap_nand_info { enum omap_ecc ecc_scheme; uint8_t cs; uint8_t ws; /* wait status pin (0,1) */ + void __iomem *fifo; }; /* We are wasting a bit of memory but al least we are safe */ @@ -350,6 +351,20 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, return 0; } +static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct omap_nand_info *info = nand_get_controller_data(chip); + u32 alignment = ((uintptr_t)buf | len) & 3; + + if (alignment & 1) + readsb(info->fifo, buf, len); + else if (alignment & 3) + readsw(info->fifo, buf, len >> 1); + else + readsl(info->fifo, buf, len >> 2); +} + #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH #define PREFETCH_CONFIG1_CS_SHIFT 24 @@ -415,7 +430,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le cnt = PREFETCH_STATUS_FIFO_CNT(cnt); for (i = 0; i < cnt / 4; i++) { - *buf++ = readl(CONFIG_SYS_NAND_BASE); + *buf++ = readl(info->fifo); len -= 4; } } while (len); @@ -425,16 +440,6 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le return 0; } -static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - - if (chip->options & NAND_BUSWIDTH_16) - nand_read_buf16(mtd, buf, len); - else - nand_read_buf(mtd, buf, len); -} - static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) { int ret; @@ -447,7 +452,7 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) */ head = ((uintptr_t)buf) % 4; if (head) { - omap_nand_read(mtd, buf, head); + omap_nand_read_buf(mtd, buf, head); buf += head; len -= head; } @@ -461,10 +466,10 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) ret = __read_prefetch_aligned(chip, (uint32_t *)buf, len - tail); if (ret < 0) { /* fallback in case the prefetch engine is busy */ - omap_nand_read(mtd, buf, len); + omap_nand_read_buf(mtd, buf, len); } else if (tail) { buf += len - tail; - omap_nand_read(mtd, buf, tail); + omap_nand_read_buf(mtd, buf, tail); } } #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */ @@ -1001,6 +1006,8 @@ int board_nand_init(struct nand_chip *nand) int32_t gpmc_config = 0; int cs = cs_next++; int err = 0; + struct omap_nand_info *info; + /* * xloader/Uboot's gpmc configuration would have configured GPMC for * nand type of memory. The following logic scans and latches on to the @@ -1029,9 +1036,12 @@ int board_nand_init(struct nand_chip *nand) nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; - omap_nand_info[cs].control = NULL; - omap_nand_info[cs].cs = cs; - omap_nand_info[cs].ws = wscfg[cs]; + + info = &omap_nand_info[cs]; + info->control = NULL; + info->cs = cs; + info->ws = wscfg[cs]; + info->fifo = (void __iomem *)CONFIG_SYS_NAND_BASE; nand_set_controller_data(nand, &omap_nand_info[cs]); nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; @@ -1062,10 +1072,7 @@ int board_nand_init(struct nand_chip *nand) #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH nand->read_buf = omap_nand_read_prefetch; #else - if (nand->options & NAND_BUSWIDTH_16) - nand->read_buf = nand_read_buf16; - else - nand->read_buf = nand_read_buf; + nand->read_buf = omap_nand_read_buf; #endif nand->dev_ready = omap_dev_ready; -- cgit v1.2.3 From 664d5369269f80d0883ede4573425e3546c87080 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 11 Oct 2022 14:50:05 +0300 Subject: mtd: rawnand: nand_spl_loaders: Fix cast type build warning Fixes the below build warning on 64-bit platforms. drivers/mtd/nand/raw/nand_spl_loaders.c:26:21: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] dst = (void *)((int)dst - page_offset); Signed-off-by: Roger Quadros Reviewed-by: Michael Trimarchi Link: https://lore.kernel.org/all/20221011115012.6181-8-rogerq@kernel.org Signed-off-by: Dario Binacchi --- drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/nand_spl_loaders.c b/drivers/mtd/nand/raw/nand_spl_loaders.c index 4befc75c04..156b44d835 100644 --- a/drivers/mtd/nand/raw/nand_spl_loaders.c +++ b/drivers/mtd/nand/raw/nand_spl_loaders.c @@ -23,7 +23,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) if (unlikely(page_offset)) { memmove(dst, dst + page_offset, CONFIG_SYS_NAND_PAGE_SIZE); - dst = (void *)((int)dst - page_offset); + dst = (void *)(dst - page_offset); page_offset = 0; } dst += CONFIG_SYS_NAND_PAGE_SIZE; -- cgit v1.2.3 From ec2c9240d508e67eca3d633ecb7f4740e2673a6a Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 11 Oct 2022 14:50:06 +0300 Subject: mtd: rawnand: omap_gpmc: Reduce .bss usage Allocate omap_ecclayout on the heap as we have limited .bss space on AM64 R5 SPL configuration. Reduces .bss usage by 2984 bytes. Signed-off-by: Roger Quadros Reviewed-By: Michael Trimarchi Link: https://lore.kernel.org/all/20221011115012.6181-9-rogerq@kernel.org Signed-off-by: Dario Binacchi --- drivers/mtd/nand/raw/omap_gpmc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index b36fe762b3..69fc09be09 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -37,7 +37,6 @@ static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2, 0x97, 0x79, 0xe5, 0x24, 0xb5}; #endif static uint8_t cs_next; -static __maybe_unused struct nand_ecclayout omap_ecclayout; #if defined(CONFIG_NAND_OMAP_GPMC_WSCFG) static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] = @@ -753,7 +752,7 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd) static int omap_select_ecc_scheme(struct nand_chip *nand, enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) { struct omap_nand_info *info = nand_get_controller_data(nand); - struct nand_ecclayout *ecclayout = &omap_ecclayout; + struct nand_ecclayout *ecclayout = nand->ecc.layout; int eccsteps = pagesize / SECTOR_BYTES; int i; @@ -1046,7 +1045,9 @@ int board_nand_init(struct nand_chip *nand) nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; nand->chip_delay = 100; - nand->ecc.layout = &omap_ecclayout; + nand->ecc.layout = kzalloc(sizeof(*nand->ecc.layout), GFP_KERNEL); + if (!nand->ecc.layout) + return -ENOMEM; /* configure driver and controller based on NAND device bus-width */ gpmc_config = readl(&gpmc_cfg->cs[cs].config1); -- cgit v1.2.3 From c21b0ca525bd818428a62dd267697071822cc9a9 Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Fri, 21 Oct 2022 08:05:36 +0200 Subject: mtd: nand: make Samsung SLC NAND usable again MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream linux commit 69fc01296c9281 commit a1286a1fc416 ("mtd: nand: Move Samsung specific init/detection logic in nand_samsung.c") introduced a regression for Samsung SLC NAND chips. Prior to this commit chip->bits_per_cell was initialized by calling nand_get_bits_per_cell() before using nand_is_slc(). With the offending commit this call is skipped, leaving chip->bits_per_cell cleared to zero when the manufacturer specific '.detect' function calls nand_is_slc() which in turn interprets bits_per_cell != 1 as indication for an MLC chip. The effect is that e.g. a K9F1G08U0F NAND chip is falsely detected as MLC NAND with 4KiB page size rather than SLC with 2KiB page size. Add a call to nand_get_bits_per_cell() before calling the .detect hook function in nand_manufacturer_detect(), so that the nand_is_slc() calls in the manufacturer specific code will return correct results. Reported-by: Marcin Gołaś Signed-off-by: Michael Trimarchi Reviewed-by: Dario Binacchi Link: https://lore.kernel.org/all/20221021060536.11747-1-michael@amarulasolutions.com Signed-off-by: Dario Binacchi --- drivers/mtd/nand/raw/nand_base.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 215b9ba84f..bc61ad03eb 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4171,10 +4171,13 @@ static void nand_manufacturer_detect(struct nand_chip *chip) * nand_decode_ext_id() otherwise. */ if (chip->manufacturer.desc && chip->manufacturer.desc->ops && - chip->manufacturer.desc->ops->detect) + chip->manufacturer.desc->ops->detect) { + /* The 3rd id byte holds MLC / multichip data */ + chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); chip->manufacturer.desc->ops->detect(chip); - else + } else { nand_decode_ext_id(chip); + } } /* -- cgit v1.2.3 From d09807ad144cb2fe3745a58caadf9a4192038839 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Sun, 30 Oct 2022 15:14:13 +0100 Subject: cmd: mtd: check if a block has to be skipped or erased As reported by patch [1], the `mtd erase' command should not erase bad blocks. To force bad block erasing you have to use the `mtd erase.dontskipbad' command. This patch tries to fix the same issue without modifying code taken from the linux kernel, in order to make further upgrades easier. [1] https://lore.kernel.org/all/20221006031501.110290-2-mikhail.kshevetskiy@iopsys.eu/ Suggested-by: Michael Trimarchi Co-developed-by: Michael Trimarchi Signed-off-by: Michael Trimarchi Co-developed-by: Mikhail Kshevetskiy Signed-off-by: Mikhail Kshevetskiy Tested-by: Mikhail Kshevetskiy Signed-off-by: Dario Binacchi --- cmd/mtd.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/cmd/mtd.c b/cmd/mtd.c index ad5cc9827d..eb6e2d6892 100644 --- a/cmd/mtd.c +++ b/cmd/mtd.c @@ -434,19 +434,31 @@ static int do_mtd_erase(struct cmd_tbl *cmdtp, int flag, int argc, erase_op.mtd = mtd; erase_op.addr = off; erase_op.len = mtd->erasesize; - erase_op.scrub = scrub; while (len) { - ret = mtd_erase(mtd, &erase_op); + if (!scrub) { + ret = mtd_block_isbad(mtd, erase_op.addr); + if (ret < 0) { + printf("Failed to get bad block at 0x%08llx\n", + erase_op.addr); + ret = CMD_RET_FAILURE; + goto out_put_mtd; + } - if (ret) { - /* Abort if its not a bad block error */ - if (ret != -EIO) - break; - printf("Skipping bad block at 0x%08llx\n", - erase_op.addr); + if (ret > 0) { + printf("Skipping bad block at 0x%08llx\n", + erase_op.addr); + ret = 0; + len -= mtd->erasesize; + erase_op.addr += mtd->erasesize; + continue; + } } + ret = mtd_erase(mtd, &erase_op); + if (ret && ret != -EIO) + break; + len -= mtd->erasesize; erase_op.addr += mtd->erasesize; } -- cgit v1.2.3 From 670789f5ba2f3330b137f637deb47671b8720c33 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Tue, 8 Nov 2022 10:07:19 +0100 Subject: mtd: nand: drop EXPORT_SYMBOL_GPL for nanddev_erase() This function is only used within this module, so it is no longer necessary to use EXPORT_SYMBOL_GPL(). This patch parallels the work done in the following patch: https://lore.kernel.org/linux-mtd/20221018170205.1733958-1-dario.binacchi@amarulasolutions.com Signed-off-by: Dario Binacchi Reviewed-By: Michael Trimarchi Link: https://lore.kernel.org/all/20221108090719.3631621-1-dario.binacchi@amarulasolutions.com --- drivers/mtd/nand/core.c | 3 +-- include/linux/mtd/nand.h | 1 - 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c index 99c29670c7..4b9dd6a926 100644 --- a/drivers/mtd/nand/core.c +++ b/drivers/mtd/nand/core.c @@ -129,7 +129,7 @@ EXPORT_SYMBOL_GPL(nanddev_isreserved); * * Return: 0 in case of success, a negative error code otherwise. */ -int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos) +static int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos) { unsigned int entry; @@ -147,7 +147,6 @@ int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos) return nand->ops->erase(nand, pos); } -EXPORT_SYMBOL_GPL(nanddev_erase); /** * nanddev_mtd_erase() - Generic mtd->_erase() implementation for NAND devices diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 7774c17ad5..aeb38dec2e 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -691,7 +691,6 @@ static inline bool nanddev_io_iter_end(struct nand_device *nand, bool nanddev_isbad(struct nand_device *nand, const struct nand_pos *pos); bool nanddev_isreserved(struct nand_device *nand, const struct nand_pos *pos); -int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos); int nanddev_markbad(struct nand_device *nand, const struct nand_pos *pos); /* BBT related functions */ -- cgit v1.2.3 From 17c2ccde22c7374df452db057b185b4c9f9b6bd0 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Sun, 20 Nov 2022 10:57:04 +0100 Subject: mtd: nand: mxs_nand_spl: don't read useless pages The patch prevents pages beyond the last from being unnecessarily read. This occurs when the last page to be read is not the last page of the last block. Before this change we would have read all the pages up to the end of the last block. Suggested-by: Michael Trimarchi Co-developed-by: Michael Trimarchi Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi Acked-by: Michael Trimarchi Link: https://lore.kernel.org/all/20221120095705.3019295-1-dario.binacchi@amarulasolutions.com --- drivers/mtd/nand/raw/mxs_nand_spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index ef03b7789d..300662994c 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -257,7 +257,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) while (block <= lastblock && size > 0) { if (!is_badblock(mtd, mtd->erasesize * block, 1)) { /* Skip bad blocks */ - while (page < nand_page_per_block) { + while (page < nand_page_per_block && size) { int curr_page = nand_page_per_block * block + page; if (mxs_read_page_ecc(mtd, page_buf, curr_page) < 0) { -- cgit v1.2.3 From fda2253d121f05921e419edffe615c607917792a Mon Sep 17 00:00:00 2001 From: Dai Okamura Date: Fri, 9 Dec 2022 20:40:21 +0900 Subject: spl: spl_legacy: fix invalid offset in SPL_COPY_PAYLOAD_ONLY This fixes the header offset calculation. This issue was found on uniphier v7 SoCs with SPL. Fixes: 06377c5a1f ("spl: spl_legacy: Fix NAND boot on OMAP3 BeagleBoard") Signed-off-by: Dai Okamura Reviewed-By: Michael Trimarchi Acked-by: Michael Trimarchi Link: https://lore.kernel.org/all/20221209114021.3074978-1-okamura.dai@socionext.com Signed-off-by: Dario Binacchi --- common/spl/spl_legacy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c index 4c7f44687e..16851c55eb 100644 --- a/common/spl/spl_legacy.c +++ b/common/spl/spl_legacy.c @@ -106,7 +106,7 @@ int spl_load_legacy_img(struct spl_image_info *spl_image, * is set */ if (spl_image->flags & SPL_COPY_PAYLOAD_ONLY) - dataptr += sizeof(hdr); + dataptr += sizeof(*hdr); load->read(load, dataptr, spl_image->size, (void *)(unsigned long)spl_image->load_addr); @@ -116,7 +116,7 @@ int spl_load_legacy_img(struct spl_image_info *spl_image, lzma_len = LZMA_LEN; /* dataptr points to compressed payload */ - dataptr = offset + sizeof(hdr); + dataptr = offset + sizeof(*hdr); debug("LZMA: Decompressing %08lx to %08lx\n", dataptr, spl_image->load_addr); -- cgit v1.2.3 From 3a68fda33fe5b53be7e15099de856acb1f41097e Mon Sep 17 00:00:00 2001 From: Derek LaHousse Date: Mon, 12 Dec 2022 07:34:17 +0100 Subject: arm: mvebu: Espressobin: Fix default env variables MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Default env variables on Espressobin boards are broken since commit c4df0f6f315c ("arm: mvebu: Espressobin: Set default value for $fdtfile env variable") as well as the 'env default -a' command. The algorithm to find free space in the default_environment[] array returns after the first env variable instead of the correct position of the last variable, where there is allocated free space. This causes that U-Boot board_late_init() function to overwrite a portion of the default environment with $ethXaddr and $fdtfile variables immediately after the first env variable and so it is overwriting other variables. This patch also adds an additional null byte to terminate the environment array. But U-Boot board_late_init() function do not fill this nul byte explicitly. And because of that, U-Boot is later trying to interpret remaining buffer as a continuation of variable list. Normally buffer should be empty but due to the above issue, it contains garbage from remaining env variables. For example 'env default -a' command results in damaging variable names. It was observed that scritaddr variable name was changed to criptaddr (without leading 's'). This bug was reported and discussed on the Armbian forum: https://forum.armbian.com/topic/19564-making-espressobin-v7-work-in-2022/?do=findComment&comment=138136 Fix these issues in two steps: 1) Change code which finds free space for dynamic env variables in default_environment[] array by jumping to the end of the variable list instead of jumping after the first defined variable. [By Derek] 2) Add code which appends terminating nul byte as indication of the end of the env list, after the last nul term env string. [By Pali] Fixes: c4df0f6f315c ("arm: mvebu: Espressobin: Set default value for $fdtfile env variable") Signed-off-by: Derek LaHousse Signed-off-by: Pali Rohár Signed-off-by: Stefan Roese --- board/Marvell/mvebu_armada-37xx/board.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index c6ecc323bb..44c72344e8 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -99,9 +99,16 @@ int board_late_init(void) if (!of_machine_is_compatible("globalscale,espressobin")) return 0; - /* Find free buffer in default_environment[] for new variables */ - while (*ptr != '\0' && *(ptr+1) != '\0') ptr++; - ptr += 2; + /* + * Find free space for new variables in default_environment[] array. + * Free space is after the last variable, each variable is termined + * by nul byte and after the last variable is additional nul byte. + * Move ptr to the position where new variable can be filled. + */ + while (*ptr != '\0') { + do { ptr++; } while (*ptr != '\0'); + ptr++; + } /* * Ensure that 'env default -a' does not erase permanent MAC addresses @@ -145,6 +152,13 @@ int board_late_init(void) strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-emmc.dtb"); else strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin.dtb"); + ptr += strlen(ptr) + 1; + + /* + * After the last variable (which is nul term string) append another nul + * byte which terminates the list. So everything after ptr is ignored. + */ + *ptr = '\0'; return 0; } -- cgit v1.2.3 From 91dae6d0a19e4d19715243487f0d0f8ca5b0c443 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 20 Sep 2022 13:39:56 +0200 Subject: phy: usbphyc: use regulator_set_enable_if_allowed for disabling vbus supply Use regulator_set_enable_if_allowed() api instead of regulator_set_enable() while disabling vbus supply. This way the driver doesn't see an error when it disable an always-on regulator for VBUS. This patch is needed for STM32MP157C-DK2 board when the regulator v3v3: buck4 used as the phy vbus supply in kernel device tree is always on with the next hack for low power use-case: &usbphyc_port0 { ... /* * Hack to keep hub active until all connected devices are suspended * otherwise the hub will be powered off as soon as the v3v3 is disabled * and it can disturb connected devices. */ connector { compatible = "usb-a-connector"; vbus-supply = <&v3v3>; }; }; Without this patch and the previous update in DT the command "usb stop" failed and the next command "usb start" cause a crash. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Reviewed-by: Marek Vasut --- drivers/phy/phy-stm32-usbphyc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c index 9f0b7d7118..dcf2194e9a 100644 --- a/drivers/phy/phy-stm32-usbphyc.c +++ b/drivers/phy/phy-stm32-usbphyc.c @@ -375,7 +375,7 @@ static int stm32_usbphyc_phy_power_off(struct phy *phy) return 0; if (usbphyc_phy->vbus) { - ret = regulator_set_enable(usbphyc_phy->vbus, false); + ret = regulator_set_enable_if_allowed(usbphyc_phy->vbus, false); if (ret) return ret; } -- cgit v1.2.3 From 30257f4699e0e58818f6e6f86021a994f485ee58 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 26 Oct 2022 15:05:10 +0200 Subject: dm: pmic: ignore disabled node in pmic_bind_children Ignore the disabled children node in pmic_bind_children() so the disabled regulators in device tree are not registered. This patch is based on the dm_scan_fdt_node() code - only the activated nodes are bound - and it solves possible issue when a deactivated regulator is bound, error for duplicated regulator name for example. Signed-off-by: Patrick Delaunay Reviewed-by: Simon Glass --- drivers/power/pmic/pmic-uclass.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/power/pmic/pmic-uclass.c b/drivers/power/pmic/pmic-uclass.c index 5dcf6d8079..0e2f5e1f41 100644 --- a/drivers/power/pmic/pmic-uclass.c +++ b/drivers/power/pmic/pmic-uclass.c @@ -39,6 +39,10 @@ int pmic_bind_children(struct udevice *pmic, ofnode parent, node_name = ofnode_get_name(node); debug("* Found child node: '%s'\n", node_name); + if (!ofnode_is_enabled(node)) { + debug(" - ignoring disabled device\n"); + continue; + } child = NULL; for (info = child_info; info->prefix && info->driver; info++) { -- cgit v1.2.3 From ed6251187afabf811a5fd49a44ebd61c53c7b378 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 13 Dec 2022 09:26:25 -0500 Subject: Revert "cmd: pxe_utils: Check fdtcontroladdr in label_boot" With the change here, all extlinux.conf files with only "KERNEL /fitImage" don't work anymore. One common example of this would be those files generated by thee Poky/OE WIC bootimg-partition bootloader partition generator. This reverts commit d5ba6188dfbf6bb68354bec86e483623f1f6dae2. Reported-by: Neil Armstrong Reported-by: Quentin Schulz Signed-off-by: Tom Rini --- boot/pxe_utils.c | 8 +------- drivers/net/tsec.c | 2 +- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c index 8133006875..96528aa14c 100644 --- a/boot/pxe_utils.c +++ b/boot/pxe_utils.c @@ -616,10 +616,7 @@ static int label_boot(struct pxe_context *ctx, struct pxe_label *label) * Scenario 2: If there is an fdt_addr specified, pass it along to * bootm, and adjust argc appropriately. * - * Scenario 3: If there is an fdtcontroladdr specified, pass it along to - * bootm, and adjust argc appropriately. - * - * Scenario 4: fdt blob is not available. + * Scenario 3: fdt blob is not available. */ bootm_argv[3] = env_get("fdt_addr_r"); @@ -724,9 +721,6 @@ static int label_boot(struct pxe_context *ctx, struct pxe_label *label) if (!bootm_argv[3]) bootm_argv[3] = env_get("fdt_addr"); - if (!bootm_argv[3]) - bootm_argv[3] = env_get("fdtcontroladdr"); - if (bootm_argv[3]) { if (!bootm_argv[2]) bootm_argv[2] = "-"; diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index d69a9ff477..519ea14b07 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -156,7 +156,7 @@ static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join) return 0; } -static int __maybe_unused tsec_set_promisc(struct udevice *dev, bool enable) +static int tsec_set_promisc(struct udevice *dev, bool enable) { struct tsec_private *priv = dev_get_priv(dev); struct tsec __iomem *regs = priv->regs; -- cgit v1.2.3 From b072aefbbe1cbbeab92c8153c07127051905d292 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Sat, 19 Nov 2022 16:10:59 +0000 Subject: sunxi: define SYS_MONITOR_LEN in Kconfig, not _defconfig Commit 08574ed339fb ("Convert CONFIG_SYS_MONITOR_LEN to Kconfig") moved the definition of said config variable from the common sunxi header to *every board's* defconfig. This is a platform choice, not board specific, so remove the variable from there, instead set the one value for all Allwinner boards in Kconfig. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec --- Kconfig | 1 + configs/A10-OLinuXino-Lime_defconfig | 1 - configs/A10s-OLinuXino-M_defconfig | 1 - configs/A13-OLinuXinoM_defconfig | 1 - configs/A13-OLinuXino_defconfig | 1 - configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 - configs/A20-OLinuXino-Lime2_defconfig | 1 - configs/A20-OLinuXino-Lime_defconfig | 1 - configs/A20-OLinuXino_MICRO-eMMC_defconfig | 1 - configs/A20-OLinuXino_MICRO_defconfig | 1 - configs/A20-Olimex-SOM-EVB_defconfig | 1 - configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 - configs/A20-Olimex-SOM204-EVB_defconfig | 1 - configs/A33-OLinuXino_defconfig | 1 - configs/Ainol_AW1_defconfig | 1 - configs/Ampe_A76_defconfig | 1 - configs/Auxtek-T003_defconfig | 1 - configs/Auxtek-T004_defconfig | 1 - configs/Bananapi_M2_Ultra_defconfig | 1 - configs/Bananapi_defconfig | 1 - configs/Bananapi_m2m_defconfig | 1 - configs/Bananapro_defconfig | 1 - configs/CHIP_defconfig | 1 - configs/CHIP_pro_defconfig | 1 - configs/CSQ_CS908_defconfig | 1 - configs/Chuwi_V7_CW0825_defconfig | 1 - configs/Colombus_defconfig | 1 - configs/Cubieboard2_defconfig | 1 - configs/Cubieboard4_defconfig | 1 - configs/Cubieboard_defconfig | 1 - configs/Cubietruck_defconfig | 1 - configs/Cubietruck_plus_defconfig | 1 - configs/Empire_electronix_d709_defconfig | 1 - configs/Empire_electronix_m712_defconfig | 1 - configs/Hummingbird_A31_defconfig | 1 - configs/Hyundai_A7HD_defconfig | 1 - configs/Itead_Ibox_A20_defconfig | 1 - configs/Lamobo_R1_defconfig | 1 - configs/LicheePi_Zero_defconfig | 1 - configs/Linksprite_pcDuino3_Nano_defconfig | 1 - configs/Linksprite_pcDuino3_defconfig | 1 - configs/Linksprite_pcDuino_defconfig | 1 - configs/MK808C_defconfig | 1 - configs/MSI_Primo73_defconfig | 1 - configs/MSI_Primo81_defconfig | 1 - configs/Marsboard_A10_defconfig | 1 - configs/Mele_A1000G_quad_defconfig | 1 - configs/Mele_A1000_defconfig | 1 - configs/Mele_I7_defconfig | 1 - configs/Mele_M3_defconfig | 1 - configs/Mele_M5_defconfig | 1 - configs/Mele_M9_defconfig | 1 - configs/Merrii_A80_Optimus_defconfig | 1 - configs/Mini-X_defconfig | 1 - configs/Nintendo_NES_Classic_Edition_defconfig | 1 - configs/Orangepi_defconfig | 1 - configs/Orangepi_mini_defconfig | 1 - configs/Sinlinx_SinA31s_defconfig | 1 - configs/Sinlinx_SinA33_defconfig | 1 - configs/Sinovoip_BPI_M2_defconfig | 1 - configs/Sinovoip_BPI_M3_defconfig | 1 - configs/Sunchip_CX-A99_defconfig | 1 - configs/UTOO_P66_defconfig | 1 - configs/Wexler_TAB7200_defconfig | 1 - configs/Wits_Pro_A20_DKT_defconfig | 1 - configs/Wobo_i5_defconfig | 1 - configs/Yones_Toptech_BD1078_defconfig | 1 - configs/Yones_Toptech_BS1078_V2_defconfig | 1 - configs/a64-olinuxino-emmc_defconfig | 1 - configs/a64-olinuxino_defconfig | 1 - configs/amarula_a64_relic_defconfig | 1 - configs/ba10_tv_box_defconfig | 1 - configs/bananapi_m1_plus_defconfig | 1 - configs/bananapi_m2_berry_defconfig | 1 - configs/bananapi_m2_plus_h3_defconfig | 1 - configs/bananapi_m2_plus_h5_defconfig | 1 - configs/bananapi_m2_zero_defconfig | 1 - configs/bananapi_m64_defconfig | 1 - configs/beelink_gs1_defconfig | 1 - configs/beelink_x2_defconfig | 1 - configs/colorfly_e708_q1_defconfig | 1 - configs/difrnce_dit4350_defconfig | 1 - configs/dserve_dsrv9703c_defconfig | 1 - configs/emlid_neutis_n5_devboard_defconfig | 1 - configs/ga10h_v1_1_defconfig | 1 - configs/gt90h_v4_defconfig | 1 - configs/h8_homlet_v2_defconfig | 1 - configs/i12-tvbox_defconfig | 1 - configs/iNet_3F_defconfig | 1 - configs/iNet_3W_defconfig | 1 - configs/iNet_86VS_defconfig | 1 - configs/iNet_D978_rev2_defconfig | 1 - configs/icnova-a20-swac_defconfig | 1 - configs/inet1_defconfig | 1 - configs/inet86dz_defconfig | 1 - configs/inet97fv2_defconfig | 1 - configs/inet98v_rev2_defconfig | 1 - configs/inet9f_rev03_defconfig | 1 - configs/inet_q972_defconfig | 1 - configs/jesurun_q5_defconfig | 1 - configs/libretech_all_h3_cc_h2_plus_defconfig | 1 - configs/libretech_all_h3_cc_h3_defconfig | 1 - configs/libretech_all_h3_cc_h5_defconfig | 1 - configs/libretech_all_h3_it_h5_defconfig | 1 - configs/libretech_all_h5_cc_h5_defconfig | 1 - configs/licheepi_nano_defconfig | 1 - configs/mixtile_loftq_defconfig | 1 - configs/mk802_a10s_defconfig | 1 - configs/mk802_defconfig | 1 - configs/mk802ii_defconfig | 1 - configs/nanopi_a64_defconfig | 1 - configs/nanopi_m1_defconfig | 1 - configs/nanopi_m1_plus_defconfig | 1 - configs/nanopi_neo2_defconfig | 1 - configs/nanopi_neo_air_defconfig | 1 - configs/nanopi_neo_defconfig | 1 - configs/nanopi_neo_plus2_defconfig | 1 - configs/nanopi_r1s_h5_defconfig | 1 - configs/oceanic_5205_5inmfd_defconfig | 1 - configs/orangepi_2_defconfig | 1 - configs/orangepi_3_defconfig | 1 - configs/orangepi_lite2_defconfig | 1 - configs/orangepi_lite_defconfig | 1 - configs/orangepi_one_defconfig | 1 - configs/orangepi_one_plus_defconfig | 1 - configs/orangepi_pc2_defconfig | 1 - configs/orangepi_pc_defconfig | 1 - configs/orangepi_pc_plus_defconfig | 1 - configs/orangepi_plus2e_defconfig | 1 - configs/orangepi_plus_defconfig | 1 - configs/orangepi_prime_defconfig | 1 - configs/orangepi_r1_defconfig | 1 - configs/orangepi_win_defconfig | 1 - configs/orangepi_zero2_defconfig | 1 - configs/orangepi_zero_defconfig | 1 - configs/orangepi_zero_plus2_defconfig | 1 - configs/orangepi_zero_plus2_h3_defconfig | 1 - configs/orangepi_zero_plus_defconfig | 1 - configs/parrot_r16_defconfig | 1 - configs/pine64-lts_defconfig | 1 - configs/pine64_plus_defconfig | 1 - configs/pine_h64_defconfig | 1 - configs/pinebook_defconfig | 1 - configs/pinecube_defconfig | 1 - configs/pinephone_defconfig | 1 - configs/pinetab_defconfig | 1 - configs/polaroid_mid2407pxe03_defconfig | 1 - configs/polaroid_mid2809pxe04_defconfig | 1 - configs/pov_protab2_ips9_defconfig | 1 - configs/q8_a13_tablet_defconfig | 1 - configs/q8_a23_tablet_800x480_defconfig | 1 - configs/q8_a33_tablet_1024x600_defconfig | 1 - configs/q8_a33_tablet_800x480_defconfig | 1 - configs/r7-tv-dongle_defconfig | 1 - configs/sopine_baseboard_defconfig | 1 - configs/sun8i_a23_evb_defconfig | 1 - configs/sunxi_Gemei_G9_defconfig | 1 - configs/tanix_tx6_defconfig | 1 - configs/tbs_a711_defconfig | 1 - configs/teres_i_defconfig | 1 - configs/x96_mate_defconfig | 1 - configs/zeropi_defconfig | 1 - 162 files changed, 1 insertion(+), 161 deletions(-) diff --git a/Kconfig b/Kconfig index 67f46467b1..0cdc9658f7 100644 --- a/Kconfig +++ b/Kconfig @@ -586,6 +586,7 @@ config SYS_SRAM_SIZE config SYS_MONITOR_LEN int "Maximum size in bytes reserved for U-Boot in memory" default 1048576 if X86 + default 786432 if ARCH_SUNXI default 0 help Size of memory reserved for monitor code, used to determine diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig index ee92ac45fb..6727932f7f 100644 --- a/configs/A10-OLinuXino-Lime_defconfig +++ b/configs/A10-OLinuXino-Lime_defconfig @@ -11,7 +11,6 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig index 2ac68039b0..99f5785751 100644 --- a/configs/A10s-OLinuXino-M_defconfig +++ b/configs/A10s-OLinuXino-M_defconfig @@ -9,7 +9,6 @@ CONFIG_MMC1_CD_PIN="PG13" CONFIG_MMC_SUNXI_SLOT_EXTRA=1 CONFIG_USB1_VBUS_PIN="PB10" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig index 8f390cb83f..f9d17b1950 100644 --- a/configs/A13-OLinuXinoM_defconfig +++ b/configs/A13-OLinuXinoM_defconfig @@ -13,7 +13,6 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y CONFIG_VIDEO_LCD_POWER="PB10" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig index ec11da5f06..8c9043559b 100644 --- a/configs/A13-OLinuXino_defconfig +++ b/configs/A13-OLinuXino_defconfig @@ -15,7 +15,6 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig index 8ce10d6f75..bccadcc7b4 100644 --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig @@ -13,7 +13,6 @@ CONFIG_SATAPWR="PC3" CONFIG_SPL_SPI_SUNXI=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index e38110b030..0a9de5ee67 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -11,7 +11,6 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig index 4e4804748e..38daf33b95 100644 --- a/configs/A20-OLinuXino-Lime_defconfig +++ b/configs/A20-OLinuXino-Lime_defconfig @@ -9,7 +9,6 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig index 113d54dc0b..d73e64c460 100644 --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig @@ -11,7 +11,6 @@ CONFIG_VIDEO_VGA=y CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig index 1e1c30ef30..8a6bb885e9 100644 --- a/configs/A20-OLinuXino_MICRO_defconfig +++ b/configs/A20-OLinuXino_MICRO_defconfig @@ -12,7 +12,6 @@ CONFIG_VIDEO_VGA=y CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig index e76e6dd093..5de6c2d9a9 100644 --- a/configs/A20-Olimex-SOM-EVB_defconfig +++ b/configs/A20-Olimex-SOM-EVB_defconfig @@ -12,7 +12,6 @@ CONFIG_USB0_VBUS_DET="PH5" CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig index 1d3cf31195..6e9bdc27d9 100644 --- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig @@ -13,7 +13,6 @@ CONFIG_SATAPWR="PC3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig index 97d0b9cee7..e0517459ee 100644 --- a/configs/A20-Olimex-SOM204-EVB_defconfig +++ b/configs/A20-Olimex-SOM204-EVB_defconfig @@ -12,7 +12,6 @@ CONFIG_SATAPWR="PC3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/A33-OLinuXino_defconfig b/configs/A33-OLinuXino_defconfig index 49c9250092..351a454339 100644 --- a/configs/A33-OLinuXino_defconfig +++ b/configs/A33-OLinuXino_defconfig @@ -16,6 +16,5 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PB2" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DCDC1_VOLT=3300 CONFIG_USB_MUSB_HOST=y diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig index 4f01188fcf..9a18af8c6e 100644 --- a/configs/Ainol_AW1_defconfig +++ b/configs/Ainol_AW1_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig index d5cf1f42e5..7bf3dfcd8a 100644 --- a/configs/Ampe_A76_defconfig +++ b/configs/Ampe_A76_defconfig @@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig index 2b9d3a88ab..7d81f12f76 100644 --- a/configs/Auxtek-T003_defconfig +++ b/configs/Auxtek-T003_defconfig @@ -8,7 +8,6 @@ CONFIG_DRAM_EMR1=0 CONFIG_USB1_VBUS_PIN="PB10" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig index f3e6944b14..4c7154b04c 100644 --- a/configs/Auxtek-T004_defconfig +++ b/configs/Auxtek-T004_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig index 0bd163afdd..18ee81b637 100644 --- a/configs/Bananapi_M2_Ultra_defconfig +++ b/configs/Bananapi_M2_Ultra_defconfig @@ -12,7 +12,6 @@ CONFIG_USB2_VBUS_PIN="PH23" # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig index 2814d77c18..6c2a1f630e 100644 --- a/configs/Bananapi_defconfig +++ b/configs/Bananapi_defconfig @@ -9,7 +9,6 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y diff --git a/configs/Bananapi_m2m_defconfig b/configs/Bananapi_m2m_defconfig index 0e73265abb..bad38a6656 100644 --- a/configs/Bananapi_m2m_defconfig +++ b/configs/Bananapi_m2m_defconfig @@ -10,7 +10,6 @@ CONFIG_MMC0_CD_PIN="PB4" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB0_ID_DET="PH8" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig index 11375991c8..94fd74754e 100644 --- a/configs/Bananapro_defconfig +++ b/configs/Bananapro_defconfig @@ -11,7 +11,6 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig index 03b2e03963..cd9bdbfd36 100644 --- a/configs/CHIP_defconfig +++ b/configs/CHIP_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y CONFIG_USB0_VBUS_PIN="PB10" CONFIG_VIDEO_COMPOSITE=y CONFIG_CHIP_DIP_SCAN=y -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_CMD_DFU=y CONFIG_DFU_RAM=y diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig index 0e7d5e7c96..5a12fbb8cd 100644 --- a/configs/CHIP_pro_defconfig +++ b/configs/CHIP_pro_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y CONFIG_USB0_VBUS_PIN="PB10" -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTDPARTS=y diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig index 73983b1f97..1cd39d498f 100644 --- a/configs/CSQ_CS908_defconfig +++ b/configs/CSQ_CS908_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig index 4f964f19f0..02b3e69584 100644 --- a/configs/Chuwi_V7_CW0825_defconfig +++ b/configs/Chuwi_V7_CW0825_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index 470d3f3ea0..270bd7d351 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_BL_EN="PM1" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig index 2c1b3d27aa..ab5e53fb62 100644 --- a/configs/Cubieboard2_defconfig +++ b/configs/Cubieboard2_defconfig @@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig index c17edba90e..04ed79afb6 100644 --- a/configs/Cubieboard4_defconfig +++ b/configs/Cubieboard4_defconfig @@ -12,6 +12,5 @@ CONFIG_USB0_ID_DET="PH16" CONFIG_USB1_VBUS_PIN="PH14" CONFIG_USB3_VBUS_PIN="PH15" CONFIG_AXP_GPIO=y -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SYS_I2C_SUN8I_RSB=y CONFIG_AXP809_POWER=y diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig index 008167509d..c017b126b8 100644 --- a/configs/Cubieboard_defconfig +++ b/configs/Cubieboard_defconfig @@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig index a424634370..c85468e582 100644 --- a/configs/Cubietruck_defconfig +++ b/configs/Cubietruck_defconfig @@ -13,7 +13,6 @@ CONFIG_SATAPWR="PH12" CONFIG_GMAC_TX_DELAY=1 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig index b44b9a71ac..13f958977b 100644 --- a/configs/Cubietruck_plus_defconfig +++ b/configs/Cubietruck_plus_defconfig @@ -15,7 +15,6 @@ CONFIG_USB2_VBUS_PIN="PL6" CONFIG_I2C0_ENABLE=y CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CONSOLE_MUX=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig index d31e867be3..a9bbe8bcff 100644 --- a/configs/Empire_electronix_d709_defconfig +++ b/configs/Empire_electronix_d709_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig index 3e15d77433..fc1f26b7a9 100644 --- a/configs/Empire_electronix_m712_defconfig +++ b/configs/Empire_electronix_m712_defconfig @@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig index 0617192632..24e8b5be1b 100644 --- a/configs/Hummingbird_A31_defconfig +++ b/configs/Hummingbird_A31_defconfig @@ -9,7 +9,6 @@ CONFIG_USB2_VBUS_PIN="" CONFIG_VIDEO_VGA_VIA_LCD=y CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig index d745a68028..482e0fb7a8 100644 --- a/configs/Hyundai_A7HD_defconfig +++ b/configs/Hyundai_A7HD_defconfig @@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig index 6474c9e90a..99df9cff24 100644 --- a/configs/Itead_Ibox_A20_defconfig +++ b/configs/Itead_Ibox_A20_defconfig @@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig index c943fd3c06..f97dc131f2 100644 --- a/configs/Lamobo_R1_defconfig +++ b/configs/Lamobo_R1_defconfig @@ -10,7 +10,6 @@ CONFIG_SATAPWR="PB3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig index 5e9732e62e..9815348bad 100644 --- a/configs/LicheePi_Zero_defconfig +++ b/configs/LicheePi_Zero_defconfig @@ -5,5 +5,4 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_V3S=y CONFIG_DRAM_CLK=360 # CONFIG_HAS_ARMV7_SECURE_BASE is not set -CONFIG_SYS_MONITOR_LEN=786432 # CONFIG_NETDEVICES is not set diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig index 469dcc11f1..e3e30a4949 100644 --- a/configs/Linksprite_pcDuino3_Nano_defconfig +++ b/configs/Linksprite_pcDuino3_Nano_defconfig @@ -10,7 +10,6 @@ CONFIG_SATAPWR="PH2" CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index c4a3f2db96..1fda0db4c9 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -8,7 +8,6 @@ CONFIG_DRAM_ZQ=122 CONFIG_SATAPWR="PH2" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig index 80eb661e77..49dcfa098e 100644 --- a/configs/Linksprite_pcDuino_defconfig +++ b/configs/Linksprite_pcDuino_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN4I=y CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig index 0a4681b557..3ed962d7cd 100644 --- a/configs/MK808C_defconfig +++ b/configs/MK808C_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig index 915a74d92a..071169fd29 100644 --- a/configs/MSI_Primo73_defconfig +++ b/configs/MSI_Primo73_defconfig @@ -10,7 +10,6 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig index d01532fe75..e77b007292 100644 --- a/configs/MSI_Primo81_defconfig +++ b/configs/MSI_Primo81_defconfig @@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_USB_MUSB_HOST=y diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig index e3ada32b2f..3c5312d882 100644 --- a/configs/Marsboard_A10_defconfig +++ b/configs/Marsboard_A10_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig index d1bc200ab8..c697d286dc 100644 --- a/configs/Mele_A1000G_quad_defconfig +++ b/configs/Mele_A1000G_quad_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_ZQ=120 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig index 3424b97677..f5b6d908cd 100644 --- a/configs/Mele_A1000_defconfig +++ b/configs/Mele_A1000_defconfig @@ -8,7 +8,6 @@ CONFIG_VIDEO_VGA=y CONFIG_VIDEO_COMPOSITE=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig index 11ba786238..2b9bca13d0 100644 --- a/configs/Mele_I7_defconfig +++ b/configs/Mele_I7_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_ZQ=120 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig index 1b04ebc22a..77cb464c93 100644 --- a/configs/Mele_M3_defconfig +++ b/configs/Mele_M3_defconfig @@ -9,7 +9,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_VIDEO_VGA=y CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig index 114c2fe827..b07dbbde2e 100644 --- a/configs/Mele_M5_defconfig +++ b/configs/Mele_M5_defconfig @@ -9,7 +9,6 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_VIDEO_COMPOSITE=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig index b24ef02f8a..be6dd41754 100644 --- a/configs/Mele_M9_defconfig +++ b/configs/Mele_M9_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_ZQ=120 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig index 2b96f6be12..c5d1f40df3 100644 --- a/configs/Merrii_A80_Optimus_defconfig +++ b/configs/Merrii_A80_Optimus_defconfig @@ -12,6 +12,5 @@ CONFIG_USB0_ID_DET="PH3" CONFIG_USB1_VBUS_PIN="PH4" CONFIG_USB3_VBUS_PIN="PH5" CONFIG_AXP_GPIO=y -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SYS_I2C_SUN8I_RSB=y CONFIG_AXP809_POWER=y diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig index 72745f2b53..e8bc148576 100644 --- a/configs/Mini-X_defconfig +++ b/configs/Mini-X_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN4I=y CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig index 94060ab107..89fb441cc7 100644 --- a/configs/Nintendo_NES_Classic_Edition_defconfig +++ b/configs/Nintendo_NES_Classic_Edition_defconfig @@ -9,7 +9,6 @@ CONFIG_DRAM_ODT_EN=y CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTDPARTS=y # CONFIG_MMC is not set diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig index b4d5feff30..c89a9a1f9d 100644 --- a/configs/Orangepi_defconfig +++ b/configs/Orangepi_defconfig @@ -12,7 +12,6 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig index 4319738111..8757dcb461 100644 --- a/configs/Orangepi_mini_defconfig +++ b/configs/Orangepi_mini_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig index a1d62fce7c..238b0073e7 100644 --- a/configs/Sinlinx_SinA31s_defconfig +++ b/configs/Sinlinx_SinA31s_defconfig @@ -10,7 +10,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=3 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index eb172c70de..4eb5300b04 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CMD_DFU=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig index fa967bcc0c..aba95270eb 100644 --- a/configs/Sinovoip_BPI_M2_defconfig +++ b/configs/Sinovoip_BPI_M2_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig index ab70eff68e..5116fab52d 100644 --- a/configs/Sinovoip_BPI_M3_defconfig +++ b/configs/Sinovoip_BPI_M3_defconfig @@ -15,7 +15,6 @@ CONFIG_USB1_VBUS_PIN="PD24" CONFIG_AXP_GPIO=y CONFIG_SATAPWR="PD25" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CONSOLE_MUX=y CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y diff --git a/configs/Sunchip_CX-A99_defconfig b/configs/Sunchip_CX-A99_defconfig index 53cead2976..bb62ae9a7a 100644 --- a/configs/Sunchip_CX-A99_defconfig +++ b/configs/Sunchip_CX-A99_defconfig @@ -12,4 +12,3 @@ CONFIG_USB0_VBUS_PIN="PH15" CONFIG_USB1_VBUS_PIN="PL7" CONFIG_USB3_VBUS_PIN="PL8" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig index d7912e18ea..b021b0a886 100644 --- a/configs/UTOO_P66_defconfig +++ b/configs/UTOO_P66_defconfig @@ -20,7 +20,6 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_TL059WV5C0=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig index 8e729b8dc9..101ce57aa4 100644 --- a/configs/Wexler_TAB7200_defconfig +++ b/configs/Wexler_TAB7200_defconfig @@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig index 2eb1331e4d..f401ac74ef 100644 --- a/configs/Wits_Pro_A20_DKT_defconfig +++ b/configs/Wits_Pro_A20_DKT_defconfig @@ -12,7 +12,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig index fb8774786e..e0687bf887 100644 --- a/configs/Wobo_i5_defconfig +++ b/configs/Wobo_i5_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=432 CONFIG_MMC0_CD_PIN="PB3" CONFIG_USB1_VBUS_PIN="PG12" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig index 31e79ac6e3..f1ceb8b552 100644 --- a/configs/Yones_Toptech_BD1078_defconfig +++ b/configs/Yones_Toptech_BD1078_defconfig @@ -19,7 +19,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig index 625f72903a..6701ecce2f 100644 --- a/configs/Yones_Toptech_BS1078_V2_defconfig +++ b/configs/Yones_Toptech_BS1078_V2_defconfig @@ -16,6 +16,5 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_MUSB_HOST=y diff --git a/configs/a64-olinuxino-emmc_defconfig b/configs/a64-olinuxino-emmc_defconfig index c3eaaa7585..8ec9eb3e9c 100644 --- a/configs/a64-olinuxino-emmc_defconfig +++ b/configs/a64-olinuxino-emmc_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig index 7632302452..16cef18bee 100644 --- a/configs/a64-olinuxino_defconfig +++ b/configs/a64-olinuxino_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig index 66c245ff0a..ae44b66d10 100644 --- a/configs/amarula_a64_relic_defconfig +++ b/configs/amarula_a64_relic_defconfig @@ -7,7 +7,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig index 9268cebed6..b89dd8ea62 100644 --- a/configs/ba10_tv_box_defconfig +++ b/configs/ba10_tv_box_defconfig @@ -9,7 +9,6 @@ CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB2_VBUS_PIN="PH12" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig index 12ea6a3236..0fbb619d62 100644 --- a/configs/bananapi_m1_plus_defconfig +++ b/configs/bananapi_m1_plus_defconfig @@ -9,7 +9,6 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig index 63f9c14982..588eea2a27 100644 --- a/configs/bananapi_m2_berry_defconfig +++ b/configs/bananapi_m2_berry_defconfig @@ -9,7 +9,6 @@ CONFIG_USB1_VBUS_PIN="PH23" # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/bananapi_m2_plus_h3_defconfig b/configs/bananapi_m2_plus_h3_defconfig index 2bd5a70a2d..26ced59fb0 100644 --- a/configs/bananapi_m2_plus_h3_defconfig +++ b/configs/bananapi_m2_plus_h3_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/bananapi_m2_plus_h5_defconfig b/configs/bananapi_m2_plus_h5_defconfig index 926cf6f5a4..fb6c945919 100644 --- a/configs/bananapi_m2_plus_h5_defconfig +++ b/configs/bananapi_m2_plus_h5_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/bananapi_m2_zero_defconfig b/configs/bananapi_m2_zero_defconfig index b351d505a4..ac3f8f5ab8 100644 --- a/configs/bananapi_m2_zero_defconfig +++ b/configs/bananapi_m2_zero_defconfig @@ -6,4 +6,3 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 CONFIG_MMC0_CD_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 diff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig index 74fa637fd3..5463b046fd 100644 --- a/configs/bananapi_m64_defconfig +++ b/configs/bananapi_m64_defconfig @@ -7,7 +7,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig index 7d8f2160c8..42925eabcb 100644 --- a/configs/beelink_gs1_defconfig +++ b/configs/beelink_gs1_defconfig @@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/beelink_x2_defconfig b/configs/beelink_x2_defconfig index 68acb6b263..6206d90900 100644 --- a/configs/beelink_x2_defconfig +++ b/configs/beelink_x2_defconfig @@ -6,6 +6,5 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=567 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig index a7496c8a0b..5d3636e34e 100644 --- a/configs/colorfly_e708_q1_defconfig +++ b/configs/colorfly_e708_q1_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_AXP_DLDO2_VOLT=1800 CONFIG_USB_MUSB_HOST=y diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig index 1b292644d1..e1067b66ee 100644 --- a/configs/difrnce_dit4350_defconfig +++ b/configs/difrnce_dit4350_defconfig @@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig index d81782f727..60910c3ce3 100644 --- a/configs/dserve_dsrv9703c_defconfig +++ b/configs/dserve_dsrv9703c_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/emlid_neutis_n5_devboard_defconfig b/configs/emlid_neutis_n5_devboard_defconfig index e482f3cb19..a3b43dffc6 100644 --- a/configs/emlid_neutis_n5_devboard_defconfig +++ b/configs/emlid_neutis_n5_devboard_defconfig @@ -8,5 +8,4 @@ CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig index 03ba9dd26b..599eeb96b4 100644 --- a/configs/ga10h_v1_1_defconfig +++ b/configs/ga10h_v1_1_defconfig @@ -17,7 +17,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_EHCI_HCD=y diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig index 4069cf14b0..1a5fe06bbe 100644 --- a/configs/gt90h_v4_defconfig +++ b/configs/gt90h_v4_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig index cf3e7ce73a..29f965200e 100644 --- a/configs/h8_homlet_v2_defconfig +++ b/configs/h8_homlet_v2_defconfig @@ -10,7 +10,6 @@ CONFIG_USB0_VBUS_PIN="PL5" CONFIG_USB1_VBUS_PIN="PL6" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CONSOLE_MUX=y CONFIG_AXP_DLDO4_VOLT=3300 CONFIG_USB_EHCI_HCD=y diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig index d75a7992a8..257dd89af4 100644 --- a/configs/i12-tvbox_defconfig +++ b/configs/i12-tvbox_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=384 CONFIG_MACPWR="PH21" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig index 67474a8e62..436e3a8c20 100644 --- a/configs/iNet_3F_defconfig +++ b/configs/iNet_3F_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig index 23d41b796d..6978f8b0aa 100644 --- a/configs/iNet_3W_defconfig +++ b/configs/iNet_3W_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig index d51561eacc..2c8ecb51de 100644 --- a/configs/iNet_86VS_defconfig +++ b/configs/iNet_86VS_defconfig @@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/iNet_D978_rev2_defconfig b/configs/iNet_D978_rev2_defconfig index 8057df5ef1..9a90252dbd 100644 --- a/configs/iNet_D978_rev2_defconfig +++ b/configs/iNet_D978_rev2_defconfig @@ -17,7 +17,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_CONS_INDEX=5 diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig index 80441b32ba..c759d7e235 100644 --- a/configs/icnova-a20-swac_defconfig +++ b/configs/icnova-a20-swac_defconfig @@ -17,7 +17,6 @@ CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo CONFIG_VIDEO_LCD_POWER="PH22" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_CMD_UNZIP=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig index 64f7787344..f81120b119 100644 --- a/configs/inet1_defconfig +++ b/configs/inet1_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/inet86dz_defconfig b/configs/inet86dz_defconfig index 086098e5f4..3ade9fea82 100644 --- a/configs/inet86dz_defconfig +++ b/configs/inet86dz_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig index 0f70e95233..d5d2dc32c9 100644 --- a/configs/inet97fv2_defconfig +++ b/configs/inet97fv2_defconfig @@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig index 5c61766fe9..bd6c45bd66 100644 --- a/configs/inet98v_rev2_defconfig +++ b/configs/inet98v_rev2_defconfig @@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig index d21d17fb98..4485f93023 100644 --- a/configs/inet9f_rev03_defconfig +++ b/configs/inet9f_rev03_defconfig @@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/inet_q972_defconfig b/configs/inet_q972_defconfig index a614821925..1769256b7d 100644 --- a/configs/inet_q972_defconfig +++ b/configs/inet_q972_defconfig @@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig index 2e6b045b54..0ff666b2ee 100644 --- a/configs/jesurun_q5_defconfig +++ b/configs/jesurun_q5_defconfig @@ -8,7 +8,6 @@ CONFIG_MACPWR="PH19" CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/libretech_all_h3_cc_h2_plus_defconfig b/configs/libretech_all_h3_cc_h2_plus_defconfig index d19e337141..8725fe64cd 100644 --- a/configs/libretech_all_h3_cc_h2_plus_defconfig +++ b/configs/libretech_all_h3_cc_h2_plus_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/libretech_all_h3_cc_h3_defconfig b/configs/libretech_all_h3_cc_h3_defconfig index 4f3ab902d1..5275fdc36d 100644 --- a/configs/libretech_all_h3_cc_h3_defconfig +++ b/configs/libretech_all_h3_cc_h3_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/libretech_all_h3_cc_h5_defconfig b/configs/libretech_all_h3_cc_h5_defconfig index a912829be5..9627401949 100644 --- a/configs/libretech_all_h3_cc_h5_defconfig +++ b/configs/libretech_all_h3_cc_h5_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/libretech_all_h3_it_h5_defconfig b/configs/libretech_all_h3_it_h5_defconfig index f1f177c681..cb7ffb4d7d 100644 --- a/configs/libretech_all_h3_it_h5_defconfig +++ b/configs/libretech_all_h3_it_h5_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPI_FLASH_XMC=y CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/libretech_all_h5_cc_h5_defconfig b/configs/libretech_all_h5_cc_h5_defconfig index 1dbcaa8c75..c3aa4b1061 100644 --- a/configs/libretech_all_h5_cc_h5_defconfig +++ b/configs/libretech_all_h5_cc_h5_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPI_FLASH_XMC=y CONFIG_SUN8I_EMAC=y CONFIG_SPI=y diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig index e7663e1d1b..12a43c1ec1 100644 --- a/configs/licheepi_nano_defconfig +++ b/configs/licheepi_nano_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=156 CONFIG_DRAM_ZQ=0 # CONFIG_VIDEO_SUNXI is not set CONFIG_SPL_SPI_SUNXI=y -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_XTX=y CONFIG_SPI=y diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig index 646594b6e0..0e4cdc4467 100644 --- a/configs/mixtile_loftq_defconfig +++ b/configs/mixtile_loftq_defconfig @@ -9,7 +9,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PH24" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig index ffcb932974..21f7a6e535 100644 --- a/configs/mk802_a10s_defconfig +++ b/configs/mk802_a10s_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=432 CONFIG_DRAM_EMR1=0 CONFIG_USB1_VBUS_PIN="PB10" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig index 1186a5361e..416565e5af 100644 --- a/configs/mk802_defconfig +++ b/configs/mk802_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_USB2_VBUS_PIN="PH12" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig index 9c31b33c43..965a9cd5c4 100644 --- a/configs/mk802ii_defconfig +++ b/configs/mk802ii_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii" CONFIG_SPL=y CONFIG_MACH_SUN4I=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/nanopi_a64_defconfig b/configs/nanopi_a64_defconfig index ed11e0a630..70fc257eeb 100644 --- a/configs/nanopi_a64_defconfig +++ b/configs/nanopi_a64_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_m1_defconfig b/configs/nanopi_m1_defconfig index 9419eaf551..dc2dbd6290 100644 --- a/configs/nanopi_m1_defconfig +++ b/configs/nanopi_m1_defconfig @@ -5,6 +5,5 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig index 89065f0411..37b7817d86 100644 --- a/configs/nanopi_m1_plus_defconfig +++ b/configs/nanopi_m1_plus_defconfig @@ -8,7 +8,6 @@ CONFIG_MACPWR="PD6" CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig index d76d37f271..95dd56aa04 100644 --- a/configs/nanopi_neo2_defconfig +++ b/configs/nanopi_neo2_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig index 09a6bfa2e0..806d95c1cc 100644 --- a/configs/nanopi_neo_air_defconfig +++ b/configs/nanopi_neo_air_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CONSOLE_MUX=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig index 6110cfd495..c025519638 100644 --- a/configs/nanopi_neo_defconfig +++ b/configs/nanopi_neo_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CONSOLE_MUX=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig index d462b63e94..924ff38f17 100644 --- a/configs/nanopi_neo_plus2_defconfig +++ b/configs/nanopi_neo_plus2_defconfig @@ -9,7 +9,6 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_r1s_h5_defconfig b/configs/nanopi_r1s_h5_defconfig index 5c332ca526..27cf172d72 100644 --- a/configs/nanopi_r1s_h5_defconfig +++ b/configs/nanopi_r1s_h5_defconfig @@ -9,7 +9,6 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/oceanic_5205_5inmfd_defconfig b/configs/oceanic_5205_5inmfd_defconfig index ca3139431f..7ce63ba665 100644 --- a/configs/oceanic_5205_5inmfd_defconfig +++ b/configs/oceanic_5205_5inmfd_defconfig @@ -10,7 +10,6 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC0_CD_PIN="" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig index 000ab3e672..7aaa5190b3 100644 --- a/configs/orangepi_2_defconfig +++ b/configs/orangepi_2_defconfig @@ -7,7 +7,6 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/orangepi_3_defconfig b/configs/orangepi_3_defconfig index 3debe90cb6..ebecf49ebd 100644 --- a/configs/orangepi_3_defconfig +++ b/configs/orangepi_3_defconfig @@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_BLUETOOTH_DT_DEVICE_FIXUP="brcm,bcm4345c5" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PHY_SUN50I_USB3=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/orangepi_lite2_defconfig b/configs/orangepi_lite2_defconfig index 37d3cf7d7d..75c97d6b89 100644 --- a/configs/orangepi_lite2_defconfig +++ b/configs/orangepi_lite2_defconfig @@ -7,6 +7,5 @@ CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig index 25f5a4fe6f..96bbd1bab6 100644 --- a/configs/orangepi_lite_defconfig +++ b/configs/orangepi_lite_defconfig @@ -5,6 +5,5 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig index 094f8d1dfa..1064b4a39d 100644 --- a/configs/orangepi_one_defconfig +++ b/configs/orangepi_one_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_one_plus_defconfig b/configs/orangepi_one_plus_defconfig index 9a2abfa102..55a8b003fb 100644 --- a/configs/orangepi_one_plus_defconfig +++ b/configs/orangepi_one_plus_defconfig @@ -7,6 +7,5 @@ CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index 356ae7ce47..777af8c60e 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -8,7 +8,6 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MACPWR="PD6" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig index 4d3fa7799c..905ff7b127 100644 --- a/configs/orangepi_pc_defconfig +++ b/configs/orangepi_pc_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=624 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig index dcdec8d088..f845138153 100644 --- a/configs/orangepi_pc_plus_defconfig +++ b/configs/orangepi_pc_plus_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=624 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig index e27b329b0a..138a6a72b8 100644 --- a/configs/orangepi_plus2e_defconfig +++ b/configs/orangepi_plus2e_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig index 5c7f0731d9..76de72aa22 100644 --- a/configs/orangepi_plus_defconfig +++ b/configs/orangepi_plus_defconfig @@ -9,7 +9,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PG13" CONFIG_SATAPWR="PG11" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig index 80de7da021..95a82e20f3 100644 --- a/configs/orangepi_prime_defconfig +++ b/configs/orangepi_prime_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_r1_defconfig b/configs/orangepi_r1_defconfig index d645168d7c..4496aa4a45 100644 --- a/configs/orangepi_r1_defconfig +++ b/configs/orangepi_r1_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=624 # CONFIG_VIDEO_DE2 is not set CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CONSOLE_MUX=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig index 1e26970230..3b78ad7e52 100644 --- a/configs/orangepi_win_defconfig +++ b/configs/orangepi_win_defconfig @@ -7,7 +7,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MACPWR="PD14" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig index 877eccf31b..ceef51b3db 100644 --- a/configs/orangepi_zero2_defconfig +++ b/configs/orangepi_zero2_defconfig @@ -11,7 +11,6 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_R_I2C_ENABLE=y CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig index 5700c1bd00..f7f3bfbcc4 100644 --- a/configs/orangepi_zero_defconfig +++ b/configs/orangepi_zero_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=624 # CONFIG_VIDEO_DE2 is not set CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CONSOLE_MUX=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/orangepi_zero_plus2_defconfig b/configs/orangepi_zero_plus2_defconfig index 6a02624cd0..9583d24c8d 100644 --- a/configs/orangepi_zero_plus2_defconfig +++ b/configs/orangepi_zero_plus2_defconfig @@ -9,7 +9,6 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_zero_plus2_h3_defconfig b/configs/orangepi_zero_plus2_h3_defconfig index d003612d50..55a251374a 100644 --- a/configs/orangepi_zero_plus2_h3_defconfig +++ b/configs/orangepi_zero_plus2_h3_defconfig @@ -8,7 +8,6 @@ CONFIG_DRAM_CLK=672 CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_zero_plus_defconfig b/configs/orangepi_zero_plus_defconfig index 1628099448..f3ecf35eee 100644 --- a/configs/orangepi_zero_plus_defconfig +++ b/configs/orangepi_zero_plus_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=624 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig index b5c60da9f1..d56c4504b6 100644 --- a/configs/parrot_r16_defconfig +++ b/configs/parrot_r16_defconfig @@ -11,7 +11,6 @@ CONFIG_USB0_ID_DET="PD10" CONFIG_USB1_VBUS_PIN="PD12" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_CONS_INDEX=5 CONFIG_USB_EHCI_HCD=y diff --git a/configs/pine64-lts_defconfig b/configs/pine64-lts_defconfig index d8f718809b..7e7c2d7910 100644 --- a/configs/pine64-lts_defconfig +++ b/configs/pine64-lts_defconfig @@ -10,7 +10,6 @@ CONFIG_MMC0_CD_PIN="" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig index 0fd24b5c5b..f42f4e5923 100644 --- a/configs/pine64_plus_defconfig +++ b/configs/pine64_plus_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_PINE64_DT_SELECTION=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus" CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index 578bd92f6a..09a4275f0e 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -11,7 +11,6 @@ CONFIG_USB3_VBUS_PIN="PL5" CONFIG_SPL_SPI_SUNXI=y # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y diff --git a/configs/pinebook_defconfig b/configs/pinebook_defconfig index 75999b2fdc..26918dd387 100644 --- a/configs/pinebook_defconfig +++ b/configs/pinebook_defconfig @@ -8,7 +8,6 @@ CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_R_I2C_ENABLE=y -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig index 3386eda886..28e347b4d9 100644 --- a/configs/pinecube_defconfig +++ b/configs/pinecube_defconfig @@ -8,7 +8,6 @@ CONFIG_DRAM_CLK=504 CONFIG_DRAM_ODT_EN=y CONFIG_I2C0_ENABLE=y # CONFIG_HAS_ARMV7_SECURE_BASE is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig index 373c8c8d14..9d39204a43 100644 --- a/configs/pinephone_defconfig +++ b/configs/pinephone_defconfig @@ -10,7 +10,6 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_PINEPHONE_DT_SELECTION=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.2" CONFIG_LED_STATUS=y CONFIG_LED_STATUS_GPIO=y diff --git a/configs/pinetab_defconfig b/configs/pinetab_defconfig index f579010824..0cc24146b3 100644 --- a/configs/pinetab_defconfig +++ b/configs/pinetab_defconfig @@ -8,4 +8,3 @@ CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 diff --git a/configs/polaroid_mid2407pxe03_defconfig b/configs/polaroid_mid2407pxe03_defconfig index 9b7ee4c9c6..17fffeb1e2 100644 --- a/configs/polaroid_mid2407pxe03_defconfig +++ b/configs/polaroid_mid2407pxe03_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig index e4b2797304..e542b71113 100644 --- a/configs/polaroid_mid2809pxe04_defconfig +++ b/configs/polaroid_mid2809pxe04_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig index e2ebf2ba0b..a62c9f8fa3 100644 --- a/configs/pov_protab2_ips9_defconfig +++ b/configs/pov_protab2_ips9_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig index 2505822b66..f269b8a588 100644 --- a/configs/q8_a13_tablet_defconfig +++ b/configs/q8_a13_tablet_defconfig @@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig index dfa220b7c7..dda1a0c51f 100644 --- a/configs/q8_a23_tablet_800x480_defconfig +++ b/configs/q8_a23_tablet_800x480_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig index 79a0fc52e1..7925677d30 100644 --- a/configs/q8_a33_tablet_1024x600_defconfig +++ b/configs/q8_a33_tablet_1024x600_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig index b2d37122fc..f3335f9d23 100644 --- a/configs/q8_a33_tablet_800x480_defconfig +++ b/configs/q8_a33_tablet_800x480_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig index 60d8d7d373..8875a09b2c 100644 --- a/configs/r7-tv-dongle_defconfig +++ b/configs/r7-tv-dongle_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=384 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig index 84890d8f5a..fbbef7a9f9 100644 --- a/configs/sopine_baseboard_defconfig +++ b/configs/sopine_baseboard_defconfig @@ -11,7 +11,6 @@ CONFIG_MMC0_CD_PIN="" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y diff --git a/configs/sun8i_a23_evb_defconfig b/configs/sun8i_a23_evb_defconfig index 148015813b..a3b1d76d8b 100644 --- a/configs/sun8i_a23_evb_defconfig +++ b/configs/sun8i_a23_evb_defconfig @@ -9,7 +9,6 @@ CONFIG_USB0_VBUS_PIN="axp_drivebus" CONFIG_USB0_VBUS_DET="axp_vbus_detect" CONFIG_USB1_VBUS_PIN="PH7" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CONS_INDEX=5 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig index b67d1fb114..3fee7c2e50 100644 --- a/configs/sunxi_Gemei_G9_defconfig +++ b/configs/sunxi_Gemei_G9_defconfig @@ -11,7 +11,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/tanix_tx6_defconfig b/configs/tanix_tx6_defconfig index d8095d0d42..0390347415 100644 --- a/configs/tanix_tx6_defconfig +++ b/configs/tanix_tx6_defconfig @@ -8,4 +8,3 @@ CONFIG_DRAM_CLK=648 CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 diff --git a/configs/tbs_a711_defconfig b/configs/tbs_a711_defconfig index 6c3d5d49cd..b3c2e69d6c 100644 --- a/configs/tbs_a711_defconfig +++ b/configs/tbs_a711_defconfig @@ -13,7 +13,6 @@ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH11" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_AXP_DCDC5_VOLT=1200 CONFIG_USB_EHCI_HCD=y diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig index 64fa2a9761..e7de85eb50 100644 --- a/configs/teres_i_defconfig +++ b/configs/teres_i_defconfig @@ -8,7 +8,6 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PL7" CONFIG_I2C0_ENABLE=y -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PREBOOT="setenv usb_pgood_delay 2000; usb start" CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig index 41a1c47bd7..4276f4f543 100644 --- a/configs/x96_mate_defconfig +++ b/configs/x96_mate_defconfig @@ -7,7 +7,6 @@ CONFIG_MACH_SUN50I_H616=y CONFIG_MMC0_CD_PIN="PF6" CONFIG_R_I2C_ENABLE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/zeropi_defconfig b/configs/zeropi_defconfig index 8365da2c47..11f3715e6d 100644 --- a/configs/zeropi_defconfig +++ b/configs/zeropi_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=408 CONFIG_MACPWR="PD6" # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CONSOLE_MUX=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y -- cgit v1.2.3 From 6cad8bea4f6daa9ee268bbf6f88ae35735692cb0 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 17 Nov 2022 22:22:27 -0600 Subject: pinctrl: sunxi: Add P2WI and RSB pinmuxes P2WI and RSB are used to communicate with a PMIC. Most SoCs have only one possible pinmux. F1C100s has two possibilities, with different mux values, so omit it until some board needs one of them. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 061104be05..c4fbda7a92 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -338,6 +338,7 @@ static const struct sunxi_pinctrl_function sun6i_a31_r_pinctrl_functions[] = { { "gpio_in", 0 }, { "gpio_out", 1 }, { "s_i2c", 2 }, /* PL0-PL1 */ + { "s_p2wi", 3 }, /* PL0-PL1 */ { "s_uart", 2 }, /* PL2-PL3 */ }; @@ -404,6 +405,7 @@ static const struct sunxi_pinctrl_function sun8i_a23_r_pinctrl_functions[] = { { "gpio_in", 0 }, { "gpio_out", 1 }, { "s_i2c", 3 }, /* PL0-PL1 */ + { "s_rsb", 2 }, /* PL0-PL1 */ { "s_uart", 2 }, /* PL2-PL3 */ }; @@ -469,6 +471,7 @@ static const struct sunxi_pinctrl_function sun8i_a83t_r_pinctrl_functions[] = { { "gpio_in", 0 }, { "gpio_out", 1 }, { "s_i2c", 2 }, /* PL8-PL9 */ + { "s_rsb", 2 }, /* PL0-PL1 */ { "s_uart", 2 }, /* PL2-PL3 */ }; @@ -574,6 +577,7 @@ static const struct sunxi_pinctrl_function sun9i_a80_r_pinctrl_functions[] = { { "gpio_out", 1 }, { "s_i2c0", 2 }, /* PN0-PN1 */ { "s_i2c1", 3 }, /* PM8-PM9 */ + { "s_rsb", 3 }, /* PN0-PN1 */ { "s_uart", 3 }, /* PL0-PL1 */ }; @@ -615,6 +619,7 @@ static const struct sunxi_pinctrl_function sun50i_a64_r_pinctrl_functions[] = { { "gpio_in", 0 }, { "gpio_out", 1 }, { "s_i2c", 2 }, /* PL8-PL9 */ + { "s_rsb", 2 }, /* PL0-PL1 */ { "s_uart", 2 }, /* PL2-PL3 */ }; @@ -680,6 +685,7 @@ static const struct sunxi_pinctrl_function sun50i_h6_r_pinctrl_functions[] = { { "gpio_in", 0 }, { "gpio_out", 1 }, { "s_i2c", 3 }, /* PL0-PL1 */ + { "s_rsb", 2 }, /* PL0-PL1 */ { "s_uart", 2 }, /* PL2-PL3 */ }; @@ -717,6 +723,7 @@ static const struct sunxi_pinctrl_function sun50i_h616_r_pinctrl_functions[] = { { "gpio_in", 0 }, { "gpio_out", 1 }, { "s_i2c", 3 }, /* PL0-PL1 */ + { "s_rsb", 2 }, /* PL0-PL1 */ { "s_uart", 2 }, /* PL2-PL3 */ }; -- cgit v1.2.3 From 705209a0957ffd9e0ad001d01cb2b468fb1b3347 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sun, 11 Dec 2022 23:00:54 +0100 Subject: sunxi: Fix serial console for A10s-OLinuXino-MICRO On this board CONFIG_CONS_INDEX needs to be 1 unlike other sun5i boards. Since this is the default, remove to bogus setting. Fixes: 7095f8641863 ("sunxi: Convert CONS_INDEX to Kconfig") Signed-off-by: Mark Kettenis Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- configs/A10s-OLinuXino-M_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig index 99f5785751..d1e3b056b4 100644 --- a/configs/A10s-OLinuXino-M_defconfig +++ b/configs/A10s-OLinuXino-M_defconfig @@ -16,6 +16,5 @@ CONFIG_SYS_I2C_SPEED=400000 CONFIG_MII=y CONFIG_SUN4I_EMAC=y CONFIG_AXP152_POWER=y -CONFIG_CONS_INDEX=2 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -- cgit v1.2.3 From 767df6a27d5395851859e56b4c97413ab9443c0e Mon Sep 17 00:00:00 2001 From: Alistair Delva Date: Mon, 26 Sep 2022 22:23:26 +0000 Subject: x86: Fix i8259 ifdef include guard When building U-Boot with clang, it notices that the i8259.h include guard does not work correctly due to a typo. Fix it. Signed-off-by: Alistair Delva Cc: Simon Glass Cc: Bin Meng Cc: Nick Desaulniers Reviewed-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/include/asm/i8259.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/i8259.h b/arch/x86/include/asm/i8259.h index b73052a6d2..90f2d3866c 100644 --- a/arch/x86/include/asm/i8259.h +++ b/arch/x86/include/asm/i8259.h @@ -7,7 +7,7 @@ /* i8259.h i8259 PIC Registers */ #ifndef _ASMI386_I8259_H_ -#define _ASMI386_I8959_H_ +#define _ASMI386_I8259_H_ /* PIC I/O mapped registers */ #define IRR 0x0 /* Interrupt Request Register */ @@ -73,4 +73,4 @@ int i8259_init(void); -#endif /* _ASMI386_I8959_H_ */ +#endif /* _ASMI386_I8259_H_ */ -- cgit v1.2.3 From f38be3086837e3637fe588f6571c2d245261e5fb Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 24 Nov 2022 11:24:37 +0800 Subject: x86: bayleybay: Adjust CONFIG_TEXT_BASE At present U-Boot no longer builds as a complete rom for bayleybay. BINMAN .binman_stamp Wrote map file './rom.map' to show errors binman: Section '/binman/rom': contents size 0x814706 (8472326) exceeds section size 0x800000 (8388608) Checking rom.map we see 'fdtmap' section is overlapped with 'intel-vga' and 'intel-fsp' sections: fffa2150 0002a000 u-boot-ucode fffb0000 00010000 intel-vga fffc0000 00038000 intel-fsp fffcc150 00000539 fdtmap Let's adjust CONFIG_TEXT_BASE to allow more space for U-Boot codes. Signed-off-by: Bin Meng --- configs/bayleybay_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index 5f43f4c0ee..3556fe6b12 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -1,5 +1,5 @@ CONFIG_X86=y -CONFIG_TEXT_BASE=0xFFF00000 +CONFIG_TEXT_BASE=0xFFE00000 CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x6FF000 -- cgit v1.2.3 From 66e2c665f3b60d726e1c26ad44ac97aa76ead6f5 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 24 Nov 2022 11:07:13 +0800 Subject: x86: minnowmax: Adjust CONFIG_TEXT_BASE At present U-Boot no longer builds as a complete rom for minnowmax. BINMAN .binman_stamp Wrote map file './rom.map' to show errors binman: Section '/binman/rom': contents size 0x803146 (8401222) exceeds section size 0x800000 (8388608) Checking rom.map we see 'fdtmap' section is overlapped with 'intel-vga' section: fffa1390 00019800 u-boot-ucode fffb0000 00010000 intel-vga fffbab90 00000539 fdtmap Let's adjust CONFIG_TEXT_BASE to allow more space for U-Boot codes. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- configs/minnowmax_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 66f3036313..e501cc55fb 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -1,5 +1,5 @@ CONFIG_X86=y -CONFIG_TEXT_BASE=0xFFF00000 +CONFIG_TEXT_BASE=0xFFE00000 CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x6EF000 -- cgit v1.2.3 From 388f93f963546b49821e0142628f70203bc99c18 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 24 Nov 2022 15:33:09 +0800 Subject: x86: conga-qeval20-qa3-e3845: Adjust CONFIG_TEXT_BASE At present U-Boot no longer builds as a complete rom for all the configs of conga-qeval20-qa3-e3845. BINMAN .binman_stamp Wrote map file './rom.map' to show errors binman: Section '/binman/rom': contents size 0x80b680 (8435328) exceeds section size 0x800000 (8388608) Checking rom.map we see 'intel-vga' section is overlapped with other sections: fff00000 000a7cb0 u-boot-with-ucode-ptr fffa0000 00010000 intel-vga fffa7cb0 00001c1a u-boot-dtb-with-ucode fffa98d0 00019800 u-boot-ucode Let's adjust CONFIG_TEXT_BASE to allow more space for U-Boot codes. Signed-off-by: Bin Meng --- configs/conga-qeval20-qa3-e3845-internal-uart_defconfig | 2 +- configs/conga-qeval20-qa3-e3845_defconfig | 2 +- configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig | 2 +- configs/theadorable-x86-conga-qa3-e3845_defconfig | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index 0d904675f7..54189b916a 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -1,5 +1,5 @@ CONFIG_X86=y -CONFIG_TEXT_BASE=0xFFF00000 +CONFIG_TEXT_BASE=0xFFE00000 CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x6EF000 diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index 6fed3f2ecd..b5b1416cff 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -1,5 +1,5 @@ CONFIG_X86=y -CONFIG_TEXT_BASE=0xFFF00000 +CONFIG_TEXT_BASE=0xFFE00000 CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x6EF000 diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig index 22544c0913..6752d110b1 100644 --- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig @@ -1,5 +1,5 @@ CONFIG_X86=y -CONFIG_TEXT_BASE=0xFFF00000 +CONFIG_TEXT_BASE=0xFFE00000 CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x6EC000 diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig index 8741ecbb2d..336ba4605c 100644 --- a/configs/theadorable-x86-conga-qa3-e3845_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig @@ -1,5 +1,5 @@ CONFIG_X86=y -CONFIG_TEXT_BASE=0xFFF00000 +CONFIG_TEXT_BASE=0xFFE00000 CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x6EC000 -- cgit v1.2.3 From 5d1c8342aeaaa13a32e86571ec054ed3582c0d67 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 24 Nov 2022 15:58:17 +0800 Subject: x86: dfi-bt700: Adjust CONFIG_TEXT_BASE At present U-Boot no longer builds as a complete rom for all the configs of dfi-bt700. BINMAN .binman_stamp Wrote map file './rom.map' to show errors binman: Section '/binman/rom': contents size 0x80e836 (8448054) exceeds section size 0x800000 (8388608) Checking rom.map we see 'intel-vga' section is overlapped with other sections: fff00000 000aac90 u-boot-with-ucode-ptr fffa0000 00010000 intel-vga fffaac90 00001df0 u-boot-dtb-with-ucode fffaca80 00019800 u-boot-ucode Let's adjust CONFIG_TEXT_BASE to allow more space for U-Boot codes. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese --- configs/dfi-bt700-q7x-151_defconfig | 2 +- configs/theadorable-x86-dfi-bt700_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig index f9b1bae413..63b8c8f92d 100644 --- a/configs/dfi-bt700-q7x-151_defconfig +++ b/configs/dfi-bt700-q7x-151_defconfig @@ -1,5 +1,5 @@ CONFIG_X86=y -CONFIG_TEXT_BASE=0xFFF00000 +CONFIG_TEXT_BASE=0xFFE00000 CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x6EF000 diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig index 4755b4754f..fea35cd915 100644 --- a/configs/theadorable-x86-dfi-bt700_defconfig +++ b/configs/theadorable-x86-dfi-bt700_defconfig @@ -1,5 +1,5 @@ CONFIG_X86=y -CONFIG_TEXT_BASE=0xFFF00000 +CONFIG_TEXT_BASE=0xFFE00000 CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x6EC000 -- cgit v1.2.3 From e23cae30801fab679e98029e0d3079592e1d3915 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 24 Nov 2022 16:19:54 +0800 Subject: x86: som-db5800-som-6867: Adjust CONFIG_TEXT_BASE At present U-Boot no longer builds as a complete rom for som-db5800-som-6867. BINMAN .binman_stamp Wrote map file './rom.map' to show errors binman: Section '/binman/rom': contents size 0x80302c (8400940) exceeds section size 0x800000 (8388608) Checking rom.map we see 'intel-vga' section is overlapped with other sections: fff00000 0009f7c8 u-boot-with-ucode-ptr fff90000 00010000 intel-vga fff9f7c8 00001aae u-boot-dtb-with-ucode Let's adjust CONFIG_TEXT_BASE to allow more space for U-Boot codes. Signed-off-by: Bin Meng --- configs/som-db5800-som-6867_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig index 5d401e6c2d..f6b2109e2b 100644 --- a/configs/som-db5800-som-6867_defconfig +++ b/configs/som-db5800-som-6867_defconfig @@ -1,5 +1,5 @@ CONFIG_X86=y -CONFIG_TEXT_BASE=0xFFF00000 +CONFIG_TEXT_BASE=0xFFE00000 CONFIG_NR_DRAM_BANKS=8 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x6EF000 -- cgit v1.2.3 From 58e2a35f2e81b0114cf05bfd6e96e4d70e47b22c Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 24 Nov 2022 11:39:23 +0800 Subject: x86: cosmetic: Fix a typo in the reserve_arch() comments It should be fsp_continue(). Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/cpu/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 86f53e78d2..6fe6eaf6c8 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -315,7 +315,7 @@ int reserve_arch(void) if (IS_ENABLED(CONFIG_HAVE_FSP)) { /* * Save stack address to CMOS so that at next S3 boot, - * we can use it as the stack address for fsp_contiue() + * we can use it as the stack address for fsp_continue() */ fsp_save_s3_stack(); } -- cgit v1.2.3 From ed82586c4054c62c35e119f4f0a14619f0ad6c2e Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 28 Nov 2022 00:03:53 +0000 Subject: sunxi: remove unused CONFIG_MMC_SUNXI_SLOT There is a CONFIG_MMC_SUNXI_SLOT definition in our sunxi_common.h config header, which was used to note the first MMC controller to initialise. The definition in that header was always set to 0, with no easy way of overriding this, and certainly none of the existing boards made any use of that (non-)feature. Remove that definition and replace it with a constant 0 in the only user, in board.c. It turns out that this is safe, as this is only used in the SPL, and the BROM also unconditionally initialises MMC0. This also removes the last legacy config symbol with SUN*I in it from the whitelist. Reviewed-by: Samuel Holland Tested-by: Samuel Holland Signed-off-by: Andre Przywara --- board/sunxi/board.c | 9 +++++++-- include/configs/sunxi-common.h | 3 --- scripts/config_whitelist.txt | 1 - 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 21a2407e06..4d2491b5a8 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -525,9 +525,14 @@ static void mmc_pinmux_setup(int sdc) int board_mmc_init(struct bd_info *bis) { + /* + * The BROM always accesses MMC port 0 (typically an SD card), and + * most boards seem to have such a slot. The others haven't reported + * any problem with unconditionally enabling this in the SPL. + */ if (!IS_ENABLED(CONFIG_UART0_PORT_F)) { - mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); - if (!sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT)) + mmc_pinmux_setup(0); + if (!sunxi_mmc_init(0)) return -1; } diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 720768629d..e89ad42ce8 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -75,9 +75,6 @@ #define CONFIG_SYS_NAND_MAX_ECCPOS 1664 #endif -/* mmc config */ -#define CONFIG_MMC_SUNXI_SLOT 0 - /* * Miscellaneous configurable options */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index c0f55e41a5..ea71f9d234 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -153,7 +153,6 @@ CONFIG_MISC_COMMON CONFIG_MIU_2BIT_21_7_INTERLEAVED CONFIG_MIU_2BIT_INTERLEAVED CONFIG_MMC_DEFAULT_DEV -CONFIG_MMC_SUNXI_SLOT CONFIG_MONITOR_IS_IN_RAM CONFIG_MPC85XX_FEC CONFIG_MPC85XX_FEC_NAME -- cgit v1.2.3 From eeaca6ac27ccfd75956c1ad6ca27d9b9caf62c96 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 28 Nov 2022 00:55:20 +0000 Subject: sunxi: remove bogus mmc_pinmux_setup() prototype Since all callers of mmc_pinmux_setup() are located after the definition of that function, there is no need for a forward declaration (anymore?). Remove the prototype along with its #ifdef guards. Reviewed-by: Samuel Holland Tested-by: Samuel Holland Signed-off-by: Andre Przywara --- board/sunxi/board.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 4d2491b5a8..4fe749feb3 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -184,10 +184,6 @@ enum env_location env_get_location(enum env_operation op, int prio) return ENVL_UNKNOWN; } -#ifdef CONFIG_DM_MMC -static void mmc_pinmux_setup(int sdc); -#endif - /* add board specific code here */ int board_init(void) { -- cgit v1.2.3 From 64531496f990c2a63211c72b953dfc084b4c2589 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 28 Nov 2022 00:02:56 +0000 Subject: sunxi: board: annotate #endif lines The legacy Allwinner code is cluttered with #ifdef's, some of them even nested, which makes the code hard to read and error prone. Eventually we will get rid of most of them, but for now let's at least annotate the #endif lines with the corresponding symbol the bracket started with. Reviewed-by: Samuel Holland Tested-by: Samuel Holland Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/board.c | 8 ++++---- arch/arm/mach-sunxi/clock_sun6i.c | 4 ++-- board/sunxi/board.c | 11 +++++------ 3 files changed, 11 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 86233637bf..0c4b6dd1ca 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -73,7 +73,7 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) return gd->ram_top; } -#endif +#endif /* CONFIG_ARM64 */ #ifdef CONFIG_SPL_BUILD static int gpio_init(void) @@ -196,7 +196,7 @@ static int spl_board_load_image(struct spl_image_info *spl_image, return 0; } SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image); -#endif +#endif /* CONFIG_SPL_BUILD */ #define SUNXI_INVALID_BOOT_SOURCE -1 @@ -457,7 +457,7 @@ void board_init_f(ulong dummy) #endif sunxi_board_init(); } -#endif +#endif /* CONFIG_SPL_BUILD */ #if !CONFIG_IS_ENABLED(SYSRESET) void reset_cpu(void) @@ -490,7 +490,7 @@ void reset_cpu(void) while (1) { } #endif } -#endif +#endif /* CONFIG_SYSRESET */ #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && defined(CONFIG_CPU_V7A) void enable_caches(void) diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index cda6949dff..6bd75a15f6 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -63,7 +63,7 @@ void clock_init_safe(void) setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE); #endif } -#endif +#endif /* CONFIG_SPL_BUILD */ void clock_init_sec(void) { @@ -172,7 +172,7 @@ void clock_set_pll1(unsigned int clk) &ccm->cpu_axi_cfg); } } -#endif +#endif /* CONFIG_SPL_BUILD */ void clock_set_pll3(unsigned int clk) { diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 4fe749feb3..827e545032 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -351,7 +351,7 @@ void board_nand_init(void) sunxi_nand_init(); #endif } -#endif +#endif /* CONFIG_NAND_SUNXI */ #ifdef CONFIG_MMC static void mmc_pinmux_setup(int sdc) @@ -554,7 +554,7 @@ int mmc_get_env_dev(void) } } #endif -#endif +#endif /* CONFIG_MMC */ #ifdef CONFIG_SPL_BUILD @@ -670,7 +670,7 @@ void sunxi_board_init(void) else printf("Failed to set core voltage! Can't set CPU frequency\n"); } -#endif +#endif /* CONFIG_SPL_BUILD */ #ifdef CONFIG_USB_GADGET int g_dnl_board_usb_cable_connected(void) @@ -699,7 +699,7 @@ int g_dnl_board_usb_cable_connected(void) return sun4i_usb_phy_vbus_detect(&phy); } -#endif +#endif /* CONFIG_USB_GADGET */ #ifdef CONFIG_SERIAL_TAG void get_board_serial(struct tag_serialnr *serialnr) @@ -928,7 +928,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) } #ifdef CONFIG_SPL_LOAD_FIT - static void set_spl_dt_name(const char *name) { struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION); @@ -996,4 +995,4 @@ int board_fit_config_name_match(const char *name) return ret; } -#endif +#endif /* CONFIG_SPL_LOAD_FIT */ -- cgit v1.2.3 From e7d962bc3c9868d84129818ad4510b63de2e55b3 Mon Sep 17 00:00:00 2001 From: Maxim Cournoyer Date: Fri, 16 Dec 2022 21:09:40 -0500 Subject: doc: fix typos Fix a few typos spot during a first read of the contribution process. Signed-off-by: Maxim Cournoyer Reviewed-by: Heinrich Schuchardt Signed-off-by: Heinrich Schuchardt --- doc/develop/process.rst | 12 ++++++------ doc/develop/sending_patches.rst | 18 +++++++++--------- doc/develop/system_configuration.rst | 6 +++--- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/doc/develop/process.rst b/doc/develop/process.rst index 0fa0143bf3..92477d05dd 100644 --- a/doc/develop/process.rst +++ b/doc/develop/process.rst @@ -165,8 +165,8 @@ document. `_ and similar additional tags. -* Reviewed-by: The patch has been reviewed and found acceptible according to - the `Reveiwer's statement of oversight +* Reviewed-by: The patch has been reviewed and found acceptable according to + the `Reviewer's statement of oversight `_. A *Reviewed-by:* tag is a statement of opinion that the patch is an appropriate modification of the code without any remaining serious technical @@ -193,8 +193,8 @@ document. * Cc: If a person should have the opportunity to comment on a patch, you may optionally add a *Cc:* tag to the patch. Git tools (git send-email) will then - automatically arrange that they receives a copy of the patch when you submit it - to the mainling list. This is the only tag which might be added without an + automatically arrange that they receives a copy of the patch when you submit + it to the mailing list. This is the only tag which might be added without an explicit action by the person it names. This tag documents that potentially interested parties have been included in the discussion. For example, when your change affects a specific board or driver, then makes @@ -209,7 +209,7 @@ like this: #. The responsible custodian inspects this patch, especially for: #. The commit message is useful, descriptive and makes correct and - appropraite usage of required *git tags*. + appropriate usage of required *git tags*. #. :doc:`codingstyle` @@ -251,7 +251,7 @@ like this: workflows and environments however. #. Although a custodian is supposed to perform their own tests it is a - well-known and accepted fact that they needs help from other developers who + well-known and accepted fact that they need help from other developers who - for example - have access to the required hardware or other relevant environments. Custodians are expected to ask for assistance with testing when required. diff --git a/doc/develop/sending_patches.rst b/doc/develop/sending_patches.rst index 173075687e..ba73d0d11b 100644 --- a/doc/develop/sending_patches.rst +++ b/doc/develop/sending_patches.rst @@ -20,8 +20,8 @@ LWN article `How to Get Your Change Into the Linux Kernel Using patman ------------ -You can use a tool called patman to prepare, check and sent patches. It creates -change logs, cover letters and patch notes. It also simplified the process of +You can use a tool called patman to prepare, check and send patches. It creates +change logs, cover letters and patch notes. It also simplifies the process of sending multiple versions of a series. See more details at :doc:`patman`. @@ -41,7 +41,7 @@ General Patch Submission Rules past commits might have input to your change, so also CC them if you think they may have feedback. -* Patches should always contain exactly one complete logical change, i. e. +* Patches should always contain exactly one complete logical change, i.e. * Changes that contain different, unrelated modifications shall be submitted as *separate* patches, one patch per changeset. @@ -68,7 +68,7 @@ General Patch Submission Rules as such -- that *precedes* your substantive patch. * For minor modifications (e.g. changed arguments of a function call), - adhere to the present codingstyle of the module. Relating checkpatch + adhere to the present coding style of the module. Relating checkpatch warnings can be ignored in this case. A respective note in the commit or cover letter why they are ignored is desired. @@ -93,7 +93,7 @@ General Patch Submission Rules visible as headline of your commit message. Make sure the subject does not exceed 60 characters or so. -* The start of the subject should be a meaningfull tag (arm:, ppc:, tegra:, +* The start of the subject should be a meaningful tag (arm:, ppc:, tegra:, net:, ext2:, etc) * Include the string "PATCH" in the Subject: line of your message, e. g. @@ -247,14 +247,14 @@ When re-posting such a new version of your patch(es), please always make sure to observe the following rules. * Make an appropriate note that this is a re-submission in the subject line, - eg. "[PATCH v2] Add support for feature X". ``git format-patch + e.g. "[PATCH v2] Add support for feature X". ``git format-patch --subject-prefix="PATCH v2"`` can be used in this case (see the example below). -* Please make sure to keep a "change log", i. e. a description of what you have +* Please make sure to keep a "change log", i.e. a description of what you have changed compared to previous versions of this patch. This change log should be added below the "---" line in the patch, which starts the "comment - section", i. e. which contains text that does not get included into the + section", i.e. which contains text that does not get included into the actual commit message. Note: it is *not* sufficient to provide a change log in some cover letter that gets sent as a separate message with the patch series. The reason is @@ -312,7 +312,7 @@ Notes 2. All code must follow the :doc:`codingstyle` requirements. 3. Before sending the patch, you *must* run some form of local testing. - Submitting a patch that does not build or function correct is a mistake. For + Submitting a patch that does not build or function correctly is a mistake. For non-trivial patches, either building a number of platforms locally or making use of :doc:`ci_testing` is strongly encouraged in order to avoid problems that can be found when attempting to merge the patch. diff --git a/doc/develop/system_configuration.rst b/doc/develop/system_configuration.rst index 52e4e1df15..40be46b082 100644 --- a/doc/develop/system_configuration.rst +++ b/doc/develop/system_configuration.rst @@ -86,12 +86,12 @@ When to use each mechanism ^^^^^^^^^^^^^^^^^^^^^^^^^^ While there are some cases where it should be fairly obvious where to use each -mechanism, as for example a command would done via Kconfig, a new I2C driver +mechanism, as for example a command would be done via Kconfig, a new I2C driver should use Kconfig and be configured via driver model and a header of values generated by an external tool should be ``CFG``, there will be cases where it's less clear and one needs to take care when implementing it. In general, configuration *options* should be done in Kconfig and configuration *settings* -should done in driver model or ``CFG``. Let us discuss things to keep in mind +should be done in driver model or ``CFG``. Let us discuss things to keep in mind when picking the appropriate mechanism. A thing to keep in mind is that we have a strong preference for using Kconfig as @@ -122,7 +122,7 @@ to use Kconfig in this case, it would result in using calculated rather than constructed values, resulting in less clear code. Consider the example of a set of register values for a memory controller. Defining this as a series of logical ORs and shifts based on other defines is more clear than the Kconfig entry that -set the calculated value alone. +sets the calculated value alone. When it has been determined that the practical solution is to utilize the ``CFG`` mechanism, the next decision is where to place these settings. It is -- cgit v1.2.3 From 63db1561f1db28c83dea1e219fe87e264a184eb4 Mon Sep 17 00:00:00 2001 From: Vincent Stehlé Date: Fri, 16 Dec 2022 17:55:04 +0100 Subject: efi: adjust ebbr to v2.1 in conformance profile MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The EFI Conformance Profile Table entry for EBBR appears in v2.1.0 of the EBBR specification[1]. Update naming accordingly. While at it, update the EBBR version referenced in the documentation. [1]: https://github.com/ARM-software/ebbr/releases/tag/v2.1.0 Signed-off-by: Vincent Stehlé Cc: Heinrich Schuchardt Cc: Ilias Apalodimas Reviewed-by: Heinrich Schuchardt --- doc/develop/uefi/uefi.rst | 6 +++--- include/efi_api.h | 2 +- lib/efi_loader/Kconfig | 6 +++--- lib/efi_loader/efi_conformance.c | 8 ++++---- lib/efi_selftest/efi_selftest_ecpt.c | 6 +++--- 5 files changed, 14 insertions(+), 14 deletions(-) diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst index e0835beba4..a944c0fb80 100644 --- a/doc/develop/uefi/uefi.rst +++ b/doc/develop/uefi/uefi.rst @@ -14,7 +14,7 @@ Development target ------------------ The implementation of UEFI in U-Boot strives to reach the requirements described -in the "Embedded Base Boot Requirements (EBBR) Specification - Release v1.0" +in the "Embedded Base Boot Requirements (EBBR) Specification - Release v2.1.0" [2]. The "Server Base Boot Requirements System Software on ARM Platforms" [3] describes a superset of the EBBR specification and may be used as further reference. @@ -799,8 +799,8 @@ Links ----- * [1] http://uefi.org/specifications - UEFI specifications -* [2] https://github.com/ARM-software/ebbr/releases/download/v1.0/ebbr-v1.0.pdf - - Embedded Base Boot Requirements (EBBR) Specification - Release v1.0 +* [2] https://github.com/ARM-software/ebbr/releases/download/v2.1.0/ebbr-v2.1.0.pdf - + Embedded Base Boot Requirements (EBBR) Specification - Release v2.1.0 * [3] https://developer.arm.com/docs/den0044/latest/server-base-boot-requirements-system-software-on-arm-platforms-version-11 - Server Base Boot Requirements System Software on ARM Platforms - Version 1.1 * [4] :doc:`iscsi` diff --git a/include/efi_api.h b/include/efi_api.h index 9bb0d44ac8..00c98e0984 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -232,7 +232,7 @@ enum efi_reset_type { #define EFI_CONFORMANCE_PROFILES_TABLE_VERSION 1 -#define EFI_CONFORMANCE_PROFILE_EBBR_2_0_GUID \ +#define EFI_CONFORMANCE_PROFILE_EBBR_2_1_GUID \ EFI_GUID(0xcce33c35, 0x74ac, 0x4087, 0xbc, 0xe7, \ 0x8b, 0x29, 0xb0, 0x2e, 0xeb, 0x27) diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index e2b643871b..b498c72206 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -384,8 +384,8 @@ config EFI_ECPT help Enabling this option created the ECPT UEFI table. -config EFI_EBBR_2_0_CONFORMANCE - bool "Add the EBBRv2.0 conformance entry to the ECPT table" +config EFI_EBBR_2_1_CONFORMANCE + bool "Add the EBBRv2.1 conformance entry to the ECPT table" depends on EFI_ECPT depends on EFI_LOADER_HII depends on EFI_RISCV_BOOT_PROTOCOL || !RISCV @@ -393,7 +393,7 @@ config EFI_EBBR_2_0_CONFORMANCE depends on EFI_UNICODE_COLLATION_PROTOCOL2 default y help - Enabling this option adds the EBBRv2.0 conformance entry to the ECPT UEFI table. + Enabling this option adds the EBBRv2.1 conformance entry to the ECPT UEFI table. config EFI_RISCV_BOOT_PROTOCOL bool "RISCV_EFI_BOOT_PROTOCOL support" diff --git a/lib/efi_loader/efi_conformance.c b/lib/efi_loader/efi_conformance.c index a49aae9249..3036d46349 100644 --- a/lib/efi_loader/efi_conformance.c +++ b/lib/efi_loader/efi_conformance.c @@ -12,8 +12,8 @@ #include static const efi_guid_t efi_ecpt_guid = EFI_CONFORMANCE_PROFILES_TABLE_GUID; -static const efi_guid_t efi_ebbr_2_0_guid = - EFI_CONFORMANCE_PROFILE_EBBR_2_0_GUID; +static const efi_guid_t efi_ebbr_2_1_guid = + EFI_CONFORMANCE_PROFILE_EBBR_2_1_GUID; /** * efi_ecpt_register() - Install the ECPT system table. @@ -38,9 +38,9 @@ efi_status_t efi_ecpt_register(void) return ret; } - if (CONFIG_IS_ENABLED(EFI_EBBR_2_0_CONFORMANCE)) + if (CONFIG_IS_ENABLED(EFI_EBBR_2_1_CONFORMANCE)) guidcpy(&ecpt->conformance_profiles[num_entries++], - &efi_ebbr_2_0_guid); + &efi_ebbr_2_1_guid); ecpt->version = EFI_CONFORMANCE_PROFILES_TABLE_VERSION; ecpt->number_of_profiles = num_entries; diff --git a/lib/efi_selftest/efi_selftest_ecpt.c b/lib/efi_selftest/efi_selftest_ecpt.c index e8cc13545d..09c5e96c5e 100644 --- a/lib/efi_selftest/efi_selftest_ecpt.c +++ b/lib/efi_selftest/efi_selftest_ecpt.c @@ -10,7 +10,7 @@ #include static const efi_guid_t guid_ecpt = EFI_CONFORMANCE_PROFILES_TABLE_GUID; -static const efi_guid_t guid_ebbr_2_0 = EFI_CONFORMANCE_PROFILE_EBBR_2_0_GUID; +static const efi_guid_t guid_ebbr_2_1 = EFI_CONFORMANCE_PROFILE_EBBR_2_1_GUID; /* * ecpt_find_guid() - find GUID in EFI Conformance Profile Table @@ -53,9 +53,9 @@ static int execute(void) return EFI_ST_FAILURE; } - if (CONFIG_IS_ENABLED(EFI_EBBR_2_0_CONFORMANCE)) { + if (CONFIG_IS_ENABLED(EFI_EBBR_2_1_CONFORMANCE)) { ++expected_entries; - if (ecpt_find_guid(ecpt, &guid_ebbr_2_0)) + if (ecpt_find_guid(ecpt, &guid_ebbr_2_1)) return EFI_ST_FAILURE; } -- cgit v1.2.3 From 5b5f6e0d61efe55df5eab82d231f2a483d3f49e7 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Fri, 9 Dec 2022 15:33:52 +0100 Subject: doc: update Sphinx requirements for certifi Upgrade to version 2022.12.7. Signed-off-by: Heinrich Schuchardt --- doc/sphinx/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/sphinx/requirements.txt b/doc/sphinx/requirements.txt index 5baec4d93e..f9f6cc6e92 100644 --- a/doc/sphinx/requirements.txt +++ b/doc/sphinx/requirements.txt @@ -1,6 +1,6 @@ alabaster==0.7.12 Babel==2.9.1 -certifi==2021.10.8 +certifi==2022.12.7 charset-normalizer==2.0.12 docutils==0.16 idna==3.3 -- cgit v1.2.3 From 93685d0dcb9488013f5d2177f7659cc8852b6da6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 5 Dec 2022 21:03:36 -0500 Subject: Makefile: With BINMAN_ALLOW_MISSING=1 don't error on missing When the user builds with BINMAN_ALLOW_MISSING=1 they're explicitly setting the flag to allow for additional binaries to be missing and so have acknowledged the output might not work. In this case we want to default to not passing a non-zero exit code. Cc: Simon Glass Reported-by: Peter Robinson Signed-off-by: Tom Rini --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index de5746399a..03de1da1bf 100644 --- a/Makefile +++ b/Makefile @@ -1334,7 +1334,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \ --toolpath $(objtree)/tools \ $(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \ build -u -d u-boot.dtb -O . -m \ - $(if $(BINMAN_ALLOW_MISSING),--allow-missing --fake-ext-blobs) \ + $(if $(BINMAN_ALLOW_MISSING),--allow-missing --ignore-missing) \ -I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \ -I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \ $(foreach f,$(BINMAN_INDIRS),-I $(f)) \ -- cgit v1.2.3 From f5315dd6290a588434e4f79bfd2886bb7df9210d Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Sun, 18 Dec 2022 20:43:38 +0800 Subject: rockchip: Only call binman when TPL available Rockchip platform use TPL to do the DRAM initialize for all the SoCs, if TPL is not available, means no available DRAM init program, and the u-boot-rockchip.bin is not functionable. Signed-off-by: Kever Yang Change-Id: I2299f1eddce5aa7d5fb1a3fb4d8aeaa995b397fa --- arch/arm/dts/rockchip-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi index 584f21eb5b..fa094b0039 100644 --- a/arch/arm/dts/rockchip-u-boot.dtsi +++ b/arch/arm/dts/rockchip-u-boot.dtsi @@ -11,7 +11,7 @@ }; }; -#ifdef CONFIG_SPL +#ifdef CONFIG_TPL &binman { simple-bin { filename = "u-boot-rockchip.bin"; -- cgit v1.2.3 From 96d926cac37dd9f5d1dc750ac463bbcd733f26f5 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Sat, 10 Sep 2022 01:47:24 +0000 Subject: rockchip: enable fdt overlays for ROCK Pi 4 series add CONFIG_OF_LIBFDT_OVERLAY=y to support fdt overlays. Signed-off-by: FUKAUMI Naoki Reviewed-by: Kever Yang --- configs/rock-pi-4-rk3399_defconfig | 1 + configs/rock-pi-4c-rk3399_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 83721cedf3..8232c6fa15 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -84,3 +84,4 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index ac9a3f9830..0543dbe1a6 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -84,3 +84,4 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y +CONFIG_OF_LIBFDT_OVERLAY=y -- cgit v1.2.3 From 4d89330b8ac1852e14f079ead75021a17b4b744e Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 9 Sep 2022 22:18:45 +0200 Subject: rockchip: rk3128-cru: sync the clock dt-binding header from Linux In order to update the DT for rk3128 sync the clock dt-binding header. This is the state as of v6.0 in Linux. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/dts/rk3128.dtsi | 6 +- drivers/clk/rockchip/clk_rk3128.c | 8 +- include/dt-bindings/clock/rk3128-cru.h | 222 +++++++++++++++++++++++---------- 3 files changed, 160 insertions(+), 76 deletions(-) diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi index 5d2499c132..3c5f54f640 100644 --- a/arch/arm/dts/rk3128.dtsi +++ b/arch/arm/dts/rk3128.dtsi @@ -172,7 +172,7 @@ interrupts = , ; #dma-cells = <1>; - clocks = <&cru ACLK_DMAC2>; + clocks = <&cru ACLK_DMAC>; clock-names = "apb_pclk"; }; }; @@ -530,8 +530,8 @@ pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>; rockchip,spi-src-clk = <0>; num-cs = <2>; - clocks =<&cru SCLK_SPI>, <&cru PCLK_SPI>; - clock-names = "spi","pclk_spi0"; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; dmas = <&pdma 8>, <&pdma 9>; #dma-cells = <2>; dma-names = "tx", "rx"; diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c index d5b2b63dd7..13e176cdad 100644 --- a/drivers/clk/rockchip/clk_rk3128.c +++ b/drivers/clk/rockchip/clk_rk3128.c @@ -438,7 +438,7 @@ static ulong rk3128_vop_set_clk(struct rk3128_cru *cru, ulong clk_id, uint hz) VIO1_SEL_GPLL << VIO1_PLL_SHIFT | (src_clk_div - 1) << VIO1_DIV_SHIFT); break; - case DCLK_LCDC: + case DCLK_VOP: if (pll_para_config(hz, &cpll_config)) return -1; rkclk_set_pll(cru, CLK_CODEC, &cpll_config); @@ -471,7 +471,7 @@ static ulong rk3128_vop_get_rate(struct rk3128_cru *cru, ulong clk_id) div = (con >> 8) & 0x1f; parent = GPLL_HZ; break; - case DCLK_LCDC: + case DCLK_VOP: con = readl(&cru->cru_clksel_con[27]); div = (con >> 8) & 0xfff; parent = rkclk_pll_get_rate(cru, CLK_CODEC); @@ -497,7 +497,7 @@ static ulong rk3128_clk_get_rate(struct clk *clk) return rk3128_peri_get_pclk(priv->cru, clk->id); case SCLK_SARADC: return rk3128_saradc_get_clk(priv->cru); - case DCLK_LCDC: + case DCLK_VOP: case ACLK_VIO0: case ACLK_VIO1: return rk3128_vop_get_rate(priv->cru, clk->id); @@ -515,7 +515,7 @@ static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate) switch (clk->id) { case 0 ... 63: return 0; - case DCLK_LCDC: + case DCLK_VOP: case ACLK_VIO0: case ACLK_VIO1: new_rate = rk3128_vop_set_clk(priv->cru, diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h index cfb3afbb28..6a47825dac 100644 --- a/include/dt-bindings/clock/rk3128-cru.h +++ b/include/dt-bindings/clock/rk3128-cru.h @@ -1,6 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Author: Elaine */ #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H @@ -9,30 +10,31 @@ /* core clocks */ #define PLL_APLL 1 #define PLL_DPLL 2 -#define PLL_GPLL 3 -#define ARMCLK 4 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define ARMCLK 5 +#define PLL_GPLL_DIV2 6 +#define PLL_GPLL_DIV3 7 /* sclk gates (special clocks) */ -#define SCLK_GPU 64 -#define SCLK_SPI 65 +#define SCLK_SPI0 65 +#define SCLK_NANDC 67 #define SCLK_SDMMC 68 #define SCLK_SDIO 69 #define SCLK_EMMC 71 -#define SCLK_NANDC 76 #define SCLK_UART0 77 #define SCLK_UART1 78 #define SCLK_UART2 79 -#define SCLK_I2S 82 +#define SCLK_I2S0 80 +#define SCLK_I2S1 81 #define SCLK_SPDIF 83 #define SCLK_TIMER0 85 #define SCLK_TIMER1 86 #define SCLK_TIMER2 87 #define SCLK_TIMER3 88 +#define SCLK_TIMER4 89 +#define SCLK_TIMER5 90 #define SCLK_SARADC 91 -#define SCLK_OTGPHY0 93 -#define SCLK_LCDC 100 -#define SCLK_HDMI 109 -#define SCLK_HEVC 111 #define SCLK_I2S_OUT 113 #define SCLK_SDMMC_DRV 114 #define SCLK_SDIO_DRV 115 @@ -40,115 +42,173 @@ #define SCLK_SDMMC_SAMPLE 118 #define SCLK_SDIO_SAMPLE 119 #define SCLK_EMMC_SAMPLE 121 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_PVTM_VIDEO 125 -#define SCLK_MAC 151 -#define SCLK_MACREF 152 -#define SCLK_SFC 160 +#define SCLK_VOP 122 +#define SCLK_MAC_SRC 124 +#define SCLK_MAC 126 +#define SCLK_MAC_REFOUT 127 +#define SCLK_MAC_REF 128 +#define SCLK_MAC_RX 129 +#define SCLK_MAC_TX 130 +#define SCLK_HEVC_CORE 134 +#define SCLK_RGA 135 +#define SCLK_CRYPTO 138 +#define SCLK_TSP 139 +#define SCLK_OTGPHY0 142 +#define SCLK_OTGPHY1 143 +#define SCLK_DDRC 144 +#define SCLK_PVTM_FUNC 145 +#define SCLK_PVTM_CORE 146 +#define SCLK_PVTM_GPU 147 +#define SCLK_MIPI_24M 148 +#define SCLK_PVTM 149 +#define SCLK_CIF_SRC 150 +#define SCLK_CIF_OUT_SRC 151 +#define SCLK_CIF_OUT 152 +#define SCLK_SFC 153 +#define SCLK_USB480M 154 -#define DCLK_LCDC 190 +/* dclk gates */ +#define DCLK_VOP 190 +#define DCLK_EBC 191 /* aclk gates */ -#define ACLK_DMAC2 194 -#define ACLK_VIO0 197 -#define ACLK_VIO1 203 -#define ACLK_VCODEC 208 -#define ACLK_CPU 209 +#define ACLK_VIO0 192 +#define ACLK_VIO1 193 +#define ACLK_DMAC 194 +#define ACLK_CPU 195 +#define ACLK_VEPU 196 +#define ACLK_VDPU 197 +#define ACLK_CIF 198 +#define ACLK_IEP 199 +#define ACLK_LCDC0 204 +#define ACLK_RGA 205 #define ACLK_PERI 210 +#define ACLK_VOP 211 +#define ACLK_GMAC 212 +#define ACLK_GPU 213 /* pclk gates */ #define PCLK_SARADC 318 +#define PCLK_WDT 319 #define PCLK_GPIO0 320 #define PCLK_GPIO1 321 #define PCLK_GPIO2 322 #define PCLK_GPIO3 323 +#define PCLK_VIO_H2P 324 +#define PCLK_MIPI 325 +#define PCLK_EFUSE 326 +#define PCLK_HDMI 327 +#define PCLK_ACODEC 328 #define PCLK_GRF 329 #define PCLK_I2C0 332 #define PCLK_I2C1 333 #define PCLK_I2C2 334 #define PCLK_I2C3 335 -#define PCLK_SPI 338 +#define PCLK_SPI0 338 #define PCLK_UART0 341 #define PCLK_UART1 342 #define PCLK_UART2 343 +#define PCLK_TSADC 344 #define PCLK_PWM 350 #define PCLK_TIMER 353 -#define PCLK_HDMI 360 -#define PCLK_CPU 362 +#define PCLK_CPU 354 #define PCLK_PERI 363 -#define PCLK_DDRUPCTL 364 -#define PCLK_WDT 368 +#define PCLK_GMAC 367 +#define PCLK_PMU_PRE 368 +#define PCLK_SIM_CARD 369 /* hclk gates */ -#define HCLK_OTG0 449 -#define HCLK_OTG1 450 +#define HCLK_SPDIF 440 +#define HCLK_GPS 441 +#define HCLK_USBHOST 442 +#define HCLK_I2S_8CH 443 +#define HCLK_I2S_2CH 444 +#define HCLK_VOP 452 #define HCLK_NANDC 453 #define HCLK_SDMMC 456 #define HCLK_SDIO 457 #define HCLK_EMMC 459 -#define HCLK_I2S 462 -#define HCLK_LCDC 465 -#define HCLK_ROM 467 -#define HCLK_VIO_BUS 472 -#define HCLK_VCODEC 476 -#define HCLK_CPU 477 +#define HCLK_CPU 460 +#define HCLK_VEPU 461 +#define HCLK_VDPU 462 +#define HCLK_LCDC0 463 +#define HCLK_EBC 465 +#define HCLK_VIO 466 +#define HCLK_RGA 467 +#define HCLK_IEP 468 +#define HCLK_VIO_H2P 469 +#define HCLK_CIF 470 +#define HCLK_HOST2 473 +#define HCLK_OTG 474 +#define HCLK_TSP 475 +#define HCLK_CRYPTO 476 #define HCLK_PERI 478 #define CLK_NR_CLKS (HCLK_PERI + 1) /* soft-reset indices */ -#define SRST_CORE0 0 -#define SRST_CORE1 1 -#define SRST_CORE0_DBG 4 -#define SRST_CORE1_DBG 5 -#define SRST_CORE0_POR 8 -#define SRST_CORE1_POR 9 -#define SRST_L2C 12 -#define SRST_TOPDBG 13 +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_ACLK_CORE 13 #define SRST_STRC_SYS_A 14 -#define SRST_PD_CORE_NIU 15 +#define SRST_L2C 15 -#define SRST_TIMER2 16 -#define SRST_CPUSYS_H 17 -#define SRST_AHB2APB_H 19 -#define SRST_TIMER3 20 +#define SRST_CPUSYS_H 18 +#define SRST_AHB2APBSYS_H 19 +#define SRST_SPDIF 20 #define SRST_INTMEM 21 #define SRST_ROM 22 #define SRST_PERI_NIU 23 -#define SRST_I2S 24 -#define SRST_DDR_PLL 25 -#define SRST_GPU_DLL 26 -#define SRST_TIMER0 27 -#define SRST_TIMER1 28 -#define SRST_CORE_DLL 29 +#define SRST_I2S_2CH 24 +#define SRST_I2S_8CH 25 +#define SRST_GPU_PVTM 26 +#define SRST_FUNC_PVTM 27 +#define SRST_CORE_PVTM 29 #define SRST_EFUSE_P 30 #define SRST_ACODEC_P 31 #define SRST_GPIO0 32 #define SRST_GPIO1 33 #define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_MIPIPHY_P 36 #define SRST_UART0 39 #define SRST_UART1 40 #define SRST_UART2 41 #define SRST_I2C0 43 #define SRST_I2C1 44 #define SRST_I2C2 45 +#define SRST_I2C3 46 #define SRST_SFC 47 -#define SRST_PWM0 48 +#define SRST_PWM 48 +#define SRST_DAP_PO 50 #define SRST_DAP 51 #define SRST_DAP_SYS 52 +#define SRST_CRYPTO 53 #define SRST_GRF 55 -#define SRST_PERIPHSYS_A 57 -#define SRST_PERIPHSYS_H 58 -#define SRST_PERIPHSYS_P 59 +#define SRST_GMAC 56 +#define SRST_PERIPH_SYS_A 57 +#define SRST_PERIPH_SYS_H 58 +#define SRST_PERIPH_SYS_P 59 +#define SRST_SMART_CARD 60 #define SRST_CPU_PERI 61 #define SRST_EMEM_PERI 62 #define SRST_USB_PERI 63 -#define SRST_DMA2 64 -#define SRST_MAC 66 +#define SRST_DMA 64 +#define SRST_GPS 67 #define SRST_NANDC 68 #define SRST_USBOTG0 69 #define SRST_OTGC0 71 @@ -156,34 +216,58 @@ #define SRST_OTGC1 74 #define SRST_DDRMSCH 79 -#define SRST_MMC0 81 +#define SRST_SDMMC 81 #define SRST_SDIO 82 #define SRST_EMMC 83 -#define SRST_SPI0 84 +#define SRST_SPI 84 #define SRST_WDT 86 #define SRST_SARADC 87 #define SRST_DDRPHY 88 #define SRST_DDRPHY_P 89 #define SRST_DDRCTRL 90 #define SRST_DDRCTRL_P 91 +#define SRST_TSP 92 +#define SRST_TSP_CLKIN 93 +#define SRST_HOST0_ECHI 94 #define SRST_HDMI_P 96 +#define SRST_VIO_ARBI_H 97 +#define SRST_VIO0_A 98 #define SRST_VIO_BUS_H 99 +#define SRST_VOP_A 100 +#define SRST_VOP_H 101 +#define SRST_VOP_D 102 #define SRST_UTMI0 103 #define SRST_UTMI1 104 #define SRST_USBPOR 105 +#define SRST_IEP_A 106 +#define SRST_IEP_H 107 +#define SRST_RGA_A 108 +#define SRST_RGA_H 109 +#define SRST_CIF0 110 +#define SRST_PMU 111 #define SRST_VCODEC_A 112 #define SRST_VCODEC_H 113 #define SRST_VIO1_A 114 -#define SRST_HEVC 115 +#define SRST_HEVC_CORE 115 #define SRST_VCODEC_NIU_A 116 -#define SRST_LCDC1_A 117 -#define SRST_LCDC1_H 118 -#define SRST_LCDC1_D 119 +#define SRST_PMU_NIU_P 117 +#define SRST_LCDC0_S 119 #define SRST_GPU 120 #define SRST_GPU_NIU_A 122 +#define SRST_EBC_A 123 +#define SRST_EBC_H 124 -#define SRST_DBG_P 131 +#define SRST_CORE_DBG 128 +#define SRST_DBG_P 129 +#define SRST_TIMER0 130 +#define SRST_TIMER1 131 +#define SRST_TIMER2 132 +#define SRST_TIMER3 133 +#define SRST_TIMER4 134 +#define SRST_TIMER5 135 +#define SRST_VIO_H2P 136 +#define SRST_VIO_MIPI_DSI 137 #endif -- cgit v1.2.3 From c643468849730ccbdaaa79bbae972015cd5f0d4b Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 9 Sep 2022 22:18:55 +0200 Subject: arm: dts: rockchip: rk3128: bulk convert gpios to their constant counterparts Bulk convert rk3128 DT gpios to their constant counterparts. sed -i -f script.sed rk3128.dtsi sed -i -f script.sed rk3128-evb.dts ================================ /rockchip,pins *=/bcheck b # to end of script :append-next-line N :check /^[^;]*$/bappend-next-line s/ Reviewed-by: Kever Yang --- arch/arm/dts/rk3128-evb.dts | 4 +-- arch/arm/dts/rk3128.dtsi | 86 ++++++++++++++++++++++----------------------- 2 files changed, 45 insertions(+), 45 deletions(-) diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts index 2fb2b0da6d..a407ac2dc5 100644 --- a/arch/arm/dts/rk3128-evb.dts +++ b/arch/arm/dts/rk3128-evb.dts @@ -82,13 +82,13 @@ &pinctrl { usb_otg { otg_vbus_drv: host-vbus-drv { - rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb_host { host_vbus_drv: host-vbus-drv { - rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi index 3c5f54f640..5a1c154798 100644 --- a/arch/arm/dts/rk3128.dtsi +++ b/arch/arm/dts/rk3128.dtsi @@ -618,85 +618,85 @@ */ emmc_clk: emmc-clk { - rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; }; emmc_cmd: emmc-cmd { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; emmc_pwren: emmc-pwren { - rockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA5 2 &pcfg_pull_none>; }; emmc_bus8: emmc-bus8 { - rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, - <1 25 RK_FUNC_2 &pcfg_pull_none>, - <1 26 RK_FUNC_2 &pcfg_pull_none>, - <1 27 RK_FUNC_2 &pcfg_pull_none>, - <1 28 RK_FUNC_2 &pcfg_pull_none>, - <1 29 RK_FUNC_2 &pcfg_pull_none>, - <1 30 RK_FUNC_2 &pcfg_pull_none>, - <1 31 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, + <1 RK_PD1 2 &pcfg_pull_none>, + <1 RK_PD2 2 &pcfg_pull_none>, + <1 RK_PD3 2 &pcfg_pull_none>, + <1 RK_PD4 2 &pcfg_pull_none>, + <1 RK_PD5 2 &pcfg_pull_none>, + <1 RK_PD6 2 &pcfg_pull_none>, + <1 RK_PD7 2 &pcfg_pull_none>; }; }; nandc{ nandc_ale:nandc-ale { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_cle:nandc-cle { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_wrn:nandc-wrn { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_rdn:nandc-rdn { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_rdy:nandc-rdy { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_cs0:nandc-cs0 { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_data: nandc-data { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; }; uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, - <0 17 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>, + <0 RK_PC1 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; uart0_rts: uart0-rts { - rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, - <2 23 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>, + <2 RK_PC7 1 &pcfg_pull_none>; }; }; uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, - <1 19 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_none>, + <1 RK_PC3 2 &pcfg_pull_none>; }; }; @@ -727,75 +727,75 @@ pwm0 { pwm0_pin: pwm0-pin { - rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; }; }; pwm1 { pwm1_pin: pwm1-pin { - rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; }; }; pwm2 { pwm2_pin: pwm2-pin { - rockchip,pins = <0 1 2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; }; }; pwm3 { pwm3_pin: pwm3-pin { - rockchip,pins = <0 27 1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; }; }; i2c0 { i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, - <0 1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, + <0 RK_PA1 1 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, - <0 3 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, + <0 RK_PA3 1 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 20 3 &pcfg_pull_none>, - <2 21 3 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, + <2 RK_PC5 3 &pcfg_pull_none>; }; }; i2c3 { i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, - <0 7 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, + <0 RK_PA7 1 &pcfg_pull_none>; }; }; spi0 { spi0_txd_mux0:spi0-txd-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; spi0_rxd_mux0:spi0-rxd-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; spi0_clk_mux0:spi0-clk-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; spi0_cs0_mux0:spi0-cs0-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; spi0_cs1_mux0:spi0-cs1-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; }; -- cgit v1.2.3 From b919d43af563147523cd2816d26a03e927104b61 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 9 Sep 2022 22:19:06 +0200 Subject: arm: dts: rockchip: move all rk3128 u-boot specific properties in separate dtsi files Move all rk3128 u-boot specific properties in separate dtsi files. Sort emmc node. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/dts/rk3128-evb-u-boot.dtsi | 7 +++++++ arch/arm/dts/rk3128-evb.dts | 10 +++++----- arch/arm/dts/rk3128-u-boot.dtsi | 19 +++++++++++++++++++ arch/arm/dts/rk3128.dtsi | 9 --------- 4 files changed, 31 insertions(+), 14 deletions(-) create mode 100644 arch/arm/dts/rk3128-evb-u-boot.dtsi create mode 100644 arch/arm/dts/rk3128-u-boot.dtsi diff --git a/arch/arm/dts/rk3128-evb-u-boot.dtsi b/arch/arm/dts/rk3128-evb-u-boot.dtsi new file mode 100644 index 0000000000..8b16bbe41c --- /dev/null +++ b/arch/arm/dts/rk3128-evb-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3128-u-boot.dtsi" + +&emmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts index a407ac2dc5..e7d8f7c9e0 100644 --- a/arch/arm/dts/rk3128-evb.dts +++ b/arch/arm/dts/rk3128-evb.dts @@ -37,6 +37,11 @@ }; }; +&emmc { + fifo-mode; + status = "okay"; +}; + &i2c1 { status = "okay"; @@ -74,11 +79,6 @@ status = "okay"; }; -&emmc { - fifo-mode; - status = "okay"; -}; - &pinctrl { usb_otg { otg_vbus_drv: host-vbus-drv { diff --git a/arch/arm/dts/rk3128-u-boot.dtsi b/arch/arm/dts/rk3128-u-boot.dtsi new file mode 100644 index 0000000000..4a98e2496f --- /dev/null +++ b/arch/arm/dts/rk3128-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rockchip-u-boot.dtsi" + +/ { + dmc: dmc@20004000 { + compatible = "rockchip,rk3128-dmc", "syscon"; + reg = <0x0 0x20004000 0x0 0x1000>; + u-boot,dm-pre-reloc; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&grf { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi index 5a1c154798..b58804b644 100644 --- a/arch/arm/dts/rk3128.dtsi +++ b/arch/arm/dts/rk3128.dtsi @@ -237,14 +237,7 @@ clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc"; }; - dmc: dmc@20004000 { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3128-dmc", "syscon"; - reg = <0x0 0x20004000 0x0 0x1000>; - }; - cru: clock-controller@20000000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3128-cru"; reg = <0x20000000 0x1000>; rockchip,grf = <&grf>; @@ -453,7 +446,6 @@ }; emmc: dwmmc@1021c000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x1021c000 0x4000>; max-frequency = <150000000>; @@ -538,7 +530,6 @@ }; grf: syscon@20008000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3128-grf", "syscon"; reg = <0x20008000 0x1000>; }; -- cgit v1.2.3 From 565d77b4c0080ba1c64f860dabbddb021689c46b Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 9 Sep 2022 22:19:24 +0200 Subject: arm: dts: rockchip: rk3128: fix DT node names The rk3128 DT node names should be generic. Rename them to the pattern defined in the DT bindings. Signed-off-by: Johan Jonker --- arch/arm/dts/rk3128-evb.dts | 5 ++++ arch/arm/dts/rk3128.dtsi | 62 ++++++++++++++++++++------------------------- 2 files changed, 33 insertions(+), 34 deletions(-) diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts index e7d8f7c9e0..93291d7873 100644 --- a/arch/arm/dts/rk3128-evb.dts +++ b/arch/arm/dts/rk3128-evb.dts @@ -15,6 +15,11 @@ stdout-path = &uart2; }; + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + vcc5v0_otg: vcc5v0-otg-drv { compatible = "regulator-fixed"; regulator-name = "vcc5v0_otg"; diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi index b58804b644..48833bff9e 100644 --- a/arch/arm/dts/rk3128.dtsi +++ b/arch/arm/dts/rk3128.dtsi @@ -8,7 +8,6 @@ #include #include #include -#include "skeleton.dtsi" / { compatible = "rockchip,rk3128"; @@ -34,11 +33,6 @@ mmc1 = &sdmmc; }; - memory { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - arm-pmu { compatible = "arm,cortex-a7-pmu"; interrupts = , @@ -52,10 +46,10 @@ #size-cells = <0>; enable-method = "rockchip,rk3128-smp"; - cpu0:cpu@0x000 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; - reg = <0x000>; + reg = <0x0>; operating-points = < /* KHz uV */ 816000 1000000 @@ -65,22 +59,22 @@ clocks = <&cru ARMCLK>; }; - cpu1:cpu@0x001 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; - reg = <0x001>; + reg = <0x1>; }; - cpu2:cpu@0x002 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a7"; - reg = <0x002>; + reg = <0x2>; }; - cpu3:cpu@0x003 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a7"; - reg = <0x003>; + reg = <0x3>; }; }; @@ -165,7 +159,7 @@ interrupt-parent = <&gic>; ranges; - pdma: pdma@20078000 { + pdma: dma-controller@20078000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x20078000 0x4000>; arm,pl330-broken-no-flushp;//2 @@ -207,7 +201,7 @@ rockchip,broadcast = <1>; }; - watchdog: wdt@2004c000 { + watchdog: watchdog@2004c000 { compatible = "rockchip,watch dog"; reg = <0x2004c000 0x100>; clock-names = "pclk_wdt"; @@ -224,7 +218,7 @@ #reset-cells = <1>; }; - nandc: nandc@10500000 { + nandc: nand-controller@10500000 { compatible = "rockchip,rk-nandc"; reg = <0x10500000 0x4000>; interrupts = ; @@ -247,7 +241,7 @@ assigned-clock-rates = <594000000>; }; - uart0: serial0@20060000 { + uart0: serial@20060000 { compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; reg = <0x20060000 0x100>; interrupts = ; @@ -262,7 +256,7 @@ #dma-cells = <2>; }; - uart1: serial1@20064000 { + uart1: serial@20064000 { compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; reg = <0x20064000 0x100>; interrupts = ; @@ -277,7 +271,7 @@ #dma-cells = <2>; }; - uart2: serial2@20068000 { + uart2: serial@20068000 { compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; reg = <0x20068000 0x100>; interrupts = ; @@ -304,7 +298,7 @@ status = "disabled"; }; - pwm0: pwm0@20050000 { + pwm0: pwm@20050000 { compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; reg = <0x20050000 0x10>; #pwm-cells = <3>; @@ -314,7 +308,7 @@ clock-names = "pwm"; }; - pwm1: pwm1@20050010 { + pwm1: pwm@20050010 { compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; reg = <0x20050010 0x10>; #pwm-cells = <3>; @@ -324,7 +318,7 @@ clock-names = "pwm"; }; - pwm2: pwm2@20050020 { + pwm2: pwm@20050020 { compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; reg = <0x20050020 0x10>; #pwm-cells = <3>; @@ -334,7 +328,7 @@ clock-names = "pwm"; }; - pwm3: pwm3@20050030 { + pwm3: pwm@20050030 { compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; reg = <0x20050030 0x10>; #pwm-cells = <3>; @@ -430,7 +424,7 @@ status = "disabled"; }; - sdmmc: dwmmc@10214000 { + sdmmc: mmc@10214000 { compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10214000 0x4000>; max-frequency = <150000000>; @@ -445,7 +439,7 @@ status = "disabled"; }; - emmc: dwmmc@1021c000 { + emmc: mmc@1021c000 { compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x1021c000 0x4000>; max-frequency = <150000000>; @@ -464,7 +458,7 @@ status = "disabled"; }; - i2c0: i2c0@20072000 { + i2c0: i2c@20072000 { compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; reg = <20072000 0x1000>; interrupts = ; @@ -476,7 +470,7 @@ pinctrl-0 = <&i2c0_xfer>; }; - i2c1: i2c1@20056000 { + i2c1: i2c@20056000 { compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; reg = <0x20056000 0x1000>; interrupts = ; @@ -488,7 +482,7 @@ pinctrl-0 = <&i2c1_xfer>; }; - i2c2: i2c2@2005a000 { + i2c2: i2c@2005a000 { compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; reg = <0x2005a000 0x1000>; interrupts = ; @@ -500,7 +494,7 @@ pinctrl-0 = <&i2c2_xfer>; }; - i2c3: i2c3@2005e000 { + i2c3: i2c@2005e000 { compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; reg = <0x2005e000 0x1000>; interrupts = ; @@ -546,7 +540,7 @@ #size-cells = <1>; ranges; - gpio0: gpio0@2007c000 { + gpio0: gpio@2007c000 { compatible = "rockchip,gpio-bank"; reg = <0x2007c000 0x100>; interrupts = ; @@ -557,7 +551,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@20080000 { + gpio1: gpio@20080000 { compatible = "rockchip,gpio-bank"; reg = <0x20080000 0x100>; interrupts = ; @@ -568,7 +562,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@20084000 { + gpio2: gpio@20084000 { compatible = "rockchip,gpio-bank"; reg = <0x20084000 0x100>; interrupts = ; @@ -579,7 +573,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio2@20088000 { + gpio3: gpio@20088000 { compatible = "rockchip,gpio-bank"; reg = <0x20088000 0x100>; interrupts = ; -- cgit v1.2.3 From 58eb6675da63ab95601cb279a54d69b0a8a35e56 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 9 Sep 2022 22:20:07 +0200 Subject: arm: dts: rockchip: rk3128: fix clocks, compatible and phys Fix rk3128 clocks, compatible and phys, so that they match the bindings. Signed-off-by: Johan Jonker --- arch/arm/dts/rk3128.dtsi | 46 +++++++++++++++++++--------------------------- 1 file changed, 19 insertions(+), 27 deletions(-) diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi index 48833bff9e..3253c64034 100644 --- a/arch/arm/dts/rk3128.dtsi +++ b/arch/arm/dts/rk3128.dtsi @@ -180,7 +180,6 @@ xin12m: xin12m { compatible = "fixed-clock"; - clocks = <&xin24m>; clock-frequency = <12000000>; clock-output-names = "xin12m"; #clock-cells = <0>; @@ -202,9 +201,9 @@ }; watchdog: watchdog@2004c000 { - compatible = "rockchip,watch dog"; + compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; reg = <0x2004c000 0x100>; - clock-names = "pclk_wdt"; + clocks = <&cru PCLK_WDT>; interrupts = ; rockchip,irq = <1>; rockchip,timeout = <60>; @@ -219,21 +218,20 @@ }; nandc: nand-controller@10500000 { - compatible = "rockchip,rk-nandc"; + compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; reg = <0x10500000 0x4000>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>; - nandc_id = <0>; - clocks = <&cru SCLK_NANDC>, - <&cru HCLK_NANDC>, - <&cru SRST_NANDC>; - clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc"; + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; + clock-names = "ahb", "nfc"; }; cru: clock-controller@20000000 { compatible = "rockchip,rk3128-cru"; reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; @@ -305,7 +303,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; }; pwm1: pwm@20050010 { @@ -315,7 +312,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pwm1_pin>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; }; pwm2: pwm@20050020 { @@ -325,7 +321,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pwm2_pin>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; }; pwm3: pwm@20050030 { @@ -335,7 +330,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pwm3_pin>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; }; sram: sram@10080400 { @@ -364,7 +358,7 @@ interrupts = ; }; - u2phy: usb2-phy { + u2phy: usb2phy { compatible = "rockchip,rk3128-usb2phy"; reg = <0x017c 0x0c>; rockchip,grf = <&grf>; @@ -372,7 +366,6 @@ clock-names = "phyclk"; #clock-cells = <0>; clock-output-names = "usb480m_phy"; - #phy-cells = <1>; status = "disabled"; u2phy_otg: otg-port { @@ -394,15 +387,14 @@ }; usb_otg: usb@10180000 { - compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb", - "snps,dwc2"; + compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; reg = <0x10180000 0x40000>; interrupts = ; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; dr_mode = "otg"; - g-use-dma; - hnp-srp-disable; - phys = <&u2phy 0>; - phy-names = "usb"; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; status = "disabled"; }; @@ -410,7 +402,7 @@ compatible = "generic-ehci"; reg = <0x101c0000 0x20000>; interrupts = ; - phys = <&u2phy 1>; + phys = <&u2phy_host>; phy-names = "usb"; status = "disabled"; }; @@ -419,19 +411,19 @@ compatible = "generic-ohci"; reg = <0x101e0000 0x20000>; interrupts = ; - phys = <&u2phy 1>; + phys = <&u2phy_host>; phy-names = "usb"; status = "disabled"; }; sdmmc: mmc@10214000 { - compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; + compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10214000 0x4000>; max-frequency = <150000000>; interrupts = ; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; @@ -446,7 +438,7 @@ interrupts = ; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; bus-width = <8>; default-sample-phase = <158>; num-slots = <1>; @@ -507,7 +499,7 @@ }; spi0: spi@20074000 { - compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi"; + compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; reg = <0x20074000 0x1000>; interrupts = ; #address-cells = <1>; -- cgit v1.2.3 From 22e443c76dcaf3957c99f44abf17a421c7975bdd Mon Sep 17 00:00:00 2001 From: Manoj Sai Date: Thu, 15 Sep 2022 12:53:19 +0530 Subject: configs:rockchip:roc-rk3399-pc:Enable more configs This patch enables the following: 1) use preboot configuration to enable usb devices. 2) Enable USB configs so keyboards and other USB devices work, update the number of ports of the usb root hub. - with this addition the updated USB device Tree: 1 Hub (12 Mb/s, 0mA) U-Boot Root Hub 1 Hub (12 Mb/s, 0mA) | U-Boot Root Hub | +-2 Hub (12 Mb/s, 100mA) USB 2.0 Hub [MTT] 1 Hub (5 Gb/s, 0mA) U-Boot XHCI Host Controller 3) enable crypto RNG support. 4) Change SPI speed and frequency: - increase the maximum SPI slave device speed, SPI flash max frequency for the environment from 10Mhz to 30MHz. - performance stats for speed update from 10MHz to 30MHz: with 10Mhz speed update: => sf update 0x300000 0x800000 0x400000 4194304 bytes written, 0 bytes skipped in 36.819s, speed 119837 B/s with 30Mhz speed update: => sf update 0x300000 0x800000 0x400000 4194304 bytes written, 0 bytes skipped in 20.319s, speed 220752 B/s Signed-off-by: Manoj Sai Signed-off-by: Da Xue Signed-off-by: dsx724 Reviewed-by: Kever Yang --- configs/roc-pc-rk3399_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index e03442afa4..cf354fd15f 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -20,6 +20,7 @@ CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 @@ -44,6 +45,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SPI_MAX_HZ=30000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y @@ -54,6 +56,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_WINBOND=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y @@ -66,6 +69,8 @@ CONFIG_PWM_ROCKCHIP=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SPI=y @@ -75,6 +80,9 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_KEYBOARD=y -- cgit v1.2.3 From 75a364eb05c3fe8482dbdad9e90347238c4e529b Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Wed, 19 Oct 2022 07:12:52 +0000 Subject: arm: dts: rockchip: enable ums/rockusb command for ROCK Pi 4 this patch add USB mass storage function and Rockusb function for Radxa ROCK Pi 4 series. Signed-off-by: FUKAUMI Naoki Reviewed-by: Kever Yang --- configs/rock-pi-4-rk3399_defconfig | 3 +++ configs/rock-pi-4c-rk3399_defconfig | 3 +++ 2 files changed, 6 insertions(+) diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 8232c6fa15..e77d7cf4dd 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -34,6 +34,8 @@ CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y @@ -78,6 +80,7 @@ CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index 0543dbe1a6..86ed03da71 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -34,6 +34,8 @@ CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y @@ -78,6 +80,7 @@ CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y -- cgit v1.2.3 From c74f6e748b360b0c88404ce200bc97055c2aef44 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Tue, 25 Oct 2022 12:58:02 +0200 Subject: rockchip: puma: fix GPT table corruption when saving U-Boot environment The GPT table is taking the first 34 sectors, which amounts to 0x4400 bytes. Saving the environment below this address in storage will corrupt the GPT table. While technically the table ends at 0x4400, some tools (e.g. bmaptool) are rounding everything to the logical block size (0x1000), so it is safer to make it point to 0x5000 so that the environment could still persist when flashing a sparse image with bmaptool or similar tools. Obviously, the default 0x4000 environment size does not work anymore, so let's set it to 0x3000 so it does fill the gap between the GPT table (rounded to 0x1000) and the start of the idbloader.img. Fixes: 56f580d3eb8d ("rockchip: dts: rk3399-puma: put environment (in MMC/SD configurations) before SPL") Cc: Quentin Schulz Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 2 +- configs/puma-rk3399_defconfig | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi index f8335c74a7..d2349ae90e 100644 --- a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi +++ b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi @@ -15,7 +15,7 @@ / { config { u-boot,spl-payload-offset = <0x80000>; /* @ 512KB */ - u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */ + u-boot,mmc-env-offset = <0x5000>; /* @ 20KB */ u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */ u-boot,boot-led = "module_led"; sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index c2b0b39c7b..0e77db66db 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -5,6 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x3000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-haikou" CONFIG_ROCKCHIP_RK3399=y -- cgit v1.2.3 From 216928c772798609ba2cb01a42b6f89832bb0587 Mon Sep 17 00:00:00 2001 From: Michal Suchanek Date: Sat, 3 Dec 2022 13:31:29 +0100 Subject: rockchip: Pinebook Pro: Do not initialize i2c before relocation The i2c locks up when initialized before relocation, and it stays broken in Linux as well breaking the ability to boot Linux. The i2c bus and pmic was not actually used in pre-reloc before commit ad607512f575 ("power: pmic: rk8xx: Support sysreset shutdown method") The cause is not known. This is board-specific, other boards that do not add the option to include the i2c bus in pre-reloc DT are not affected. Signed-off-by: Michal Suchanek Reviewed-by: Peter Robinson Tested-by: Peter Robinson Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi index 2d87bea933..fd87102c0b 100644 --- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi @@ -20,14 +20,6 @@ rockchip,panel = <&edp_panel>; }; -&i2c0 { - u-boot,dm-pre-reloc; -}; - -&rk808 { - u-boot,dm-pre-reloc; -}; - &sdhci { max-frequency = <25000000>; u-boot,dm-pre-reloc; -- cgit v1.2.3 From b5194c22585d1f3869b2126a87dabecb5ef2627e Mon Sep 17 00:00:00 2001 From: John Keeping Date: Tue, 6 Dec 2022 12:48:55 +0000 Subject: phy: rockchip: handle clock without enable function If a clock doesn't supply the enable hook, clk_enable() will return -ENOSYS. In this case the clock is always enabled so there is no error and the phy initialisation should continue. Signed-off-by: John Keeping Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 62b8ba3a4a..b32a498ea7 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -119,7 +119,7 @@ static int rockchip_usb2phy_init(struct phy *phy) int ret; ret = clk_enable(&priv->phyclk); - if (ret) { + if (ret && ret != -ENOSYS) { dev_err(phy->dev, "failed to enable phyclk (ret=%d)\n", ret); return ret; } -- cgit v1.2.3 From bea9267d7e6dbeea6afec1cf44d0b3cfee9eb210 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Thu, 10 Nov 2022 14:49:15 +0530 Subject: rockchip: capsule: Add functions for supporting capsule updates Add functions needed to support the UEFI capsule update feature on rockchip boards. Currently, the feature is being enabled on the RockPi4 boards with firmware images residing on GPT partitioned storage media. Signed-off-by: Sughosh Ganu Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/board.c | 153 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 154 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 69d51ff378..4898260017 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -246,6 +246,7 @@ config ROCKCHIP_RK3399 select DM_PMIC select DM_REGULATOR_FIXED select BOARD_LATE_INIT + imply PARTITION_TYPE_GUID imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_SDRAM_COMMON diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index cbe00d646c..6e05a8f76e 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -6,11 +6,15 @@ #include #include #include +#include #include #include #include +#include +#include #include #include +#include #include #include #include @@ -22,8 +26,157 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION) + +#define DFU_ALT_BUF_LEN SZ_1K + +static struct efi_fw_image *fw_images; + +static bool updatable_image(struct disk_partition *info) +{ + int i; + bool ret = false; + efi_guid_t image_type_guid; + + uuid_str_to_bin(info->type_guid, image_type_guid.b, + UUID_STR_FORMAT_GUID); + + for (i = 0; i < num_image_type_guids; i++) { + if (!guidcmp(&fw_images[i].image_type_id, &image_type_guid)) { + ret = true; + break; + } + } + + return ret; +} + +static void set_image_index(struct disk_partition *info, int index) +{ + int i; + efi_guid_t image_type_guid; + + uuid_str_to_bin(info->type_guid, image_type_guid.b, + UUID_STR_FORMAT_GUID); + + for (i = 0; i < num_image_type_guids; i++) { + if (!guidcmp(&fw_images[i].image_type_id, &image_type_guid)) { + fw_images[i].image_index = index; + break; + } + } +} + +static int get_mmc_desc(struct blk_desc **desc) +{ + int ret; + struct mmc *mmc; + struct udevice *dev; + + /* + * For now the firmware images are assumed to + * be on the SD card + */ + ret = uclass_get_device(UCLASS_MMC, 1, &dev); + if (ret) + return -1; + + mmc = mmc_get_mmc_dev(dev); + if (!mmc) + return -ENODEV; + + if ((ret = mmc_init(mmc))) + return ret; + + *desc = mmc_get_blk_desc(mmc); + if (!*desc) + return -1; + + return 0; +} + +void set_dfu_alt_info(char *interface, char *devstr) +{ + const char *name; + bool first = true; + int p, len, devnum, ret; + char buf[DFU_ALT_BUF_LEN]; + struct disk_partition info; + struct blk_desc *desc = NULL; + + ret = get_mmc_desc(&desc); + if (ret) { + log_err("Unable to get mmc desc\n"); + return; + } + + memset(buf, 0, sizeof(buf)); + name = blk_get_uclass_name(desc->uclass_id); + devnum = desc->devnum; + len = strlen(buf); + + len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, + "%s %d=", name, devnum); + + for (p = 1; p <= MAX_SEARCH_PARTITIONS; p++) { + if (part_get_info(desc, p, &info)) + continue; + + /* Add entry to dfu_alt_info only for updatable images */ + if (updatable_image(&info)) { + if (!first) + len += snprintf(buf + len, + DFU_ALT_BUF_LEN - len, ";"); + + len += snprintf(buf + len, DFU_ALT_BUF_LEN - len, + "%s%d_%s part %d %d", + name, devnum, info.name, devnum, p); + first = false; + } + } + + log_debug("dfu_alt_info => %s\n", buf); + env_set("dfu_alt_info", buf); +} + +static void gpt_capsule_update_setup(void) +{ + int p, i, ret; + struct disk_partition info; + struct blk_desc *desc = NULL; + + fw_images = update_info.images; + rockchip_capsule_update_board_setup(); + + ret = get_mmc_desc(&desc); + if (ret) { + log_err("Unable to get mmc desc\n"); + return; + } + + for (p = 1, i = 1; p <= MAX_SEARCH_PARTITIONS; p++) { + if (part_get_info(desc, p, &info)) + continue; + + /* + * Since we have a GPT partitioned device, the updatable + * images could be stored in any order. Populate the + * image_index at runtime. + */ + if (updatable_image(&info)) { + set_image_index(&info, i); + i++; + } + } +} +#endif /* CONFIG_EFI_HAVE_CAPSULE_SUPPORT && CONFIG_EFI_PARTITION */ + __weak int rk_board_late_init(void) { +#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION) + gpt_capsule_update_setup(); +#endif + return 0; } -- cgit v1.2.3 From e86c789ca372b52e5872d9c9d5081be420cc4b6b Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Thu, 10 Nov 2022 14:49:16 +0530 Subject: rockpi4: board: Add firmware image information for capsule updates Add information that will be needed for enabling the UEFI capsule update feature on the RockPi4 boards. With the feature enabled, it would be possible to update the idbloader and u-boot.itb images on the RockPi4B and RockPi4C variants. Signed-off-by: Sughosh Ganu Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/misc.h | 1 + board/rockchip/evb_rk3399/evb-rk3399.c | 55 ++++++++++++++++++++++++++++++- include/configs/rk3399_common.h | 16 +++++++++ 3 files changed, 71 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-rockchip/misc.h b/arch/arm/include/asm/arch-rockchip/misc.h index b6b03c934e..4155af8c3b 100644 --- a/arch/arm/include/asm/arch-rockchip/misc.h +++ b/arch/arm/include/asm/arch-rockchip/misc.h @@ -11,3 +11,4 @@ int rockchip_cpuid_from_efuse(const u32 cpuid_offset, u8 *cpuid); int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length); int rockchip_setup_macaddr(void); +void rockchip_capsule_update_board_setup(void); diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index abb76585cf..f56b379b93 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -5,11 +5,25 @@ #include #include +#include #include #include #include +#include #include +#define ROCKPI4_UPDATABLE_IMAGES 2 + +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +static struct efi_fw_image fw_images[ROCKPI4_UPDATABLE_IMAGES] = {0}; + +struct efi_capsule_update_info update_info = { + .images = fw_images, +}; + +u8 num_image_type_guids = ROCKPI4_UPDATABLE_IMAGES; +#endif + #ifndef CONFIG_SPL_BUILD int board_early_init_f(void) { @@ -29,4 +43,43 @@ int board_early_init_f(void) out: return 0; } -#endif + +#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION) +static bool board_is_rockpi_4b(void) +{ + return CONFIG_IS_ENABLED(TARGET_EVB_RK3399) && + of_machine_is_compatible("radxa,rockpi4b"); +} + +static bool board_is_rockpi_4c(void) +{ + return CONFIG_IS_ENABLED(TARGET_EVB_RK3399) && + of_machine_is_compatible("radxa,rockpi4c"); +} + +void rockchip_capsule_update_board_setup(void) +{ + if (board_is_rockpi_4b()) { + efi_guid_t idbldr_image_type_guid = + ROCKPI_4B_IDBLOADER_IMAGE_GUID; + efi_guid_t uboot_image_type_guid = ROCKPI_4B_UBOOT_IMAGE_GUID; + + guidcpy(&fw_images[0].image_type_id, &idbldr_image_type_guid); + guidcpy(&fw_images[1].image_type_id, &uboot_image_type_guid); + + fw_images[0].fw_name = u"ROCKPI4B-IDBLOADER"; + fw_images[1].fw_name = u"ROCKPI4B-UBOOT"; + } else if (board_is_rockpi_4c()) { + efi_guid_t idbldr_image_type_guid = + ROCKPI_4C_IDBLOADER_IMAGE_GUID; + efi_guid_t uboot_image_type_guid = ROCKPI_4C_UBOOT_IMAGE_GUID; + + guidcpy(&fw_images[0].image_type_id, &idbldr_image_type_guid); + guidcpy(&fw_images[1].image_type_id, &uboot_image_type_guid); + + fw_images[0].fw_name = u"ROCKPI4C-IDBLOADER"; + fw_images[1].fw_name = u"ROCKPI4C-UBOOT"; + } +} +#endif /* CONFIG_EFI_HAVE_CAPSULE_SUPPORT && CONFIG_EFI_PARTITION */ +#endif /* !CONFIG_SPL_BUILD */ diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 2f9aee5819..f0a9ab8f83 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -24,6 +24,22 @@ #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf8000000 +#define ROCKPI_4B_IDBLOADER_IMAGE_GUID \ + EFI_GUID(0x02f4d760, 0xcfd5, 0x43bd, 0x8e, 0x2d, \ + 0xa4, 0x2a, 0xcb, 0x33, 0xc6, 0x60) + +#define ROCKPI_4B_UBOOT_IMAGE_GUID \ + EFI_GUID(0x4ce292da, 0x1dd8, 0x428d, 0xa1, 0xc2, \ + 0x77, 0x74, 0x3e, 0xf8, 0xb9, 0x6e) + +#define ROCKPI_4C_IDBLOADER_IMAGE_GUID \ + EFI_GUID(0xfd68510c, 0x12d3, 0x4f0a, 0xb8, 0xd3, \ + 0xd8, 0x79, 0xe1, 0xd3, 0xa5, 0x40) + +#define ROCKPI_4C_UBOOT_IMAGE_GUID \ + EFI_GUID(0xb81fb4ae, 0xe4f3, 0x471b, 0x99, 0xb4, \ + 0x0b, 0x3d, 0xa5, 0x49, 0xce, 0x13) + #ifndef CONFIG_SPL_BUILD #define ENV_MEM_LAYOUT_SETTINGS \ -- cgit v1.2.3 From bdd3a47e025759549dcbfe2ea549e458e3b767d0 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Thu, 10 Nov 2022 14:49:17 +0530 Subject: rockpi4: capsule: Enable UEFI capsule update on RockPi4 boards Enable the UEFI capsule update functionality on the RockPi4B and RockPi4C boards. Support is being enabled for updating the idbloader and u-boot firmware images residing on GPT partitioned uSD card storage device. Signed-off-by: Sughosh Ganu Reviewed-by: Kever Yang --- configs/rock-pi-4-rk3399_defconfig | 8 ++++++++ configs/rock-pi-4c-rk3399_defconfig | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index e77d7cf4dd..7dc5f5fa36 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y @@ -42,6 +43,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y @@ -88,3 +90,9 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_TOOLS_MKEFICAPSULE=y +CONFIG_HEXDUMP=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index 86ed03da71..45f8958f90 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_TPL=y CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y @@ -42,6 +43,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y @@ -88,3 +90,9 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_TOOLS_MKEFICAPSULE=y +CONFIG_HEXDUMP=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y -- cgit v1.2.3 From 2243922edca9f56a9d5519b9d6e36f5d7a18434d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 19 Dec 2022 08:45:26 -0500 Subject: Prepare v2023.01-rc4 Signed-off-by: Tom Rini --- Makefile | 2 +- doc/develop/release_cycle.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 03de1da1bf..c977c906b0 100644 --- a/Makefile +++ b/Makefile @@ -3,7 +3,7 @@ VERSION = 2023 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc3 +EXTRAVERSION = -rc4 NAME = # *DOCUMENTATION* diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 6ee67ef445..9af63731cd 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -69,7 +69,7 @@ For the next scheduled release, release candidates were made on:: * U-Boot v2023.01-rc3 was released on Mon 05 December 2022. -.. * U-Boot v2023.01-rc4 was released on Mon 05 December 2022. +* U-Boot v2023.01-rc4 was released on Mon 19 December 2022. .. * U-Boot v2023.01-rc5 was released on Mon 19 December 2022. -- cgit v1.2.3