From a339f5249d6ad5ea8201d7513c05fa580244dabd Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Thu, 28 Mar 2019 22:27:53 +0100 Subject: socfpga: add Simon Goldschmidt as co-custodian This updates MAINTAINERS and git-mailrc to add me as a co-custodian for socfpga. Signed-off-by: Simon Goldschmidt Acked-by: Stefan Roese Acked-by: Marek Vasut --- MAINTAINERS | 1 + doc/git-mailrc | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index b9cb686a05..d293cc6f7f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -90,6 +90,7 @@ F: cmd/arm/ ARM ALTERA SOCFPGA M: Marek Vasut +M: Simon Goldschmidt S: Maintainted T: git git://git.denx.de/u-boot-socfpga.git F: arch/arm/mach-socfpga/ diff --git a/doc/git-mailrc b/doc/git-mailrc index f989792e8d..13137017fe 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -37,6 +37,7 @@ alias monstr Michal Simek alias prom Minkyu Kang alias ptomsich Philipp Tomsich alias sbabic Stefano Babic +alias simongoldschmidt Simon Goldschmidt alias sjg Simon Glass alias smcnutt Scott McNutt alias stroese Stefan Roese @@ -62,7 +63,7 @@ alias s3c samsung alias s5pc samsung alias samsung uboot, prom alias snapdragon uboot, mateusz -alias socfpga uboot, marex, dinh +alias socfpga uboot, marex, dinh, simongoldschmidt alias sunxi uboot, jagan, maxime alias tegra uboot, sjg, Tom Warren , Stephen Warren alias tegra2 tegra -- cgit v1.2.3 From 4f25617758b2e768e6579202269180c5b7a817eb Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Tue, 26 Mar 2019 13:38:52 +0100 Subject: eeprom: fix DM_I2C support without CONFIG_SYS_I2C_EEPROM_BUS The current device model enabled eeprom code only works if CONFIG_SYS_I2C_EEPROM_BUS is set. This patch makes it work without that define so that the bus number passed to 'eeprom_init' is used. Signed-off-by: Simon Goldschmidt Reviewed-by: Heiko Schocher --- cmd/eeprom.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/cmd/eeprom.c b/cmd/eeprom.c index 6c29b33ba3..7b1f81477f 100644 --- a/cmd/eeprom.c +++ b/cmd/eeprom.c @@ -59,6 +59,10 @@ #endif #endif +#if defined(CONFIG_DM_I2C) +int eeprom_i2c_bus; +#endif + __weak int eeprom_write_enable(unsigned dev_addr, int state) { return 0; @@ -67,7 +71,9 @@ __weak int eeprom_write_enable(unsigned dev_addr, int state) void eeprom_init(int bus) { /* I2C EEPROM */ -#if defined(CONFIG_SYS_I2C) +#if defined(CONFIG_DM_I2C) + eeprom_i2c_bus = bus; +#elif defined(CONFIG_SYS_I2C) if (bus >= 0) i2c_set_bus_num(bus); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); @@ -124,14 +130,14 @@ static int eeprom_rw_block(unsigned offset, uchar *addr, unsigned alen, { int ret = 0; -#if defined(CONFIG_DM_I2C) && defined(CONFIG_SYS_I2C_EEPROM_BUS) +#if defined(CONFIG_DM_I2C) struct udevice *dev; - ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_EEPROM_BUS, addr[0], + ret = i2c_get_chip_for_busnum(eeprom_i2c_bus, addr[0], alen - 1, &dev); if (ret) { printf("%s: Cannot find udev for a bus %d\n", __func__, - CONFIG_SYS_I2C_EEPROM_BUS); + eeprom_i2c_bus); return CMD_RET_FAILURE; } @@ -141,15 +147,12 @@ static int eeprom_rw_block(unsigned offset, uchar *addr, unsigned alen, ret = dm_i2c_write(dev, offset, buffer, len); #else /* Non DM I2C support - will be removed */ -#if defined(CONFIG_SYS_I2C_EEPROM_BUS) - i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS); -#endif if (read) ret = i2c_read(addr[0], offset, alen - 1, buffer, len); else ret = i2c_write(addr[0], offset, alen - 1, buffer, len); -#endif /* CONFIG_DM_I2C && CONFIG_SYS_I2C_EEPROM_BUS */ +#endif /* CONFIG_DM_I2C */ if (ret) ret = CMD_RET_FAILURE; @@ -164,6 +167,10 @@ static int eeprom_rw(unsigned dev_addr, unsigned offset, uchar *buffer, int rcode = 0; uchar addr[3]; +#if defined(CONFIG_SYS_I2C_EEPROM_BUS) + eeprom_init(CONFIG_SYS_I2C_EEPROM_BUS); +#endif + while (offset < end) { alen = eeprom_addr(dev_addr, offset, addr); -- cgit v1.2.3 From bbecfd4cf2a8f7baeef6037303b8b4380a71aa12 Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Tue, 26 Mar 2019 13:38:53 +0100 Subject: Revert "cmd: Kconfig: Do not include EEPROM if DM_I2C is used without DM_I2C_COMPAT" This reverts commit 65a97e7fcf54feb7c4ebe1aee8a572830af4cf51. The 'eeprom' command has been converted to work with DM_I2C in a patch submitted around the same time as this commit: commit 0c07a9b4078d ("eeprom: Add device model based I2C support to eeprom command") Signed-off-by: Simon Goldschmidt Reviewed-by: Simon Glass Reviewed-by: Heiko Schocher --- cmd/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/cmd/Kconfig b/cmd/Kconfig index 5d1999ee0b..31ca7a2d02 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -455,7 +455,6 @@ config CRC32_VERIFY config CMD_EEPROM bool "eeprom - EEPROM subsystem" - depends on !DM_I2C || DM_I2C_COMPAT help (deprecated, needs conversion to driver model) Provides commands to read and write EEPROM (Electrically Erasable -- cgit v1.2.3 From 36821b3f55adc26c593520d8c207eea36c5c264a Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Thu, 28 Mar 2019 21:11:48 +0100 Subject: i2c: designware: fix reset handling on socfpga gen5 Using this driver on socfpga gen5 with DM_I2C enabled leads to a data abort as the 'i2c' reset property cannot be found (the gen5 dtsi does not provide reset-names). The actual bug was to check 'if (&priv->reset_ctl)', which is never false. While at it, convert the driver to use 'reset_get_bulk' instead of looking at a specific named reset and also make it release the reset on driver remove before starting the OS. Fixes: 622597dee4f6 ("i2c: designware: add reset ctrl to driver") Signed-off-by: Simon Goldschmidt Reviewed-by: Heiko Schocher --- drivers/i2c/designware_i2c.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 63e40823f1..9ccc2411a6 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -34,7 +34,7 @@ static struct dw_scl_sda_cfg byt_config = { struct dw_i2c { struct i2c_regs *regs; struct dw_scl_sda_cfg *scl_sda_cfg; - struct reset_ctl reset_ctl; + struct reset_ctl_bulk resets; }; #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED @@ -562,16 +562,22 @@ static int designware_i2c_probe(struct udevice *bus) priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus); } - ret = reset_get_by_name(bus, "i2c", &priv->reset_ctl); + ret = reset_get_bulk(bus, &priv->resets); if (ret) - pr_info("reset_get_by_name() failed: %d\n", ret); - - if (&priv->reset_ctl) - reset_deassert(&priv->reset_ctl); + dev_warn(bus, "Can't get reset: %d\n", ret); + else + reset_deassert_bulk(&priv->resets); return __dw_i2c_init(priv->regs, 0, 0); } +static int designware_i2c_remove(struct udevice *dev) +{ + struct dw_i2c *priv = dev_get_priv(dev); + + return reset_release_bulk(&priv->resets); +} + static int designware_i2c_bind(struct udevice *dev) { static int num_cards; @@ -613,6 +619,8 @@ U_BOOT_DRIVER(i2c_designware) = { .bind = designware_i2c_bind, .probe = designware_i2c_probe, .priv_auto_alloc_size = sizeof(struct dw_i2c), + .remove = designware_i2c_remove, + .flags = DM_FLAG_OS_PREPARE, .ops = &designware_i2c_ops, }; -- cgit v1.2.3 From 4e829e9841f80c540150a14b4d12169139a0b7b9 Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Thu, 28 Mar 2019 21:11:49 +0100 Subject: rtc: m41t62: add compatible for m41t82 This adds a compatible string for m41t82. This ensures that this driver can be used for m41t82 in DM mode, too (asit was usable for this model in non-DM mode before). In addition, the HT bit has to be reset during probe, since the m41t82 chip sets it when entering battery standby mode. This patch ensures this driver works on socfpga_socrates. Signed-off-by: Simon Goldschmidt Reviewed-by: Stefan Roese --- drivers/rtc/m41t62.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index 2ee7e00b02..6161b76712 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -155,6 +155,15 @@ static int m41t62_rtc_reset(struct udevice *dev) return ret; } +/* + * Make sure HT bit is cleared. This bit is set on entering battery backup + * mode, so do this before the first read access. + */ +static int m41t62_rtc_probe(struct udevice *dev) +{ + return m41t62_rtc_reset(dev); +} + static const struct rtc_ops m41t62_rtc_ops = { .get = m41t62_rtc_get, .set = m41t62_rtc_set, @@ -163,6 +172,7 @@ static const struct rtc_ops m41t62_rtc_ops = { static const struct udevice_id m41t62_rtc_ids[] = { { .compatible = "st,m41t62" }, + { .compatible = "st,m41t82" }, { .compatible = "microcrystal,rv4162" }, { } }; @@ -172,6 +182,7 @@ U_BOOT_DRIVER(rtc_m41t62) = { .id = UCLASS_RTC, .of_match = m41t62_rtc_ids, .ops = &m41t62_rtc_ops, + .probe = &m41t62_rtc_probe, }; #else /* NON DM RTC code - will be removed */ -- cgit v1.2.3 From d1aa159d999f876e28bb200cca69a0a8c86ed888 Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Thu, 28 Mar 2019 21:11:50 +0100 Subject: arm: socfpga: socrates: make rtc work This patch makes the on-board RTC work on the socfpga_socrates board. This rtc is present on the board, but it does not work (fails with a timeout). This patch adds a weak pull-up on the I2C0-SCL pin connected to the m41t82 RTC on this board. While the SDA line has a pull-up on the pcb, the pull-up on the SCL line seems to be missing. To work around this, enable the weak-pull-up feature on this pin. After applying this patch, the rtc timeout is gone and the 'date' command can access the rtc chip. Signed-off-by: Simon Goldschmidt Reviewed-by: Stefan Roese --- board/ebv/socrates/qts/iocsr_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/ebv/socrates/qts/iocsr_config.h b/board/ebv/socrates/qts/iocsr_config.h index 011fa2bac3..18b9c6ce4d 100644 --- a/board/ebv/socrates/qts/iocsr_config.h +++ b/board/ebv/socrates/qts/iocsr_config.h @@ -108,7 +108,7 @@ const unsigned long iocsr_scan_chain2_table[] = { 0x00018004, 0x06001209, 0x00004000, - 0x20002412, + 0x20042412, 0x00904800, 0x00000030, 0x80000000, -- cgit v1.2.3 From ac1ec53e26d68493f01b0adf44e45a995da640df Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Thu, 28 Mar 2019 21:11:51 +0100 Subject: configs: socfpga: socrates: enable rtc support This enables DM_RTC and RTC_M41T62 to enable support for the rtc on the socrates board. Signed-off-by: Simon Goldschmidt Reviewed-by: Stefan Roese --- configs/socfpga_socrates_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 45fd78a15c..242d938f9c 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -61,6 +61,8 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_DM_RTC=y +CONFIG_RTC_M41T62=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y -- cgit v1.2.3 From 798baf7ca35f81eab27dc49289745b19bde3cd39 Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Tue, 9 Apr 2019 21:02:03 +0200 Subject: arm: socfpga: fix comment about SPL memory layout The comment about SPL memory layout for socfpga gen5 is outdated: the initial malloc memory is now at the end of the SRAM, gd is below it (see board_init_f_alloc_reserve). Signed-off-by: Simon Goldschmidt Acked-by: Marek Vasut --- include/configs/socfpga_common.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index f9e2cdc1b3..32ee7426b6 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -236,9 +236,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * * 0xFFFF_0000 ...... Start of SRAM * 0xFFFF_xxxx ...... Top of stack (grows down) - * 0xFFFF_yyyy ...... Malloc area - * 0xFFFF_zzzz ...... Global Data - * 0xFFFF_FF00 ...... End of SRAM + * 0xFFFF_yyyy ...... Global Data + * 0xFFFF_zzzz ...... Malloc area + * 0xFFFF_FFFF ...... End of SRAM * * SRAM Memory layout for Arria 10: * 0xFFE0_0000 ...... Start of SRAM (bottom) -- cgit v1.2.3 From 4399e48deb55a5786515e089fe9f0aa6e0ce5d6a Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Tue, 9 Apr 2019 21:02:04 +0200 Subject: arm: socfpga: put initial U-Boot stack into DDR If SPL post-reloc stage puts the stack into DDR, U-Boot should be able to do that, too. The reason to do so is that this way, U-Boot initial stack can be larger than SPL initial stack. In situations where we want to save the SPL in SRAM for next boot without reloading, this prevents overwriting the SPL DTB in SRAM if U-Boot stack usage gets too high. To achieve this, the malloc definition for a10 is moved up and sligthly changed to ensure CONFIG_SYS_INIT_RAM_SIZE is the remaining available size. Signed-off-by: Simon Goldschmidt Acked-by: Marek Vasut --- include/configs/socfpga_common.h | 42 +++++++++++++++++++--------------------- 1 file changed, 20 insertions(+), 22 deletions(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 32ee7426b6..a501b5209f 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -26,7 +26,13 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ +/* SPL memory allocation configuration, this is for FAT implementation */ +#ifndef CONFIG_SYS_SPL_MALLOC_SIZE +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000 +#endif +#define CONFIG_SYS_INIT_RAM_SIZE (0x40000 - CONFIG_SYS_SPL_MALLOC_SIZE) +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE) #endif /* @@ -38,12 +44,23 @@ #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \ (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE))) -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_BOOTCOUNT_ADDR +#define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR #else -#define CONFIG_SYS_INIT_SP_ADDR \ +#define CONFIG_SPL_STACK \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) #endif +/* + * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc + * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage + * in U-Boot pre-reloc is higher than in SPL. + */ +#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR +#else +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK +#endif + #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* @@ -252,16 +269,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE #endif -#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) -/* SPL memory allocation configuration, this is for FAT implementation */ -#ifndef CONFIG_SYS_SPL_MALLOC_START -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \ - CONFIG_SYS_SPL_MALLOC_SIZE + \ - CONFIG_SYS_INIT_RAM_ADDR) -#endif -#endif - /* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) @@ -292,15 +299,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #endif #endif -/* - * Stack setup - */ -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) -#define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START -#endif - /* Extra Environment */ #ifndef CONFIG_SPL_BUILD -- cgit v1.2.3 From aef44283ac8e4d150f9faa87e16d9b962fc7ef5d Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Tue, 9 Apr 2019 21:02:05 +0200 Subject: arm: socfpga: imply/default common config options This commit moves common config options used in all socfpga boards to select/imply in Kconfig. This both cleans up the defconfig files as well as makes future changes easier. Options implied/defaulted for all sub-arches: - SPL, SPL_DM, USE_TINY_PRINTF, NR_DRAM_BANKS Options implied/defaulted for implied for A10 & gen5: - FPGA_SOCFPGA, SYS_MALLOC_F_LEN, SYS_TEXT_BASE Options implied/defaulted for gen5: - SPL_STACK_R, SPL_SYS_MALLOC_SIMPLE, SPL_STACK_R_ADDR Signed-off-by: Simon Goldschmidt Acked-by: Marek Vasut --- arch/arm/Kconfig | 2 ++ arch/arm/mach-socfpga/Kconfig | 20 ++++++++++++++++++++ configs/socfpga_arria10_defconfig | 6 ------ configs/socfpga_arria5_defconfig | 10 ---------- configs/socfpga_cyclone5_defconfig | 10 ---------- configs/socfpga_dbm_soc1_defconfig | 10 ---------- configs/socfpga_de0_nano_soc_defconfig | 10 ---------- configs/socfpga_de10_nano_defconfig | 10 ---------- configs/socfpga_de1_soc_defconfig | 10 ---------- configs/socfpga_is1_defconfig | 8 -------- configs/socfpga_sockit_defconfig | 10 ---------- configs/socfpga_socrates_defconfig | 10 ---------- configs/socfpga_sr1500_defconfig | 10 ---------- configs/socfpga_stratix10_defconfig | 2 -- configs/socfpga_vining_fpga_defconfig | 10 ---------- 15 files changed, 22 insertions(+), 116 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f58f8fb235..dd5ac69a8e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -839,6 +839,8 @@ config ARCH_SOCFPGA imply DM_SPI imply DM_SPI_FLASH imply FAT_WRITE + imply SPL + imply SPL_DM imply SPL_LIBDISK_SUPPORT imply SPL_MMC_SUPPORT imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 5e87371f8c..3c6c63067d 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -1,8 +1,22 @@ if ARCH_SOCFPGA +config NR_DRAM_BANKS + default 1 + +config SPL_STACK_R_ADDR + default 0x00800000 if TARGET_SOCFPGA_GEN5 + config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE default 0xa2 +config SYS_MALLOC_F_LEN + default 0x2000 if TARGET_SOCFPGA_ARRIA10 + default 0x2000 if TARGET_SOCFPGA_GEN5 + +config SYS_TEXT_BASE + default 0x01000040 if TARGET_SOCFPGA_ARRIA10 + default 0x01000040 if TARGET_SOCFPGA_GEN5 + config TARGET_SOCFPGA_ARRIA5 bool select TARGET_SOCFPGA_GEN5 @@ -21,6 +35,8 @@ config TARGET_SOCFPGA_ARRIA10 select SYSCON select SPL_SYSCON if SPL select ETH_DESIGNWARE_SOCFPGA + imply FPGA_SOCFPGA + imply USE_TINY_PRINTF config TARGET_SOCFPGA_CYCLONE5 bool @@ -29,6 +45,10 @@ config TARGET_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_GEN5 bool select ALTERA_SDRAM + imply FPGA_SOCFPGA + imply SPL_STACK_R + imply SPL_SYS_MALLOC_SIMPLE + imply USE_TINY_PRINTF config TARGET_SOCFPGA_STRATIX10 bool diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index f321a0ac3b..b3540cfe42 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -1,12 +1,9 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_SYS_TEXT_BASE=0x01000040 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y -CONFIG_SPL=y CONFIG_IDENT_STRING="socfpga_arria10" CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" # CONFIG_USE_BOOTCOMMAND is not set @@ -28,9 +25,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" # CONFIG_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_DM_MMC=y @@ -42,4 +37,3 @@ CONFIG_SPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_DESIGNWARE_APB_TIMER=y -CONFIG_USE_TINY_PRINTF=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 2f04092649..d514b14364 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -1,12 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_SYS_TEXT_BASE=0x01000040 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y -CONFIG_SPL=y -CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_arria5_socdk.dtb" CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -39,10 +32,8 @@ CONFIG_CMD_UBI=y # CONFIG_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y -CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y @@ -72,4 +63,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USE_TINY_PRINTF=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 2625aadf40..2d1a20154a 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -1,12 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_SYS_TEXT_BASE=0x01000040 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y -CONFIG_SPL=y -CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socdk.dtb" CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -39,10 +32,8 @@ CONFIG_CMD_UBI=y # CONFIG_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y -CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y @@ -73,4 +64,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USE_TINY_PRINTF=y diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index b6f4f8a3dd..233d1334b3 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -1,11 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_SYS_TEXT_BASE=0x01000040 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1=y -CONFIG_SPL=y -CONFIG_SPL_STACK_R_ADDR=0x00800000 -CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" @@ -15,8 +10,6 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -41,9 +34,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_dbm_soc1" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SPL_DM=y CONFIG_DFU_MMC=y -CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y @@ -67,4 +58,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USE_TINY_PRINTF=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 9a89bb5d68..dfd2d0f504 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -1,12 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_SYS_TEXT_BASE=0x01000040 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y -CONFIG_SPL=y -CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -17,8 +12,6 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -40,9 +33,7 @@ CONFIG_CMD_UBI=y # CONFIG_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SPL_DM=y CONFIG_DFU_MMC=y -CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y @@ -68,4 +59,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USE_TINY_PRINTF=y diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index db516891ba..d02a8d7d87 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -1,12 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_SYS_TEXT_BASE=0x01000040 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_TERASIC_DE10_NANO=y -CONFIG_SPL=y -CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de10_nano.dtb" CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -36,9 +29,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" # CONFIG_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_nano" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SPL_DM=y CONFIG_DFU_MMC=y -CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y @@ -64,4 +55,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USE_TINY_PRINTF=y diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index 5bed755723..c860bb45ad 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -1,12 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_SYS_TEXT_BASE=0x01000040 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y -CONFIG_SPL=y -CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -17,8 +12,6 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -36,8 +29,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" # CONFIG_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SPL_DM=y -CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y @@ -55,5 +46,4 @@ CONFIG_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y -CONFIG_USE_TINY_PRINTF=y # CONFIG_EFI_LOADER is not set diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index cd7211d202..7c81a83fc6 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -1,12 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_SYS_TEXT_BASE=0x01000040 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_IS1=y -CONFIG_SPL=y -CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" @@ -17,7 +12,6 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -36,11 +30,9 @@ CONFIG_CMD_UBI=y # CONFIG_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8 -CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 4c17d1a9e4..805bbe1a1a 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -1,12 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_SYS_TEXT_BASE=0x01000040 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y -CONFIG_SPL=y -CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sockit.dtb" CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -39,10 +32,8 @@ CONFIG_CMD_UBI=y # CONFIG_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y -CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y @@ -73,4 +64,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USE_TINY_PRINTF=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 242d938f9c..2b9357798c 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -1,12 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_SYS_TEXT_BASE=0x01000040 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y -CONFIG_SPL=y -CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -16,8 +11,6 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socrates.dtb" CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -40,10 +33,8 @@ CONFIG_CMD_UBI=y # CONFIG_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y -CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y @@ -75,4 +66,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USE_TINY_PRINTF=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index b8de47a4b1..6542045ca2 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -1,12 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_SYS_TEXT_BASE=0x01000040 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_SR1500=y -CONFIG_SPL=y -CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -18,8 +13,6 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -40,11 +33,9 @@ CONFIG_CMD_UBI=y # CONFIG_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8 -CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y @@ -64,4 +55,3 @@ CONFIG_MII=y CONFIG_DM_RESET=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y -CONFIG_USE_TINY_PRINTF=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 4848013b21..a6a28893ca 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_TEXT_BASE=0x1000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y -CONFIG_SPL=y CONFIG_IDENT_STRING="socfpga_stratix10" CONFIG_SPL_FS_FAT=y CONFIG_NR_DRAM_BANKS=2 @@ -30,7 +29,6 @@ CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 3eba09dcb1..7b47b111b7 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -1,12 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_SYS_TEXT_BASE=0x01000040 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y -CONFIG_SPL=y -CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y @@ -19,8 +14,6 @@ CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y @@ -45,12 +38,10 @@ CONFIG_CMD_UBI=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y -CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_LED_STATUS=y @@ -90,4 +81,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USE_TINY_PRINTF=y -- cgit v1.2.3 From 9dc61aac2ddc05b7118599c12c2a390d642189af Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Tue, 9 Apr 2019 21:02:06 +0200 Subject: arm: socfpga: gen5: reduce SPL pre-reloc malloc By enabling debug prints in malloc_simple, we can see that SPL for socfpga gen5 does by far not need the 8 KiB malloc pool currently allocated for SPL in pre-reloc phase. On socfpga_socrates, 1304 bytes are currently used (and this increases by ~200 bytes only for the sdram/reset fixes in socfpga-next). To prevent wasting precious SRAM space, let's reduce the initial heap used for SPL to 2 KiB. This is still some hundred bytes more than currently used. Also, the gen5 SPL enables stack and heap in DDR memory pretty early. Only the initial uclass/dm parsing, serial console and DDR initialization is done in the initial heap, so these 2 KiB should be enough for all boards. Signed-off-by: Simon Goldschmidt Acked-by: Marek Vasut --- arch/arm/mach-socfpga/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 3c6c63067d..8f7b79f586 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -6,6 +6,9 @@ config NR_DRAM_BANKS config SPL_STACK_R_ADDR default 0x00800000 if TARGET_SOCFPGA_GEN5 +config SPL_SYS_MALLOC_F_LEN + default 0x800 if TARGET_SOCFPGA_GEN5 + config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE default 0xa2 -- cgit v1.2.3 From 0b7eb4337d47c0d1029a412b50e5dc0c11f3474c Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Thu, 28 Mar 2019 22:09:35 +0100 Subject: arm: socfpga: move vining_fpga to DM_I2C All socfpga boards except for vining_fpga use DM_I2C. Enable DM_I2C for this board and set the EEPROM defines via Kconfig (enabling CONFIG_I2C_EEPROM from MISC). Signed-off-by: Simon Goldschmidt Series-changes: 2 - added (this) patch to move socfpga_vining to DM_I2C --- board/samtec/vining_fpga/socfpga.c | 9 +-------- configs/socfpga_vining_fpga_defconfig | 8 +++++++- include/configs/socfpga_common.h | 26 -------------------------- include/configs/socfpga_vining_fpga.h | 9 --------- 4 files changed, 8 insertions(+), 44 deletions(-) diff --git a/board/samtec/vining_fpga/socfpga.c b/board/samtec/vining_fpga/socfpga.c index d99aac6828..efc8ddf162 100644 --- a/board/samtec/vining_fpga/socfpga.c +++ b/board/samtec/vining_fpga/socfpga.c @@ -52,14 +52,7 @@ int misc_init_r(void) u32 serial; int ret; - /* EEPROM is at bus 0. */ - ret = i2c_set_bus_num(0); - if (ret) { - puts("Cannot select EEPROM I2C bus.\n"); - return 0; - } - - /* EEPROM is at address 0x50. */ + /* EEPROM is at address 0x50 (at bus CONFIG_SYS_EEPROM_BUS_NUM). */ ret = eeprom_read(0x50, 0, data, sizeof(data)); if (ret) { puts("Cannot read I2C EEPROM.\n"); diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 7b47b111b7..4a7f775337 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -16,8 +16,8 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y @@ -44,6 +44,7 @@ CONFIG_DFU_RAM=y CONFIG_DFU_SF=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_LED_STATUS=y CONFIG_LED_STATUS_GPIO=y CONFIG_LED_STATUS0=y @@ -55,6 +56,11 @@ CONFIG_LED_STATUS_BIT2=54 CONFIG_LED_STATUS3=y CONFIG_LED_STATUS_BIT3=65 CONFIG_LED_STATUS_CMD=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=70 CONFIG_DM_MMC=y CONFIG_MMC_DW=y CONFIG_MTD_DEVICE=y diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index a501b5209f..a65fc804e3 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -149,32 +149,6 @@ #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS #endif -/* - * I2C support - */ -#ifndef CONFIG_DM_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS -#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS -#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS -#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS -/* Using standard mode which the speed up to 100Kb/s */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SPEED1 100000 -#define CONFIG_SYS_I2C_SPEED2 100000 -#define CONFIG_SYS_I2C_SPEED3 100000 -/* Address of device when used as slave */ -#define CONFIG_SYS_I2C_SLAVE 0x02 -#define CONFIG_SYS_I2C_SLAVE1 0x02 -#define CONFIG_SYS_I2C_SLAVE2 0x02 -#define CONFIG_SYS_I2C_SLAVE3 0x02 -#ifndef __ASSEMBLY__ -/* Clock supplied to I2C controller in unit of MHz */ -unsigned int cm_get_l4_sp_clk_hz(void); -#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) -#endif -#endif /* CONFIG_DM_I2C */ - /* * QSPI support */ diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 5517ed722d..0e547a1295 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -16,15 +16,6 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* I2C EEPROM */ -#ifdef CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_BUS 0 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 -#endif - /* * Status LEDs: * 0 ... Top Green -- cgit v1.2.3 From 71f574df9ade8cf5d55d9e4c92b6d872b66a7b33 Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Wed, 9 Jan 2019 20:47:52 +0100 Subject: arm: socfpga: clean up socfpga_common.h Remove outdated macros and comments (not used any more, outdated due to DM conversion) from socfpga_common.h. Signed-off-by: Simon Goldschmidt Series-changes: 3 - changed commit message: s/defines/macros and comments/ Series-changes: 2 - remove even more outdated things --- include/configs/socfpga_common.h | 40 ---------------------------------------- 1 file changed, 40 deletions(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index a65fc804e3..5b5e5f5d43 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -72,29 +72,12 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot argument buffer size */ -#ifndef CONFIG_SYS_HOSTNAME -#define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD -#endif - /* * Cache */ #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS -/* - * EPCS/EPCQx1 Serial Flash Controller - */ -#ifdef CONFIG_ALTERA_SPI -/* - * The base address is configurable in QSys, each board must specify the - * base address based on it's particular FPGA configuration. Please note - * that the address here is incremented by 0x400 from the Base address - * selected in QSys, since the SPI registers are at offset +0x400. - * #define CONFIG_SYS_SPI_BASE 0xff240400 - */ -#endif - /* * Ethernet on SoC (EMAC) */ @@ -162,15 +145,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() #endif -/* - * Designware SPI support - */ - -/* - * Serial Driver - */ -#define CONFIG_SYS_NS16550_SERIAL - /* * USB */ @@ -206,20 +180,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_ENV_SECT_SIZE (64 * 1024) #endif -/* - * mtd partitioning for serial NOR flash - * - * device nor0 , # parts = 6 - * #: name size offset mask_flags - * 0: u-boot 0x00100000 0x00000000 0 - * 1: env1 0x00040000 0x00100000 0 - * 2: env2 0x00040000 0x00140000 0 - * 3: UBI 0x03e80000 0x00180000 0 - * 4: boot 0x00e80000 0x00180000 0 - * 5: rootfs 0x01000000 0x01000000 0 - * - */ - /* * SPL * -- cgit v1.2.3 From faea9e7a78d78b178a26198ab8459f6daf423792 Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Wed, 9 Jan 2019 20:49:09 +0100 Subject: arm: socfpga: remove CONFIG_SYS_BOOTMAPSZ socfpga_common.h defines CONFIG_SYS_BOOTMAPSZ to 64 MiB. Since having this define overrides the 'bootm_size' env variable for the whole socfpga platform, let's remove this define from socfpga_common.h and instead rely on the 'bootm_size' env variable (which is initialized to 160 MiB in the same file's default env). This gives users the chance to override it in their own environment. Signed-off-by: Simon Goldschmidt Acked-by: Marek Vasut Series-to: Marek Vasut Series-to: u-boot@lists.denx.de Cover-letter: arm: socfpga: clean up socfpga_common.h This series cleans up the include/configs/socfpga_common.h file a bit. It removes some defines that are used nowhere and cleans up some leftovers after various subsystems have been converted to use DM. END --- include/configs/socfpga_common.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 5b5e5f5d43..5eccb01d1d 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -10,8 +10,6 @@ */ #define CONFIG_CLOCKS -#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) - #define CONFIG_TIMESTAMP /* Print image info with timestamp */ /* -- cgit v1.2.3 From 4aab2329b282956b3a8a22de7bd30116d1c8df20 Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Tue, 2 Apr 2019 21:29:41 +0200 Subject: arm: socfpga: clean up board config files Remove outdated defines (not used any more, outdated due to DM conversion) from various socfpga files in include/config. Signed-off-by: Simon Goldschmidt Acked-by: Marek Vasut Series-version: 3 Series-changes: 2 - added (this) patch with further cleanups to the socfpga board config files --- include/configs/socfpga_arria10_socdk.h | 6 ------ include/configs/socfpga_arria5_socdk.h | 2 -- include/configs/socfpga_cyclone5_socdk.h | 2 -- include/configs/socfpga_de0_nano_soc.h | 2 -- include/configs/socfpga_de10_nano.h | 2 -- include/configs/socfpga_de1_soc.h | 2 -- include/configs/socfpga_is1.h | 2 -- include/configs/socfpga_sockit.h | 2 -- include/configs/socfpga_socrates.h | 2 -- include/configs/socfpga_sr1500.h | 11 ----------- include/configs/socfpga_vining_fpga.h | 9 --------- 11 files changed, 42 deletions(-) diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index 0f116fbf2d..92630c5e6e 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -19,12 +19,6 @@ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 -/* Ethernet on SoC (EMAC) */ - -/* - * U-Boot environment configurations - */ - /* * Serial / UART configurations */ diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index 24fcdd8b5a..af6137aeb1 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -14,8 +14,6 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* Ethernet on SoC (EMAC) */ - /* The rest of the configuration is shared */ #include diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 18da8496ef..028db2a09e 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -14,8 +14,6 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* Ethernet on SoC (EMAC) */ - /* The rest of the configuration is shared */ #include diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index d3224d5bd3..21108e3447 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -14,8 +14,6 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* Ethernet on SoC (EMAC) */ - /* The rest of the configuration is shared */ #include diff --git a/include/configs/socfpga_de10_nano.h b/include/configs/socfpga_de10_nano.h index 2fcabff8af..d85f98fbd4 100644 --- a/include/configs/socfpga_de10_nano.h +++ b/include/configs/socfpga_de10_nano.h @@ -14,8 +14,6 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* Ethernet on SoC (EMAC) */ - /* The rest of the configuration is shared */ #include diff --git a/include/configs/socfpga_de1_soc.h b/include/configs/socfpga_de1_soc.h index f37099c58f..9919d292dc 100644 --- a/include/configs/socfpga_de1_soc.h +++ b/include/configs/socfpga_de1_soc.h @@ -14,8 +14,6 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* Ethernet on SoC (EMAC) */ - /* The rest of the configuration is shared */ #include diff --git a/include/configs/socfpga_is1.h b/include/configs/socfpga_is1.h index c233c208a5..c4da5947f3 100644 --- a/include/configs/socfpga_is1.h +++ b/include/configs/socfpga_is1.h @@ -19,8 +19,6 @@ /* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) #define CONFIG_ARP_TIMEOUT 500UL - -/* PHY */ #endif /* The rest of the configuration is shared */ diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index 3a7f354914..972999949a 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -14,8 +14,6 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* Ethernet on SoC (EMAC) */ - /* The rest of the configuration is shared */ #include diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h index f0d9347891..7faea150a9 100644 --- a/include/configs/socfpga_socrates.h +++ b/include/configs/socfpga_socrates.h @@ -14,8 +14,6 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* Ethernet on SoC (EMAC) */ - /* The rest of the configuration is shared */ #include diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index b6a98611c0..3a8ccc3021 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -19,8 +19,6 @@ /* The PHY is autodetected, so no MII PHY address is needed here */ #define PHY_ANEG_TIMEOUT 8000 -/* Environment */ - /* Enable SPI NOR flash reset, needed for SPI booting */ #define CONFIG_SPI_N25Q256A_RESET @@ -36,15 +34,6 @@ #define CONFIG_ENV_OFFSET 0x000e0000 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) -/* - * The QSPI NOR flash layout on SR1500: - * - * 0000.0000 - 0003.ffff: SPL (4 times) - * 0004.0000 - 000d.ffff: U-Boot - * 000e.0000 - 000e.ffff: env1 - * 000f.0000 - 000f.ffff: env2 - */ - /* The rest of the configuration is shared */ #include diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 0e547a1295..29a92b9146 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -16,18 +16,9 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* - * Status LEDs: - * 0 ... Top Green - * 1 ... Top Red - * 2 ... Bottom Green - * 3 ... Bottom Red - */ - /* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) #define CONFIG_BOOTP_SEND_HOSTNAME -/* PHY */ #endif /* Extra Environment */ -- cgit v1.2.3 From bf068c7643f23c3f0936e3d1d292cc537acaf3bb Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Wed, 24 Apr 2019 13:21:47 +0800 Subject: arm: socfpga: mailbox: Fix off-by-one error on command length checking A mailbox command contains 1-u32 header + arguments. The "len" variable only contains the length of the arguments, but not the 1-u32 header. Include the length of header when checking the ring buffer space to prevent off-by-one error. Signed-off-by: Ley Foon Tan Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/mailbox_s10.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 3c33223936..4498ab55df 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -55,11 +55,11 @@ static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len, cout = MBOX_READL(MBOX_COUT) % MBOX_CMD_BUFFER_SIZE; /* if command buffer is full or not enough free space - * to fit the data + * to fit the data. Note, len is in u32 unit. */ if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout || ((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) % - MBOX_CMD_BUFFER_SIZE) < len) + MBOX_CMD_BUFFER_SIZE) < (len + 1)) return -ENOMEM; /* write header to circular buffer */ -- cgit v1.2.3