From 41cad11dbfc69454edf03ba0dc8fb05196bd74a8 Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Mon, 3 Apr 2023 11:39:32 +0800 Subject: riscv: dts: jh7110: Add L2 pretcher configuration Add L2 pretcher configuration for starfive jh7110 SoC. Signed-off-by: Samin Guo --- arch/riscv/dts/jh7110-u-boot.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index 21a14bdc4d..e45b6cde3b 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -71,6 +71,16 @@ }; }; +&cachectrl { + reg = <0x0 0x2010000 0x0 0x4000>, + <0x0 0x2030000 0x0 0x80000>, + <0x0 0x8000000 0x0 0x2000000>; + reg-names = "control", "prefetcher", "sideband"; + prefetch-dist-size = <0x4>; + prefetch-hart-mask = <0x1e>; + prefetch-enable; +}; + &uart0 { clock-frequency = <24000000>; current-speed = <115200>; -- cgit v1.2.3