From 517ee6420564ed40d53d49f1d2d96c71ad275c6a Mon Sep 17 00:00:00 2001 From: Clément Péron Date: Fri, 12 Apr 2019 16:15:26 +0200 Subject: arm: dts: h6: Add Beelink GS1 initial support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Beelink GS1 is an Allwinner H6 based TV box, which support: - Allwinner H6 Quad-core 64-bit ARM Cortex-A53 - GPU Mali-T720 - 2GB LPDDR3 RAM - 16GB eMMC - AXP805 PMIC - 1Gbps GMAC via RTL8211E - USB 2.0 and 3.0 Host - HDMI port - S/PDIF port - 5V/2A DC power supply - Wi-Fi/BT via Fn-Link 6222B-SRB (RTL8222BS) Linux commit details about the sun50i-h6-beelink-gs1.dts sync: "arm64: dts: allwinner: h6: Introduce Beelink GS1 board" (sha1: 089bee8dd119ba084dee6b17a2e1a53df4f30193) Signed-off-by: Clément Péron Reviewed-by: Jagan Teki --- arch/arm/dts/Makefile | 1 + arch/arm/dts/sun50i-h6-beelink-gs1.dts | 184 +++++++++++++++++++++++++++++++++ board/sunxi/MAINTAINERS | 6 ++ configs/beelink_gs1_defconfig | 15 +++ 4 files changed, 206 insertions(+) create mode 100644 arch/arm/dts/sun50i-h6-beelink-gs1.dts create mode 100644 configs/beelink_gs1_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0aee8dfde0..4bba8b81f8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -469,6 +469,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ sun50i-h5-orangepi-prime.dtb \ sun50i-h5-orangepi-zero-plus2.dtb dtb-$(CONFIG_MACH_SUN50I_H6) += \ + sun50i-h6-beelink-gs1.dtb \ sun50i-h6-orangepi-lite2.dtb \ sun50i-h6-orangepi-one-plus.dtb \ sun50i-h6-pine-h64.dtb diff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts b/arch/arm/dts/sun50i-h6-beelink-gs1.dts new file mode 100644 index 0000000000..54b0882bed --- /dev/null +++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2019 Clément Péron + */ + +/dts-v1/; + +#include "sun50i-h6.dtsi" + +#include + +/ { + model = "Beelink GS1"; + compatible = "azw,beelink-gs1", "allwinner,sun50i-h6"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + power { + label = "beelink:white:power"; + gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + default-state = "on"; + }; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the DC jack */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&mmc0 { + vmmc-supply = <®_cldo1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_cldo1>; + vqmmc-supply = <®_bldo2>; + non-removable; + cap-mmc-hw-reset; + bus-width = <8>; + status = "okay"; +}; + +&r_i2c { + status = "okay"; + + axp805: pmic@36 { + compatible = "x-powers,axp805", "x-powers,axp806"; + reg = <0x36>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + x-powers,self-working-mode; + vina-supply = <®_vcc5v>; + vinb-supply = <®_vcc5v>; + vinc-supply = <®_vcc5v>; + vind-supply = <®_vcc5v>; + vine-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + bldoin-supply = <®_vcc5v>; + cldoin-supply = <®_vcc5v>; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; + }; + + reg_aldo2: aldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ac200"; + regulator-enable-ramp-delay = <100000>; + }; + + reg_aldo3: aldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc25-dram"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-bias-pll"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-efuse-pcie-hdmi-io"; + }; + + reg_bldo3: bldo3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dcxoio"; + }; + + bldo4 { + /* unused */ + }; + + reg_cldo1: cldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-1"; + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-gpu"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <960000>; + regulator-max-microvolt = <960000>; + regulator-name = "vdd-sys"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; + }; + + sw { + /* unused */ + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 338f374e56..03153f7252 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -166,6 +166,12 @@ M: Jagan Teki S: Maintained F: configs/bananapi_m64_defconfig +BEELINK GS1 +M: Clément Péron +S: Maintained +F: configs/beelink_gs1_defconfig +F: arch/arm/dts/sun50i-h6-beelink-gs1.dts + COLOMBUS BOARD M: Maxime Ripard S: Maintained diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig new file mode 100644 index 0000000000..ef4dd29549 --- /dev/null +++ b/configs/beelink_gs1_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN50I_H6=y +CONFIG_MMC0_CD_PIN="PF6" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +# CONFIG_PSCI_RESET is not set +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-beelink-gs1" +CONFIG_LED=y +CONFIG_LED_GPIO=y -- cgit v1.2.3 From 0eabec145fda8bb6b4faebfbbce506a357445956 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Wed, 13 Feb 2019 18:50:36 +0100 Subject: sunxi: Fix build when CONFIG_CMD_PXE or CONFIG_CMD_DHCP are disabled MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes a compilation failure with disabled PXE or DHCP command when using sunxi platform. Signed-off-by: Ondřej Jirman Reviewed-by: Jagan Teki --- include/configs/sunxi-common.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index a498393472..79afba2aba 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -393,6 +393,18 @@ extern int soft_i2c_gpio_scl; #define BOOT_TARGET_DEVICES_USB(func) #endif +#ifdef CONFIG_CMD_PXE +#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) +#else +#define BOOT_TARGET_DEVICES_PXE(func) +#endif + +#ifdef CONFIG_CMD_DHCP +#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) +#else +#define BOOT_TARGET_DEVICES_DHCP(func) +#endif + /* FEL boot support, auto-execute boot.scr if a script address was provided */ #define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \ "bootcmd_fel=" \ @@ -408,8 +420,8 @@ extern int soft_i2c_gpio_scl; BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_SCSI(func) \ BOOT_TARGET_DEVICES_USB(func) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) + BOOT_TARGET_DEVICES_PXE(func) \ + BOOT_TARGET_DEVICES_DHCP(func) #ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT #define BOOTCMD_SUNXI_COMPAT \ -- cgit v1.2.3 From 0cbee8544b4e5282d20d6bc40c505c6fa0589773 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 8 May 2019 19:42:16 +0530 Subject: spi: atcspi200: Change include order Like clk_get_by_index, there is requirement for clk_get_by_index_nodev. In this case to make common code functionalities for dev and nodev, clk_get_by_index is trying to get the index of clock by passing ofnode instead of actual dev like current gpio uclass does. In these scenarios with current order of include files the atcspi200_spi driver is unable to find CONFIG_ENV_SIZE. In file included from arch/nds32/include/asm/u-boot.h:24, from include/dm/of.h:10, from include/dm/ofnode.h:12, from include/clk.h:11, from drivers/spi/atcspi200_spi.c:9: include/environment.h:145:19: error: 'CONFIG_ENV_SIZE' undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'? #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE) So, fix consists of changing the order of include files in atcspi200_spi.c to include first common.h file. Reviewed-by: Bin Meng Signed-off-by: Jagan Teki --- drivers/spi/atcspi200_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c index af96c6d21e..e0cc323444 100644 --- a/drivers/spi/atcspi200_spi.c +++ b/drivers/spi/atcspi200_spi.c @@ -6,8 +6,8 @@ * Author: Rick Chen (rick@andestech.com) */ -#include #include +#include #include #include #include -- cgit v1.2.3 From db2f6961477115045df6acf36667ede2644b934d Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 8 May 2019 19:52:18 +0530 Subject: clk: sifive: fu540-prci: Change include order Like clk_get_by_index, there is requirement for clk_get_by_index_nodev. In this case to make common code functionalities for dev and nodev, clk_get_by_index is trying to get the index of clock by passing ofnode instead of actual dev like current gpio uclass does. In these scenarios with current order of include files the fu540-prci driver is unable to find CONFIG_ENV_SIZE. In file included from arch/riscv/include/asm/u-boot.h:23:0, from include/dm/of.h:10, from include/dm/ofnode.h:12, from include/clk.h:11, from include/clk-uclass.h:13, from drivers/clk/sifive/fu540-prci.c:32: include/environment.h:145:19: error: 'CONFIG_ENV_SIZE' undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'? #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE) So, fix consists of changing the order of include files in fu540-prci.c to include first common.h file. Cc: Anup Patel Cc: Rick Chen Cc: Paul Walmsley Reviewed-by: Bin Meng Signed-off-by: Jagan Teki --- drivers/clk/sifive/fu540-prci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index e1b5f8e6a9..2d47ebc6b1 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -28,10 +28,10 @@ * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset" */ +#include #include #include #include -#include #include #include #include -- cgit v1.2.3 From b24f9057e8a1c2e26acd3bdc2ba933cf9979b375 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 8 May 2019 19:56:16 +0530 Subject: serial: sifive: Change include order Like clk_get_by_index, there is requirement for clk_get_by_index_nodev. In this case to make common code functionalities for dev and nodev, clk_get_by_index is trying to get the index of clock by passing ofnode instead of actual dev like current gpio uclass does. In these scenarios with current order of include files the serial_sifive driver is unable to find CONFIG_ENV_SIZE. In file included from arch/riscv/include/asm/u-boot.h:23:0, from include/dm/of.h:10, from include/dm/ofnode.h:12, from include/clk.h:11, from drivers/serial/serial_sifive.c:6: include/environment.h:145:19: error: 'CONFIG_ENV_SIZE' undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'? #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE) So, fix consists of changing the order of include files in serial_sifive.c to include first common.h file. Cc: Anup Patel Cc: Rick Chen Cc: Paul Walmsley Reviewed-by: Bin Meng Signed-off-by: Jagan Teki --- drivers/serial/serial_sifive.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c index 537bc7a975..fdfef69aaa 100644 --- a/drivers/serial/serial_sifive.c +++ b/drivers/serial/serial_sifive.c @@ -3,8 +3,8 @@ * Copyright (C) 2018 Anup Patel */ -#include #include +#include #include #include #include -- cgit v1.2.3 From 75f98314f92f64fd3526464006d934d4fe9b2710 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 28 Feb 2019 00:26:52 +0530 Subject: clk: Get the CLK by index without device Getting a CLK by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process CLK operation for child without udevice but with ofnode. So add clk_get_by_index_nodev() and move the common code in clk_get_by_index_tail() to use for clk_get_by_index() Cc: Stephen Warren Signed-off-by: Jagan Teki Reviewed-by: Simon Glass --- drivers/clk/clk-uclass.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++- include/clk.h | 15 ++++++++++++ 2 files changed, 75 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 844b87cc33..d9236c5b51 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -54,6 +54,46 @@ static int clk_of_xlate_default(struct clk *clk, return 0; } +static int clk_get_by_index_tail(int ret, ofnode node, + struct ofnode_phandle_args *args, + const char *list_name, int index, + struct clk *clk) +{ + struct udevice *dev_clk; + const struct clk_ops *ops; + + assert(clk); + clk->dev = NULL; + if (ret) + goto err; + + ret = uclass_get_device_by_ofnode(UCLASS_CLK, args->node, &dev_clk); + if (ret) { + debug("%s: uclass_get_device_by_of_offset failed: err=%d\n", + __func__, ret); + return ret; + } + + clk->dev = dev_clk; + + ops = clk_dev_ops(dev_clk); + + if (ops->of_xlate) + ret = ops->of_xlate(clk, args); + else + ret = clk_of_xlate_default(clk, args); + if (ret) { + debug("of_xlate() failed: %d\n", ret); + return ret; + } + + return clk_request(dev_clk, clk); +err: + debug("%s: Node '%s', property '%s', failed to request CLK index %d: %d\n", + __func__, ofnode_get_name(node), list_name, index, ret); + return ret; +} + static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name, int index, struct clk *clk) { @@ -100,7 +140,26 @@ static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name, int clk_get_by_index(struct udevice *dev, int index, struct clk *clk) { - return clk_get_by_indexed_prop(dev, "clocks", index, clk); + struct ofnode_phandle_args args; + int ret; + + ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0, + index, &args); + + return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks", + index > 0, clk); +} + +int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk) +{ + struct ofnode_phandle_args args; + int ret; + + ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0, + index > 0, &args); + + return clk_get_by_index_tail(ret, node, &args, "clocks", + index > 0, clk); } int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk) diff --git a/include/clk.h b/include/clk.h index 8e366163f9..d24e99713a 100644 --- a/include/clk.h +++ b/include/clk.h @@ -8,6 +8,7 @@ #ifndef _CLK_H_ #define _CLK_H_ +#include #include #include @@ -100,6 +101,20 @@ int clk_get_by_index_platdata(struct udevice *dev, int index, */ int clk_get_by_index(struct udevice *dev, int index, struct clk *clk); +/** + * clock_get_by_index_nodev - Get/request a clock by integer index + * without a device. + * + * This is a version of clk_get_by_index() that does not use a device. + * + * @node: The client ofnode. + * @index: The index of the clock to request, within the client's list of + * clocks. + * @clock A pointer to a clock struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk); + /** * clock_get_bulk - Get/request all clocks of a device. * -- cgit v1.2.3 From dcb63fcd16c579378e68ab34849b47dda45f41b2 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 28 Feb 2019 00:26:53 +0530 Subject: clk: Use clk_get_by_index_tail() clk_get_by_index_tail() now handle common clk get by index code so use it from clk_get_by_indexed_prop(). Cc: Stephen Warren Reviewed-by: Simon Glass Signed-off-by: Jagan Teki --- drivers/clk/clk-uclass.c | 24 ++---------------------- 1 file changed, 2 insertions(+), 22 deletions(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index d9236c5b51..79b3b0494c 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -99,8 +99,6 @@ static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name, { int ret; struct ofnode_phandle_args args; - struct udevice *dev_clk; - const struct clk_ops *ops; debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk); @@ -115,27 +113,9 @@ static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name, return ret; } - ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk); - if (ret) { - debug("%s: uclass_get_device_by_of_offset failed: err=%d\n", - __func__, ret); - return ret; - } - - clk->dev = dev_clk; - - ops = clk_dev_ops(dev_clk); - if (ops->of_xlate) - ret = ops->of_xlate(clk, &args); - else - ret = clk_of_xlate_default(clk, &args); - if (ret) { - debug("of_xlate() failed: %d\n", ret); - return ret; - } - - return clk_request(dev_clk, clk); + return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks", + index > 0, clk); } int clk_get_by_index(struct udevice *dev, int index, struct clk *clk) -- cgit v1.2.3 From d7a672e35f4788f95cee36797f7cf80474fd151b Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 5 Mar 2019 19:42:44 +0530 Subject: test/dm: clk: Add clk_get_by_index[_nodev] test Add sample dm clk test for clk_get_by_index and clk_get_by_index_nodev functionality code. Cc: Stephen Warren Signed-off-by: Jagan Teki Reviewed-by: Simon Glass --- test/dm/clk.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/test/dm/clk.c b/test/dm/clk.c index 112d5cbbc9..f301ecbb45 100644 --- a/test/dm/clk.c +++ b/test/dm/clk.c @@ -4,12 +4,33 @@ */ #include +#include #include #include #include #include #include +/* Base test of the clk uclass */ +static int dm_test_clk_base(struct unit_test_state *uts) +{ + struct udevice *dev; + struct clk clk_method1; + struct clk clk_method2; + + /* Get the device using the clk device */ + ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test", &dev)); + + /* Get the same clk port in 2 different ways and compare */ + ut_assertok(clk_get_by_index(dev, 1, &clk_method1)); + ut_assertok(clk_get_by_index_nodev(dev_ofnode(dev), 1, &clk_method2)); + ut_asserteq(clk_method1.id, clk_method2.id); + + return 0; +} + +DM_TEST(dm_test_clk_base, DM_TESTF_SCAN_FDT); + static int dm_test_clk(struct unit_test_state *uts) { struct udevice *dev_fixed, *dev_fixed_factor, *dev_clk, *dev_test; -- cgit v1.2.3 From ea9dc35aab9fd9e87cbb73a3a63fcbea4d6378c3 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 28 Feb 2019 00:26:55 +0530 Subject: reset: Get the RESET by index without device Getting a RESET by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process RESET operation for child without udevice but with ofnode. So add reset_get_by_index_nodev() and move the common code in reset_get_by_index_tail() to use for reset_get_by_index() Cc: Stephen Warren Signed-off-by: Jagan Teki Reviewed-by: Simon Glass --- drivers/reset/reset-uclass.c | 53 ++++++++++++++++++++++++++++++-------------- include/reset.h | 16 +++++++++++++ 2 files changed, 52 insertions(+), 17 deletions(-) diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c index 89e39c6b5a..ee1a423ffb 100644 --- a/drivers/reset/reset-uclass.c +++ b/drivers/reset/reset-uclass.c @@ -29,41 +29,34 @@ static int reset_of_xlate_default(struct reset_ctl *reset_ctl, return 0; } -int reset_get_by_index(struct udevice *dev, int index, - struct reset_ctl *reset_ctl) +static int reset_get_by_index_tail(int ret, ofnode node, + struct ofnode_phandle_args *args, + const char *list_name, int index, + struct reset_ctl *reset_ctl) { - struct ofnode_phandle_args args; - int ret; struct udevice *dev_reset; struct reset_ops *ops; - debug("%s(dev=%p, index=%d, reset_ctl=%p)\n", __func__, dev, index, - reset_ctl); + assert(reset_ctl); reset_ctl->dev = NULL; - - ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0, - index, &args); - if (ret) { - debug("%s: fdtdec_parse_phandle_with_args() failed: %d\n", - __func__, ret); + if (ret) return ret; - } - ret = uclass_get_device_by_ofnode(UCLASS_RESET, args.node, + ret = uclass_get_device_by_ofnode(UCLASS_RESET, args->node, &dev_reset); if (ret) { debug("%s: uclass_get_device_by_ofnode() failed: %d\n", __func__, ret); - debug("%s %d\n", ofnode_get_name(args.node), args.args[0]); + debug("%s %d\n", ofnode_get_name(args->node), args->args[0]); return ret; } ops = reset_dev_ops(dev_reset); reset_ctl->dev = dev_reset; if (ops->of_xlate) - ret = ops->of_xlate(reset_ctl, &args); + ret = ops->of_xlate(reset_ctl, args); else - ret = reset_of_xlate_default(reset_ctl, &args); + ret = reset_of_xlate_default(reset_ctl, args); if (ret) { debug("of_xlate() failed: %d\n", ret); return ret; @@ -78,6 +71,32 @@ int reset_get_by_index(struct udevice *dev, int index, return 0; } +int reset_get_by_index(struct udevice *dev, int index, + struct reset_ctl *reset_ctl) +{ + struct ofnode_phandle_args args; + int ret; + + ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0, + index, &args); + + return reset_get_by_index_tail(ret, dev_ofnode(dev), &args, "resets", + index > 0, reset_ctl); +} + +int reset_get_by_index_nodev(ofnode node, int index, + struct reset_ctl *reset_ctl) +{ + struct ofnode_phandle_args args; + int ret; + + ret = ofnode_parse_phandle_with_args(node, "resets", "#reset-cells", 0, + index > 0, &args); + + return reset_get_by_index_tail(ret, node, &args, "resets", + index > 0, reset_ctl); +} + int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk) { int i, ret, err, count; diff --git a/include/reset.h b/include/reset.h index 65aa7a4ce5..57bbc0b49d 100644 --- a/include/reset.h +++ b/include/reset.h @@ -6,6 +6,7 @@ #ifndef _RESET_H #define _RESET_H +#include #include /** @@ -99,6 +100,21 @@ struct reset_ctl_bulk { int reset_get_by_index(struct udevice *dev, int index, struct reset_ctl *reset_ctl); +/** + * reset_get_by_index_nodev - Get/request a reset signal by integer index + * without a device. + * + * This is a version of reset_get_by_index() that does not use a device. + * + * @node: The client ofnode. + * @index: The index of the reset signal to request, within the client's + * list of reset signals. + * @reset_ctl A pointer to a reset control struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int reset_get_by_index_nodev(ofnode node, int index, + struct reset_ctl *reset_ctl); + /** * reset_get_bulk - Get/request all reset signals of a device. * -- cgit v1.2.3 From 41cdb28549d21855bb79d06c5ce6dec5da4a50e1 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 28 Feb 2019 00:26:56 +0530 Subject: test/dm: reset: Add reset_get_by_index[_nodev] test Add sample dm reset test for reset_get_by_index and reset_get_by_index_nodev functionality code. Cc: Stephen Warren Signed-off-by: Jagan Teki Reviewed-by: Simon Glass --- test/dm/reset.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/test/dm/reset.c b/test/dm/reset.c index c02866a2f0..c61daed490 100644 --- a/test/dm/reset.c +++ b/test/dm/reset.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -15,6 +16,28 @@ /* This is the other reset phandle specifier handled by bulk */ #define OTHER_RESET_ID 2 +/* Base test of the reset uclass */ +static int dm_test_reset_base(struct unit_test_state *uts) +{ + struct udevice *dev; + struct reset_ctl reset_method1; + struct reset_ctl reset_method2; + + /* Get the device using the reset device */ + ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "reset-ctl-test", + &dev)); + + /* Get the same reset port in 2 different ways and compare */ + ut_assertok(reset_get_by_index(dev, 1, &reset_method1)); + ut_assertok(reset_get_by_index_nodev(dev_ofnode(dev), 1, + &reset_method2)); + ut_asserteq(reset_method1.id, reset_method2.id); + + return 0; +} + +DM_TEST(dm_test_reset_base, DM_TESTF_SCAN_FDT); + static int dm_test_reset(struct unit_test_state *uts) { struct udevice *dev_reset; -- cgit v1.2.3 From 2348453c41ad52c798d542752dd5d0c1ef621874 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 28 Feb 2019 00:27:00 +0530 Subject: net: sun8i_emac: Add EPHY CLK and RESET support Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger Cc: Lothar Felten Signed-off-by: Jagan Teki Acked-by: Joe Hershberger --- drivers/net/sun8i_emac.c | 74 +++++++++++++++++++++++++++++++++++++----------- 1 file changed, 57 insertions(+), 17 deletions(-) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 98bd7a5823..c0a440886e 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -138,7 +138,9 @@ struct emac_eth_dev { struct phy_device *phydev; struct mii_dev *bus; struct clk tx_clk; + struct clk ephy_clk; struct reset_ctl tx_rst; + struct reset_ctl ephy_rst; #ifdef CONFIG_DM_GPIO struct gpio_desc reset_gpio; #endif @@ -653,7 +655,6 @@ static int sun8i_eth_write_hwaddr(struct udevice *dev) static int sun8i_emac_board_setup(struct emac_eth_dev *priv) { - struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; int ret; ret = clk_enable(&priv->tx_clk); @@ -670,16 +671,20 @@ static int sun8i_emac_board_setup(struct emac_eth_dev *priv) } } - if (priv->variant == H3_EMAC) { - /* Only H3/H5 have clock controls for internal EPHY */ - if (priv->use_internal_phy) { - /* Set clock gating for ephy */ - setbits_le32(&ccm->bus_gate4, - BIT(AHB_GATE_OFFSET_EPHY)); - - /* Deassert EPHY */ - setbits_le32(&ccm->ahb_reset2_cfg, - BIT(AHB_RESET_OFFSET_EPHY)); + /* Only H3/H5 have clock controls for internal EPHY */ + if (clk_valid(&priv->ephy_clk)) { + ret = clk_enable(&priv->ephy_clk); + if (ret) { + dev_err(dev, "failed to enable EPHY TX clock\n"); + return ret; + } + } + + if (reset_valid(&priv->ephy_rst)) { + ret = reset_deassert(&priv->ephy_rst); + if (ret) { + dev_err(dev, "failed to deassert EPHY TX clock\n"); + return ret; } } @@ -839,6 +844,44 @@ static const struct eth_ops sun8i_emac_eth_ops = { .stop = sun8i_emac_eth_stop, }; +static int sun8i_get_ephy_nodes(struct emac_eth_dev *priv) +{ + int node, ret; + + /* look for mdio-mux node for internal PHY node */ + node = fdt_path_offset(gd->fdt_blob, + "/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1"); + if (node < 0) { + debug("failed to get mdio-mux with internal PHY\n"); + return node; + } + + ret = fdt_node_check_compatible(gd->fdt_blob, node, + "allwinner,sun8i-h3-mdio-internal"); + if (ret < 0) { + debug("failed to find mdio-internal node\n"); + return ret; + } + + ret = clk_get_by_index_nodev(offset_to_ofnode(node), 0, + &priv->ephy_clk); + if (ret) { + dev_err(dev, "failed to get EPHY TX clock\n"); + return ret; + } + + ret = reset_get_by_index_nodev(offset_to_ofnode(node), 0, + &priv->ephy_rst); + if (ret) { + dev_err(dev, "failed to get EPHY TX reset\n"); + return ret; + } + + priv->use_internal_phy = true; + + return 0; +} + static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) { struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev); @@ -920,12 +963,9 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) } if (priv->variant == H3_EMAC) { - int parent = fdt_parent_offset(gd->fdt_blob, offset); - - if (parent >= 0 && - !fdt_node_check_compatible(gd->fdt_blob, parent, - "allwinner,sun8i-h3-mdio-internal")) - priv->use_internal_phy = true; + ret = sun8i_get_ephy_nodes(priv); + if (ret) + return ret; } priv->interface = pdata->phy_interface; -- cgit v1.2.3 From 997b857ae31f3cff5edc6219d5da670e8d588c27 Mon Sep 17 00:00:00 2001 From: Jonas Smedegaard Date: Sat, 20 Apr 2019 18:24:16 +0800 Subject: sun50i: a64: Add Olimex A64-Teres-I board initial support Olimex A64-Teres-I board is a mainboard (the only one so far) for Olimex Teres-I DIY laptop kit. Key features: - Allwinner A64 Cortex-A53 - Mali-400MP2 GPU - AXP803 PMIC - 2GB DDR3 RAM - MicroSD Slot - 16GB eMMC Flash - eDP LCD display - HDMI - USB Host - Battery management - 5V DC power supply - Certified Open Source Hardware (OSHW) Works: - i2C - MMC/SD - PWM backlight Known broken: - Internal keyboard (seems to be because the keyboard firmware loads a bootloader first, and then disconnects bootloader and connect real keyboard). External ones connected to the USB port work fine. This patch enables support for the A64-Teres-I board to u-boot, including enabling screen backlight (lacking from Linux device-tree). Linux commit details about the sun50i-a64-teres-i.dts sync: "arm64: dts: allwinner: a64: Rename uart0_pins_a label to uart0_pb_pins" (sha1: d91ebb95b96c8840932dc3a10c9f243712555467) Cosmetic warnings regarding whitespace and placement of SPDX notice for dts file was ignored. config and .dtsi file are adapted from pinebook files. Tested-by: Jonas Smedegaard Signed-off-by: Jonas Smedegaard Signed-off-by: Icenowy Zheng Reviewed-by: Jagan Teki [jagan: move board entry in MAINTAINERS file at proper position] Signed-off-by: Jagan Teki --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi | 41 +++++ arch/arm/dts/sun50i-a64-teres-i.dts | 270 ++++++++++++++++++++++++++++ board/sunxi/MAINTAINERS | 6 + configs/teres_i_defconfig | 22 +++ 5 files changed, 341 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi create mode 100644 arch/arm/dts/sun50i-a64-teres-i.dts create mode 100644 configs/teres_i_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 4bba8b81f8..d8dea45711 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -484,7 +484,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-pine64-plus.dtb \ sun50i-a64-pine64.dtb \ sun50i-a64-pinebook.dtb \ - sun50i-a64-sopine-baseboard.dtb + sun50i-a64-sopine-baseboard.dtb \ + sun50i-a64-teres-i.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb \ diff --git a/arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi b/arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi new file mode 100644 index 0000000000..1a64b7d09c --- /dev/null +++ b/arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Vasily Khoruzhick + * + */ + +#include "sunxi-u-boot.dtsi" + +/ { + vdd_bl: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "bl-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ + enable-active-high; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 0>; + brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>; + default-brightness-level = <2>; + enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ + power-supply = <&vdd_bl>; + }; +}; + +/* The ANX6345 eDP-bridge is on i2c */ +&i2c0 { + anx6345: edp-bridge@38 { + compatible = "analogix,anx6345"; + reg = <0x38>; + reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ + status = "okay"; + }; +}; + +&pwm { + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-a64-teres-i.dts b/arch/arm/dts/sun50i-a64-teres-i.dts new file mode 100644 index 0000000000..c455b24dd0 --- /dev/null +++ b/arch/arm/dts/sun50i-a64-teres-i.dts @@ -0,0 +1,270 @@ +/* + * Copyright (C) Harald Geyer + * based on sun50i-a64-olinuxino.dts by Jagan Teki + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +/dts-v1/; + +#include "sun50i-a64.dtsi" + +#include +#include +#include + +/ { + model = "Olimex A64 Teres-I"; + compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + + framebuffer-lcd { + eDP25-supply = <®_dldo2>; + eDP12-supply = <®_dldo3>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + lid-switch { + label = "Lid Switch"; + gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ + linux,input-type = ; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + capslock { + label = "teres-i:green:capslock"; + gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */ + }; + + numlock { + label = "teres-i:green:numlock"; + gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */ + }; + }; + + reg_usb1_vbus: usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ + status = "okay"; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ + }; +}; + +&ehci1 { + status = "okay"; +}; + + +/* The ANX6345 eDP-bridge is on i2c0. There is no linux (mainline) + * driver for this chip at the moment, the bootloader initializes it. + * However it can be accessed with the i2c-dev driver from user space. + */ +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_dcdc1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_aldo2>; + vqmmc-supply = <®_dldo4>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8723bs: wifi@1 { + reg = <1>; + interrupt-parent = <&r_pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp803: pmic@3a3 { + compatible = "x-powers,axp803"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; +}; + +#include "axp803.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc-pe"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1040000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpux"; +}; + +/* DCDC3 is polyphased with DCDC2 */ + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-ddr3"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-hdmi"; +}; + +®_dldo2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-pd"; +}; + +®_dldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd-edp"; +}; + +®_dldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +®_eldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "cpvdd"; +}; + +®_eldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dvdd-csi"; +}; + +®_fldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-1v2-hsic"; +}; + +/* + * The A64 chip cannot work without this regulator off, although + * it seems to be only driving the AR100 core. + * Maybe we don't still know well about CPUs domain. + */ +®_fldo2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&simplefb_hdmi { + vcc-hdmi-supply = <®_dldo1>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 03153f7252..bdd1854197 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -358,6 +358,12 @@ S: Maintained F: configs/A20-Olimex-SOM204-EVB_defconfig F: configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +OLIMEX TERES-I BOARD +M: Jonas Smedegaard +M: Icenowy Zheng +S: Maintained +F: configs/teres_i_defconfig + ORANGEPI LITE2 BOARD M: Jagan Teki S: Maintained diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig new file mode 100644 index 0000000000..421a8d3d40 --- /dev/null +++ b/configs/teres_i_defconfig @@ -0,0 +1,22 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN50I=y +CONFIG_DRAM_CLK=552 +CONFIG_DRAM_ZQ=3881949 +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_USB1_VBUS_PIN="PL7" +CONFIG_I2C0_ENABLE=y +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-teres-i" +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_SUNXI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +# CONFIG_USB_GADGET is not set +CONFIG_VIDEO_BRIDGE=y +CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y -- cgit v1.2.3 From b39eab2ffd55690ee2cd6e82bb30904b6faf45e5 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 3 May 2019 10:27:40 +0800 Subject: sunxi: Enable EMAC on the Cubietruck Plus The Cubietruck Plus has an RTL8211E PHY connected to the EMAC using RGMII. The PHY is powered by DLDO4 @ 3.3V, while the I/O pins are powered by DLDO3 @ 2.5V. This patch enables the EMAC and Realtek PHY drivers in the defconfig. The device tree file already has the EMAC enabled. Signed-off-by: Chen-Yu Tsai Reviewed-by: Jagan Teki --- configs/Cubietruck_plus_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig index 869bffcfca..044af12779 100644 --- a/configs/Cubietruck_plus_defconfig +++ b/configs/Cubietruck_plus_defconfig @@ -20,6 +20,8 @@ CONFIG_CONSOLE_MUX=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus" +CONFIG_PHY_REALTEK=y +CONFIG_SUN8I_EMAC=y CONFIG_AXP_DLDO3_VOLT=2500 CONFIG_AXP_DLDO4_VOLT=3300 CONFIG_AXP_FLDO1_VOLT=1200 -- cgit v1.2.3 From c23b33f5311abe32db96884318996d2b41db4c94 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 3 May 2019 10:27:41 +0800 Subject: sunxi: Enable EMAC on the Bananapi M3 The Bananapi M3 has an RTL8211E PHY connected to the EMAC using RGMII. The PHY is powered by DCDC1 through SW @ 3.3V. The board is designed to use 3.3V with RGMII, instead of the standard reduced voltage of 2.5V we see everywhere. DLDO3, which provides the I/O voltages, is raised to match. This patch enables the EMAC and Realtek PHY drivers in the defconfig. The device tree file already has the EMAC enabled. Signed-off-by: Chen-Yu Tsai Reviewed-by: Jagan Teki --- configs/Sinovoip_BPI_M3_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig index 79743a9c9a..b9ab00cb8a 100644 --- a/configs/Sinovoip_BPI_M3_defconfig +++ b/configs/Sinovoip_BPI_M3_defconfig @@ -21,8 +21,10 @@ CONFIG_CONSOLE_MUX=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-bananapi-m3" +CONFIG_PHY_REALTEK=y +CONFIG_SUN8I_EMAC=y CONFIG_AXP_DCDC5_VOLT=1200 -CONFIG_AXP_DLDO3_VOLT=2500 +CONFIG_AXP_DLDO3_VOLT=3300 CONFIG_AXP_SW_ON=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -- cgit v1.2.3