From c8be85f3ffdc3a3cb51d1b54a9b5737c830b7fbe Mon Sep 17 00:00:00 2001 From: Sinan Akman Date: Tue, 11 May 2021 14:18:02 -0400 Subject: mpc8379erdb: enable DM_USB DM_PCI DM_ETH Signed-off-by: Sinan Akman --- arch/powerpc/cpu/mpc83xx/pci.c | 2 ++ arch/powerpc/dts/mpc8379erdb.dts | 52 +++++++++++++++++++++++++++++++ board/freescale/mpc837xerdb/mpc837xerdb.c | 11 ++++++- configs/MPC837XERDB_defconfig | 18 +++++------ 4 files changed, 73 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c index 5c289d0022..507ab3417b 100644 --- a/arch/powerpc/cpu/mpc83xx/pci.c +++ b/arch/powerpc/cpu/mpc83xx/pci.c @@ -27,6 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct pci_controller pci_hose[MAX_BUSES]; static int pci_num_buses; +#if !defined(CONFIG_DM_PCI) static void pci_init_bus(int bus, struct pci_region *reg) { volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; @@ -184,6 +185,7 @@ void mpc83xx_pcislave_unlock(int bus) hose->last_busno = pci_hose_scan(hose); } #endif +#endif /* CONFIG_DM_PCI */ #if defined(CONFIG_OF_LIBFDT) void ft_pci_setup(void *blob, struct bd_info *bd) diff --git a/arch/powerpc/dts/mpc8379erdb.dts b/arch/powerpc/dts/mpc8379erdb.dts index b1881b161c..2e7c8f103c 100644 --- a/arch/powerpc/dts/mpc8379erdb.dts +++ b/arch/powerpc/dts/mpc8379erdb.dts @@ -69,6 +69,58 @@ device_type = "ipic"; }; + usb@23000 { + compatible = "fsl-usb2-dr"; + reg = <0x23000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&ipic>; + interrupts = <38 0x8>; + phy_type = "ulpi"; + }; + + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <32 0x8 33 0x8 34 0x8>; + phy-connection-type = "mii"; + interrupt-parent = <&ipic>; + fixed-link = <1 0 1000 0 0>; + phy-handle = <&phy>; + fsl,magic-packet; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-mdio"; + reg = <0x520 0x20>; + + phy: ethernet-phy@2 { + interrupt-parent = <&ipic>; + interrupts = <17 0x8>; + reg = <0x2>; + device_type = "ethernet-phy"; + }; + }; + }; + + pci0: pci@e0008300 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + reg = <0x0 0xe0008300 0x0 0x00000fff>; + compatible = "fsl,mpc837x-pci"; + clock-frequency = <0>; + }; + }; }; diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 624e92ef9c..66b3d9a465 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -176,7 +176,7 @@ int board_early_init_f(void) } #ifdef CONFIG_FSL_ESDHC -#if !(CONFIG_IS_ENABLED(DM_MMC)) +#if !(CONFIG_IS_ENABLED(DM_MMC) || CONFIG_IS_ENABLED(DM_USB)) int board_mmc_init(struct bd_info *bd) { struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; @@ -217,6 +217,15 @@ int misc_init_r(void) return rc; } +int board_late_init(void) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; +#ifdef CONFIG_USB + clrsetbits_be32(&immap->sysconf.sicrl, SICRL_USB_A, 0x40000000); +#endif + return 0; +} + #if defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 003ebd8c6b..446d5948da 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -147,7 +147,9 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCIE" CONFIG_BOOTDELAY=6 +CONFIG_BOARD_LATE_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_PCI_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y @@ -172,16 +174,14 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_RGMII=y +CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_PCI=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -- cgit v1.2.3 From 7dd42be9f9d9c941844c3441b5b61a18e576c672 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 15 May 2021 14:44:19 +0200 Subject: ARM: integrator: Drop PCI support We didn't convert the Integrator to use DM for PCI in time, and we don't use it either so let's just drop PCI support from the Integrator. Signed-off-by: Linus Walleij Reviewed-by: Tom Rini --- board/armltd/integrator/Makefile | 1 - board/armltd/integrator/integrator.c | 1 - board/armltd/integrator/pci.c | 462 -------------------------------- board/armltd/integrator/pci_v3.h | 187 ------------- configs/integratorap_cm720t_defconfig | 4 - configs/integratorap_cm920t_defconfig | 4 - configs/integratorap_cm926ejs_defconfig | 4 - configs/integratorap_cm946es_defconfig | 4 - 8 files changed, 667 deletions(-) delete mode 100644 board/armltd/integrator/pci.c delete mode 100644 board/armltd/integrator/pci_v3.h diff --git a/board/armltd/integrator/Makefile b/board/armltd/integrator/Makefile index 8c906e3f07..107e59bf0f 100644 --- a/board/armltd/integrator/Makefile +++ b/board/armltd/integrator/Makefile @@ -10,5 +10,4 @@ obj-y := lowlevel_init.o obj-y += integrator.o -obj-$(CONFIG_PCI) += pci.o obj-y += timer.o diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index 3e864e8e7a..388795809d 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -181,7 +181,6 @@ int board_eth_init(struct bd_info *bis) #ifdef CONFIG_SMC91111 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); #endif - rc += pci_eth_init(bis); return rc; } #endif diff --git a/board/armltd/integrator/pci.c b/board/armltd/integrator/pci.c deleted file mode 100644 index 28efc33f1f..0000000000 --- a/board/armltd/integrator/pci.c +++ /dev/null @@ -1,462 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, - * - * (C) Copyright 2011 - * Linaro - * Linus Walleij - */ -#include -#include -#include -#include -#include -#include -#include -#include "integrator-sc.h" -#include "pci_v3.h" - -#define INTEGRATOR_BOOT_ROM_BASE 0x20000000 -#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 - -/* - * These are in the physical addresses on the CPU side, i.e. - * where we read and write stuff - you don't want to try to - * move these around - */ -#define PHYS_PCI_MEM_BASE 0x40000000 -#define PHYS_PCI_IO_BASE 0x60000000 /* PCI I/O space base */ -#define PHYS_PCI_CONFIG_BASE 0x61000000 -#define PHYS_PCI_V3_BASE 0x62000000 /* V360EPC registers */ -#define SZ_256M 0x10000000 - -/* - * These are in the PCI BUS address space - * Set to 0x00000000 in the Linux kernel, 0x40000000 in Boot monitor - * we follow the example of the kernel, because that is the address - * range that devices actually use - what would they be doing at - * 0x40000000? - */ -#define PCI_BUS_NONMEM_START 0x00000000 -#define PCI_BUS_NONMEM_SIZE SZ_256M - -#define PCI_BUS_PREMEM_START (PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE) -#define PCI_BUS_PREMEM_SIZE SZ_256M - -#if PCI_BUS_NONMEM_START & 0x000fffff -#error PCI_BUS_NONMEM_START must be megabyte aligned -#endif -#if PCI_BUS_PREMEM_START & 0x000fffff -#error PCI_BUS_PREMEM_START must be megabyte aligned -#endif - -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -#define PCI_ENET0_IOADDR 0x60000000 /* First card in PCI I/O space */ -#define PCI_ENET0_MEMADDR 0x40000000 /* First card in PCI memory space */ -static struct pci_config_table pci_integrator_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { } -}; -#endif /* CONFIG_PCI_PNP */ - -/* V3 access routines */ -#define v3_writeb(o, v) __raw_writeb(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) -#define v3_readb(o) (__raw_readb(PHYS_PCI_V3_BASE + (unsigned int)(o))) - -#define v3_writew(o, v) __raw_writew(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) -#define v3_readw(o) (__raw_readw(PHYS_PCI_V3_BASE + (unsigned int)(o))) - -#define v3_writel(o, v) __raw_writel(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) -#define v3_readl(o) (__raw_readl(PHYS_PCI_V3_BASE + (unsigned int)(o))) - -static unsigned long v3_open_config_window(pci_dev_t bdf, int offset) -{ - unsigned int address, mapaddress; - unsigned int busnr = PCI_BUS(bdf); - unsigned int devfn = PCI_FUNC(bdf); - - /* - * Trap out illegal values - */ - if (offset > 255) - BUG(); - if (busnr > 255) - BUG(); - if (devfn > 255) - BUG(); - - if (busnr == 0) { - /* - * Linux calls the thing U-Boot calls "DEV" "SLOT" - * instead, but it's the same 5 bits - */ - int slot = PCI_DEV(bdf); - - /* - * local bus segment so need a type 0 config cycle - * - * build the PCI configuration "address" with one-hot in - * A31-A11 - * - * mapaddress: - * 3:1 = config cycle (101) - * 0 = PCI A1 & A0 are 0 (0) - */ - address = PCI_FUNC(bdf) << 8; - mapaddress = V3_LB_MAP_TYPE_CONFIG; - - if (slot > 12) - /* - * high order bits are handled by the MAP register - */ - mapaddress |= 1 << (slot - 5); - else - /* - * low order bits handled directly in the address - */ - address |= 1 << (slot + 11); - } else { - /* - * not the local bus segment so need a type 1 config cycle - * - * address: - * 23:16 = bus number - * 15:11 = slot number (7:3 of devfn) - * 10:8 = func number (2:0 of devfn) - * - * mapaddress: - * 3:1 = config cycle (101) - * 0 = PCI A1 & A0 from host bus (1) - */ - mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN; - address = (busnr << 16) | (devfn << 8); - } - - /* - * Set up base0 to see all 512Mbytes of memory space (not - * prefetchable), this frees up base1 for re-use by - * configuration memory - */ - v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | - V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE); - - /* - * Set up base1/map1 to point into configuration space. - */ - v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) | - V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP1, mapaddress); - - return PHYS_PCI_CONFIG_BASE + address + offset; -} - -static void v3_close_config_window(void) -{ - /* - * Reassign base1 for use by prefetchable PCI memory - */ - v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | - V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | - V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | - V3_LB_MAP_TYPE_MEM_MULTIPLE); - - /* - * And shrink base0 back to a 256M window (NOTE: MAP0 already correct) - */ - v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | - V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); -} - -static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t bdf, - int offset, unsigned char *val) -{ - unsigned long addr; - - addr = v3_open_config_window(bdf, offset); - *val = __raw_readb(addr); - v3_close_config_window(); - return 0; -} - -static int pci_integrator_read__word(struct pci_controller *hose, - pci_dev_t bdf, int offset, - unsigned short *val) -{ - unsigned long addr; - - addr = v3_open_config_window(bdf, offset); - *val = __raw_readw(addr); - v3_close_config_window(); - return 0; -} - -static int pci_integrator_read_dword(struct pci_controller *hose, - pci_dev_t bdf, int offset, - unsigned int *val) -{ - unsigned long addr; - - addr = v3_open_config_window(bdf, offset); - *val = __raw_readl(addr); - v3_close_config_window(); - return 0; -} - -static int pci_integrator_write_byte(struct pci_controller *hose, - pci_dev_t bdf, int offset, - unsigned char val) -{ - unsigned long addr; - - addr = v3_open_config_window(bdf, offset); - __raw_writeb((u8)val, addr); - __raw_readb(addr); - v3_close_config_window(); - return 0; -} - -static int pci_integrator_write_word(struct pci_controller *hose, - pci_dev_t bdf, int offset, - unsigned short val) -{ - unsigned long addr; - - addr = v3_open_config_window(bdf, offset); - __raw_writew((u8)val, addr); - __raw_readw(addr); - v3_close_config_window(); - return 0; -} - -static int pci_integrator_write_dword(struct pci_controller *hose, - pci_dev_t bdf, int offset, - unsigned int val) -{ - unsigned long addr; - - addr = v3_open_config_window(bdf, offset); - __raw_writel((u8)val, addr); - __raw_readl(addr); - v3_close_config_window(); - return 0; -} - -struct pci_controller integrator_hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_integrator_config_table, -#endif -}; - -void pci_init_board(void) -{ - struct pci_controller *hose = &integrator_hose; - u16 val; - - /* setting this register will take the V3 out of reset */ - __raw_writel(SC_PCI_PCIEN, SC_PCI); - - /* Wait for 230 ms (from spec) before accessing any V3 registers */ - mdelay(230); - - /* Now write the Base I/O Address Word to PHYS_PCI_V3_BASE + 0x6E */ - v3_writew(V3_LB_IO_BASE, (PHYS_PCI_V3_BASE >> 16)); - - /* Wait for the mailbox to settle */ - do { - v3_writeb(V3_MAIL_DATA, 0xAA); - v3_writeb(V3_MAIL_DATA + 4, 0x55); - } while (v3_readb(V3_MAIL_DATA) != 0xAA || - v3_readb(V3_MAIL_DATA + 4) != 0x55); - - /* Make sure that V3 register access is not locked, if it is, unlock it */ - if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK) - v3_writew(V3_SYSTEM, 0xA05F); - - /* - * Ensure that the slave accesses from PCI are disabled while we - * setup memory windows - */ - val = v3_readw(V3_PCI_CMD); - val &= ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN); - v3_writew(V3_PCI_CMD, val); - - /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */ - val = v3_readw(V3_SYSTEM); - val &= ~V3_SYSTEM_M_RST_OUT; - v3_writew(V3_SYSTEM, val); - - /* Make all accesses from PCI space retry until we're ready for them */ - val = v3_readw(V3_PCI_CFG); - val |= V3_PCI_CFG_M_RETRY_EN; - v3_writew(V3_PCI_CFG, val); - - /* - * Set up any V3 PCI Configuration Registers that we absolutely have to. - * LB_CFG controls Local Bus protocol. - * Enable LocalBus byte strobes for READ accesses too. - * set bit 7 BE_IMODE and bit 6 BE_OMODE - */ - val = v3_readw(V3_LB_CFG); - val |= 0x0C0; - v3_writew(V3_LB_CFG, val); - - /* PCI_CMD controls overall PCI operation. Enable PCI bus master. */ - val = v3_readw(V3_PCI_CMD); - val |= V3_COMMAND_M_MASTER_EN; - v3_writew(V3_PCI_CMD, val); - - /* - * PCI_MAP0 controls where the PCI to CPU memory window is on - * Local Bus - */ - v3_writel(V3_PCI_MAP0, - (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512MB | - V3_PCI_MAP_M_REG_EN | - V3_PCI_MAP_M_ENABLE)); - - /* PCI_BASE0 is the PCI address of the start of the window */ - v3_writel(V3_PCI_BASE0, INTEGRATOR_BOOT_ROM_BASE); - - /* PCI_MAP1 is LOCAL address of the start of the window */ - v3_writel(V3_PCI_MAP1, - (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1GB | - V3_PCI_MAP_M_REG_EN | - V3_PCI_MAP_M_ENABLE)); - - /* PCI_BASE1 is the PCI address of the start of the window */ - v3_writel(V3_PCI_BASE1, INTEGRATOR_HDR0_SDRAM_BASE); - - /* - * Set up memory the windows from local bus memory into PCI - * configuration, I/O and Memory regions. - * PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. - */ - v3_writew(V3_LB_BASE2, - v3_addr_to_lb_map(PHYS_PCI_IO_BASE) | V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP2, 0); - - /* PCI Configuration, use LB_BASE1/LB_MAP1. */ - - /* - * PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 - * Map first 256Mbytes as non-prefetchable via BASE0/MAP0 - */ - v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | - V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP0, - v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | V3_LB_MAP_TYPE_MEM); - - /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */ - v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | - V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | - V3_LB_BASE_ENABLE); - v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | - V3_LB_MAP_TYPE_MEM_MULTIPLE); - - /* Dump PCI to local address space mappings */ - debug("LB_BASE0 = %08x\n", v3_readl(V3_LB_BASE0)); - debug("LB_MAP0 = %04x\n", v3_readw(V3_LB_MAP0)); - debug("LB_BASE1 = %08x\n", v3_readl(V3_LB_BASE1)); - debug("LB_MAP1 = %04x\n", v3_readw(V3_LB_MAP1)); - debug("LB_BASE2 = %04x\n", v3_readw(V3_LB_BASE2)); - debug("LB_MAP2 = %04x\n", v3_readw(V3_LB_MAP2)); - debug("LB_IO_BASE = %04x\n", v3_readw(V3_LB_IO_BASE)); - - /* - * Allow accesses to PCI Configuration space and set up A1, A0 for - * type 1 config cycles - */ - val = v3_readw(V3_PCI_CFG); - val &= ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1); - val |= V3_PCI_CFG_M_AD_LOW0; - v3_writew(V3_PCI_CFG, val); - - /* now we can allow incoming PCI MEMORY accesses */ - val = v3_readw(V3_PCI_CMD); - val |= V3_COMMAND_M_MEM_EN; - v3_writew(V3_PCI_CMD, val); - - /* - * Set RST_OUT to take the PCI bus is out of reset, PCI devices can - * now initialise. - */ - val = v3_readw(V3_SYSTEM); - val |= V3_SYSTEM_M_RST_OUT; - v3_writew(V3_SYSTEM, val); - - /* Lock the V3 system register so that no one else can play with it */ - val = v3_readw(V3_SYSTEM); - val |= V3_SYSTEM_M_LOCK; - v3_writew(V3_SYSTEM, val); - - /* - * Configure and register the PCI hose - */ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space, window 0 256 MB non-prefetchable */ - pci_set_region(hose->regions + 0, - PCI_BUS_NONMEM_START, PHYS_PCI_MEM_BASE, - SZ_256M, - PCI_REGION_MEM); - - /* System memory space, window 1 256 MB prefetchable */ - pci_set_region(hose->regions + 1, - PCI_BUS_PREMEM_START, PHYS_PCI_MEM_BASE + SZ_256M, - SZ_256M, - PCI_REGION_MEM | - PCI_REGION_PREFETCH); - - /* PCI I/O space */ - pci_set_region(hose->regions + 2, - 0x00000000, PHYS_PCI_IO_BASE, 0x01000000, - PCI_REGION_IO); - - /* PCI Memory - config space */ - pci_set_region(hose->regions + 3, - 0x00000000, PHYS_PCI_CONFIG_BASE, 0x01000000, - PCI_REGION_MEM); - /* PCI V3 regs */ - pci_set_region(hose->regions + 4, - 0x00000000, PHYS_PCI_V3_BASE, 0x01000000, - PCI_REGION_MEM); - - hose->region_count = 5; - - pci_set_ops(hose, - pci_integrator_read_byte, - pci_integrator_read__word, - pci_integrator_read_dword, - pci_integrator_write_byte, - pci_integrator_write_word, - pci_integrator_write_dword); - - pci_register_hose(hose); - - pciauto_config_init(hose); - pciauto_config_device(hose, 0); - - hose->last_busno = pci_hose_scan(hose); -} diff --git a/board/armltd/integrator/pci_v3.h b/board/armltd/integrator/pci_v3.h deleted file mode 100644 index 8d09e6966d..0000000000 --- a/board/armltd/integrator/pci_v3.h +++ /dev/null @@ -1,187 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * arch/arm/include/asm/hardware/pci_v3.h - * - * Internal header file PCI V3 chip - * - * Copyright (C) ARM Limited - * Copyright (C) 2000-2001 Deep Blue Solutions Ltd. - */ -#ifndef ASM_ARM_HARDWARE_PCI_V3_H -#define ASM_ARM_HARDWARE_PCI_V3_H - -/* ------------------------------------------------------------------------------- - * V3 Local Bus to PCI Bridge definitions - * ------------------------------------------------------------------------------- - * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04 - * All V3 register names are prefaced by V3_ to avoid clashing with any other - * PCI definitions. Their names match the user's manual. - * - * I'm assuming that I20 is disabled. - * - */ -#define V3_PCI_VENDOR 0x00000000 -#define V3_PCI_DEVICE 0x00000002 -#define V3_PCI_CMD 0x00000004 -#define V3_PCI_STAT 0x00000006 -#define V3_PCI_CC_REV 0x00000008 -#define V3_PCI_HDR_CFG 0x0000000C -#define V3_PCI_IO_BASE 0x00000010 -#define V3_PCI_BASE0 0x00000014 -#define V3_PCI_BASE1 0x00000018 -#define V3_PCI_SUB_VENDOR 0x0000002C -#define V3_PCI_SUB_ID 0x0000002E -#define V3_PCI_ROM 0x00000030 -#define V3_PCI_BPARAM 0x0000003C -#define V3_PCI_MAP0 0x00000040 -#define V3_PCI_MAP1 0x00000044 -#define V3_PCI_INT_STAT 0x00000048 -#define V3_PCI_INT_CFG 0x0000004C -#define V3_LB_BASE0 0x00000054 -#define V3_LB_BASE1 0x00000058 -#define V3_LB_MAP0 0x0000005E -#define V3_LB_MAP1 0x00000062 -#define V3_LB_BASE2 0x00000064 -#define V3_LB_MAP2 0x00000066 -#define V3_LB_SIZE 0x00000068 -#define V3_LB_IO_BASE 0x0000006E -#define V3_FIFO_CFG 0x00000070 -#define V3_FIFO_PRIORITY 0x00000072 -#define V3_FIFO_STAT 0x00000074 -#define V3_LB_ISTAT 0x00000076 -#define V3_LB_IMASK 0x00000077 -#define V3_SYSTEM 0x00000078 -#define V3_LB_CFG 0x0000007A -#define V3_PCI_CFG 0x0000007C -#define V3_DMA_PCI_ADR0 0x00000080 -#define V3_DMA_PCI_ADR1 0x00000090 -#define V3_DMA_LOCAL_ADR0 0x00000084 -#define V3_DMA_LOCAL_ADR1 0x00000094 -#define V3_DMA_LENGTH0 0x00000088 -#define V3_DMA_LENGTH1 0x00000098 -#define V3_DMA_CSR0 0x0000008B -#define V3_DMA_CSR1 0x0000009B -#define V3_DMA_CTLB_ADR0 0x0000008C -#define V3_DMA_CTLB_ADR1 0x0000009C -#define V3_DMA_DELAY 0x000000E0 -#define V3_MAIL_DATA 0x000000C0 -#define V3_PCI_MAIL_IEWR 0x000000D0 -#define V3_PCI_MAIL_IERD 0x000000D2 -#define V3_LB_MAIL_IEWR 0x000000D4 -#define V3_LB_MAIL_IERD 0x000000D6 -#define V3_MAIL_WR_STAT 0x000000D8 -#define V3_MAIL_RD_STAT 0x000000DA -#define V3_QBA_MAP 0x000000DC - -/* PCI COMMAND REGISTER bits - */ -#define V3_COMMAND_M_FBB_EN (1 << 9) -#define V3_COMMAND_M_SERR_EN (1 << 8) -#define V3_COMMAND_M_PAR_EN (1 << 6) -#define V3_COMMAND_M_MASTER_EN (1 << 2) -#define V3_COMMAND_M_MEM_EN (1 << 1) -#define V3_COMMAND_M_IO_EN (1 << 0) - -/* SYSTEM REGISTER bits - */ -#define V3_SYSTEM_M_RST_OUT (1 << 15) -#define V3_SYSTEM_M_LOCK (1 << 14) - -/* PCI_CFG bits - */ -#define V3_PCI_CFG_M_I2O_EN (1 << 15) -#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14) -#define V3_PCI_CFG_M_IO_DIS (1 << 13) -#define V3_PCI_CFG_M_EN3V (1 << 12) -#define V3_PCI_CFG_M_RETRY_EN (1 << 10) -#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) -#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) - -/* PCI_BASE register bits (PCI -> Local Bus) - */ -#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000 -#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00 -#define V3_PCI_BASE_M_PREFETCH (1 << 3) -#define V3_PCI_BASE_M_TYPE (3 << 1) -#define V3_PCI_BASE_M_IO (1 << 0) - -/* PCI MAP register bits (PCI -> Local bus) - */ -#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 -#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) -#define V3_PCI_MAP_M_ROM_SIZE (3 << 10) -#define V3_PCI_MAP_M_SWAP (3 << 8) -#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 -#define V3_PCI_MAP_M_REG_EN (1 << 1) -#define V3_PCI_MAP_M_ENABLE (1 << 0) - -#define V3_PCI_MAP_M_ADR_SIZE_1MB (0 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_2MB (1 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_4MB (2 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_8MB (3 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_16MB (4 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_32MB (5 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_64MB (6 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_128MB (7 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_256MB (8 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_512MB (9 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_1GB (10 << 4) -#define V3_PCI_MAP_M_ADR_SIZE_2GB (11 << 4) - -/* - * LB_BASE0,1 register bits (Local bus -> PCI) - */ -#define V3_LB_BASE_ADR_BASE 0xfff00000 -#define V3_LB_BASE_SWAP (3 << 8) -#define V3_LB_BASE_ADR_SIZE (15 << 4) -#define V3_LB_BASE_PREFETCH (1 << 3) -#define V3_LB_BASE_ENABLE (1 << 0) - -#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) -#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) -#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) -#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) -#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) -#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) -#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) -#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) -#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) -#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) -#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) -#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) - -#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) - -/* - * LB_MAP0,1 register bits (Local bus -> PCI) - */ -#define V3_LB_MAP_MAP_ADR 0xfff0 -#define V3_LB_MAP_TYPE (7 << 1) -#define V3_LB_MAP_AD_LOW_EN (1 << 0) - -#define V3_LB_MAP_TYPE_IACK (0 << 1) -#define V3_LB_MAP_TYPE_IO (1 << 1) -#define V3_LB_MAP_TYPE_MEM (3 << 1) -#define V3_LB_MAP_TYPE_CONFIG (5 << 1) -#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) - -/* PCI MAP register bits (PCI -> Local bus) */ -#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) - -/* - * LB_BASE2 register bits (Local bus -> PCI IO) - */ -#define V3_LB_BASE2_ADR_BASE 0xff00 -#define V3_LB_BASE2_SWAP (3 << 6) -#define V3_LB_BASE2_ENABLE (1 << 0) - -#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) - -/* - * LB_MAP2 register bits (Local bus -> PCI IO) - */ -#define V3_LB_MAP2_MAP_ADR 0xff00 - -#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) - -#endif diff --git a/configs/integratorap_cm720t_defconfig b/configs/integratorap_cm720t_defconfig index 5d28135a82..378bf936d7 100644 --- a/configs/integratorap_cm720t_defconfig +++ b/configs/integratorap_cm720t_defconfig @@ -16,7 +16,6 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Integrator-AP # " CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y -CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_MMC is not set @@ -24,8 +23,5 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y -CONFIG_EEPRO100=y -CONFIG_TULIP=y -CONFIG_PCI=y CONFIG_BAUDRATE=38400 CONFIG_OF_LIBFDT=y diff --git a/configs/integratorap_cm920t_defconfig b/configs/integratorap_cm920t_defconfig index 0e914e91eb..4ec2961a4e 100644 --- a/configs/integratorap_cm920t_defconfig +++ b/configs/integratorap_cm920t_defconfig @@ -16,7 +16,6 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Integrator-AP # " CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y -CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_MMC is not set @@ -24,8 +23,5 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y -CONFIG_EEPRO100=y -CONFIG_TULIP=y -CONFIG_PCI=y CONFIG_BAUDRATE=38400 CONFIG_OF_LIBFDT=y diff --git a/configs/integratorap_cm926ejs_defconfig b/configs/integratorap_cm926ejs_defconfig index d28bc0f976..012d346500 100644 --- a/configs/integratorap_cm926ejs_defconfig +++ b/configs/integratorap_cm926ejs_defconfig @@ -16,7 +16,6 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Integrator-AP # " CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y -CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_MMC is not set @@ -24,8 +23,5 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y -CONFIG_EEPRO100=y -CONFIG_TULIP=y -CONFIG_PCI=y CONFIG_BAUDRATE=38400 CONFIG_OF_LIBFDT=y diff --git a/configs/integratorap_cm946es_defconfig b/configs/integratorap_cm946es_defconfig index ae44f01ff5..1868c7024f 100644 --- a/configs/integratorap_cm946es_defconfig +++ b/configs/integratorap_cm946es_defconfig @@ -16,7 +16,6 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Integrator-AP # " CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y -CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_MMC is not set @@ -24,8 +23,5 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y -CONFIG_EEPRO100=y -CONFIG_TULIP=y -CONFIG_PCI=y CONFIG_BAUDRATE=38400 CONFIG_OF_LIBFDT=y -- cgit v1.2.3 From 9fe79ca0ac3469a00a7d7fba94155758e2ac2cdf Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 4 Jun 2021 14:25:36 +1200 Subject: arm: iproc: Add higher speed configurations Add support for 1.3GHz, 1.35GHz and 1.4GHz parts. This is based on equivalent code in Broadcom's LDK 5.0.6. Signed-off-by: Chris Packham --- arch/arm/cpu/armv7/iproc-common/armpll.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/arch/arm/cpu/armv7/iproc-common/armpll.c b/arch/arm/cpu/armv7/iproc-common/armpll.c index efa3d9e5a9..8c3a323f06 100644 --- a/arch/arm/cpu/armv7/iproc-common/armpll.c +++ b/arch/arm/cpu/armv7/iproc-common/armpll.c @@ -19,19 +19,22 @@ struct armpll_parameters { }; struct armpll_parameters armpll_clk_tab[] = { - { 25, 64, 1, 1, 0}, - { 100, 64, 1, 1, 2}, - { 400, 64, 1, 1, 6}, - { 448, 71, 713050, 1, 6}, - { 500, 80, 1, 1, 6}, - { 560, 89, 629145, 1, 6}, - { 600, 96, 1, 1, 6}, - { 800, 64, 1, 1, 7}, - { 896, 71, 713050, 1, 7}, - { 1000, 80, 1, 1, 7}, - { 1100, 88, 1, 1, 7}, - { 1120, 89, 629145, 1, 7}, - { 1200, 96, 1, 1, 7}, + { 25, 64, 1, 1, 0}, + { 100, 64, 1, 1, 2}, + { 400, 64, 1, 1, 6}, + { 448, 71, 713050, 1, 6}, + { 500, 80, 1, 1, 6}, + { 560, 89, 629145, 1, 6}, + { 600, 96, 1, 1, 6}, + { 800, 64, 1, 1, 7}, + { 896, 71, 713050, 1, 7}, + { 1000, 80, 1, 1, 7}, + { 1100, 88, 1, 1, 7}, + { 1120, 89, 629145, 1, 7}, + { 1200, 96, 1, 1, 7}, + { 1300, 104, 1, 1, 7}, + { 1350, 108, 1, 1, 7}, + { 1400, 112, 1, 1, 7}, }; uint32_t armpll_config(uint32_t clkmhz) -- cgit v1.2.3 From ada6894febd02c7154bafbb3a08fb775b071e40c Mon Sep 17 00:00:00 2001 From: Masami Hiramatsu Date: Fri, 4 Jun 2021 18:43:23 +0900 Subject: ata: ahci-pci: Use scsi_ops to initialize ops Without this fix, scsi-scan will cause a synchronous abort when accessing ops->scan. Signed-off-by: Masami Hiramatsu Reviewed-by: Simon Glass --- drivers/ata/ahci-pci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c index 11ec98b56f..b1d231e0f9 100644 --- a/drivers/ata/ahci-pci.c +++ b/drivers/ata/ahci-pci.c @@ -5,6 +5,7 @@ #include #include +#include #include #include @@ -28,6 +29,7 @@ static const struct udevice_id ahci_pci_ids[] = { U_BOOT_DRIVER(ahci_pci) = { .name = "ahci_pci", .id = UCLASS_AHCI, + .ops = &scsi_ops, .of_match = ahci_pci_ids, .bind = ahci_pci_bind, .probe = ahci_pci_probe, -- cgit v1.2.3 From 2f7dddc2a5c1c091b24588ef9ba1917ebd268595 Mon Sep 17 00:00:00 2001 From: Masami Hiramatsu Date: Fri, 4 Jun 2021 18:43:34 +0900 Subject: dm: pci: Skip setting VGA bridge bits if parent device is the host bus Commit bbbcb5262839 ("dm: pci: Enable VGA address forwarding on bridges") sets the VGA bridge bits by checking pplat->class, but if the parent device is the pci host bus device, it can be skipped. Moreover, it shouldn't access the pplat because the parent has different plat data. Without this fix, "pci enum" command cause a synchronous abort. pci_auto_config_devices: start PCI Autoconfig: Bus Memory region: [78000000-7fffffff], Physical Memory [78000000-7fffffffx] PCI Autoconfig: Bus I/O region: [0-ffff], Physical Memory [77f00000-77f0ffffx] pci_auto_config_devices: device pci_6:0.0 PCI Autoconfig: BAR 0, Mem, size=0x1000000, address=0x78000000 bus_lower=0x79000000 PCI Autoconfig: BAR 1, Mem, size=0x8000000, No room in resource, avail start=79000000 / size=8000000, need=8000000 PCI: Failed autoconfig bar 14 PCI Autoconfig: BAR 2, I/O, size=0x4, address=0x1000 bus_lower=0x1004 PCI Autoconfig: BAR 3, Mem, size=0x2000000, address=0x7a000000 bus_lower=0x7c000000 PCI Autoconfig: BAR 4, I/O, size=0x80, address=0x1080 bus_lower=0x1100 PCI Autoconfig: ROM, size=0x80000, address=0x7c000000 bus_lower=0x7c080000 "Synchronous Abort" handler, esr 0x96000006 elr: 00000000e002bd28 lr : 00000000e002bce8 (reloc) elr: 00000000fff6fd28 lr : 00000000fff6fce8 x0 : 0000000000001041 x1 : 000000000000003e x2 : 00000000ffb0f8c8 x3 : 0000000000000001 x4 : 0000000000000080 x5 : 0000000000000000 x6 : 00000000fff718fc x7 : 000000000000000f x8 : 00000000ffb0f238 x9 : 0000000000000008 x10: 0000000000000000 x11: 0000000000000010 x12: 0000000000000006 x13: 000000000001869f x14: 00000000ffb0fcd0 x15: 0000000000000020 x16: 00000000fff71cc4 x17: 0000000000000000 x18: 00000000ffb13d90 x19: 00000000ffb14320 x20: 0000000000000000 x21: 00000000ffb14090 x22: 00000000ffb0f8c8 x23: 0000000000000001 x24: 00000000ffb14c10 x25: 0000000000000000 x26: 0000000000000000 x27: 0000000000000000 x28: 00000000ffb14c70 x29: 00000000ffb0f830 Code: 52800843 52800061 52800e00 97ffcf65 (b9400280) Resetting CPU ... Signed-off-by: Masami Hiramatsu Reviewed-by: Simon Glass --- drivers/pci/pci-uclass.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 22a033e632..afe4f1974a 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -550,6 +550,9 @@ int pci_auto_config_devices(struct udevice *bus) max_bus = ret; sub_bus = max(sub_bus, max_bus); + if (dev_get_parent(dev) == bus) + continue; + pplat = dev_get_parent_plat(dev); if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8)) set_vga_bridge_bits(dev); -- cgit v1.2.3 From 7a672057dcd36792f01529922fc85892a03be22d Mon Sep 17 00:00:00 2001 From: Masami Hiramatsu Date: Fri, 4 Jun 2021 18:43:55 +0900 Subject: gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs Since some SoCs and boards do not hae extra asm/arch/gpio.h, introduce CONFIG_GPIO_EXTRA_HEADER instead of adding !define(CONFIG_ARCH_XXXX) in asm/gpio.h. Signed-off-by: Masami Hiramatsu --- arch/arm/Kconfig | 94 +++++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/gpio.h | 8 +--- 2 files changed, 95 insertions(+), 7 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0448787b8b..993772b643 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -90,6 +90,9 @@ config HAS_VBAR config HAS_THUMB2 bool +config GPIO_EXTRA_HEADER + bool + # Used for compatibility with asm files copied from the kernel config ARM_ASM_UNIFIED bool @@ -518,25 +521,30 @@ choice config ARCH_AT91 bool "Atmel AT91" + select GPIO_EXTRA_HEADER select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB select SPL_SEPARATE_BSS if SPL config TARGET_EDB93XX bool "Support edb93xx" select CPU_ARM920T + select GPIO_EXTRA_HEADER select PL010_SERIAL config TARGET_ASPENITE bool "Support aspenite" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config TARGET_GPLUGD bool "Support gplugd" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config ARCH_DAVINCI bool "TI DaVinci" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select SPL_DM_SPI if SPL imply CMD_SAVES help @@ -547,6 +555,7 @@ config ARCH_KIRKWOOD select ARCH_MISC_INIT select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config ARCH_MVEBU bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)" @@ -555,6 +564,7 @@ config ARCH_MVEBU select DM_SERIAL select DM_SPI select DM_SPI_FLASH + select GPIO_EXTRA_HEADER select SPL_DM_SPI if SPL select SPL_DM_SPI_FLASH if SPL select OF_CONTROL @@ -565,11 +575,13 @@ config ARCH_MVEBU config ARCH_ORION5X bool "Marvell Orion" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config TARGET_SPEAR300 bool "Support spear300" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -577,6 +589,7 @@ config TARGET_SPEAR310 bool "Support spear310" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -584,6 +597,7 @@ config TARGET_SPEAR320 bool "Support spear320" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -591,6 +605,7 @@ config TARGET_SPEAR600 bool "Support spear600" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -601,6 +616,7 @@ config TARGET_STV0991 select DM_SERIAL select DM_SPI select DM_SPI_FLASH + select GPIO_EXTRA_HEADER select PL01X_SERIAL select SPI select SPI_FLASH @@ -610,18 +626,21 @@ config TARGET_X600 bool "Support x600" select BOARD_LATE_INIT select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL select SUPPORT_SPL config TARGET_FLEA3 bool "Support flea3" select CPU_ARM1136 + select GPIO_EXTRA_HEADER config ARCH_BCM283X bool "Broadcom BCM283X family" select DM select DM_GPIO select DM_SERIAL + select GPIO_EXTRA_HEADER select OF_CONTROL select PL01X_SERIAL select SERIAL_SEARCH_ALL @@ -650,6 +669,7 @@ config ARCH_BCMSTB bool "Broadcom BCM7XXX family" select CPU_V7A select DM + select GPIO_EXTRA_HEADER select OF_CONTROL select OF_PRIOR_STAGE imply CMD_DM @@ -660,6 +680,7 @@ config ARCH_BCMSTB config TARGET_BCMCYGNUS bool "Support bcmcygnus" select CPU_V7A + select GPIO_EXTRA_HEADER imply BCM_SF2_ETH imply BCM_SF2_ETH_GMAC imply CMD_HASH @@ -671,6 +692,7 @@ config TARGET_BCMCYGNUS config TARGET_BCMNS2 bool "Support Broadcom Northstar2" select ARM64 + select GPIO_EXTRA_HEADER help Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit ARMv8 Cortex-A57 processors targeting a broad range of networking @@ -695,6 +717,7 @@ config ARCH_EXYNOS select DM_SPI select DM_SPI_FLASH select SPI + select GPIO_EXTRA_HEADER imply SYS_THUMB_BUILD imply CMD_DM imply FAT_WRITE @@ -706,6 +729,7 @@ config ARCH_S5PC1XX select DM_GPIO select DM_I2C select DM_SERIAL + select GPIO_EXTRA_HEADER imply CMD_DM config ARCH_HIGHBANK @@ -726,6 +750,7 @@ config ARCH_INTEGRATOR bool "ARM Ltd. Integrator family" select DM select DM_SERIAL + select GPIO_EXTRA_HEADER select PL01X_SERIAL imply CMD_DM @@ -736,6 +761,7 @@ config ARCH_IPQ40XX select DM_GPIO select DM_SERIAL select DM_RESET + select GPIO_EXTRA_HEADER select MSM_SMEM select PINCTRL select CLK @@ -747,6 +773,7 @@ config ARCH_KEYSTONE bool "TI Keystone" select CMD_POWEROFF select CPU_V7A + select GPIO_EXTRA_HEADER select SUPPORT_SPL select SYS_ARCH_TIMER select SYS_THUMB_BUILD @@ -763,6 +790,7 @@ config ARCH_K3 config ARCH_OMAP2PLUS bool "TI OMAP2+" select CPU_V7A + select GPIO_EXTRA_HEADER select SPL_BOARD_INIT if SPL select SPL_STACK_R if SPL select SUPPORT_SPL @@ -771,6 +799,7 @@ config ARCH_OMAP2PLUS config ARCH_MESON bool "Amlogic Meson" + select GPIO_EXTRA_HEADER imply DISTRO_DEFAULTS imply DM_RNG help @@ -781,6 +810,7 @@ config ARCH_MESON config ARCH_MEDIATEK bool "MediaTek SoCs" select DM + select GPIO_EXTRA_HEADER select OF_CONTROL select SPL_DM if SPL select SPL_LIBCOMMON_SUPPORT if SPL @@ -797,6 +827,7 @@ config ARCH_LPC32XX select DM select DM_GPIO select DM_SERIAL + select GPIO_EXTRA_HEADER select SPL_DM if SPL select SUPPORT_SPL imply CMD_DM @@ -805,12 +836,14 @@ config ARCH_IMX8 bool "NXP i.MX8 platform" select ARM64 select DM + select GPIO_EXTRA_HEADER select OF_CONTROL select ENABLE_ARM_SOC_BOOT0_HOOK config ARCH_IMX8M bool "NXP i.MX8M platform" select ARM64 + select GPIO_EXTRA_HEADER select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -823,33 +856,39 @@ config ARCH_IMXRT select CPU_V7M select DM select DM_SERIAL + select GPIO_EXTRA_HEADER select SUPPORT_SPL imply CMD_DM config ARCH_MX23 bool "NXP i.MX23 family" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL select SUPPORT_SPL config ARCH_MX25 bool "NXP MX25" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER imply MXC_GPIO config ARCH_MX28 bool "NXP i.MX28 family" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL select SUPPORT_SPL config ARCH_MX31 bool "NXP i.MX31 family" select CPU_ARM1136 + select GPIO_EXTRA_HEADER config ARCH_MX7ULP bool "NXP MX7ULP" select CPU_V7A + select GPIO_EXTRA_HEADER select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -861,6 +900,7 @@ config ARCH_MX7 bool "Freescale MX7" select ARCH_MISC_INIT select CPU_V7A + select GPIO_EXTRA_HEADER select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -871,6 +911,7 @@ config ARCH_MX7 config ARCH_MX6 bool "Freescale MX6" select CPU_V7A + select GPIO_EXTRA_HEADER select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -886,18 +927,21 @@ config ARCH_MX5 bool "Freescale MX5" select BOARD_EARLY_INIT_F select CPU_V7A + select GPIO_EXTRA_HEADER imply MXC_GPIO config ARCH_NEXELL bool "Nexell S5P4418/S5P6818 SoC" select ENABLE_ARM_SOC_BOOT0_HOOK select DM + select GPIO_EXTRA_HEADER config ARCH_OWL bool "Actions Semi OWL SoCs" select DM select DM_ETH select DM_SERIAL + select GPIO_EXTRA_HEADER select OWL_SERIAL select CLK select CLK_OWL @@ -920,6 +964,7 @@ config ARCH_RMOBILE bool "Renesas ARM SoCs" select DM select DM_SERIAL + select GPIO_EXTRA_HEADER imply BOARD_EARLY_INIT_F imply CMD_DM imply FAT_WRITE @@ -932,6 +977,7 @@ config ARCH_SNAPDRAGON select DM select DM_GPIO select DM_SERIAL + select GPIO_EXTRA_HEADER select MSM_SMEM select OF_CONTROL select OF_SEPARATE @@ -947,6 +993,7 @@ config ARCH_SOCFPGA select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select DM select DM_SERIAL + select GPIO_EXTRA_HEADER select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select OF_CONTROL select SPL_DM_RESET if DM_RESET @@ -998,6 +1045,7 @@ config ARCH_SUNXI select DM_SCSI if SCSI select DM_SERIAL select DM_USB if DISTRO_DEFAULTS + select GPIO_EXTRA_HEADER select OF_BOARD_SETUP select OF_CONTROL select OF_SEPARATE @@ -1057,6 +1105,7 @@ config ARCH_VERSAL select DM_ETH if NET select DM_MMC if MMC select DM_SERIAL + select GPIO_EXTRA_HEADER select OF_CONTROL imply BOARD_LATE_INIT imply ENV_VARS_UBOOT_RUNTIME_CONFIG @@ -1064,6 +1113,7 @@ config ARCH_VERSAL config ARCH_VF610 bool "Freescale Vybrid" select CPU_V7A + select GPIO_EXTRA_HEADER select SYS_FSL_ERRATUM_ESDHC111 imply CMD_MTDPARTS imply MTD_RAW_NAND @@ -1080,6 +1130,7 @@ config ARCH_ZYNQ select DM_SPI select DM_SPI_FLASH select DM_USB if USB + select GPIO_EXTRA_HEADER select OF_CONTROL select SPI select SPL_BOARD_INIT if SPL @@ -1106,6 +1157,7 @@ config ARCH_ZYNQMP_R5 select DM_ETH if NET select DM_MMC if MMC select DM_SERIAL + select GPIO_EXTRA_HEADER select OF_CONTROL imply CMD_DM imply DM_USB_GADGET @@ -1123,6 +1175,7 @@ config ARCH_ZYNQMP select DM_SPI_FLASH if DM_SPI select DM_USB if USB select FIRMWARE + select GPIO_EXTRA_HEADER select OF_CONTROL select SPL_BOARD_INIT if SPL select SPL_CLK if SPL @@ -1143,23 +1196,27 @@ config ARCH_ZYNQMP config ARCH_TEGRA bool "NVIDIA Tegra" + select GPIO_EXTRA_HEADER imply DISTRO_DEFAULTS imply FAT_WRITE config TARGET_VEXPRESS64_AEMV8A bool "Support vexpress_aemv8a" select ARM64 + select GPIO_EXTRA_HEADER select PL01X_SERIAL config TARGET_VEXPRESS64_BASE_FVP bool "Support Versatile Express ARMv8a FVP BASE model" select ARM64 + select GPIO_EXTRA_HEADER select PL01X_SERIAL select SEMIHOSTING config TARGET_VEXPRESS64_JUNO bool "Support Versatile Express Juno Development Platform" select ARM64 + select GPIO_EXTRA_HEADER select PL01X_SERIAL select DM select OF_CONTROL @@ -1188,6 +1245,7 @@ config TARGET_LS2080A_EMU select ARM64 select ARMV8_MULTIENTRY select FSL_DDR_SYNC_REFRESH + select GPIO_EXTRA_HEADER help Support for Freescale LS2080A_EMU platform. The LS2080A Development System (EMULATOR) is a pre-silicon @@ -1201,6 +1259,7 @@ config TARGET_LS1088AQDS select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER select SUPPORT_SPL select FSL_DDR_INTERACTIVE if !SD_BOOT help @@ -1216,6 +1275,7 @@ config TARGET_LS2080AQDS select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER select SUPPORT_SPL imply SCSI imply SCSI_AHCI @@ -1237,6 +1297,7 @@ config TARGET_LS2080ARDB select SUPPORT_SPL select FSL_DDR_BIST select FSL_DDR_INTERACTIVE if !SPL + select GPIO_EXTRA_HEADER imply SCSI imply SCSI_AHCI help @@ -1251,6 +1312,7 @@ config TARGET_LS2081ARDB select ARM64 select ARMV8_MULTIENTRY select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER select SUPPORT_SPL help Support for Freescale LS2081ARDB platform. @@ -1265,6 +1327,7 @@ config TARGET_LX2160ARDB select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER help Support for NXP LX2160ARDB platform. The lx2160ardb (LX2160A Reference design board (RDB) @@ -1278,6 +1341,7 @@ config TARGET_LX2160AQDS select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER help Support for NXP LX2160AQDS platform. The lx2160aqds (LX2160A QorIQ Development System (QDS) @@ -1292,6 +1356,7 @@ config TARGET_LX2162AQDS select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER help Support for NXP LX2162AQDS platform. The lx2162aqds support is based on LX2160A Layerscape Architecture processor. @@ -1302,6 +1367,7 @@ config TARGET_HIKEY select DM select DM_GPIO select DM_SERIAL + select GPIO_EXTRA_HEADER select OF_CONTROL select PL01X_SERIAL select SPECIFY_CONSOLE_INDEX @@ -1315,6 +1381,7 @@ config TARGET_HIKEY960 select ARM64 select DM select DM_SERIAL + select GPIO_EXTRA_HEADER select OF_CONTROL select PL01X_SERIAL imply CMD_DM @@ -1328,6 +1395,7 @@ config TARGET_POPLAR select DM select DM_SERIAL select DM_USB + select GPIO_EXTRA_HEADER select OF_CONTROL select PL01X_SERIAL imply CMD_DM @@ -1343,6 +1411,7 @@ config TARGET_LS1012AQDS select ARM64 select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER help Support for Freescale LS1012AQDS platform. The LS1012A Development System (QDS) is a high-performance @@ -1355,6 +1424,7 @@ config TARGET_LS1012ARDB select ARM64 select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER imply SCSI imply SCSI_AHCI help @@ -1369,6 +1439,7 @@ config TARGET_LS1012A2G5RDB select ARM64 select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER imply SCSI help Support for Freescale LS1012A2G5RDB platform. @@ -1382,6 +1453,7 @@ config TARGET_LS1012AFRWY select ARM64 select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER imply SCSI imply SCSI_AHCI help @@ -1395,6 +1467,7 @@ config TARGET_LS1012AFRDM select ARCH_LS1012A select ARM64 select ARCH_SUPPORT_TFABOOT + select GPIO_EXTRA_HEADER help Support for Freescale LS1012AFRDM platform. The LS1012A Freedom board (FRDM) is a high-performance @@ -1408,6 +1481,7 @@ config TARGET_LS1028AQDS select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER help Support for Freescale LS1028AQDS platform The LS1028A Development System (QDS) is a high-performance @@ -1421,6 +1495,7 @@ config TARGET_LS1028ARDB select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER help Support for Freescale LS1028ARDB platform The LS1028A Development System (RDB) is a high-performance @@ -1436,6 +1511,7 @@ config TARGET_LS1088ARDB select BOARD_LATE_INIT select SUPPORT_SPL select FSL_DDR_INTERACTIVE if !SD_BOOT + select GPIO_EXTRA_HEADER help Support for NXP LS1088ARDB platform. The LS1088A Reference design board (RDB) is a high-performance @@ -1456,6 +1532,7 @@ config TARGET_LS1021AQDS select SYS_FSL_DDR select FSL_DDR_INTERACTIVE select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI + select GPIO_EXTRA_HEADER select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI imply SCSI @@ -1471,6 +1548,7 @@ config TARGET_LS1021ATWR select LS1_DEEP_SLEEP select SUPPORT_SPL select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI + select GPIO_EXTRA_HEADER imply SCSI config TARGET_PG_WCOM_SELI8 @@ -1484,6 +1562,7 @@ config TARGET_PG_WCOM_SELI8 select CPU_V7_HAS_VIRT select SYS_FSL_DDR select FSL_DDR_INTERACTIVE + select GPIO_EXTRA_HEADER select VENDOR_KM imply SCSI help @@ -1520,6 +1599,7 @@ config TARGET_LS1021ATSN select CPU_V7_HAS_VIRT select LS1_DEEP_SLEEP select SUPPORT_SPL + select GPIO_EXTRA_HEADER imply SCSI config TARGET_LS1021AIOT @@ -1532,6 +1612,7 @@ config TARGET_LS1021AIOT select CPU_V7_HAS_VIRT select SUPPORT_SPL select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI + select GPIO_EXTRA_HEADER imply SCSI help Support for Freescale LS1021AIOT platform. @@ -1551,6 +1632,7 @@ config TARGET_LS1043AQDS select FSL_DDR_INTERACTIVE if !SPL select FSL_DSPI if !SPL_NO_DSPI select DM_SPI_FLASH if FSL_DSPI + select GPIO_EXTRA_HEADER imply SCSI imply SCSI_AHCI help @@ -1567,6 +1649,7 @@ config TARGET_LS1043ARDB select SUPPORT_SPL select FSL_DSPI if !SPL_NO_DSPI select DM_SPI_FLASH if FSL_DSPI + select GPIO_EXTRA_HEADER help Support for Freescale LS1043ARDB platform. @@ -1583,6 +1666,7 @@ config TARGET_LS1046AQDS select FSL_DDR_BIST if !SPL select FSL_DDR_INTERACTIVE if !SPL select FSL_DDR_INTERACTIVE if !SPL + select GPIO_EXTRA_HEADER imply SCSI help Support for Freescale LS1046AQDS platform. @@ -1603,6 +1687,7 @@ config TARGET_LS1046ARDB select SUPPORT_SPL select FSL_DDR_BIST select FSL_DDR_INTERACTIVE if !SPL + select GPIO_EXTRA_HEADER imply SCSI help Support for Freescale LS1046ARDB platform. @@ -1619,6 +1704,7 @@ config TARGET_LS1046AFRWY select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select DM_SPI_FLASH if DM_SPI + select GPIO_EXTRA_HEADER imply SCSI help Support for Freescale LS1046AFRWY platform. @@ -1647,6 +1733,7 @@ config TARGET_SL28 select DM_SERIAL select DM_SPI select DM_USB + select GPIO_EXTRA_HEADER select SPL_DM if SPL select SPL_DM_SPI if SPL select SPL_DM_SPI_FLASH if SPL @@ -1659,6 +1746,7 @@ config TARGET_SL28 config TARGET_COLIBRI_PXA270 bool "Support colibri_pxa270" select CPU_PXA + select GPIO_EXTRA_HEADER config ARCH_UNIPHIER bool "Socionext UniPhier SoCs" @@ -1695,6 +1783,7 @@ config ARCH_STM32 select CPU_V7M select DM select DM_SERIAL + select GPIO_EXTRA_HEADER imply CMD_DM config ARCH_STI @@ -1720,6 +1809,7 @@ config ARCH_STM32MP select DM_GPIO select DM_RESET select DM_SERIAL + select GPIO_EXTRA_HEADER select MISC select OF_CONTROL select OF_LIBFDT @@ -1782,6 +1872,7 @@ config ARCH_OCTEONTX bool "Support OcteonTX SoCs" select CLK select DM + select GPIO_EXTRA_HEADER select ARM64 select OF_CONTROL select OF_LIVE @@ -1792,6 +1883,7 @@ config ARCH_OCTEONTX2 bool "Support OcteonTX2 SoCs" select CLK select DM + select GPIO_EXTRA_HEADER select ARM64 select OF_CONTROL select OF_LIVE @@ -1801,6 +1893,7 @@ config ARCH_OCTEONTX2 config TARGET_THUNDERX_88XX bool "Support ThunderX 88xx" select ARM64 + select GPIO_EXTRA_HEADER select OF_CONTROL select PL01X_SERIAL select SYS_CACHE_SHIFT_7 @@ -1814,6 +1907,7 @@ config ARCH_ASPEED config TARGET_DURIAN bool "Support Phytium Durian Platform" select ARM64 + select GPIO_EXTRA_HEADER help Support for durian platform. It has 2GB Sdram, uart and pcie. diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 7609367884..650783ae73 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,10 +1,4 @@ -#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \ - !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM68360) && \ - !defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \ - !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \ - !defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM) && \ - !defined(CONFIG_TARGET_BCMNS3) && !defined(CONFIG_TARGET_TOTAL_COMPUTE) && \ - !defined(CONFIG_ARCH_QEMU) +#ifdef CONFIG_GPIO_EXTRA_HEADER #include #endif #include -- cgit v1.2.3 From 3296d52bb5d32000da308658c396e8e4975e18a6 Mon Sep 17 00:00:00 2001 From: Masami Hiramatsu Date: Fri, 4 Jun 2021 18:44:06 +0900 Subject: pci: synquacer: Add SynQuacer ECAM based PCIe driver Add ECAM based SynQuacer PCIe RC driver. This driver configures the PCIe RC and filter out a ghost pcie config. Since the Linux kernel expects "socionext,synquacer-pcie-ecam" device is configured by firmware (EDK2), it doesn't re-configure in the kernel. So as same as EDK2, U-Boot needs to configure it before boot the kernel. Signed-off-by: Masami Hiramatsu --- drivers/pci/Kconfig | 12 + drivers/pci/Makefile | 1 + drivers/pci/pcie_ecam_synquacer.c | 600 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 613 insertions(+) create mode 100644 drivers/pci/pcie_ecam_synquacer.c diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index b2b7b253f8..782179eb0f 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -81,6 +81,18 @@ config PCIE_ECAM_GENERIC Say Y here if you want to enable support for generic ECAM-based PCIe host controllers, such as the one emulated by QEMU. +config PCIE_ECAM_SYNQUACER + bool "SynQuacer ECAM-based PCI host controller support" + default n + depends on DM_PCI + select PCI_INIT_R + select PCI_REGION_MULTI_ENTRY + help + Say Y here if you want to enable support for Socionext + SynQuacer SoC's ECAM-based PCIe host controllers. + Note that this must be configured when boot because Linux driver + expects the PCIe RC has been configured in the bootloader. + config PCI_PHYTIUM bool "Phytium PCIe support" depends on DM_PCI diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index c742bb2c94..6568dc9a08 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -16,6 +16,7 @@ endif obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o +obj-$(CONFIG_PCIE_ECAM_SYNQUACER) += pcie_ecam_synquacer.o obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o diff --git a/drivers/pci/pcie_ecam_synquacer.c b/drivers/pci/pcie_ecam_synquacer.c new file mode 100644 index 0000000000..c6e7c59f8a --- /dev/null +++ b/drivers/pci/pcie_ecam_synquacer.c @@ -0,0 +1,600 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SynQuacer PCIE host driver + * + * Based on drivers/pci/pcie_ecam_generic.c + * + * Copyright (C) 2016 Imagination Technologies + * Copyright (C) 2021 Linaro Ltd. + */ + +#include +#include +#include +#include + +#include +#include +#include + +/* iATU registers */ +#define IATU_VIEWPORT_OFF 0x900 +#define IATU_VIEWPORT_INBOUND BIT(31) +#define IATU_VIEWPORT_OUTBOUND 0 +#define IATU_VIEWPORT_REGION_INDEX(idx) ((idx) & 7) + +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH BIT(12) + +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908 +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT(31) +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE BIT(28) +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT 0xF +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT 0xFF + +#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C +#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910 +#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914 +#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918 +#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C + +/* Clock and resets */ +#define CORE_CONTROL 0x000 +#define APP_LTSSM_ENABLE BIT(4) +#define DEVICE_TYPE (BIT(3) | BIT(2) | BIT(1) | BIT(0)) + +#define AXI_CLK_STOP 0x004 +#define DBI_ACLK_STOP BIT(8) +#define SLV_ACLK_STOP BIT(4) +#define MSTR_ACLK_STOP BIT(0) +#define DBI_CSYSREQ_REG BIT(9) +#define SLV_CSYSREQ_REG BIT(5) +#define MSTR_CSYSREQ_REG BIT(1) + +#define RESET_CONTROL_1 0x00C +#define PERST_N_O_REG BIT(5) +#define PERST_N_I_REG BIT(4) +#define BUTTON_RST_N_REG BIT(1) +#define PWUP_RST_N_REG BIT(0) + +#define RESET_CONTROL_2 0x010 + +#define RESET_SELECT_1 0x014 +#define SQU_RST_SEL BIT(29) +#define PHY_RST_SEL BIT(28) +#define PWR_RST_SEL BIT(24) +#define STI_RST_SEL BIT(20) +#define N_STI_RST_SEL BIT(16) +#define CORE_RST_SEL BIT(12) +#define PERST_SEL BIT(4) +#define BUTTON_RST_SEL BIT(1) +#define PWUP_RST_SEL BIT(0) + +#define RESET_SELECT_2 0x018 +#define DBI_ARST_SEL BIT(8) +#define SLV_ARST_SEL BIT(4) +#define MSTR_ARST_SEL BIT(0) + +#define EM_CONTROL 0x030 +#define PRE_DET_STT_REG BIT(4) + +#define EM_SELECT 0x034 +#define PRE_DET_STT_SEL BIT(4) + +#define PM_CONTROL_2 0x050 +#define SYS_AUX_PWR_DET BIT(8) + +#define PHY_CONFIG_COM_6 0x114 +#define PIPE_PORT_SEL GENMASK(1, 0) + +#define LINK_MONITOR 0x210 +#define SMLH_LINK_UP BIT(0) + +#define LINK_CAPABILITIES_REG 0x07C +#define PCIE_CAP_MAX_LINK_WIDTH GENMASK(7, 4) +#define PCIE_CAP_MAX_LINK_SPEED GENMASK(3, 0) + +#define LINK_CONTROL_LINK_STATUS_REG 0x080 +#define PCIE_CAP_NEGO_LINK_WIDTH GENMASK(23, 20) +#define PCIE_CAP_LINK_SPEED GENMASK(19, 16) + +#define TYPE1_CLASS_CODE_REV_ID_REG 0x008 +#define BASE_CLASS_CODE 0xFF000000 +#define BASE_CLASS_CODE_VALUE 0x06 +#define SUBCLASS_CODE 0x00FF0000 +#define SUBCLASS_CODE_VALUE 0x04 +#define PROGRAM_INTERFACE 0x0000FF00 +#define PROGRAM_INTERFACE_VALUE 0x00 + +#define GEN2_CONTROL_OFF 0x80c +#define DIRECT_SPEED_CHANGE BIT(17) + +#define MISC_CONTROL_1_OFF 0x8BC +#define DBI_RO_WR_EN BIT(0) + +static void or_writel(void *base, u32 offs, u32 val) +{ + writel(readl(base + offs) | val, base + offs); +} + +static void masked_writel(void *base, u32 offs, u32 mask, u32 val) +{ + u32 data; + int shift = ffs(mask); /* Note that ffs() returns 1 for 0x1 */ + + if (val && shift > 1) + val <<= shift - 1; + + if (mask != ~0) + data = (readl(base + offs) & ~mask) | val; + else + data = val; + + writel(data, base + offs); +} + +static u32 masked_readl(void *base, u32 offs, u32 mask) +{ + u32 data; + int shift = ffs(mask); /* Note that ffs() returns 1 for 0x1 */ + + data = readl(base + offs); + + if (mask != ~0) + data &= mask; + if (shift > 1) + data >>= shift - 1; + + return data; +} + +/* + * Since SynQuacer's PCIe RC is expected to be initialized in the + * firmware (including U-Boot), devicetree doesn't have control + * blocks. + * + * Thus, this will initialize the PCIe RC with fixed addresses. + */ + +#define SYNQUACER_PCI_SEG0_CONFIG_BASE 0x60000000 +#define SYNQUACER_PCI_SEG0_CONFIG_SIZE 0x07f00000 +#define SYNQUACER_PCI_SEG0_DBI_BASE 0x583d0000 +#define SYNQUACER_PCI_SEG0_EXS_BASE 0x58390000 + +#define SYNQUACER_PCI_SEG1_CONFIG_BASE 0x70000000 +#define SYNQUACER_PCI_SEG1_CONFIG_SIZE 0x07f00000 +#define SYNQUACER_PCI_SEG1_DBI_BASE 0x583c0000 +#define SYNQUACER_PCI_SEG1_EXS_BASE 0x58380000 + +#define SIZE_16KB 0x00004000 +#define SIZE_64KB 0x00010000 +#define SIZE_1MB 0x00100000 + +#define SYNQUACER_PCI_DBI_SIZE SIZE_16KB +#define SYNQUACER_PCI_EXS_SIZE SIZE_64KB + +#define NUM_SQ_PCI_RC 2 + +static const struct synquacer_pcie_base { + phys_addr_t cfg_base; + phys_addr_t dbi_base; + phys_addr_t exs_base; +} synquacer_pci_bases[NUM_SQ_PCI_RC] = { + { + .cfg_base = SYNQUACER_PCI_SEG0_CONFIG_BASE, + .dbi_base = SYNQUACER_PCI_SEG0_DBI_BASE, + .exs_base = SYNQUACER_PCI_SEG0_EXS_BASE, + }, { + .cfg_base = SYNQUACER_PCI_SEG1_CONFIG_BASE, + .dbi_base = SYNQUACER_PCI_SEG1_DBI_BASE, + .exs_base = SYNQUACER_PCI_SEG1_EXS_BASE, + }, +}; + +/** + * struct synquacer_ecam_pcie - synquacer_ecam PCIe controller state + * @cfg_base: The base address of memory mapped configuration space + */ +struct synquacer_ecam_pcie { + void *cfg_base; + pci_size_t size; + void *dbi_base; + void *exs_base; + int first_busno; + + struct pci_region mem; + struct pci_region io; + struct pci_region mem64; +}; + +DECLARE_GLOBAL_DATA_PTR; + +/** + * pci_synquacer_ecam_conf_address() - Calculate the address of a config access + * @bus: Pointer to the PCI bus + * @bdf: Identifies the PCIe device to access + * @offset: The offset into the device's configuration space + * @paddress: Pointer to the pointer to write the calculates address to + * + * Calculates the address that should be accessed to perform a PCIe + * configuration space access for a given device identified by the PCIe + * controller device @pcie and the bus, device & function numbers in @bdf. If + * access to the device is not valid then the function will return an error + * code. Otherwise the address to access will be written to the pointer pointed + * to by @paddress. + */ +static int pci_synquacer_ecam_conf_address(const struct udevice *bus, + pci_dev_t bdf, uint offset, + void **paddress) +{ + struct synquacer_ecam_pcie *pcie = dev_get_priv(bus); + void *addr; + + addr = pcie->cfg_base; + addr += (PCI_BUS(bdf) - pcie->first_busno) << 20; + addr += PCI_DEV(bdf) << 15; + addr += PCI_FUNC(bdf) << 12; + addr += offset; + *paddress = addr; + + return 0; +} + +static bool pci_synquacer_ecam_addr_valid(const struct udevice *bus, + pci_dev_t bdf) +{ + struct synquacer_ecam_pcie *pcie = dev_get_priv(bus); + int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16); + + /* + * The Synopsys DesignWare PCIe controller in ECAM mode will not filter + * type 0 config TLPs sent to devices 1 and up on its downstream port, + * resulting in devices appearing multiple times on bus 0 unless we + * filter out those accesses here. + */ + if (PCI_BUS(bdf) == pcie->first_busno && PCI_DEV(bdf) > 0) + return false; + + return (PCI_BUS(bdf) >= pcie->first_busno && + PCI_BUS(bdf) < pcie->first_busno + num_buses); +} + +/** + * pci_synquacer_ecam_read_config() - Read from configuration space + * @bus: Pointer to the PCI bus + * @bdf: Identifies the PCIe device to access + * @offset: The offset into the device's configuration space + * @valuep: A pointer at which to store the read value + * @size: Indicates the size of access to perform + * + * Read a value of size @size from offset @offset within the configuration + * space of the device identified by the bus, device & function numbers in @bdf + * on the PCI bus @bus. + */ +static int pci_synquacer_ecam_read_config(const struct udevice *bus, + pci_dev_t bdf, uint offset, + ulong *valuep, enum pci_size_t size) +{ + if (!pci_synquacer_ecam_addr_valid(bus, bdf)) { + *valuep = pci_get_ff(size); + return 0; + } + + return pci_generic_mmap_read_config(bus, pci_synquacer_ecam_conf_address, + bdf, offset, valuep, size); +} + +/** + * pci_synquacer_ecam_write_config() - Write to configuration space + * @bus: Pointer to the PCI bus + * @bdf: Identifies the PCIe device to access + * @offset: The offset into the device's configuration space + * @value: The value to write + * @size: Indicates the size of access to perform + * + * Write the value @value of size @size from offset @offset within the + * configuration space of the device identified by the bus, device & function + * numbers in @bdf on the PCI bus @bus. + */ +static int pci_synquacer_ecam_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + if (!pci_synquacer_ecam_addr_valid(bus, bdf)) + return 0; + + return pci_generic_mmap_write_config(bus, pci_synquacer_ecam_conf_address, + bdf, offset, value, size); +} + +/** + * pci_synquacer_ecam_of_to_plat() - Translate from DT to device state + * @dev: A pointer to the device being operated on + * + * Translate relevant data from the device tree pertaining to device @dev into + * state that the driver will later make use of. This state is stored in the + * device's private data structure. + * + * Return: 0 on success, else -EINVAL + */ +static int pci_synquacer_ecam_of_to_plat(struct udevice *dev) +{ + struct synquacer_ecam_pcie *pcie = dev_get_priv(dev); + struct fdt_resource reg_res; + int i, err; + + debug("%s: called for %s\n", __func__, dev->name); + + err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg", + 0, ®_res); + if (err < 0) { + pr_err("\"reg\" resource not found\n"); + return err; + } + + /* Find the correct pair of the DBI/EXS base address */ + for (i = 0; i < NUM_SQ_PCI_RC; i++) { + if (synquacer_pci_bases[i].cfg_base == reg_res.start) + break; + } + if (i == NUM_SQ_PCI_RC) { + pr_err("Unknown ECAM base address %lx.\n", + (unsigned long)reg_res.start); + return -ENOENT; + } + pcie->dbi_base = map_physmem(synquacer_pci_bases[i].dbi_base, + SYNQUACER_PCI_DBI_SIZE, MAP_NOCACHE); + if (!pcie->dbi_base) { + pr_err("Failed to map DBI for %s\n", dev->name); + return -ENOMEM; + } + + pcie->exs_base = map_physmem(synquacer_pci_bases[i].exs_base, + SYNQUACER_PCI_EXS_SIZE, MAP_NOCACHE); + if (!pcie->exs_base) { + pr_err("Failed to map EXS for %s\n", dev->name); + return -ENOMEM; + } + + pcie->size = fdt_resource_size(®_res); + pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE); + if (!pcie->cfg_base) { + pr_err("Failed to map config space for %s\n", dev->name); + return -ENOMEM; + } + debug("mappings DBI: %p EXS: %p CFG: %p\n", pcie->dbi_base, pcie->exs_base, pcie->cfg_base); + + return 0; +} + +static void pci_synquacer_pre_init(struct synquacer_ecam_pcie *pcie) +{ + void *base = pcie->exs_base; + + masked_writel(base, EM_SELECT, PRE_DET_STT_SEL, 0); + masked_writel(base, EM_CONTROL, PRE_DET_STT_REG, 0); + masked_writel(base, EM_CONTROL, PRE_DET_STT_REG, 1); + + /* 1: Assert all PHY / LINK resets */ + masked_writel(base, RESET_SELECT_1, PERST_SEL, 0); + masked_writel(base, RESET_CONTROL_1, PERST_N_I_REG, 0); + masked_writel(base, RESET_CONTROL_1, PERST_N_O_REG, 0); + + /* Device Reset(PERST#) is effective afrer Set device_type (RC) */ + masked_writel(base, RESET_SELECT_1, PWUP_RST_SEL, 0); + masked_writel(base, RESET_CONTROL_1, PWUP_RST_N_REG, 0); + masked_writel(base, RESET_SELECT_1, BUTTON_RST_SEL, 0); + masked_writel(base, RESET_CONTROL_1, BUTTON_RST_N_REG, 0); + masked_writel(base, RESET_SELECT_1, PWR_RST_SEL, 1); + masked_writel(base, RESET_SELECT_2, MSTR_ARST_SEL, 1); + masked_writel(base, RESET_SELECT_2, SLV_ARST_SEL, 1); + masked_writel(base, RESET_SELECT_2, DBI_ARST_SEL, 1); + masked_writel(base, RESET_SELECT_1, CORE_RST_SEL, 1); + masked_writel(base, RESET_SELECT_1, STI_RST_SEL, 1); + masked_writel(base, RESET_SELECT_1, N_STI_RST_SEL, 1); + masked_writel(base, RESET_SELECT_1, SQU_RST_SEL, 1); + masked_writel(base, RESET_SELECT_1, PHY_RST_SEL, 1); + + /* 2: Set P_app_ltssm_enable='0' for reprogramming before linkup. */ + masked_writel(base, CORE_CONTROL, APP_LTSSM_ENABLE, 0); + + /* 3: Set device_type (RC) */ + masked_writel(base, CORE_CONTROL, DEVICE_TYPE, 4); +} + +static void pci_synquacer_dbi_init(void *dbi_base) +{ + masked_writel(dbi_base, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 1); + /* 4 Lanes */ + masked_writel(dbi_base, LINK_CAPABILITIES_REG, + PCIE_CAP_MAX_LINK_WIDTH, 4); + /* Gen 2 */ + masked_writel(dbi_base, LINK_CAPABILITIES_REG, + PCIE_CAP_MAX_LINK_SPEED, 2); + + masked_writel(dbi_base, TYPE1_CLASS_CODE_REV_ID_REG, + BASE_CLASS_CODE, BASE_CLASS_CODE_VALUE); + masked_writel(dbi_base, TYPE1_CLASS_CODE_REV_ID_REG, + SUBCLASS_CODE, SUBCLASS_CODE_VALUE); + masked_writel(dbi_base, TYPE1_CLASS_CODE_REV_ID_REG, + PROGRAM_INTERFACE, PROGRAM_INTERFACE_VALUE); + + masked_writel(dbi_base, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 0); +} + +static void pcie_sq_prog_outbound_atu(void *dbi_base, int index, + u64 cpu_base, u64 pci_base, u64 size, + u32 type, u32 flags) +{ + debug("%s: %p, %d, %llx, %llx, %llx, %x, %x\n", __func__, + dbi_base, index, cpu_base, pci_base, size, type, flags); + + writel(IATU_VIEWPORT_OUTBOUND | IATU_VIEWPORT_REGION_INDEX(index), + dbi_base + IATU_VIEWPORT_OFF); + + writel((u32)(cpu_base & 0xffffffff), + dbi_base + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0); + writel((u32)(cpu_base >> 32), + dbi_base + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0); + writel((u32)(cpu_base + size - 1), + dbi_base + IATU_LIMIT_ADDR_OFF_OUTBOUND_0); + + writel((u32)(pci_base & 0xffffffff), + dbi_base + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0); + writel((u32)(pci_base >> 32), + dbi_base + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0); + + writel(type, dbi_base + IATU_REGION_CTRL_1_OFF_OUTBOUND_0); + writel(IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN | flags, + dbi_base + IATU_REGION_CTRL_2_OFF_OUTBOUND_0); +} + +static void pci_synquacer_post_init(struct synquacer_ecam_pcie *pcie) +{ + void *base = pcie->exs_base; + + /* + * 4: Set Bifurcation 1=disable 4=able + * 5: Supply Reference (It has executed) + * 6: Wait for 10usec (Reference Clocks is stable) + * 7: De assert PERST# + */ + masked_writel(base, RESET_CONTROL_1, PERST_N_I_REG, 1); + masked_writel(base, RESET_CONTROL_1, PERST_N_O_REG, 1); + + /* 8: Assert SYS_AUX_PWR_DET */ + masked_writel(base, PM_CONTROL_2, SYS_AUX_PWR_DET, 1); + + /* 9: Supply following clocks */ + masked_writel(base, AXI_CLK_STOP, MSTR_CSYSREQ_REG, 1); + masked_writel(base, AXI_CLK_STOP, MSTR_ACLK_STOP, 0); + masked_writel(base, AXI_CLK_STOP, SLV_CSYSREQ_REG, 1); + masked_writel(base, AXI_CLK_STOP, SLV_ACLK_STOP, 0); + masked_writel(base, AXI_CLK_STOP, DBI_CSYSREQ_REG, 1); + masked_writel(base, AXI_CLK_STOP, DBI_ACLK_STOP, 0); + + /* + * 10: De assert PHY reset + * 11: De assert LINK's PMC reset + */ + masked_writel(base, RESET_CONTROL_1, PWUP_RST_N_REG, 1); + masked_writel(base, RESET_CONTROL_1, BUTTON_RST_N_REG, 1); + + /* 12: PHY auto + * 13: Wrapper auto + * 14-17: PHY auto + * 18: Wrapper auto + * 19: Update registers through DBI AXI Slave interface + */ + pci_synquacer_dbi_init(pcie->dbi_base); + + or_writel(pcie->dbi_base, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Force link speed change to Gen2 at link up */ + or_writel(pcie->dbi_base, GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE); + + /* Region 0: MMIO32 range */ + pcie_sq_prog_outbound_atu(pcie->dbi_base, 0, + pcie->mem.phys_start, + pcie->mem.bus_start, + pcie->mem.size, + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT); + + /* Region 1: Type 0 config space */ + pcie_sq_prog_outbound_atu(pcie->dbi_base, 1, + (u64)pcie->cfg_base, + 0, + SIZE_64KB, + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE); + + /* Region 2: Type 1 config space */ + pcie_sq_prog_outbound_atu(pcie->dbi_base, 2, + (u64)pcie->cfg_base + SIZE_64KB, + 0, + (u64)pcie->io.phys_start - (u64)pcie->cfg_base - SIZE_64KB, + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE); + + /* Region 3: port I/O range */ + pcie_sq_prog_outbound_atu(pcie->dbi_base, 3, + pcie->io.phys_start, + pcie->io.bus_start, + pcie->io.size, + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO, + 0); + + /* Region 4: MMIO64 range */ + pcie_sq_prog_outbound_atu(pcie->dbi_base, 4, + pcie->mem64.phys_start, + pcie->mem64.bus_start, + pcie->mem64.size, + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT); + + /* enable link */ + if (masked_readl(base, CORE_CONTROL, APP_LTSSM_ENABLE) == 0) + masked_writel(base, CORE_CONTROL, APP_LTSSM_ENABLE, 1); +} + +static int pci_synquacer_ecam_probe(struct udevice *dev) +{ + struct synquacer_ecam_pcie *pcie = dev_get_priv(dev); + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *hose = dev_get_uclass_priv(ctlr); + + debug("Probe synquacer pcie for bus %d\n", dev_seq(dev)); + pcie->first_busno = dev_seq(dev); + + /* Store the IO and MEM windows settings for configuring ATU */ + pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */ + pcie->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */ + pcie->io.size = hose->regions[0].size; /* IO size */ + + pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */ + pcie->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */ + pcie->mem.size = hose->regions[1].size; /* MEM size */ + + pcie->mem64.phys_start = hose->regions[2].phys_start; /* MEM64 base */ + pcie->mem64.bus_start = hose->regions[2].bus_start; /* MEM64_bus_addr */ + pcie->mem64.size = hose->regions[2].size; /* MEM64 size */ + + pci_synquacer_pre_init(pcie); + + mdelay(150); + + pci_synquacer_post_init(pcie); + + /* It takes a while to stabilize the PCIe bus for scanning */ + mdelay(100); + + return 0; +} + +static const struct dm_pci_ops pci_synquacer_ecam_ops = { + .read_config = pci_synquacer_ecam_read_config, + .write_config = pci_synquacer_ecam_write_config, +}; + +static const struct udevice_id pci_synquacer_ecam_ids[] = { + { .compatible = "socionext,synquacer-pcie-ecam" }, + { } +}; + +U_BOOT_DRIVER(pci_synquacer_ecam) = { + .name = "pci_synquacer_ecam", + .id = UCLASS_PCI, + .of_match = pci_synquacer_ecam_ids, + .ops = &pci_synquacer_ecam_ops, + .probe = pci_synquacer_ecam_probe, + .of_to_plat = pci_synquacer_ecam_of_to_plat, + .priv_auto = sizeof(struct synquacer_ecam_pcie), +}; -- cgit v1.2.3 From dadd43c143685a6ed7d9a14575e14dba34d77160 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Fri, 4 Jun 2021 18:44:16 +0900 Subject: mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver Signed-off-by: Jassi Brar Signed-off-by: Masami Hiramatsu Reviewed-by: Jaehoon Chung --- drivers/mmc/Kconfig | 10 +++++++ drivers/mmc/Makefile | 1 + drivers/mmc/f_sdh30.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 92 insertions(+) create mode 100644 drivers/mmc/f_sdh30.c diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 0909f502a1..63152aae4d 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -561,6 +561,16 @@ config MMC_SDHCI_IPROC If unsure, say N. +config MMC_SDHCI_F_SDH30 + bool "SDHCI support for Fujitsu Semiconductor F_SDH30" + depends on BLK && DM_MMC + depends on MMC_SDHCI + help + This selects the Secure Digital Host Controller Interface (SDHCI) + Needed by some Fujitsu SoC for MMC / SD / SDIO support. + If you have a controller with this interface, say Y or M here. + If unsure, say N. + config MMC_SDHCI_KONA bool "SDHCI support on Broadcom KONA platform" depends on MMC_SDHCI diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 89d6af3db3..f5fd59093e 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -76,3 +76,4 @@ obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o obj-$(CONFIG_MMC_MTK) += mtk-sd.o +obj-$(CONFIG_MMC_SDHCI_F_SDH30) += f_sdh30.o diff --git a/drivers/mmc/f_sdh30.c b/drivers/mmc/f_sdh30.c new file mode 100644 index 0000000000..3a85d9e348 --- /dev/null +++ b/drivers/mmc/f_sdh30.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Socionext F_SDH30 eMMC driver + * Copyright 2021 Linaro Ltd. + * Copyright 2021 Socionext, Inc. + */ + +#include +#include +#include +#include +#include + +struct f_sdh30_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +DECLARE_GLOBAL_DATA_PTR; + +static int f_sdh30_sdhci_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct f_sdh30_plat *plat = dev_get_plat(dev); + struct sdhci_host *host = dev_get_priv(dev); + int ret; + + ret = mmc_of_parse(dev, &plat->cfg); + if (ret) + return ret; + + host->mmc = &plat->mmc; + host->mmc->dev = dev; + host->mmc->priv = host; + + ret = sdhci_setup_cfg(&plat->cfg, host, 200000000, 400000); + if (ret) + return ret; + + upriv->mmc = host->mmc; + + mmc_set_clock(host->mmc, host->mmc->cfg->f_min, MMC_CLK_ENABLE); + + return sdhci_probe(dev); +} + +static int f_sdh30_of_to_plat(struct udevice *dev) +{ + struct sdhci_host *host = dev_get_priv(dev); + + host->name = strdup(dev->name); + host->ioaddr = dev_read_addr_ptr(dev); + host->bus_width = dev_read_u32_default(dev, "bus-width", 4); + host->index = dev_read_u32_default(dev, "index", 0); + + return 0; +} + +static int f_sdh30_bind(struct udevice *dev) +{ + struct f_sdh30_plat *plat = dev_get_plat(dev); + + return sdhci_bind(dev, &plat->mmc, &plat->cfg); +} + +static const struct udevice_id f_sdh30_mmc_ids[] = { + { .compatible = "fujitsu,mb86s70-sdhci-3.0" }, + { } +}; + +U_BOOT_DRIVER(f_sdh30_drv) = { + .name = "f_sdh30_sdhci", + .id = UCLASS_MMC, + .of_match = f_sdh30_mmc_ids, + .of_to_plat = f_sdh30_of_to_plat, + .ops = &sdhci_ops, + .bind = f_sdh30_bind, + .probe = f_sdh30_sdhci_probe, + .priv_auto = sizeof(struct sdhci_host), + .plat_auto = sizeof(struct f_sdh30_plat), +}; -- cgit v1.2.3 From 971a344285731b7bb076fe59c4ecbd68d8c9bb66 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Fri, 4 Jun 2021 18:44:27 +0900 Subject: spi: synquacer: Add HSSPI SPI controller driver for SynQuacer This is a driver for the HSSPI SPI controller on SynQuacer SoC. The HSSPI has command sequence mode (memory mapped) and direct mode (FIFO access). The driver will operate it under the direct mode. And before booting OS, it switch back to the command sequence mode since that is compatible with default EDK2 behavior. Signed-off-by: Jassi Brar Signed-off-by: Masami Hiramatsu --- drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/spi-synquacer.c | 491 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 500 insertions(+) create mode 100644 drivers/spi/spi-synquacer.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index e317d8a2c6..5c2a60a214 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -488,4 +488,12 @@ config MXC_SPI Enable the MXC SPI controller driver. This driver can be used on various i.MX SoCs such as i.MX31/35/51/6/7. +config SYNQUACER_SPI + bool "Socionext SynQuacer HS-SPI driver" + depends on ARCH_SYNQUACER + help + Enable the Socionext HS-SPI driver for SynQuacer. This driver can + be used to access the SPI interface and SPI NOR flash on platforms + embedding this HS-SPI IP core. + endif # menu "SPI Support" diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 3dc83089b8..f70851e4bc 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o obj-$(CONFIG_FSL_ESPI) += fsl_espi.o obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o +obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c new file mode 100644 index 0000000000..ce558c4bc0 --- /dev/null +++ b/drivers/spi/spi-synquacer.c @@ -0,0 +1,491 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * spi-synquacer.c - Socionext Synquacer SPI driver + * Copyright 2021 Linaro Ltd. + * Copyright 2021 Socionext, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MCTRL 0x0 +#define MEN 0 +#define CSEN 1 +#define IPCLK 3 +#define MES 4 +#define SYNCON 5 + +#define PCC0 0x4 +#define PCC(n) (PCC0 + (n) * 4) +#define RTM 3 +#define ACES 2 +#define SAFESYNC 16 +#define CPHA 0 +#define CPOL 1 +#define SSPOL 4 +#define SDIR 7 +#define SS2CD 5 +#define SENDIAN 8 +#define CDRS_SHIFT 9 +#define CDRS_MASK 0x7f + +#define TXF 0x14 +#define TXE 0x18 +#define TXC 0x1c +#define RXF 0x20 +#define RXE 0x24 +#define RXC 0x28 +#define TFLETE 4 +#define RFMTE 5 + +#define FAULTF 0x2c +#define FAULTC 0x30 + +#define DMCFG 0x34 +#define SSDC 1 +#define MSTARTEN 2 + +#define DMSTART 0x38 +#define TRIGGER 0 +#define DMSTOP 8 +#define CS_MASK 3 +#define CS_SHIFT 16 +#define DATA_TXRX 0 +#define DATA_RX 1 +#define DATA_TX 2 +#define DATA_MASK 3 +#define DATA_SHIFT 26 +#define BUS_WIDTH 24 + +#define DMBCC 0x3c +#define DMSTATUS 0x40 +#define RX_DATA_MASK 0x1f +#define RX_DATA_SHIFT 8 +#define TX_DATA_MASK 0x1f +#define TX_DATA_SHIFT 16 + +#define TXBITCNT 0x44 + +#define FIFOCFG 0x4c +#define BPW_MASK 0x3 +#define BPW_SHIFT 8 +#define RX_FLUSH 11 +#define TX_FLUSH 12 +#define RX_TRSHLD_MASK 0xf +#define RX_TRSHLD_SHIFT 0 +#define TX_TRSHLD_MASK 0xf +#define TX_TRSHLD_SHIFT 4 + +#define TXFIFO 0x50 +#define RXFIFO 0x90 +#define MID 0xfc + +#define FIFO_DEPTH 16 +#define TX_TRSHLD 4 +#define RX_TRSHLD (FIFO_DEPTH - TX_TRSHLD) + +#define TXBIT 1 +#define RXBIT 2 + +DECLARE_GLOBAL_DATA_PTR; + +struct synquacer_spi_plat { + void __iomem *base; + bool aces, rtm; +}; + +struct synquacer_spi_priv { + void __iomem *base; + bool aces, rtm; + int speed, cs, mode, rwflag; + void *rx_buf; + const void *tx_buf; + unsigned int tx_words, rx_words; +}; + +static void read_fifo(struct synquacer_spi_priv *priv) +{ + u32 len = readl(priv->base + DMSTATUS); + u8 *buf = priv->rx_buf; + int i; + + len = (len >> RX_DATA_SHIFT) & RX_DATA_MASK; + len = min_t(unsigned int, len, priv->rx_words); + + for (i = 0; i < len; i++) + *buf++ = readb(priv->base + RXFIFO); + + priv->rx_buf = buf; + priv->rx_words -= len; +} + +static void write_fifo(struct synquacer_spi_priv *priv) +{ + u32 len = readl(priv->base + DMSTATUS); + const u8 *buf = priv->tx_buf; + int i; + + len = (len >> TX_DATA_SHIFT) & TX_DATA_MASK; + len = min_t(unsigned int, FIFO_DEPTH - len, priv->tx_words); + + for (i = 0; i < len; i++) + writeb(*buf++, priv->base + TXFIFO); + + priv->tx_buf = buf; + priv->tx_words -= len; +} + +static void synquacer_cs_set(struct synquacer_spi_priv *priv, bool active) +{ + u32 val; + + val = readl(priv->base + DMSTART); + val &= ~(CS_MASK << CS_SHIFT); + val |= priv->cs << CS_SHIFT; + + if (active) { + writel(val, priv->base + DMSTART); + + val = readl(priv->base + DMSTART); + val &= ~BIT(DMSTOP); + writel(val, priv->base + DMSTART); + } else { + val |= BIT(DMSTOP); + writel(val, priv->base + DMSTART); + + if (priv->rx_buf) { + u32 buf[16]; + + priv->rx_buf = buf; + priv->rx_words = 16; + read_fifo(priv); + } + } +} + +static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx) +{ + struct udevice *bus = dev->parent; + struct synquacer_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); + u32 val, div, bus_width; + int rwflag; + + rwflag = (rx ? 1 : 0) | (tx ? 2 : 0); + + /* if nothing to do */ + if (slave_plat->mode == priv->mode && + rwflag == priv->rwflag && + slave_plat->cs == priv->cs && + slave_plat->max_hz == priv->speed) + return; + + priv->rwflag = rwflag; + priv->cs = slave_plat->cs; + priv->mode = slave_plat->mode; + priv->speed = slave_plat->max_hz; + + if (priv->mode & SPI_TX_BYTE) + bus_width = 1; + else if (priv->mode & SPI_TX_DUAL) + bus_width = 2; + else if (priv->mode & SPI_TX_QUAD) + bus_width = 4; + else if (priv->mode & SPI_TX_OCTAL) + bus_width = 8; + + div = DIV_ROUND_UP(125000000, priv->speed); + + val = readl(priv->base + PCC(priv->cs)); + val &= ~BIT(RTM); + val &= ~BIT(ACES); + val &= ~BIT(SAFESYNC); + if ((priv->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) && div < 3) + val |= BIT(SAFESYNC); + if ((priv->mode & (SPI_TX_QUAD | SPI_RX_QUAD)) && div < 6) + val |= BIT(SAFESYNC); + + if (priv->mode & SPI_CPHA) + val |= BIT(CPHA); + else + val &= ~BIT(CPHA); + + if (priv->mode & SPI_CPOL) + val |= BIT(CPOL); + else + val &= ~BIT(CPOL); + + if (priv->mode & SPI_CS_HIGH) + val |= BIT(SSPOL); + else + val &= ~BIT(SSPOL); + + if (priv->mode & SPI_LSB_FIRST) + val |= BIT(SDIR); + else + val &= ~BIT(SDIR); + + if (priv->aces) + val |= BIT(ACES); + + if (priv->rtm) + val |= BIT(RTM); + + val |= (3 << SS2CD); + val |= BIT(SENDIAN); + + val &= ~(CDRS_MASK << CDRS_SHIFT); + val |= ((div >> 1) << CDRS_SHIFT); + + writel(val, priv->base + PCC(priv->cs)); + + val = readl(priv->base + FIFOCFG); + val &= ~(BPW_MASK << BPW_SHIFT); + val |= (0 << BPW_SHIFT); + writel(val, priv->base + FIFOCFG); + + val = readl(priv->base + DMSTART); + val &= ~(DATA_MASK << DATA_SHIFT); + + if (tx && rx) + val |= (DATA_TXRX << DATA_SHIFT); + else if (rx) + val |= (DATA_RX << DATA_SHIFT); + else + val |= (DATA_TX << DATA_SHIFT); + + val &= ~(3 << BUS_WIDTH); + val |= ((bus_width >> 1) << BUS_WIDTH); + writel(val, priv->base + DMSTART); +} + +static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *tx_buf, void *rx_buf, + unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct synquacer_spi_priv *priv = dev_get_priv(bus); + u32 val, words, busy; + + val = readl(priv->base + FIFOCFG); + val |= (1 << RX_FLUSH); + val |= (1 << TX_FLUSH); + writel(val, priv->base + FIFOCFG); + + synquacer_spi_config(dev, rx_buf, tx_buf); + + priv->tx_buf = tx_buf; + priv->rx_buf = rx_buf; + + words = bitlen / 8; + + if (tx_buf) { + busy |= BIT(TXBIT); + priv->tx_words = words; + } else { + busy &= ~BIT(TXBIT); + priv->tx_words = 0; + } + + if (rx_buf) { + busy |= BIT(RXBIT); + priv->rx_words = words; + } else { + busy &= ~BIT(RXBIT); + priv->rx_words = 0; + } + + if (flags & SPI_XFER_BEGIN) + synquacer_cs_set(priv, true); + + if (tx_buf) + write_fifo(priv); + + if (rx_buf) { + val = readl(priv->base + FIFOCFG); + val &= ~(RX_TRSHLD_MASK << RX_TRSHLD_SHIFT); + val |= ((priv->rx_words > FIFO_DEPTH ? + RX_TRSHLD : priv->rx_words) << RX_TRSHLD_SHIFT); + writel(val, priv->base + FIFOCFG); + } + + writel(~0, priv->base + TXC); + writel(~0, priv->base + RXC); + + /* Trigger */ + val = readl(priv->base + DMSTART); + val |= BIT(TRIGGER); + writel(val, priv->base + DMSTART); + + while (busy & (BIT(RXBIT) | BIT(TXBIT))) { + if (priv->rx_words) + read_fifo(priv); + else + busy &= ~BIT(RXBIT); + + if (priv->tx_words) { + write_fifo(priv); + } else { + u32 len; + + do { /* wait for shifter to empty out */ + cpu_relax(); + len = readl(priv->base + DMSTATUS); + len = (len >> TX_DATA_SHIFT) & TX_DATA_MASK; + } while (tx_buf && len); + busy &= ~BIT(TXBIT); + } + } + + if (flags & SPI_XFER_END) + synquacer_cs_set(priv, false); + + return 0; +} + +static int synquacer_spi_set_speed(struct udevice *bus, uint speed) +{ + return 0; +} + +static int synquacer_spi_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} + +static int synquacer_spi_claim_bus(struct udevice *dev) +{ + return 0; +} + +static int synquacer_spi_release_bus(struct udevice *dev) +{ + return 0; +} + +static void synquacer_spi_disable_module(struct synquacer_spi_priv *priv) +{ + writel(0, priv->base + MCTRL); + while (readl(priv->base + MCTRL) & BIT(MES)) + cpu_relax(); +} + +static void synquacer_spi_init(struct synquacer_spi_priv *priv) +{ + u32 val; + + synquacer_spi_disable_module(priv); + + writel(0, priv->base + TXE); + writel(0, priv->base + RXE); + val = readl(priv->base + TXF); + writel(val, priv->base + TXC); + val = readl(priv->base + RXF); + writel(val, priv->base + RXC); + val = readl(priv->base + FAULTF); + writel(val, priv->base + FAULTC); + + val = readl(priv->base + DMCFG); + val &= ~BIT(SSDC); + val &= ~BIT(MSTARTEN); + writel(val, priv->base + DMCFG); + + /* Enable module with direct mode */ + val = readl(priv->base + MCTRL); + val &= ~BIT(IPCLK); + val &= ~BIT(CSEN); + val |= BIT(MEN); + val |= BIT(SYNCON); + writel(val, priv->base + MCTRL); +} + +static void synquacer_spi_exit(struct synquacer_spi_priv *priv) +{ + u32 val; + + synquacer_spi_disable_module(priv); + + /* Enable module with command sequence mode */ + val = readl(priv->base + MCTRL); + val &= ~BIT(IPCLK); + val |= BIT(CSEN); + val |= BIT(MEN); + val |= BIT(SYNCON); + writel(val, priv->base + MCTRL); + + while (!(readl(priv->base + MCTRL) & BIT(MES))) + cpu_relax(); +} + +static int synquacer_spi_probe(struct udevice *bus) +{ + struct synquacer_spi_plat *plat = dev_get_plat(bus); + struct synquacer_spi_priv *priv = dev_get_priv(bus); + + priv->base = plat->base; + priv->aces = plat->aces; + priv->rtm = plat->rtm; + + synquacer_spi_init(priv); + return 0; +} + +static int synquacer_spi_remove(struct udevice *bus) +{ + struct synquacer_spi_priv *priv = dev_get_priv(bus); + + synquacer_spi_exit(priv); + return 0; +} + +static int synquacer_spi_of_to_plat(struct udevice *bus) +{ + struct synquacer_spi_plat *plat = dev_get_plat(bus); + struct clk clk; + + plat->base = dev_read_addr_ptr(bus); + + plat->aces = dev_read_bool(bus, "socionext,set-aces"); + plat->rtm = dev_read_bool(bus, "socionext,use-rtm"); + + clk_get_by_name(bus, "iHCLK", &clk); + clk_enable(&clk); + + return 0; +} + +static const struct dm_spi_ops synquacer_spi_ops = { + .claim_bus = synquacer_spi_claim_bus, + .release_bus = synquacer_spi_release_bus, + .xfer = synquacer_spi_xfer, + .set_speed = synquacer_spi_set_speed, + .set_mode = synquacer_spi_set_mode, +}; + +static const struct udevice_id synquacer_spi_ids[] = { + { .compatible = "socionext,synquacer-spi" }, + { /* Sentinel */ } +}; + +U_BOOT_DRIVER(synquacer_spi) = { + .name = "synquacer_spi", + .id = UCLASS_SPI, + .of_match = synquacer_spi_ids, + .ops = &synquacer_spi_ops, + .of_to_plat = synquacer_spi_of_to_plat, + .plat_auto = sizeof(struct synquacer_spi_plat), + .priv_auto = sizeof(struct synquacer_spi_priv), + .probe = synquacer_spi_probe, + .flags = DM_FLAG_OS_PREPARE, + .remove = synquacer_spi_remove, +}; -- cgit v1.2.3 From 4483fbab811698905493af7026e474ffa5e19365 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Fri, 4 Jun 2021 18:44:48 +0900 Subject: i2c: synquacer: SNI Synquacer I2C controller Add driver for class of I2C controllers found on Socionext Synquacer platform. Signed-off-by: Jassi Brar --- drivers/i2c/Kconfig | 7 + drivers/i2c/Makefile | 1 + drivers/i2c/synquacer_i2c.c | 338 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 346 insertions(+) create mode 100644 drivers/i2c/synquacer_i2c.c diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 57a4efb88e..ce0d796d09 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -455,6 +455,13 @@ config SYS_I2C_STM32F7 _ Optional clock stretching _ Software reset +config SYS_I2C_SYNQUACER + bool "Socionext SynQuacer I2C controller" + depends on ARCH_SYNQUACER && DM_I2C + help + Support for Socionext Synquacer I2C controller. This I2C controller + will be used for RTC and LS-connector on DeveloperBox. + config SYS_I2C_TEGRA bool "NVIDIA Tegra internal I2C controller" depends on ARCH_TEGRA diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 8c9f1fcd8b..06a1150f03 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o +obj-$(CONFIG_SYS_I2C_SYNQUACER) += synquacer_i2c.o obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o diff --git a/drivers/i2c/synquacer_i2c.c b/drivers/i2c/synquacer_i2c.c new file mode 100644 index 0000000000..6672d9435e --- /dev/null +++ b/drivers/i2c/synquacer_i2c.c @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define REG_BSR 0x0 +#define REG_BCR 0x4 +#define REG_CCR 0x8 +#define REG_ADR 0xc +#define REG_DAR 0x10 +#define REG_CSR 0x14 +#define REG_FSR 0x18 +#define REG_BC2R 0x1c + +/* I2C register bit definitions */ +#define BSR_FBT BIT(0) // First Byte Transfer +#define BSR_GCA BIT(1) // General Call Address +#define BSR_AAS BIT(2) // Address as Slave +#define BSR_TRX BIT(3) // Transfer/Receive +#define BSR_LRB BIT(4) // Last Received Bit +#define BSR_AL BIT(5) // Arbitration Lost +#define BSR_RSC BIT(6) // Repeated Start Cond. +#define BSR_BB BIT(7) // Bus Busy + +#define BCR_INT BIT(0) // Interrupt +#define BCR_INTE BIT(1) // Interrupt Enable +#define BCR_GCAA BIT(2) // Gen. Call Access Ack. +#define BCR_ACK BIT(3) // Acknowledge +#define BCR_MSS BIT(4) // Master Slave Select +#define BCR_SCC BIT(5) // Start Condition Cont. +#define BCR_BEIE BIT(6) // Bus Error Int Enable +#define BCR_BER BIT(7) // Bus Error + +#define CCR_CS_MASK (0x1f) // CCR Clock Period Sel. +#define CCR_EN BIT(5) // Enable +#define CCR_FM BIT(6) // Speed Mode Select + +#define CSR_CS_MASK (0x3f) // CSR Clock Period Sel. + +#define BC2R_SCLL BIT(0) // SCL Low Drive +#define BC2R_SDAL BIT(1) // SDA Low Drive +#define BC2R_SCLS BIT(4) // SCL Status +#define BC2R_SDAS BIT(5) // SDA Status + +/* PCLK frequency */ +#define BUS_CLK_FR(rate) (((rate) / 20000000) + 1) + +#define I2C_CLK_DEF 62500000 + +/* STANDARD MODE frequency */ +#define CLK_MASTER_STD(rate) \ + DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_SPEED_STANDARD_RATE) - 2, 2) +/* FAST MODE frequency */ +#define CLK_MASTER_FAST(rate) \ + DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_SPEED_FAST_RATE) - 2) * 2, 3) + +/* (clkrate <= 18000000) */ +/* calculate the value of CS bits in CCR register on standard mode */ +#define CCR_CS_STD_MAX_18M(rate) \ + ((CLK_MASTER_STD(rate) - 65) \ + & CCR_CS_MASK) + +/* calculate the value of CS bits in CSR register on standard mode */ +#define CSR_CS_STD_MAX_18M(rate) 0x00 + +/* calculate the value of CS bits in CCR register on fast mode */ +#define CCR_CS_FAST_MAX_18M(rate) \ + ((CLK_MASTER_FAST(rate) - 1) \ + & CCR_CS_MASK) + +/* calculate the value of CS bits in CSR register on fast mode */ +#define CSR_CS_FAST_MAX_18M(rate) 0x00 + +/* (clkrate > 18000000) */ +/* calculate the value of CS bits in CCR register on standard mode */ +#define CCR_CS_STD_MIN_18M(rate) \ + ((CLK_MASTER_STD(rate) - 1) \ + & CCR_CS_MASK) + +/* calculate the value of CS bits in CSR register on standard mode */ +#define CSR_CS_STD_MIN_18M(rate) \ + (((CLK_MASTER_STD(rate) - 1) >> 5) \ + & CSR_CS_MASK) + +/* calculate the value of CS bits in CCR register on fast mode */ +#define CCR_CS_FAST_MIN_18M(rate) \ + ((CLK_MASTER_FAST(rate) - 1) \ + & CCR_CS_MASK) + +/* calculate the value of CS bits in CSR register on fast mode */ +#define CSR_CS_FAST_MIN_18M(rate) \ + (((CLK_MASTER_FAST(rate) - 1) >> 5) \ + & CSR_CS_MASK) + +/* min I2C clock frequency 14M */ +#define MIN_CLK_RATE (14 * 1000000) +/* max I2C clock frequency 200M */ +#define MAX_CLK_RATE (200 * 1000000) +/* I2C clock frequency 18M */ +#define CLK_RATE_18M (18 * 1000000) + +#define SPEED_FM 400 // Fast Mode +#define SPEED_SM 100 // Standard Mode + +DECLARE_GLOBAL_DATA_PTR; + +struct synquacer_i2c { + void __iomem *base; + unsigned long pclkrate; + unsigned long speed_khz; +}; + +static int wait_irq(struct udevice *dev) +{ + struct synquacer_i2c *i2c = dev_get_priv(dev); + int timeout = 500000; + + do { + if (readb(i2c->base + REG_BCR) & BCR_INT) + return 0; + } while (timeout--); + + pr_err("%s: timeout\n", __func__); + return -1; +} + +static int synquacer_i2c_xfer_start(struct synquacer_i2c *i2c, + int addr, int read) +{ + u8 bsr, bcr; + + writeb((addr << 1) | (read ? 1 : 0), i2c->base + REG_DAR); + + bsr = readb(i2c->base + REG_BSR); + bcr = readb(i2c->base + REG_BCR); + + if ((bsr & BSR_BB) && !(bcr & BCR_MSS)) + return -EBUSY; + + if (bsr & BSR_BB) { + writeb(bcr | BCR_SCC, i2c->base + REG_BCR); + } else { + if (bcr & BCR_MSS) + return -EAGAIN; + /* Start Condition + Enable Interrupts */ + writeb(bcr | BCR_MSS | BCR_INTE | BCR_BEIE, i2c->base + REG_BCR); + } + + udelay(100); + return 0; +} + +static int synquacer_i2c_xfer(struct udevice *bus, + struct i2c_msg *msg, int nmsgs) +{ + struct synquacer_i2c *i2c = dev_get_priv(bus); + u8 bsr, bcr; + int idx; + + for (; nmsgs > 0; nmsgs--, msg++) { + synquacer_i2c_xfer_start(i2c, msg->addr, msg->flags & I2C_M_RD); + if (wait_irq(bus)) + return -EREMOTEIO; + + bsr = readb(i2c->base + REG_BSR); + if (bsr & BSR_LRB) { + debug("%s: No ack received\n", __func__); + return -EREMOTEIO; + } + + idx = 0; + do { + bsr = readb(i2c->base + REG_BSR); + bcr = readb(i2c->base + REG_BCR); + if (bcr & BCR_BER) { + debug("%s: Bus error detected\n", __func__); + return -EREMOTEIO; + } + if ((bsr & BSR_AL) || !(bcr & BCR_MSS)) { + debug("%s: Arbitration lost\n", __func__); + return -EREMOTEIO; + } + + if (msg->flags & I2C_M_RD) { + bcr = BCR_MSS | BCR_INTE | BCR_BEIE; + if (idx < msg->len - 1) + bcr |= BCR_ACK; + writeb(bcr, i2c->base + REG_BCR); + if (wait_irq(bus)) + return -EREMOTEIO; + bsr = readb(i2c->base + REG_BSR); + if (!(bsr & BSR_FBT)) + msg->buf[idx++] = readb(i2c->base + REG_DAR); + } else { + writeb(msg->buf[idx++], i2c->base + REG_DAR); + bcr = BCR_MSS | BCR_INTE | BCR_BEIE; + writeb(bcr, i2c->base + REG_BCR); + if (wait_irq(bus)) + return -EREMOTEIO; + bsr = readb(i2c->base + REG_BSR); + if (bsr & BSR_LRB) { + debug("%s: no ack\n", __func__); + return -EREMOTEIO; + } + } + } while (idx < msg->len); + } + + /* Force bus state to idle, terminating any ongoing transfer */ + writeb(0, i2c->base + REG_BCR); + udelay(100); + + return 0; +} + +static void synquacer_i2c_hw_reset(struct synquacer_i2c *i2c) +{ + /* Disable clock */ + writeb(0, i2c->base + REG_CCR); + writeb(0, i2c->base + REG_CSR); + + /* Set own Address */ + writeb(0, i2c->base + REG_ADR); + + /* Set PCLK frequency */ + writeb(BUS_CLK_FR(i2c->pclkrate), i2c->base + REG_FSR); + + /* clear IRQ (INT=0, BER=0), Interrupt Disable */ + writeb(0, i2c->base + REG_BCR); + writeb(0, i2c->base + REG_BC2R); +} + +static int synquacer_i2c_get_bus_speed(struct udevice *bus) +{ + struct synquacer_i2c *i2c = dev_get_priv(bus); + + return i2c->speed_khz * 1000; +} + +static int synquacer_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + struct synquacer_i2c *i2c = dev_get_priv(bus); + u32 rt = i2c->pclkrate; + u8 ccr_cs, csr_cs; + + /* Set PCLK frequency */ + writeb(BUS_CLK_FR(i2c->pclkrate), i2c->base + REG_FSR); + + if (speed >= SPEED_FM * 1000) { + i2c->speed_khz = SPEED_FM; + if (i2c->pclkrate <= CLK_RATE_18M) { + ccr_cs = CCR_CS_FAST_MAX_18M(rt); + csr_cs = CSR_CS_FAST_MAX_18M(rt); + } else { + ccr_cs = CCR_CS_FAST_MIN_18M(rt); + csr_cs = CSR_CS_FAST_MIN_18M(rt); + } + + /* Set Clock and enable, Set fast mode */ + writeb(ccr_cs | CCR_FM | CCR_EN, i2c->base + REG_CCR); + writeb(csr_cs, i2c->base + REG_CSR); + } else { + i2c->speed_khz = SPEED_SM; + if (i2c->pclkrate <= CLK_RATE_18M) { + ccr_cs = CCR_CS_STD_MAX_18M(rt); + csr_cs = CSR_CS_STD_MAX_18M(rt); + } else { + ccr_cs = CCR_CS_STD_MIN_18M(rt); + csr_cs = CSR_CS_STD_MIN_18M(rt); + } + + /* Set Clock and enable, Set standard mode */ + writeb(ccr_cs | CCR_EN, i2c->base + REG_CCR); + writeb(csr_cs, i2c->base + REG_CSR); + } + + return 0; +} + +static int synquacer_i2c_of_to_plat(struct udevice *bus) +{ + struct synquacer_i2c *priv = dev_get_priv(bus); + struct clk ck; + int ret; + + ret = clk_get_by_index(bus, 0, &ck); + if (ret < 0) { + priv->pclkrate = I2C_CLK_DEF; + } else { + clk_enable(&ck); + priv->pclkrate = clk_get_rate(&ck); + } + + return 0; +} + +static int synquacer_i2c_probe(struct udevice *bus) +{ + struct synquacer_i2c *i2c = dev_get_priv(bus); + + i2c->base = dev_read_addr_ptr(bus); + synquacer_i2c_hw_reset(i2c); + synquacer_i2c_set_bus_speed(bus, 400000); /* set default speed */ + return 0; +} + +static const struct dm_i2c_ops synquacer_i2c_ops = { + .xfer = synquacer_i2c_xfer, + .set_bus_speed = synquacer_i2c_set_bus_speed, + .get_bus_speed = synquacer_i2c_get_bus_speed, +}; + +static const struct udevice_id synquacer_i2c_ids[] = { + { + .compatible = "socionext,synquacer-i2c", + }, + { } +}; + +U_BOOT_DRIVER(sni_synquacer_i2c) = { + .name = "sni_synquacer_i2c", + .id = UCLASS_I2C, + .of_match = synquacer_i2c_ids, + .of_to_plat = synquacer_i2c_of_to_plat, + .probe = synquacer_i2c_probe, + .priv_auto = sizeof(struct synquacer_i2c), + .ops = &synquacer_i2c_ops, +}; -- cgit v1.2.3 From 2f1f797efa331ff4ab0c5dcac6cbb0081c431282 Mon Sep 17 00:00:00 2001 From: Masami Hiramatsu Date: Fri, 4 Jun 2021 18:44:59 +0900 Subject: ARM: dts: synquacer: Add device trees for DeveloperBox Add device trees for 96boards EE DeveloperBox and basement SynQuacer SoC dtsi. These files are imported from EDK2 commit 83d38b0b4c0f240d4488c600bbe87cea391f3922 as-is (except for the changes #include path and some macros). And add U-Boot specific changes in synquacer-sc2a11-developerbox-u-boot.dtsi Signed-off-by: Masami Hiramatsu --- arch/arm/dts/Makefile | 1 + arch/arm/dts/synquacer-sc2a11-caches.dtsi | 73 +++ .../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 75 +++ arch/arm/dts/synquacer-sc2a11-developerbox.dts | 56 ++ arch/arm/dts/synquacer-sc2a11.dtsi | 595 +++++++++++++++++++++ 5 files changed, 800 insertions(+) create mode 100644 arch/arm/dts/synquacer-sc2a11-caches.dtsi create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox.dts create mode 100644 arch/arm/dts/synquacer-sc2a11.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index eef94c4706..da4d0ed7c6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -249,6 +249,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ cn9130-crb-A.dtb \ cn9130-crb-B.dtb +dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \ uniphier-ld11-global.dtb \ uniphier-ld11-ref.dtb diff --git a/arch/arm/dts/synquacer-sc2a11-caches.dtsi b/arch/arm/dts/synquacer-sc2a11-caches.dtsi new file mode 100644 index 0000000000..177ddf8c2b --- /dev/null +++ b/arch/arm/dts/synquacer-sc2a11-caches.dtsi @@ -0,0 +1,73 @@ +/** @file + * Copyright (c) 2018, Linaro Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + */ + +#define __L1(cpuref, l2ref) \ +cpuref { \ + i-cache-size = <0x8000>; \ + i-cache-line-size = <64>; \ + i-cache-sets = <256>; \ + d-cache-size = <0x8000>; \ + d-cache-line-size = <64>; \ + d-cache-sets = <128>; \ + l2-cache = ; \ +}; + +#define __L2(idx) \ +L2_##idx: l2-cache##idx { \ + cache-size = <0x40000>; \ + cache-line-size = <64>; \ + cache-sets = <256>; \ + cache-unified; \ + next-level-cache = <&L3>; \ +}; + +/ { + __L2(0) + __L2(1) + __L2(2) + __L2(3) + __L2(4) + __L2(5) + __L2(6) + __L2(7) + __L2(8) + __L2(9) + __L2(10) + __L2(11) + + L3: l3-cache { + cache-level = <3>; + cache-size = <0x400000>; + cache-line-size = <64>; + cache-sets = <4096>; + cache-unified; + }; +}; + +__L1(&CPU0, &L2_0) +__L1(&CPU1, &L2_0) +__L1(&CPU2, &L2_1) +__L1(&CPU3, &L2_1) +__L1(&CPU4, &L2_2) +__L1(&CPU5, &L2_2) +__L1(&CPU6, &L2_3) +__L1(&CPU7, &L2_3) +__L1(&CPU8, &L2_4) +__L1(&CPU9, &L2_4) +__L1(&CPU10, &L2_5) +__L1(&CPU11, &L2_5) +__L1(&CPU12, &L2_6) +__L1(&CPU13, &L2_6) +__L1(&CPU14, &L2_7) +__L1(&CPU15, &L2_7) +__L1(&CPU16, &L2_8) +__L1(&CPU17, &L2_8) +__L1(&CPU18, &L2_9) +__L1(&CPU19, &L2_9) +__L1(&CPU20, &L2_10) +__L1(&CPU21, &L2_10) +__L1(&CPU22, &L2_11) +__L1(&CPU23, &L2_11) diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi new file mode 100644 index 0000000000..2f13a42235 --- /dev/null +++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// Copyright (c) 2021, Linaro Limited. All rights reserved. +// + +/ { + aliases { + spi_nor = &spi_nor; + i2c0 = &i2c0; + }; + + spi_nor: spi@54800000 { + compatible = "socionext,synquacer-spi"; + reg = <0x00 0x54800000 0x00 0x1000>; + interrupts = <0x00 0x9c 0x04 0x00 0x9d 0x04 0x00 0x9e 0x04>; + clocks = <&clk_alw_1_8>; + clock-names = "iHCLK"; + socionext,use-rtm; + socionext,set-aces; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + active_clk_edges; + chipselect_num = <1>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <31250000>; + spi-rx-bus-width = <0x1>; + spi-tx-bus-width = <0x1>; + }; + }; + + i2c0: i2c@51200000 { + compatible = "socionext,synquacer-i2c"; + reg = <0x0 0x51200000 0x0 0x1000>; + interrupts = ; + clocks = <&clk_i2c>; + clock-names = "pclk"; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + firmware { + optee { + status = "okay"; + }; + }; +}; + +&smmu { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&sdhci { + status = "okay"; +}; diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox.dts b/arch/arm/dts/synquacer-sc2a11-developerbox.dts new file mode 100644 index 0000000000..42b6cbbb82 --- /dev/null +++ b/arch/arm/dts/synquacer-sc2a11-developerbox.dts @@ -0,0 +1,56 @@ +/** @file + * Copyright (c) 2017, Linaro Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + */ + +/dts-v1/; + +#include "synquacer-sc2a11.dtsi" + +#define KEY_POWER 116 + +/ { + model = "Socionext Developer Box"; + compatible = "socionext,developer-box", "socionext,synquacer"; + + gpio-keys { + compatible = "gpio-keys"; + interrupt-parent = <&exiu>; + + power { + label = "Power Button"; + linux,code = ; + interrupts = ; + wakeup-source; + }; + }; +}; + +#ifdef TPM2_ENABLE +&tpm { + status = "okay"; +}; +#endif + +&gpio { + gpio-line-names = "DSW3-PIN1", "DSW3-PIN2", "DSW3-PIN3", "DSW3-PIN4", + "DSW3-PIN5", "DSW3-PIN6", "DSW3-PIN7", "DSW3-PIN8", + "PSIN#", "PWROFF#", "GPIO-A", "GPIO-B", + "GPIO-C", "GPIO-D", "PCIE1EXTINT", "PCIE0EXTINT", + "PHY2-INT#", "PHY1-INT#", "GPIO-E", "GPIO-F", + "GPIO-G", "GPIO-H", "GPIO-I", "GPIO-J", + "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27", + "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31"; +}; + +&netsec { + phy-mode = "rgmii-id"; +}; + +&mdio_netsec { + phy_netsec: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; diff --git a/arch/arm/dts/synquacer-sc2a11.dtsi b/arch/arm/dts/synquacer-sc2a11.dtsi new file mode 100644 index 0000000000..1fe7d214b9 --- /dev/null +++ b/arch/arm/dts/synquacer-sc2a11.dtsi @@ -0,0 +1,595 @@ +/** @file + * Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + */ + +/* These are added for U-Boot to avoid compilation error */ +#define PcdNetsecEepromBase 0x08080000 +#define FixedPcdGet32(n) n + +#define GIC_SPI 0 +#define GIC_PPI 1 + +#define IRQ_TYPE_NONE 0 +#define IRQ_TYPE_EDGE_RISING 1 +#define IRQ_TYPE_EDGE_FALLING 2 +#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) +#define IRQ_TYPE_LEVEL_HIGH 4 +#define IRQ_TYPE_LEVEL_LOW 8 + +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + aliases { + serial0 = &soc_uart0; + serial1 = &fuart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU4: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x200>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU5: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x201>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU6: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x300>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU7: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x301>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU8: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x400>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU9: cpu@401 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x401>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU10: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x500>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU11: cpu@501 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x501>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU12: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x600>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU13: cpu@601 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x601>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU14: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x700>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU15: cpu@701 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x701>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU16: cpu@800 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x800>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU17: cpu@801 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x801>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU18: cpu@900 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x900>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU19: cpu@901 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x901>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU20: cpu@a00 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0xa00>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU21: cpu@a01 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0xa01>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU22: cpu@b00 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0xb00>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU23: cpu@b01 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0xb01>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + }; + cluster1 { + core0 { + cpu = <&CPU2>; + }; + core1 { + cpu = <&CPU3>; + }; + }; + cluster2 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + }; + cluster3 { + core0 { + cpu = <&CPU6>; + }; + core1 { + cpu = <&CPU7>; + }; + }; + cluster4 { + core0 { + cpu = <&CPU8>; + }; + core1 { + cpu = <&CPU9>; + }; + }; + cluster5 { + core0 { + cpu = <&CPU10>; + }; + core1 { + cpu = <&CPU11>; + }; + }; + cluster6 { + core0 { + cpu = <&CPU12>; + }; + core1 { + cpu = <&CPU13>; + }; + }; + cluster7 { + core0 { + cpu = <&CPU14>; + }; + core1 { + cpu = <&CPU15>; + }; + }; + cluster8 { + core0 { + cpu = <&CPU16>; + }; + core1 { + cpu = <&CPU17>; + }; + }; + cluster9 { + core0 { + cpu = <&CPU18>; + }; + core1 { + cpu = <&CPU19>; + }; + }; + cluster10 { + core0 { + cpu = <&CPU20>; + }; + core1 { + cpu = <&CPU21>; + }; + }; + cluster11 { + core0 { + cpu = <&CPU22>; + }; + core1 { + cpu = <&CPU23>; + }; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <300>; + exit-latency-us = <1200>; + min-residency-us = <2000>; + local-timer-stop; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <400>; + exit-latency-us = <1200>; + min-residency-us = <2500>; + local-timer-stop; + }; + }; + + gic: interrupt-controller@30000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x30000000 0x0 0x10000>, // GICD + <0x0 0x30400000 0x0 0x300000>, // GICR + <0x0 0x2c000000 0x0 0x2000>, // GICC + <0x0 0x2c010000 0x0 0x1000>, // GICH + <0x0 0x2c020000 0x0 0x10000>; // GICV + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + interrupts = ; + + its: gic-its@30020000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x30020000 0x0 0x20000>; + #msi-cells = <1>; + msi-controller; + socionext,synquacer-pre-its = <0x58000000 0x200000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , // secure + , // non-secure + , // virtual + ; // HYP + }; + + mmio-timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <0>; + interrupts = ; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + clk_uart: refclk62500khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <62500000>; + clock-output-names = "uartclk"; + }; + + clk_apb: refclk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "apb_pclk"; + }; + + soc_uart0: uart@2a400000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2a400000 0x0 0x1000>; + interrupts = ; + clocks = <&clk_uart>, <&clk_apb>; + clock-names = "uartclk", "apb_pclk"; + }; + + fuart: uart@51040000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x51040000 0x0 0x1000>; + interrupts = ; + clocks = <&clk_uart>, <&clk_apb>; + clock-names = "baudclk", "apb_pclk"; + reg-io-width = <4>; + reg-shift = <2>; + }; + + clk_netsec: refclk250mhz { + compatible = "fixed-clock"; + clock-frequency = <250000000>; + #clock-cells = <0>; + }; + + netsec: ethernet@522d0000 { + compatible = "socionext,synquacer-netsec"; + reg = <0 0x522d0000 0x0 0x10000>, + <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>; + interrupts = ; + clocks = <&clk_netsec>; + clock-names = "phy_ref_clk"; + max-speed = <1000>; + max-frame-size = <9000>; + phy-handle = <&phy_netsec>; + dma-coherent; + + mdio_netsec: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + smmu: iommu@582c0000 { + compatible = "arm,mmu-500", "arm,smmu-v2"; + reg = <0x0 0x582c0000 0x0 0x10000>; + #global-interrupts = <1>; + interrupts = , + , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + pcie0: pcie@60000000 { + compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam"; + device_type = "pci"; + reg = <0x0 0x60000000 0x0 0x7f00000>; + bus-range = <0x0 0x7e>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x1000000 0x00 0x00000000 0x00 0x67f00000 0x0 0x00010000>, + <0x2000000 0x00 0x68000000 0x00 0x68000000 0x0 0x08000000>, + <0x3000000 0x3e 0x00000000 0x3e 0x00000000 0x1 0x00000000>; + + #interrupt-cells = <0x1>; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + + msi-map = <0x000 &its 0x0 0x7f00>; + dma-coherent; + status = "disabled"; + }; + + pcie1: pcie@70000000 { + compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam"; + device_type = "pci"; + reg = <0x0 0x70000000 0x0 0x7f00000>; + bus-range = <0x0 0x7e>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x1000000 0x00 0x00000000 0x00 0x77f00000 0x0 0x00010000>, + <0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>, + <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>; + + #interrupt-cells = <0x1>; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + + msi-map = <0x0 &its 0x10000 0x7f00>; + dma-coherent; + status = "disabled"; + }; + + gpio: gpio@51000000 { + compatible = "socionext,synquacer-gpio", "fujitsu,mb86s70-gpio"; + reg = <0x0 0x51000000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clk_apb>; + base = <0>; + }; + + exiu: interrupt-controller@510c0000 { + compatible = "socionext,synquacer-exiu"; + reg = <0x0 0x510c0000 0x0 0x20>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <3>; + socionext,spi-base = <112>; + }; + + clk_alw_b_0: bclk200 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "sd_bclk"; + }; + + clk_alw_c_0: sd4clk800 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "sd_sd4clk"; + }; + + sdhci: sdhci@52300000 { + compatible = "socionext,synquacer-sdhci", "fujitsu,mb86s70-sdhci-3.0"; + reg = <0 0x52300000 0x0 0x1000>; + interrupts = , + ; + bus-width = <8>; + cap-mmc-highspeed; + fujitsu,cmd-dat-delay-select; + clocks = <&clk_alw_c_0 &clk_alw_b_0>; + clock-names = "core", "iface"; + dma-coherent; + status = "disabled"; + }; + + clk_alw_1_8: spi_ihclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "iHCLK"; + }; + + spi: spi@54810000 { + compatible = "socionext,synquacer-spi"; + reg = <0x0 0x54810000 0x0 0x1000>; + interrupts = , + , + ; + clocks = <&clk_alw_1_8>; + clock-names = "iHCLK"; + socionext,use-rtm; + socionext,set-aces; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + clk_i2c: i2c_pclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <62500000>; + clock-output-names = "pclk"; + }; + + i2c: i2c@51210000 { + compatible = "socionext,synquacer-i2c"; + reg = <0x0 0x51210000 0x0 0x1000>; + interrupts = ; + clocks = <&clk_i2c>; + clock-names = "pclk"; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + tpm: tpm_tis@10000000 { + compatible = "socionext,synquacer-tpm-mmio"; + reg = <0x0 0x10000000 0x0 0x5000>; + status = "disabled"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + }; +}; + +#include "synquacer-sc2a11-caches.dtsi" -- cgit v1.2.3 From 5cd4a355e0f0addb718642b877939819b772936c Mon Sep 17 00:00:00 2001 From: Masami Hiramatsu Date: Fri, 4 Jun 2021 18:45:10 +0900 Subject: board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu --- arch/arm/Kconfig | 14 +++ board/socionext/developerbox/Kconfig | 36 +++++++ board/socionext/developerbox/MAINTAINERS | 14 +++ board/socionext/developerbox/Makefile | 9 ++ board/socionext/developerbox/developerbox.c | 146 ++++++++++++++++++++++++++++ configs/synquacer_developerbox_defconfig | 112 +++++++++++++++++++++ doc/board/index.rst | 1 + doc/board/socionext/developerbox.rst | 87 +++++++++++++++++ doc/board/socionext/index.rst | 9 ++ include/configs/synquacer.h | 109 +++++++++++++++++++++ 10 files changed, 537 insertions(+) create mode 100644 board/socionext/developerbox/Kconfig create mode 100644 board/socionext/developerbox/MAINTAINERS create mode 100644 board/socionext/developerbox/Makefile create mode 100644 board/socionext/developerbox/developerbox.c create mode 100644 configs/synquacer_developerbox_defconfig create mode 100644 doc/board/socionext/developerbox.rst create mode 100644 doc/board/socionext/index.rst create mode 100644 include/configs/synquacer.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 993772b643..03529d7b46 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1778,6 +1778,19 @@ config ARCH_UNIPHIER Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation) +config ARCH_SYNQUACER + bool "Socionext SynQuacer SoCs" + select ARM64 + select DM + select GIC_V3 + select PSCI_RESET + select SYSRESET + select SYSRESET_PSCI + select OF_CONTROL + help + Support for SynQuacer SoC family developed by Socionext Inc. + This SoC is used on 96boards EE DeveloperBox. + config ARCH_STM32 bool "Support STMicroelectronics STM32 MCU with cortex M" select CPU_V7M @@ -2121,6 +2134,7 @@ source "board/isee/igep003x/Kconfig" source "board/kontron/sl28/Kconfig" source "board/myir/mys_6ulx/Kconfig" source "board/seeed/npi_imx6ull/Kconfig" +source "board/socionext/developerbox/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" source "board/spear/spear320/Kconfig" diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig new file mode 100644 index 0000000000..706b8dc0f1 --- /dev/null +++ b/board/socionext/developerbox/Kconfig @@ -0,0 +1,36 @@ +if ARCH_SYNQUACER + +choice + prompt "SC2A11 Cortex-A53 MPCore 24cores" + optional + +config TARGET_DEVELOPERBOX + bool "Socionext DeveloperBox" + select PCI + select DM_PCI + select PCIE_ECAM_SYNQUACER + select SYS_DISABLE_DCACHE_OPS + select OF_BOARD_SETUP + help + Choose this option if you build the U-Boot for the DeveloperBox + 96boards Enterprise Edition. + This board will booted from SCP firmware and it enables SMMU, thus + the dcache is updated automatically when DMA operation is executed. +endchoice + +config SYS_SOC + default "sc2a11" + +if TARGET_DEVELOPERBOX + +config SYS_BOARD + default "developerbox" + +config SYS_VENDOR + default "socionext" + +config SYS_CONFIG_NAME + default "synquacer" + +endif +endif diff --git a/board/socionext/developerbox/MAINTAINERS b/board/socionext/developerbox/MAINTAINERS new file mode 100644 index 0000000000..aa672b6e05 --- /dev/null +++ b/board/socionext/developerbox/MAINTAINERS @@ -0,0 +1,14 @@ +DEVELOPER BOX +M: Masami Hiramatsu +M: Jassi Brar +S: Maintained +F: arch/arm/dts/synquacer-* +F: board/socionext/developerbox/* +F: configs/synquacer_developerbox_defconfig +F: drivers/i2c/synquacer_i2c.c +F: drivers/mmc/f_sdh30.c +F: drivers/net/sni_netsec.c +F: drivers/pci/pcie_ecam_synquacer.c +F: drivers/spi/spi-synquacer.c +F: include/configs/synquacer.h +F: doc/board/socionext/developerbox.rst diff --git a/board/socionext/developerbox/Makefile b/board/socionext/developerbox/Makefile new file mode 100644 index 0000000000..4a46de995a --- /dev/null +++ b/board/socionext/developerbox/Makefile @@ -0,0 +1,9 @@ +# +# Author: Masami Hiramatsu +# +# Copyright (C) 2021 Linaro Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := developerbox.o diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c new file mode 100644 index 0000000000..34335baec3 --- /dev/null +++ b/board/socionext/developerbox/developerbox.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * u-boot/board/socionext/developerbox/developerbox.c + * + * Copyright (C) 2016-2017 Socionext Inc. + * Copyright (C) 2021 Linaro Ltd. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +static struct mm_region sc2a11_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_OUTER_SHARE + }, { + /* 1st DDR block */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = PHYS_SDRAM_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* 2nd DDR place holder */ + 0, + }, { + /* 3rd DDR place holder */ + 0, + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = sc2a11_mem_map; + +#define DDR_REGION_INDEX(i) (1 + (i)) +#define MAX_DDR_REGIONS 3 + +struct draminfo_entry { + u64 base; + u64 size; +}; + +struct draminfo { + u32 nr_regions; + u32 reserved; + struct draminfo_entry entry[3]; +}; + +struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE; + +DECLARE_GLOBAL_DATA_PTR; + +#define LOAD_OFFSET 0x100 + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET; + + gd->env_addr = (ulong)&default_environment[0]; + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* Remove SPI NOR and I2C0 for making DT compatible with EDK2 */ + fdt_del_node_and_alias(blob, "spi_nor"); + fdt_del_node_and_alias(blob, "i2c0"); + + return 0; +} + +/* + * DRAM configuration + */ + +int dram_init(void) +{ + struct draminfo_entry *ent = synquacer_draminfo->entry; + struct mm_region *mr; + int i, ri; + + if (synquacer_draminfo->nr_regions < 1) { + log_err("Failed to get correct DRAM information\n"); + return -1; + } + + /* + * U-Boot RAM size must be under the first DRAM region so that it doesn't + * access secure memory which is at the end of the first DRAM region. + */ + gd->ram_size = ent[0].size; + + /* Update memory region maps */ + for (i = 0; i < synquacer_draminfo->nr_regions; i++) { + if (i >= MAX_DDR_REGIONS) + break; + + ri = DDR_REGION_INDEX(i); + mem_map[ri].phys = ent[i].base; + mem_map[ri].size = ent[i].size; + if (i == 0) + continue; + + mr = &mem_map[DDR_REGION_INDEX(0)]; + mem_map[ri].virt = mr->virt + mr->size; + mem_map[ri].attrs = mr->attrs; + } + + return 0; +} + +int dram_init_banksize(void) +{ + struct draminfo_entry *ent = synquacer_draminfo->entry; + int i; + + for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) { + if (i < synquacer_draminfo->nr_regions) { + debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base); + gd->bd->bi_dram[i].start = ent[i].base; + gd->bd->bi_dram[i].size = ent[i].size; + } + } + + return 0; +} + +int print_cpuinfo(void) +{ + printf("CPU: SC2A11:Cortex-A53 MPCore 24cores\n"); + return 0; +} diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig new file mode 100644 index 0000000000..cbc09d3225 --- /dev/null +++ b/configs/synquacer_developerbox_defconfig @@ -0,0 +1,112 @@ +CONFIG_ARM=y +CONFIG_ARCH_SYNQUACER=y +CONFIG_SYS_TEXT_BASE=0x08200000 +CONFIG_ENV_SIZE=0x30000 +CONFIG_ENV_OFFSET=0x300000 +CONFIG_DEBUG_UART_BASE=0x2a400000 +CONFIG_DEBUG_UART_CLOCK=62500000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_DEVELOPERBOX=y +CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox" +CONFIG_AHCI=y +CONFIG_BOOTSTAGE_STASH_SIZE=4096 +CONFIG_BOOTM_EFI=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTEFI=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_GPT=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_NVEDIT_INFO=y +CONFIG_CMD_DM=y +CONFIG_CMD_MII=y +CONFIG_CMD_NET=y +CONFIG_CMD_BOOTP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_DATE=y +CONFIG_CMD_RTC=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_SATA=y +CONFIG_CMD_NVME=y +CONFIG_CMD_USB=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDPARTS_DEFAULT="nor1:448k(BootStrap-BL1),576k(Flash-Writer),512k(SCP-BL2),480k(FIP-TFA),32k(Stg2-Tables),1m@2m(U-Boot),1m@3m(UBoot-Env),2m@5m(Ex-OPTEE)" +CONFIG_MTDIDS_DEFAULT="nor1=nor1" +CONFIG_CMD_LOG=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_EFI_PARTITION=y +CONFIG_EFI_LOADER=y +CONFIG_EFI_DEVICE_PATH_TO_TEXT=y +CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2=y +CONFIG_EFI_UNICODE_CAPITALIZATION=y +CONFIG_EFI_HAVE_RUNTIME_RESET=y +CONFIG_EFI_GET_TIME=y +CONFIG_EFI_SET_TIME=y +CONFIG_CMD_EFI_VARIABLE_FILE_STORE=Y +CONFIG_OF_SEPARATE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_ENV_SPI_BUS=y +CONFIG_ENV_SPI_BUS=0 +CONFIG_USE_ENV_SPI_CS=y +CONFIG_ENV_SPI_CS=0 +CONFIG_PROT_UDP=y +CONFIG_BAUDRATE=115200 +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_CONS_INDEX=0 +CONFIG_DM_SERIAL=y +CONFIG_PL01X_SERIAL=y +CONFIG_SATA=y +CONFIG_NVME=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_SYNQUACER=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_F_SDH30=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=31250000 +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHYLIB_10G=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SNI_NETSEC=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_PHY_GIGE=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF8563=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SYNQUACER_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_STORAGE=y diff --git a/doc/board/index.rst b/doc/board/index.rst index 747511f7dd..7349e468b2 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -22,6 +22,7 @@ Board-specific doc rockchip/index sifive/index sipeed/index + socionext/index st/index tbs/index toradex/index diff --git a/doc/board/socionext/developerbox.rst b/doc/board/socionext/developerbox.rst new file mode 100644 index 0000000000..2d943c23be --- /dev/null +++ b/doc/board/socionext/developerbox.rst @@ -0,0 +1,87 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Introduction +============ + +DeveloperBox is a certified 96boards Enterprise Edition board. The board/SoC has: - + +* Socionext SC2A11 24-cores ARM Cortex-A53 on tbe Mini-ATX form factor motherboard +* 4 DIMM slots (4GB DDR4-2400 UDIMM shipped by default) +* 1 4xPCIe Gen2 slot and 2 1xPCIe Gen2 slots + (1x slots are connected via PCIe bridge chip) +* 4 USB-3.0 ports +* 2 SATA ports +* 1 GbE network port +* 1 USB-UART serial port (micro USB) +* 64MB SPI NOR Flash +* 8GB eMMC Flash Storage +* 96boards LS connector + +The DeveloperBox schematic can be found here: - +https://www.96boards.org/documentation/enterprise/developerbox/hardware-docs/mzsc2am_v03_20180115_a.pdf + +And the other documents can be found here: - +https://www.96boards.org/documentation/enterprise/developerbox/ + + +Currently, the U-Boot port supports: - + +* USB +* eMMC +* SPI-NOR +* SATA +* GbE + +The DeveloperBox boots the TF-A and EDK2 as a main bootloader by default. +The DeveloperBox U-Boot port will replace the EDK2 and boot from TF-A as +BL33, but no need to combine with it. + +Compile from source +=================== + +You can build U-Boot without any additinal source code.:: + + cd u-boot + export ARCH=arm64 + export CROSS_COMPILE=aarch64-linux-gnu- + make SynQuacer_defconfig + make -j `noproc` + +Then, expand the binary to 1MB for preparing flash.:: + + cp u-boot.bin SPI_NOR_UBOOT.fd + truncate -s 1M SPI_NOR_UBOOT.fd + +Installation +============ + +You can install the SNI_NOR_UBOOT.fd via NOR flash writer. + +Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine or other mezzanine which can connect to LS-UART0 port. +Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the board on again. The flash writer program will be started automatically; don’t forget to turn the DSW2-7 off again after flashing. + +*!!CAUTION!! If you failed to write the U-Boot image on wrong address, the board can be bricked. See below page if you need to recover the bricked board. See the following page for more detail* + +https://www.96boards.org/documentation/enterprise/developerbox/installation/board-recovery.md.html + +When the serial flasher is running correctly is will show the following boot messages shown via LS-UART0:: + + + /*------------------------------------------*/ + /* SC2A11 "SynQuacer" series Flash writer */ + /* */ + /* Version: cd254ac */ + /* Build: 12/15/17 11:25:45 */ + /*------------------------------------------*/ + + Command Input > + +Once the flasher tool is running we are ready flash the UEFI image:: + + flash rawwrite 200000 100000 + >> Send SPI_NOR_UBOOT.fd via XMODEM (Control-A S in minicom) << + +*!!NOTE!! The flasher command parameter is different from the command for board recovery. U-Boot uses the offset 200000 (2-five-0, 2M in hex) and the size 100000 (1-five-0, 1M in hex).* + +After transferring the SPI_NOR_UBOOT.fd, turn off the DSW2-7 and reset the board. + diff --git a/doc/board/socionext/index.rst b/doc/board/socionext/index.rst new file mode 100644 index 0000000000..4673dcc45b --- /dev/null +++ b/doc/board/socionext/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Socionext +========= + +.. toctree:: + :maxdepth: 2 + + developerbox diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h new file mode 100644 index 0000000000..0dab4de1f1 --- /dev/null +++ b/include/configs/synquacer.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016-2017 Socionext Inc. + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Timers for fasp(TIMCLK) */ +#define CONFIG_SYS_HZ 1000 /* 1 msec */ +#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */ + +/* + * SDRAM (for initialize) + */ +#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */ +#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */ + +#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */ +#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE + +#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */ + +/* + * Boot info + */ +#define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */ +#define CONFIG_SYS_MALLOC_LEN (0x01000000) /* 16Mbyte size of malloc() */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default kernel load address */ + +/* + * Hardware drivers support + */ + +/* RTC */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 + +/* Serial (pl011) */ +#define UART_CLK (62500000) +#define CONFIG_SERIAL_MULTI +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK UART_CLK +#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)} + +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ + +/* Support MTD */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BASE (0x08000000) +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} + +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512 * 1024)) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 128 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ +/* #define CONFIG_SYS_PCI_64BIT 1 */ + +/* Distro boot settings */ +#ifndef CONFIG_SPL_BUILD +#ifdef CONFIG_CMD_USB +#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICE_USB(func) +#endif + +#ifdef CONFIG_CMD_MMC +#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICE_MMC(func) +#endif + +#ifdef CONFIG_CMD_NVME +#define BOOT_TARGET_DEVICE_NVME(func) func(NVME, nvme, 0) +#else +#define BOOT_TARGET_DEVICE_NVME(func) +#endif + +#ifdef CONFIG_CMD_SCSI +#define BOOT_TARGET_DEVICE_SCSI(func) func(SCSI, scsi, 0) func(SCSI, scsi, 1) +#else +#define BOOT_TARGET_DEVICE_SCSI(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICE_USB(func) \ + BOOT_TARGET_DEVICE_MMC(func) \ + BOOT_TARGET_DEVICE_SCSI(func) \ + BOOT_TARGET_DEVICE_NVME(func) \ + +#include +#else /* CONFIG_SPL_BUILD */ +#define BOOTENV +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_addr_r=0x9fe00000\0" \ + "kernel_addr_r=0x90000000\0" \ + "ramdisk_addr_r=0xa0000000\0" \ + "scriptaddr=0x88000000\0" \ + "pxefile_addr_r=0x88100000\0" \ + BOOTENV + +#endif /* __CONFIG_H */ -- cgit v1.2.3 From 6ae303b62b7c1d858e16a12b5ba86a41fcfa2d0f Mon Sep 17 00:00:00 2001 From: Masami Hiramatsu Date: Fri, 4 Jun 2021 18:45:21 +0900 Subject: doc: qemu: arm64: Fix the documentation of capsule update Since the EDK2 GenerateCapsule script is out of date and it doesn't generate the supported version capsule file, the document should refer the mkeficapsule in tools. Signed-off-by: Masami Hiramatsu --- doc/board/emulation/qemu_capsule_update.rst | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/doc/board/emulation/qemu_capsule_update.rst b/doc/board/emulation/qemu_capsule_update.rst index 33ce4bcd32..0a2286d039 100644 --- a/doc/board/emulation/qemu_capsule_update.rst +++ b/doc/board/emulation/qemu_capsule_update.rst @@ -39,16 +39,9 @@ In addition, the following config needs to be disabled(QEMU ARM specific):: CONFIG_TFABOOT -The capsule file can be generated by using the GenerateCapsule.py -script in EDKII:: - - $ ./BaseTools/BinWrappers/PosixLike/GenerateCapsule -e -o \ - --fw-version --lsv --guid \ - e2bb9c06-70e9-4b14-97a3-5a7913176e3f --verbose --update-image-index \ - --verbose +The capsule file can be generated by using the tools/mkeficapsule:: -The above is a wrapper script(GenerateCapsule) which eventually calls -the actual GenerateCapsule.py script. + $ mkeficapsule --raw --index 1 As per the UEFI specification, the capsule file needs to be placed on the EFI System Partition, under the \EFI\UpdateCapsule directory. The -- cgit v1.2.3 From 3a37386f18c82f7270e892dbd51e3f00cf5d8a19 Mon Sep 17 00:00:00 2001 From: Masami Hiramatsu Date: Fri, 4 Jun 2021 18:45:31 +0900 Subject: configs: synquacer: Enable EFI capsule update support Enable EFI capsule update support. With the EFI capsule update, you can update U-Boot, TF-A and OP-TEE. TF-A and OP-TEE are usually combined as a FIP binary, but if the binary is bigger than 480KB, you have to modify FIP header, split the OP-TEE and stores the OP-TEE binary in the different place. This configuration supports both cases. Signed-off-by: Masami Hiramatsu --- configs/synquacer_developerbox_defconfig | 17 +++++++++++++++++ include/configs/synquacer.h | 6 ++++++ 2 files changed, 23 insertions(+) diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index cbc09d3225..d42db9a1d6 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -110,3 +110,20 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT=y +CONFIG_EFI_CAPSULE_FIRMWARE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y +CONFIG_EFI_CAPSULE_FMP_HEADER=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_CMD_DFU=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MTD=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_DFU_SF_PART=y +CONFIG_FIT=y +CONFIG_OF_LIBFDT=y +CONFIG_CMD_ERASEENV=y diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 0dab4de1f1..8fe10d7485 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -61,6 +61,11 @@ /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ /* #define CONFIG_SYS_PCI_64BIT 1 */ +#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \ + "mtd nor1=u-boot.bin raw 200000 100000;" \ + "fip.bin raw 180000 78000;" \ + "optee.bin raw 500000 100000\0" + /* Distro boot settings */ #ifndef CONFIG_SPL_BUILD #ifdef CONFIG_CMD_USB @@ -104,6 +109,7 @@ "ramdisk_addr_r=0xa0000000\0" \ "scriptaddr=0x88000000\0" \ "pxefile_addr_r=0x88100000\0" \ + DEFAULT_DFU_ALT_INFO \ BOOTENV #endif /* __CONFIG_H */ -- cgit v1.2.3 From bd4dbf9e435345cf859922fca74dc0603d7dac2b Mon Sep 17 00:00:00 2001 From: Trevor Woerner Date: Thu, 10 Jun 2021 22:37:02 -0400 Subject: lpc32xx: Kconfig: switch to CONFIG_CONS_INDEX There's nothing special or unique to the lpc32xx that requires its own config parameter for specifying the console uart index. Therefore instead of using the lpc32xx-specific CONFIG_SYS_LPC32XX_UART include parameter, use the already-available CONFIG_CONS_INDEX from Kconfig. Signed-off-by: Trevor Woerner Reviewed-by: Simon Glass --- arch/arm/include/asm/arch-lpc32xx/config.h | 4 ++-- arch/arm/mach-lpc32xx/devices.c | 3 +-- board/timll/devkit3250/devkit3250.c | 2 +- board/timll/devkit3250/devkit3250_spl.c | 2 +- board/work-microwave/work_92105/work_92105.c | 2 +- board/work-microwave/work_92105/work_92105_spl.c | 2 +- configs/devkit3250_defconfig | 2 ++ configs/work_92105_defconfig | 2 ++ include/configs/devkit3250.h | 5 ----- include/configs/work_92105.h | 5 ----- scripts/config_whitelist.txt | 1 - 11 files changed, 11 insertions(+), 19 deletions(-) diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 0836091af2..45e46f9946 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -12,8 +12,8 @@ /* Basic CPU architecture */ /* UART configuration */ -#if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \ - (CONFIG_SYS_LPC32XX_UART == 7) +#if (CONFIG_CONS_INDEX == 1) || (CONFIG_CONS_INDEX == 2) || \ + (CONFIG_CONS_INDEX == 7) #if !defined(CONFIG_LPC32XX_HSUART) #define CONFIG_LPC32XX_HSUART #endif diff --git a/arch/arm/mach-lpc32xx/devices.c b/arch/arm/mach-lpc32xx/devices.c index e1e2e0d094..0a4fef295a 100644 --- a/arch/arm/mach-lpc32xx/devices.c +++ b/arch/arm/mach-lpc32xx/devices.c @@ -23,8 +23,7 @@ void lpc32xx_uart_init(unsigned int uart_id) return; /* Disable loopback mode, if it is set by S1L bootloader */ - clrbits_le32(&ctrl->loop, - UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART)); + clrbits_le32(&ctrl->loop, UART_LOOPBACK(uart_id)); if (uart_id < 3 || uart_id > 6) return; diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c index 3c744b943f..9d4ffb0f97 100644 --- a/board/timll/devkit3250/devkit3250.c +++ b/board/timll/devkit3250/devkit3250.c @@ -38,7 +38,7 @@ void reset_periph(void) int board_early_init_f(void) { - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + lpc32xx_uart_init(CONFIG_CONS_INDEX); lpc32xx_i2c_init(1); lpc32xx_i2c_init(2); lpc32xx_ssp_init(); diff --git a/board/timll/devkit3250/devkit3250_spl.c b/board/timll/devkit3250/devkit3250_spl.c index 47af78ae0b..12e8ae9c39 100644 --- a/board/timll/devkit3250/devkit3250_spl.c +++ b/board/timll/devkit3250/devkit3250_spl.c @@ -49,7 +49,7 @@ void spl_board_init(void) /* First of all silence buzzer controlled by GPO_20 */ writel((1 << 20), &gpio->p3_outp_clr); - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + lpc32xx_uart_init(CONFIG_CONS_INDEX); preloader_console_init(); ddr_init(&dram_64mb); diff --git a/board/work-microwave/work_92105/work_92105.c b/board/work-microwave/work_92105/work_92105.c index bdcecff730..5d12f84cfe 100644 --- a/board/work-microwave/work_92105/work_92105.c +++ b/board/work-microwave/work_92105/work_92105.c @@ -37,7 +37,7 @@ void reset_periph(void) int board_early_init_f(void) { /* initialize serial port for console */ - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + lpc32xx_uart_init(CONFIG_CONS_INDEX); /* enable I2C, SSP, MAC, NAND */ lpc32xx_i2c_init(1); /* only I2C1 has devices, I2C2 has none */ lpc32xx_ssp_init(); diff --git a/board/work-microwave/work_92105/work_92105_spl.c b/board/work-microwave/work_92105/work_92105_spl.c index a31553a2d2..d9401145f2 100644 --- a/board/work-microwave/work_92105/work_92105_spl.c +++ b/board/work-microwave/work_92105/work_92105_spl.c @@ -58,7 +58,7 @@ const struct emc_dram_settings dram_128mb = { void spl_board_init(void) { /* initialize serial port for console */ - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + lpc32xx_uart_init(CONFIG_CONS_INDEX); /* initialize console */ preloader_console_init(); /* init DDR and NAND to chainload U-Boot */ diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index 93c048cee8..9ae70f7d46 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -51,6 +51,8 @@ CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ADDR=31 CONFIG_PHY_SMSC=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_CONS_INDEX=5 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_USB=y diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index c3f666dcfe..e9605adedd 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -48,5 +48,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_SMSC=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_CONS_INDEX=5 CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 5d2b77b4a3..921a38c01e 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -30,11 +30,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ - GENERATED_GBL_DATA_SIZE) -/* - * Serial Driver - */ -#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */ - /* * DMA */ diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 7874b77f3f..076a1b065e 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -35,11 +35,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ - GENERATED_GBL_DATA_SIZE) -/* - * Serial Driver - */ -#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */ - /* * Ethernet Driver */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index e549a5557f..624d851f0d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2734,7 +2734,6 @@ CONFIG_SYS_LOW CONFIG_SYS_LOWMEM_BASE CONFIG_SYS_LOW_RES_TIMER CONFIG_SYS_LPAE_SDRAM_BASE -CONFIG_SYS_LPC32XX_UART CONFIG_SYS_LS1_DDR_BLOCK1_SIZE CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS -- cgit v1.2.3 From eb5807e68f4334bcc610acd827c889e0abe9231b Mon Sep 17 00:00:00 2001 From: Trevor Woerner Date: Thu, 10 Jun 2021 22:37:03 -0400 Subject: lpc32xx: import device tree from Linux Import the dtsi, dts, and clock binding files for the lpc32xx ea3250 board directly and unmodified from the latest Linux kernel. Signed-off-by: Trevor Woerner --- arch/arm/dts/lpc3250-ea3250.dts | 273 ++++++++++++++++ arch/arm/dts/lpc32xx.dtsi | 508 ++++++++++++++++++++++++++++++ include/dt-bindings/clock/lpc32xx-clock.h | 58 ++++ 3 files changed, 839 insertions(+) create mode 100644 arch/arm/dts/lpc3250-ea3250.dts create mode 100644 arch/arm/dts/lpc32xx.dtsi create mode 100644 include/dt-bindings/clock/lpc32xx-clock.h diff --git a/arch/arm/dts/lpc3250-ea3250.dts b/arch/arm/dts/lpc3250-ea3250.dts new file mode 100644 index 0000000000..63c6f17bb7 --- /dev/null +++ b/arch/arm/dts/lpc3250-ea3250.dts @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Embedded Artists LPC3250 board + * + * Copyright 2012 Roland Stigge + */ + +/dts-v1/; +#include "lpc32xx.dtsi" + +/ { + model = "Embedded Artists LPC3250 board based on NXP LPC3250"; + compatible = "ea,ea3250", "nxp,lpc3250"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x4000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + button { + label = "Interrupt Key"; + linux,code = <103>; + gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ + }; + + key1 { + label = "KEY1"; + linux,code = <1>; + gpios = <&pca9532 0 0>; + }; + + key2 { + label = "KEY2"; + linux,code = <2>; + gpios = <&pca9532 1 0>; + }; + + key3 { + label = "KEY3"; + linux,code = <3>; + gpios = <&pca9532 2 0>; + }; + + key4 { + label = "KEY4"; + linux,code = <4>; + gpios = <&pca9532 3 0>; + }; + + joy0 { + label = "Joystick Key 0"; + linux,code = <10>; + gpios = <&gpio 2 0 0>; /* P2.0 */ + }; + + joy1 { + label = "Joystick Key 1"; + linux,code = <11>; + gpios = <&gpio 2 1 0>; /* P2.1 */ + }; + + joy2 { + label = "Joystick Key 2"; + linux,code = <12>; + gpios = <&gpio 2 2 0>; /* P2.2 */ + }; + + joy3 { + label = "Joystick Key 3"; + linux,code = <13>; + gpios = <&gpio 2 3 0>; /* P2.3 */ + }; + + joy4 { + label = "Joystick Key 4"; + linux,code = <14>; + gpios = <&gpio 2 4 0>; /* P2.4 */ + }; + }; + + leds { + compatible = "gpio-leds"; + + /* LEDs on OEM Board */ + + led1 { + gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */ + linux,default-trigger = "timer"; + default-state = "off"; + }; + + led2 { + gpios = <&gpio 2 10 1>; /* P2.10, active low */ + default-state = "off"; + }; + + led3 { + gpios = <&gpio 2 11 1>; /* P2.11, active low */ + default-state = "off"; + }; + + led4 { + gpios = <&gpio 2 12 1>; /* P2.12, active low */ + default-state = "off"; + }; + + /* LEDs on Base Board */ + + lede1 { + gpios = <&pca9532 8 0>; + default-state = "off"; + }; + lede2 { + gpios = <&pca9532 9 0>; + default-state = "off"; + }; + lede3 { + gpios = <&pca9532 10 0>; + default-state = "off"; + }; + lede4 { + gpios = <&pca9532 11 0>; + default-state = "off"; + }; + lede5 { + gpios = <&pca9532 12 0>; + default-state = "off"; + }; + lede6 { + gpios = <&pca9532 13 0>; + default-state = "off"; + }; + lede7 { + gpios = <&pca9532 14 0>; + default-state = "off"; + }; + lede8 { + gpios = <&pca9532 15 0>; + default-state = "off"; + }; + }; +}; + +/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */ +&adc { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + + uda1380: uda1380@18 { + compatible = "nxp,uda1380"; + reg = <0x18>; + power-gpio = <&gpio 3 10 0>; + reset-gpio = <&gpio 3 2 0>; + dac-clk = "wspll"; + }; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; + + eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + }; + + pca9532: pca9532@60 { + compatible = "nxp,pca9532"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x60>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2cusb { + clock-frequency = <100000>; + + isp1301: usb-transceiver@2d { + compatible = "nxp,isp1301"; + reg = <0x2d>; + }; +}; + +&mac { + phy-mode = "rmii"; + use-iram; + status = "okay"; +}; + +/* Here, choose exactly one from: ohci, usbd */ +&ohci /* &usbd */ { + transceiver = <&isp1301>; + status = "okay"; +}; + +&sd { + wp-gpios = <&pca9532 5 0>; + cd-gpios = <&pca9532 4 0>; + cd-inverted; + bus-width = <4>; + status = "okay"; +}; + +/* 128MB Flash via SLC NAND controller */ +&slc { + status = "okay"; + + nxp,wdr-clks = <14>; + nxp,wwidth = <260000000>; + nxp,whold = <104000000>; + nxp,wsetup = <200000000>; + nxp,rdr-clks = <14>; + nxp,rwidth = <34666666>; + nxp,rhold = <104000000>; + nxp,rsetup = <200000000>; + nand-on-flash-bbt; + gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + mtd0@0 { + label = "ea3250-boot"; + reg = <0x00000000 0x00080000>; + read-only; + }; + + mtd1@80000 { + label = "ea3250-uboot"; + reg = <0x00080000 0x000c0000>; + read-only; + }; + + mtd2@140000 { + label = "ea3250-kernel"; + reg = <0x00140000 0x00400000>; + }; + + mtd3@540000 { + label = "ea3250-rootfs"; + reg = <0x00540000 0x07ac0000>; + }; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&uart6 { + status = "okay"; +}; diff --git a/arch/arm/dts/lpc32xx.dtsi b/arch/arm/dts/lpc32xx.dtsi new file mode 100644 index 0000000000..c87066d6c9 --- /dev/null +++ b/arch/arm/dts/lpc32xx.dtsi @@ -0,0 +1,508 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NXP LPC32xx SoC + * + * Copyright (C) 2015-2019 Vladimir Zapolskiy + * Copyright 2012 Roland Stigge + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "nxp,lpc3220"; + interrupt-parent = <&mic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0x0>; + }; + }; + + clocks { + xtal_32k: xtal_32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32k"; + }; + + xtal: xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <13000000>; + clock-output-names = "xtal"; + }; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x00000000 0x00000000 0x10000000>, + <0x20000000 0x20000000 0x30000000>, + <0xe0000000 0xe0000000 0x04000000>; + + iram: sram@8000000 { + compatible = "mmio-sram"; + reg = <0x08000000 0x20000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x08000000 0x20000>; + }; + + /* + * Enable either SLC or MLC + */ + slc: flash@20020000 { + compatible = "nxp,lpc3220-slc"; + reg = <0x20020000 0x1000>; + clocks = <&clk LPC32XX_CLK_SLC>; + status = "disabled"; + }; + + mlc: flash@200a8000 { + compatible = "nxp,lpc3220-mlc"; + reg = <0x200a8000 0x11000>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_MLC>; + status = "disabled"; + }; + + dma: dma@31000000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0x31000000 0x1000>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_DMA>; + clock-names = "apb_pclk"; + }; + + usb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x0 0x31020000 0x00001000>; + + /* + * Enable either ohci or usbd (gadget)! + */ + ohci: ohci@0 { + compatible = "nxp,ohci-nxp", "usb-ohci"; + reg = <0x0 0x300>; + interrupt-parent = <&sic1>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usbclk LPC32XX_USB_CLK_HOST>; + status = "disabled"; + }; + + usbd: usbd@0 { + compatible = "nxp,lpc3220-udc"; + reg = <0x0 0x300>; + interrupt-parent = <&sic1>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, + <30 IRQ_TYPE_LEVEL_HIGH>, + <28 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_LOW>; + clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; + status = "disabled"; + }; + + i2cusb: i2c@300 { + compatible = "nxp,pnx-i2c"; + reg = <0x300 0x100>; + interrupt-parent = <&sic1>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usbclk LPC32XX_USB_CLK_I2C>; + #address-cells = <1>; + #size-cells = <0>; + }; + + usbclk: clock-controller@f00 { + compatible = "nxp,lpc3220-usb-clk"; + reg = <0xf00 0x100>; + #clock-cells = <1>; + }; + }; + + clcd: clcd@31040000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x31040000 0x1000>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>; + clock-names = "clcdclk", "apb_pclk"; + status = "disabled"; + }; + + mac: ethernet@31060000 { + compatible = "nxp,lpc-eth"; + reg = <0x31060000 0x1000>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_MAC>; + status = "disabled"; + }; + + emc: memory-controller@31080000 { + compatible = "arm,pl175", "arm,primecell"; + reg = <0x31080000 0x1000>; + clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>; + clock-names = "mpmcclk", "apb_pclk"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xe0000000 0x01000000>, + <1 0xe1000000 0x01000000>, + <2 0xe2000000 0x01000000>, + <3 0xe3000000 0x01000000>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x20000000 0x20000000 0x30000000>; + + /* + * ssp0 and spi1 are shared pins; + * enable one in your board dts, as needed. + */ + ssp0: spi@20084000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x20084000 0x1000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_SSP0>; + clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@20088000 { + compatible = "nxp,lpc3220-spi"; + reg = <0x20088000 0x1000>; + clocks = <&clk LPC32XX_CLK_SPI1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* + * ssp1 and spi2 are shared pins; + * enable one in your board dts, as needed. + */ + ssp1: spi@2008c000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x2008c000 0x1000>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_SSP1>; + clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@20090000 { + compatible = "nxp,lpc3220-spi"; + reg = <0x20090000 0x1000>; + clocks = <&clk LPC32XX_CLK_SPI2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2s0: i2s@20094000 { + compatible = "nxp,lpc3220-i2s"; + reg = <0x20094000 0x1000>; + status = "disabled"; + }; + + sd: sd@20098000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x20098000 0x1000>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_SD>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + i2s1: i2s@2009c000 { + compatible = "nxp,lpc3220-i2s"; + reg = <0x2009c000 0x1000>; + status = "disabled"; + }; + + /* UART5 first since it is the default console, ttyS0 */ + uart5: serial@40090000 { + /* actually, ns16550a w/ 64 byte fifos! */ + compatible = "nxp,lpc3220-uart"; + reg = <0x40090000 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + clocks = <&clk LPC32XX_CLK_UART5>; + status = "disabled"; + }; + + uart3: serial@40080000 { + compatible = "nxp,lpc3220-uart"; + reg = <0x40080000 0x1000>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + clocks = <&clk LPC32XX_CLK_UART3>; + status = "disabled"; + }; + + uart4: serial@40088000 { + compatible = "nxp,lpc3220-uart"; + reg = <0x40088000 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + clocks = <&clk LPC32XX_CLK_UART4>; + status = "disabled"; + }; + + uart6: serial@40098000 { + compatible = "nxp,lpc3220-uart"; + reg = <0x40098000 0x1000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + clocks = <&clk LPC32XX_CLK_UART6>; + status = "disabled"; + }; + + i2c1: i2c@400a0000 { + compatible = "nxp,pnx-i2c"; + reg = <0x400a0000 0x100>; + interrupt-parent = <&sic1>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk LPC32XX_CLK_I2C1>; + }; + + i2c2: i2c@400a8000 { + compatible = "nxp,pnx-i2c"; + reg = <0x400a8000 0x100>; + interrupt-parent = <&sic1>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk LPC32XX_CLK_I2C2>; + }; + + mpwm: mpwm@400e8000 { + compatible = "nxp,lpc3220-motor-pwm"; + reg = <0x400e8000 0x78>; + status = "disabled"; + #pwm-cells = <2>; + }; + }; + + fab { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x20000000 0x20000000 0x30000000>; + + /* System Control Block */ + scb { + compatible = "simple-bus"; + ranges = <0x0 0x040004000 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + + clk: clock-controller@0 { + compatible = "nxp,lpc3220-clk"; + reg = <0x00 0x114>; + #clock-cells = <1>; + + clocks = <&xtal_32k>, <&xtal>; + clock-names = "xtal_32k", "xtal"; + }; + }; + + mic: interrupt-controller@40008000 { + compatible = "nxp,lpc3220-mic"; + reg = <0x40008000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sic1: interrupt-controller@4000c000 { + compatible = "nxp,lpc3220-sic"; + reg = <0x4000c000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&mic>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>, + <30 IRQ_TYPE_LEVEL_LOW>; + }; + + sic2: interrupt-controller@40010000 { + compatible = "nxp,lpc3220-sic"; + reg = <0x40010000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&mic>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>, + <31 IRQ_TYPE_LEVEL_LOW>; + }; + + uart1: serial@40014000 { + compatible = "nxp,lpc3220-hsuart"; + reg = <0x40014000 0x1000>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart2: serial@40018000 { + compatible = "nxp,lpc3220-hsuart"; + reg = <0x40018000 0x1000>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart7: serial@4001c000 { + compatible = "nxp,lpc3220-hsuart"; + reg = <0x4001c000 0x1000>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + rtc: rtc@40024000 { + compatible = "nxp,lpc3220-rtc"; + reg = <0x40024000 0x1000>; + interrupt-parent = <&sic1>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_RTC>; + }; + + gpio: gpio@40028000 { + compatible = "nxp,lpc3220-gpio"; + reg = <0x40028000 0x1000>; + gpio-controller; + #gpio-cells = <3>; /* bank, pin, flags */ + }; + + timer4: timer@4002c000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x4002c000 0x1000>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk LPC32XX_CLK_TIMER4>; + clock-names = "timerclk"; + status = "disabled"; + }; + + timer5: timer@40030000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40030000 0x1000>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk LPC32XX_CLK_TIMER5>; + clock-names = "timerclk"; + status = "disabled"; + }; + + watchdog: watchdog@4003c000 { + compatible = "nxp,pnx4008-wdt"; + reg = <0x4003c000 0x1000>; + clocks = <&clk LPC32XX_CLK_WDOG>; + }; + + timer0: timer@40044000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40044000 0x1000>; + clocks = <&clk LPC32XX_CLK_TIMER0>; + clock-names = "timerclk"; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + }; + + /* + * TSC vs. ADC: Since those two share the same + * hardware, you need to choose from one of the + * following two and do 'status = "okay";' for one of + * them + */ + + adc: adc@40048000 { + compatible = "nxp,lpc3220-adc"; + reg = <0x40048000 0x1000>; + interrupt-parent = <&sic1>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_ADC>; + status = "disabled"; + }; + + tsc: tsc@40048000 { + compatible = "nxp,lpc3220-tsc"; + reg = <0x40048000 0x1000>; + interrupt-parent = <&sic1>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_ADC>; + status = "disabled"; + }; + + timer1: timer@4004c000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x4004c000 0x1000>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk LPC32XX_CLK_TIMER1>; + clock-names = "timerclk"; + }; + + key: key@40050000 { + compatible = "nxp,lpc3220-key"; + reg = <0x40050000 0x1000>; + clocks = <&clk LPC32XX_CLK_KEY>; + interrupt-parent = <&sic1>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer2: timer@40058000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40058000 0x1000>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk LPC32XX_CLK_TIMER2>; + clock-names = "timerclk"; + status = "disabled"; + }; + + pwm1: pwm@4005c000 { + compatible = "nxp,lpc3220-pwm"; + reg = <0x4005c000 0x4>; + clocks = <&clk LPC32XX_CLK_PWM1>; + assigned-clocks = <&clk LPC32XX_CLK_PWM1>; + assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; + status = "disabled"; + }; + + pwm2: pwm@4005c004 { + compatible = "nxp,lpc3220-pwm"; + reg = <0x4005c004 0x4>; + clocks = <&clk LPC32XX_CLK_PWM2>; + assigned-clocks = <&clk LPC32XX_CLK_PWM2>; + assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; + status = "disabled"; + }; + + timer3: timer@40060000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40060000 0x1000>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk LPC32XX_CLK_TIMER3>; + clock-names = "timerclk"; + status = "disabled"; + }; + }; + }; +}; diff --git a/include/dt-bindings/clock/lpc32xx-clock.h b/include/dt-bindings/clock/lpc32xx-clock.h new file mode 100644 index 0000000000..e624d3a527 --- /dev/null +++ b/include/dt-bindings/clock/lpc32xx-clock.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2015 Vladimir Zapolskiy + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ + +#ifndef __DT_BINDINGS_LPC32XX_CLOCK_H +#define __DT_BINDINGS_LPC32XX_CLOCK_H + +/* LPC32XX System Control Block clocks */ +#define LPC32XX_CLK_RTC 1 +#define LPC32XX_CLK_DMA 2 +#define LPC32XX_CLK_MLC 3 +#define LPC32XX_CLK_SLC 4 +#define LPC32XX_CLK_LCD 5 +#define LPC32XX_CLK_MAC 6 +#define LPC32XX_CLK_SD 7 +#define LPC32XX_CLK_DDRAM 8 +#define LPC32XX_CLK_SSP0 9 +#define LPC32XX_CLK_SSP1 10 +#define LPC32XX_CLK_UART3 11 +#define LPC32XX_CLK_UART4 12 +#define LPC32XX_CLK_UART5 13 +#define LPC32XX_CLK_UART6 14 +#define LPC32XX_CLK_IRDA 15 +#define LPC32XX_CLK_I2C1 16 +#define LPC32XX_CLK_I2C2 17 +#define LPC32XX_CLK_TIMER0 18 +#define LPC32XX_CLK_TIMER1 19 +#define LPC32XX_CLK_TIMER2 20 +#define LPC32XX_CLK_TIMER3 21 +#define LPC32XX_CLK_TIMER4 22 +#define LPC32XX_CLK_TIMER5 23 +#define LPC32XX_CLK_WDOG 24 +#define LPC32XX_CLK_I2S0 25 +#define LPC32XX_CLK_I2S1 26 +#define LPC32XX_CLK_SPI1 27 +#define LPC32XX_CLK_SPI2 28 +#define LPC32XX_CLK_MCPWM 29 +#define LPC32XX_CLK_HSTIMER 30 +#define LPC32XX_CLK_KEY 31 +#define LPC32XX_CLK_PWM1 32 +#define LPC32XX_CLK_PWM2 33 +#define LPC32XX_CLK_ADC 34 +#define LPC32XX_CLK_HCLK_PLL 35 +#define LPC32XX_CLK_PERIPH 36 + +/* LPC32XX USB clocks */ +#define LPC32XX_USB_CLK_I2C 1 +#define LPC32XX_USB_CLK_DEVICE 2 +#define LPC32XX_USB_CLK_HOST 3 + +#endif /* __DT_BINDINGS_LPC32XX_CLOCK_H */ -- cgit v1.2.3 From faf78fd464f46269887be90e5b9d2db405aa5f4e Mon Sep 17 00:00:00 2001 From: Trevor Woerner Date: Thu, 10 Jun 2021 22:37:04 -0400 Subject: arm: lpc32xx: add EA LPC3250 DevKitv2 board support Add basic support for running U-Boot on the Embedded Artists LPC3250 Developer's Kit v2 board by launching U-Boot from the board's s1l loader (which comes pre-installed on the board). Signed-off-by: Trevor Woerner --- arch/arm/dts/Makefile | 2 + arch/arm/dts/lpc3250-ea3250-u-boot.dtsi | 15 +++ arch/arm/mach-lpc32xx/Kconfig | 4 + board/ea/ea-lpc3250devkitv2/Kconfig | 15 +++ board/ea/ea-lpc3250devkitv2/MAINTAINERS | 9 ++ board/ea/ea-lpc3250devkitv2/Makefile | 4 + board/ea/ea-lpc3250devkitv2/README.rst | 132 +++++++++++++++++++++++ board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c | 37 +++++++ configs/ea-lpc3250devkitv2_defconfig | 23 ++++ include/configs/ea-lpc3250devkitv2.h | 37 +++++++ 10 files changed, 278 insertions(+) create mode 100644 arch/arm/dts/lpc3250-ea3250-u-boot.dtsi create mode 100644 board/ea/ea-lpc3250devkitv2/Kconfig create mode 100644 board/ea/ea-lpc3250devkitv2/MAINTAINERS create mode 100644 board/ea/ea-lpc3250devkitv2/Makefile create mode 100644 board/ea/ea-lpc3250devkitv2/README.rst create mode 100644 board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c create mode 100644 configs/ea-lpc3250devkitv2_defconfig create mode 100644 include/configs/ea-lpc3250devkitv2.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index da4d0ed7c6..59d8078558 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1117,6 +1117,8 @@ dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb +dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here diff --git a/arch/arm/dts/lpc3250-ea3250-u-boot.dtsi b/arch/arm/dts/lpc3250-ea3250-u-boot.dtsi new file mode 100644 index 0000000000..0c82e512c6 --- /dev/null +++ b/arch/arm/dts/lpc3250-ea3250-u-boot.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Trevor Woerner + */ + +/{ + model = "Embedded Artists LPC3250 DevKit v2 board based on the NXP LPC3250 SoC"; + chosen { + stdout-path = &uart5; + }; +}; + +&uart5 { + compatible = "nxp,lpc3220-uart", "ns16550a"; +}; diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig index 986ad738ac..185bda41c2 100644 --- a/arch/arm/mach-lpc32xx/Kconfig +++ b/arch/arm/mach-lpc32xx/Kconfig @@ -12,9 +12,13 @@ config TARGET_DEVKIT3250 config TARGET_WORK_92105 bool "Work Microwave Work_92105" +config TARGET_EA_LPC3250DEVKITV2 + bool "Embedded Artists LPC3250 Developer's Kit v2" + endchoice source "board/timll/devkit3250/Kconfig" source "board/work-microwave/work_92105/Kconfig" +source "board/ea/ea-lpc3250devkitv2/Kconfig" endif diff --git a/board/ea/ea-lpc3250devkitv2/Kconfig b/board/ea/ea-lpc3250devkitv2/Kconfig new file mode 100644 index 0000000000..368ce027e6 --- /dev/null +++ b/board/ea/ea-lpc3250devkitv2/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EA_LPC3250DEVKITV2 + +config SYS_BOARD + default "ea-lpc3250devkitv2" + +config SYS_VENDOR + default "ea" + +config SYS_SOC + default "lpc32xx" + +config SYS_CONFIG_NAME + default "ea-lpc3250devkitv2" + +endif diff --git a/board/ea/ea-lpc3250devkitv2/MAINTAINERS b/board/ea/ea-lpc3250devkitv2/MAINTAINERS new file mode 100644 index 0000000000..b4b9362f5b --- /dev/null +++ b/board/ea/ea-lpc3250devkitv2/MAINTAINERS @@ -0,0 +1,9 @@ +EMBEDDED ARTISTS LPC3250 DEVKIT v2 +M: Trevor Woerner +S: Maintained +F: board/ea/ea-lpc3250devkitv2 +F: include/configs/ea-lpc3250devkitv2.h +F: configs/ea-lpc3250devkitv2_defconfig +F: arch/arm/dts/lpc32xx.dtsi +F: arch/arm/dts/lpc3250-ea3250.dts +F: arch/arm/dts/lpc3250-ea3250-u-boot.dtsi diff --git a/board/ea/ea-lpc3250devkitv2/Makefile b/board/ea/ea-lpc3250devkitv2/Makefile new file mode 100644 index 0000000000..a4a40b6d4f --- /dev/null +++ b/board/ea/ea-lpc3250devkitv2/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2021 Trevor Woerner + +obj-y += ea-lpc3250devkitv2.o diff --git a/board/ea/ea-lpc3250devkitv2/README.rst b/board/ea/ea-lpc3250devkitv2/README.rst new file mode 100644 index 0000000000..56b5d0dbb1 --- /dev/null +++ b/board/ea/ea-lpc3250devkitv2/README.rst @@ -0,0 +1,132 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +ToC: +- Introduction +- Booting +- Debugging + + +Introduction +============ +The Embedded Artists LPC3250 Developer's Kit v2 features the LPC3250 SoC +which is based on the ARM926EJ-S CPU. The kit features a base board and +a removable OEM board which features the SoC. Details, schematics, and +documentation are available from the Embedded Artists product website: + + https://www.embeddedartists.com/products/lpc3250-developers-kit-v2/ + +The base board includes:: +- 200 pos, 0.6mm pitch SODIMM connector for OEM Board +- LCD expansion connector with control signals for touch screen interface +- Expansion connector with all OEM Board signals +- Ethernet connector (RJ45) +- CAN interface & connector (provision for second CAN interface, but not mounted) +- MMC/SD interface & connector +- USB1: OTG or Host interface & connector +- USB2: Device or Host interface & connector +- Provision for NXP JN5148 RF module (former Jennic) interface (RF module not included) +- Full modem RS232 (cannot be fully used on 32-bit databus OEM boards) +- RS422/485 interface & connector +- Provision for IrDA transceiver interface (transceiver not mounted) +- I2S audio codec (mic in, line in, line out, headphone out) +- SWD/JTAG connector +- Trace connector and pads for ETM connector +- Serial Expansion Connector, 14-pos connector with UART/I2C/SPI/GPIO pins +- Power supply, either via USB or external 5V DC +- Optional coin cell battery for RTC and LED on ALARM output (coin cell not included) +- OEM Board current measuring +- Parallel NOR flash on external memory bus +- 16-bit register and LEDs on external memory bus +- 5-key joystick +- LM75 temperature sensor (I2C connected) +- 5 push-button keys (four via I2C and one on ISP-ENABLE) +- 9 LEDs (8 via I2C and one on ISP-ENABLE) +- Trimming potentiometer to analog input +- USB-to-serial bridge on UART #0 (FT232R) and ISP functionality +- Reset push-button and LED +- Speaker output on analog output from OEM Board, or from I2S audio codec +- 160x150 mm in size + +The OEM board:: +- ARMv5 ARM926EJ-S @ 266 MHz with hard-float VFPv2 +- 256 KByte IRAM, 64 MByte SDRAM +- 128 MByte NAND flash +- 4 MByte NOR Flash +- Graphics Output: Parallel RGB +- Hardware 2D/3D Graphic: No +- Hardware Video: SW only +- Graphics input: No +- Audio: I2S +- Ethernet: 10/100 Mbps +- USB: 1x FS USB 2.0 OTG +- Wi-Fi: No +- FlexIO: No +- Serial: 2x I2C, 2x SPI, 7x UART +- ADC/PWM: 3 ch (10-bit) / 2 ch +- SD: MCI +- PCIe: No +- Serial ATA: No +- Size: 68 x 48 mm +- Connector: 200 pos SODIMM + + +Booting +======= +The processor will start its code execution from an internal ROM, +containing the boot code. This boot loader can load code from one of four +external sources to internal RAM (IRAM) at address 0x0:: +- UART5 +- SSP0 (in SPI mode) +- EMC Static CS0 memory +- NAND FLASH + +The ROM boot loader loads code as a single contiguous block at a maximum +size of 56 kByte. Programs larger than this size must be loaded in more +steps, for example, by a secondary boot loader. + +Kickstart Loader +---------------- +By default the Embedded Artists LPC3250 OEM Board is programmed with the +kickstart loader in block 0 of the NAND flash. The responsibility of this +loader is to load an application stored in block 1 and onwards of the NAND +flash. The kickstart loader will load the application into internal RAM +(IRAM) at address 0x0. + +Stage 1 Loader (s1l) +-------------------- +By default the Embedded Artists LPC3250 OEM Board is programmed with the +stage 1 loader (s1l) in block 1 of the NAND flash. This application will be +loaded by the kickstart loader when the LPC3250 OEM Board powers up. The +S1L loader will initialize the board, such as clocks and external memory +and then start a console where you can give input commands to the loader. +S1L offers the following booting options:: +- MMC/SD card +- UART5 +- NAND Flash + +U-Boot with kickstart+s1l +------------------------- +Out of the box, the easiest way to get U-Boot running on the EA LPC3250 +DevKit v2 board is to build the ea-lpc3250devkitv2_defconfig, copy the +resulting u-boot.bin to a vfat-formatted MMC/SD card, insert the MMC/SD card +into the MMC/SD card slot on the board, reset the board (SW1), and:: + + Embedded Artist 3250 Board (S1L 2.0) + Build date: Oct 31 2016 13:00:37 + + EA3250>load blk u-boot.bin raw 0x83000000 + File loaded successfully + + EA3250>exec 0x83000000 + + +Debugging +========= +JTAG debugging of the Embedded Artists LPC3250 Developer's Kit v2 board is +easy thanks to the included/populated 20-pin JTAG port on the main board (J8). +openocd 0.11 has been used with this board along with the ARM-USB-OCD-H JTAG +dongle from Olimex successfully as follows: + + # openocd \ + -f interface/ftdi/olimex-arm-usb-ocd-h.cfg \ + -f board/phytec_lpc3250.cfg diff --git a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c new file mode 100644 index 0000000000..7a19400041 --- /dev/null +++ b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board init file for Embedded Artists LPC3250 DevKit v2 + * Copyright (C) 2021 Trevor Woerner + */ + +#include +#include +#include +#include + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int +board_early_init_f(void) +{ + lpc32xx_uart_init(CONFIG_CONS_INDEX); + return 0; +} + +int +board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x2000; + return 0; +} + +int +dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_64M); + return 0; +} diff --git a/configs/ea-lpc3250devkitv2_defconfig b/configs/ea-lpc3250devkitv2_defconfig new file mode 100644 index 0000000000..dc90e16475 --- /dev/null +++ b/configs/ea-lpc3250devkitv2_defconfig @@ -0,0 +1,23 @@ +CONFIG_ARM=y +CONFIG_SYS_ICACHE_OFF=y +CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_LPC32XX=y +CONFIG_SYS_TEXT_BASE=0x83000000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_TARGET_EA_LPC3250DEVKITV2=y +CONFIG_DEFAULT_DEVICE_TREE="lpc3250-ea3250" +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +# CONFIG_AUTOBOOT is not set +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="EA-LPC3250v2=> " +CONFIG_CMD_GPIO=y +CONFIG_OF_CONTROL=y +# CONFIG_NET is not set +CONFIG_LPC32XX_GPIO=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_CONS_INDEX=5 +CONFIG_SYS_NS16550=y +CONFIG_PANIC_HANG=y diff --git a/include/configs/ea-lpc3250devkitv2.h b/include/configs/ea-lpc3250devkitv2.h new file mode 100644 index 0000000000..c1a37c8a79 --- /dev/null +++ b/include/configs/ea-lpc3250devkitv2.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Embedded Artists LPC3250 DevKit v2 + * Copyright (C) 2021 Trevor Woerner + */ + +#ifndef __CONFIG_EA_LPC3250DEVKITV2_H__ +#define __CONFIG_EA_LPC3250DEVKITV2_H__ + +#include +#include + +/* + * SoC and board defines + */ +#define CONFIG_MACH_TYPE MACH_TYPE_LPC3XXX +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_SIZE_LIMIT 0x000fffff /* maximum allowable size for full U-Boot binary */ + +/* + * RAM + */ +#define CONFIG_SYS_MALLOC_LEN SZ_4M +#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE + +/* + * cmd + */ +#define CONFIG_SYS_LOAD_ADDR 0x80100000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE) + +/* + * SoC-specific config + */ +#include + +#endif -- cgit v1.2.3 From 1028403f2f53093f7c17dd57055d1e8da815348f Mon Sep 17 00:00:00 2001 From: Trevor Woerner Date: Thu, 10 Jun 2021 22:37:05 -0400 Subject: lpc32xx: i2c: remove unused define The LPC32XX_I2C_STAT_DRMI is not used anywhere so remove it. Signed-off-by: Trevor Woerner --- drivers/i2c/lpc32xx_i2c.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c index f89f7955e4..0ae116617c 100644 --- a/drivers/i2c/lpc32xx_i2c.c +++ b/drivers/i2c/lpc32xx_i2c.c @@ -38,7 +38,6 @@ /* Status register values */ #define LPC32XX_I2C_STAT_TFF 0x00000400 #define LPC32XX_I2C_STAT_RFE 0x00000200 -#define LPC32XX_I2C_STAT_DRMI 0x00000008 #define LPC32XX_I2C_STAT_NAI 0x00000004 #define LPC32XX_I2C_STAT_TDI 0x00000001 -- cgit v1.2.3 From 3f70acdb7dc8c274a09e4421f78e25eac33fef76 Mon Sep 17 00:00:00 2001 From: Trevor Woerner Date: Thu, 10 Jun 2021 22:37:06 -0400 Subject: lpc32xx: i2c: fix base address The lpc32xx driver was not obtaining the per-device base address correctly from the device tree. Fix the FIXME in order to get the correct base address. Signed-off-by: Trevor Woerner --- drivers/i2c/lpc32xx_i2c.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c index 0ae116617c..6abff263bd 100644 --- a/drivers/i2c/lpc32xx_i2c.c +++ b/drivers/i2c/lpc32xx_i2c.c @@ -282,11 +282,7 @@ static int lpc32xx_i2c_probe(struct udevice *bus) { struct lpc32xx_i2c_dev *dev = dev_get_plat(bus); - /* - * FIXME: This is not permitted - * dev_seq(bus) = dev->index; - */ - + dev->base = dev_read_addr_ptr(bus); __i2c_init(dev->base, dev->speed, 0, dev->index); return 0; } -- cgit v1.2.3 From 103f233ebf1662c1302f28bd39b6bdac3035f79b Mon Sep 17 00:00:00 2001 From: Trevor Woerner Date: Thu, 10 Jun 2021 22:37:07 -0400 Subject: lpc32xx: i2c: finish DM/OF code Add the of_match/compatible string to the lpc32xx i2c driver so it works correctly with device-tree. Signed-off-by: Trevor Woerner --- drivers/i2c/lpc32xx_i2c.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c index 6abff263bd..774129ad8e 100644 --- a/drivers/i2c/lpc32xx_i2c.c +++ b/drivers/i2c/lpc32xx_i2c.c @@ -348,9 +348,15 @@ static const struct dm_i2c_ops lpc32xx_i2c_ops = { .set_bus_speed = lpc32xx_i2c_set_bus_speed, }; +static const struct udevice_id lpc32xx_i2c_ids[] = { + { .compatible = "nxp,pnx-i2c" }, + { } +}; + U_BOOT_DRIVER(i2c_lpc32xx) = { - .id = UCLASS_I2C, .name = "i2c_lpc32xx", + .id = UCLASS_I2C, + .of_match = lpc32xx_i2c_ids, .probe = lpc32xx_i2c_probe, .ops = &lpc32xx_i2c_ops, }; -- cgit v1.2.3 From 0705556bc4d82d0fe72b68bab3a83b4e52b128df Mon Sep 17 00:00:00 2001 From: Trevor Woerner Date: Thu, 10 Jun 2021 22:37:08 -0400 Subject: Kconfig: convert CONFIG_SYS_I2C_LPC32XX Convert the CONFIG_SYS_I2C_LPC32XX configuration symbol from an include directive to a Kconfig value. Signed-off-by: Trevor Woerner Reviewed-by: Simon Glass --- configs/devkit3250_defconfig | 1 + configs/work_92105_defconfig | 1 + drivers/i2c/Kconfig | 6 ++++++ include/configs/devkit3250.h | 1 - include/configs/work_92105.h | 1 - scripts/config_whitelist.txt | 1 - 6 files changed, 8 insertions(+), 3 deletions(-) diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index 9ae70f7d46..c0354bce1a 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_JFFS2=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y +CONFIG_SYS_I2C_LPC32XX=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index e9605adedd..507f24fc37 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -42,6 +42,7 @@ CONFIG_DOS_PARTITION=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_VERSION_VARIABLE=y +CONFIG_SYS_I2C_LPC32XX=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index ce0d796d09..41065dd502 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -169,6 +169,12 @@ config SYS_I2C_IMX_LPI2C help Add support for the NXP i.MX LPI2C driver. +config SYS_I2C_LPC32XX + bool "LPC32XX I2C driver" + depends on ARCH_LPC32XX + help + Enable support for the LPC32xx I2C driver. + config SYS_I2C_MESON bool "Amlogic Meson I2C driver" depends on DM_I2C && ARCH_MESON diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 921a38c01e..465d9ce8e9 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -41,7 +41,6 @@ * I2C */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_LPC32XX #define CONFIG_SYS_I2C_SPEED 100000 /* diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 076a1b065e..d498c8f3bc 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -47,7 +47,6 @@ * I2C driver */ -#define CONFIG_SYS_I2C_LPC32XX #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_SPEED 350000 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 624d851f0d..ca6066b85e 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2542,7 +2542,6 @@ CONFIG_SYS_I2C_INIT_BOARD CONFIG_SYS_I2C_LDI_ADDR CONFIG_SYS_I2C_LM75_ADDR CONFIG_SYS_I2C_LM90_ADDR -CONFIG_SYS_I2C_LPC32XX CONFIG_SYS_I2C_LPC32XX_SLAVE CONFIG_SYS_I2C_LPC32XX_SPEED CONFIG_SYS_I2C_MAC1_BUS -- cgit v1.2.3 From ba621fe3a97e2b576eec3a27a06aa28af123badc Mon Sep 17 00:00:00 2001 From: Trevor Woerner Date: Thu, 10 Jun 2021 22:37:09 -0400 Subject: lpc32xx: ea-lpc3250devkitv2: enable i2c (DM) Enable a DMed i2c driver for the ea-lpc3250devkitv2 board. Include some sample commands/output for testing. Signed-off-by: Trevor Woerner --- board/ea/ea-lpc3250devkitv2/README.rst | 54 ++++++++++++++++++++++++ board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c | 4 ++ configs/ea-lpc3250devkitv2_defconfig | 3 ++ 3 files changed, 61 insertions(+) diff --git a/board/ea/ea-lpc3250devkitv2/README.rst b/board/ea/ea-lpc3250devkitv2/README.rst index 56b5d0dbb1..1b78000331 100644 --- a/board/ea/ea-lpc3250devkitv2/README.rst +++ b/board/ea/ea-lpc3250devkitv2/README.rst @@ -4,6 +4,7 @@ ToC: - Introduction - Booting - Debugging +- i2c Introduction @@ -130,3 +131,56 @@ dongle from Olimex successfully as follows: # openocd \ -f interface/ftdi/olimex-arm-usb-ocd-h.cfg \ -f board/phytec_lpc3250.cfg + + +i2c +=== +Some of the LEDs on the board are connected via an I/O Expander (PCA9532) that +is attached to the i2c1 bus. Here is a sample session of toggling some of +these LEDs via i2c in U-Boot: + +show the existing i2c busses: + EA-LPC3250v2=> i2c bus + Bus 0: i2c@300 + Bus 1: i2c@400a0000 + Bus 2: i2c@400a8000 + +set i2c1 as the current bus: + EA-LPC3250v2=> i2c dev 1 + Setting bus to 1 + +see what potential devices are found with rudimentary probing on i2c1: + EA-LPC3250v2=> i2c probe + Valid chip addresses: 1A 1D 48 50 57 60 66 6E + +According to the schematics the i2c slave address of the PCA9532 is 0x60. + +dump all of the 10 registers from the I/O Expander; NOTE that the 0x10 in the +command specifies the self-incrementing mode of the PCA9532; also NOTE that +the values repeat themseves to fill out a full 16 bytes: + EA-LPC3250v2=> i2c md 0x60 0x10 10 + 0010: 00 ff 00 80 00 80 00 00 00 00 4f ff 00 80 00 80 ..........O..... + +turn on LEDs 23, 25, 27, and 29 (green): + EA-LPC3250v2=> i2c mw 0x60 9 0x55 + +turn on LEDs 22, 24, 26, and 28 (red): + EA-LPC3250v2=> i2c mw 0x60 8 0x55 + +dim the green LEDs (23, 25, 27, 29): + EA-LPC3250v2=> i2c mw 0x60 3 0x20 + EA-LPC3250v2=> i2c mw 0x60 9 0xaa + +turn off all LEDs (23-29): + EA-LPC3250v2=> i2c mw 0x60 8 0 + EA-LPC3250v2=> i2c mw 0x60 9 0 + +read value of switches (input): + EA-LPC3250v2=> i2c md 0x60 0 1 + 0000: 4f O +[none are pressed] + +press and hold SW2 while running the following: + EA-LPC3250v2=> i2c md 0x60 0 1 + 0000: 4e N +[SW2 is pressed] diff --git a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c index 7a19400041..72cf46c749 100644 --- a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c +++ b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c @@ -19,6 +19,10 @@ int board_early_init_f(void) { lpc32xx_uart_init(CONFIG_CONS_INDEX); + if (IS_ENABLED(CONFIG_SYS_I2C_LPC32XX)) { + lpc32xx_i2c_init(1); + lpc32xx_i2c_init(2); + } return 0; } diff --git a/configs/ea-lpc3250devkitv2_defconfig b/configs/ea-lpc3250devkitv2_defconfig index dc90e16475..e8d60b573e 100644 --- a/configs/ea-lpc3250devkitv2_defconfig +++ b/configs/ea-lpc3250devkitv2_defconfig @@ -14,9 +14,12 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="EA-LPC3250v2=> " CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_OF_CONTROL=y # CONFIG_NET is not set CONFIG_LPC32XX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_LPC32XX=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_CONS_INDEX=5 CONFIG_SYS_NS16550=y -- cgit v1.2.3 From 9b6b25c63512604bb17a40a6005dff451699ef5e Mon Sep 17 00:00:00 2001 From: Sheep Sun Date: Sun, 20 Jun 2021 10:34:34 +0800 Subject: arm: snapdragon: Use correct GICC register on APQ8016 The GICC register used by u-boot is 0x0a20c000, which is actually a GICC for WCNSS, the WLAN processor. U-boot runs on the Application Processor, therefore it should use APCS GICC instead. Hence, correct it with APCS GICC register address. Signed-off-by: Sheep Sun --- arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h index 520e2e6bd7..d9a3b1af98 100644 --- a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h +++ b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h @@ -8,7 +8,7 @@ #define _MACH_SYSMAP_APQ8016_H #define GICD_BASE (0x0b000000) -#define GICC_BASE (0x0a20c000) +#define GICC_BASE (0x0b002000) /* Clocks: (from CLK_CTL_BASE) */ #define GPLL0_STATUS (0x2101C) -- cgit v1.2.3 From 6d430e11a86463745eeaec9292401ffbdfbc07d3 Mon Sep 17 00:00:00 2001 From: Sheep Sun Date: Sun, 20 Jun 2021 10:34:35 +0800 Subject: arm: snapdragon: Fix typo in clk_bcr_update() Fix typo in clock-snapdragon.c Signed-off-by: Sheep Sun --- arch/arm/mach-snapdragon/clock-snapdragon.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index fbe0b5212f..2b76371718 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -56,15 +56,15 @@ void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk) } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL)); } -#define APPS_CMD_RGCR_UPDATE BIT(0) +#define APPS_CMD_RCGR_UPDATE BIT(0) -/* Update clock command via CMD_RGCR */ -void clk_bcr_update(phys_addr_t apps_cmd_rgcr) +/* Update clock command via CMD_RCGR */ +void clk_bcr_update(phys_addr_t apps_cmd_rcgr) { - setbits_le32(apps_cmd_rgcr, APPS_CMD_RGCR_UPDATE); + setbits_le32(apps_cmd_rcgr, APPS_CMD_RCGR_UPDATE); /* Wait for frequency to be updated. */ - while (readl(apps_cmd_rgcr) & APPS_CMD_RGCR_UPDATE) + while (readl(apps_cmd_rcgr) & APPS_CMD_RCGR_UPDATE) ; } -- cgit v1.2.3 From 698c1df4d1bed2778d3344b98dabf4e4ba0efd0d Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Sun, 27 Jun 2021 13:06:15 +0200 Subject: arm: dts: db410c: Add missing cd-gpios for SD card detection It looks like SD card detection is broken at the moment for DB410c. The eMMC is detected correctly, but the SD card is not. This is probably similar to the issue fixed in commit 850514740358 ("mmc: msm_sdhci: Use mmc_of_parse for setting host_caps") for eMMC, except that the SD card does not have a property like "non-removable" that skips the card detection. The SDHCI on DB410c cannot detect itself if a SD card is inserted, so add the necessary cd-gpios to make SD card detection work again. While at it, fix the #gpio-cells for the soc_gpios to avoid DTC warnings - the soc_gpios are actually already used with two cells for the gpio-leds so this was just wrong all the time. Cc: Ramon Fried Signed-off-by: Stephan Gerhold Reviewed-by: Ramon Fried --- arch/arm/dts/dragonboard410c.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts index fa348bc621..7e56140df2 100644 --- a/arch/arm/dts/dragonboard410c.dts +++ b/arch/arm/dts/dragonboard410c.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "skeleton64.dtsi" +#include #include / { @@ -91,7 +92,7 @@ gpio-controller; gpio-count = <122>; gpio-bank-name="soc"; - #gpio-cells = <1>; + #gpio-cells = <2>; }; ehci@78d9000 { @@ -123,6 +124,7 @@ bus-width = <0x4>; clock = <&clkc 1>; clock-frequency = <200000000>; + cd-gpios = <&soc_gpios 38 GPIO_ACTIVE_LOW>; }; wcnss { -- cgit v1.2.3 From 725cf89512eba9a49d447f009e0b97fdf2ae5dd6 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 28 Jun 2021 10:40:09 +0200 Subject: serial: serial_msm: Ensure BAM/single character mode are disabled At the moment, the U-Boot serial_msm driver does not initialize the UART_DM_DMEN register with the required value. Usually this does not cause any problems, because there is Qualcomm's LK bootloader running before U-Boot which initializes the register with the correct value. It's important that this register is initialized correctly, because the U-Boot driver does not make use of the BAM/DMA or single character mode functionality of the UART controller. A different bootloader before U-Boot might initialize the register differently. For example, on DragonBoard 410c U-Boot can also be installed to the "aboot" partition (replacing LK entirely). In this case U-Boot is loaded directly by SBL, which seems to use the single-character mode for some reason. In single character mode there is always just one char in the FIFO, instead of the 4 characters expected by msm_serial_fetch(). It also causes issues with "earlycon" later in the Linux kernel, which tries to output 4 chars at once, but only the first char will be written. This causes early UART log in Linux to be corrupted like this: [ 00ano:ameoi .Q1B[ 00ac _idaM00080oo'ahani-lcle._20). 15NdNii 5 SPMSJ20:U2 [ 00rkoolmsamel [ 00Fw ]elamletopsioble [ 00ore instead of [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd030] [ 0.000000] Machine model: Qualcomm Technologies, Inc. APQ 8016 SBC [ 0.000000] earlycon: msm_serial_dm0 at MMIO 0x00000000078b0000 (options '') [ 0.000000] printk: bootconsole [msm_serial_dm0] enabled Make sure to initialize UART_DM_DMEN correctly to fix this issue when loading U-Boot directly after SBL (instead of through LK). There is no functional difference when loading U-Boot through LK since LK also initializes UART_DM_DMEN to 0x0. [1] [1]: https://git.linaro.org/landing-teams/working/qualcomm/lk.git/tree/platform/msm_shared/uart_dm.c?h=dragonboard410c-LA.BR.1.2.7-03810-8x16.0-linaro3#n203 Cc: Ramon Fried Signed-off-by: Stephan Gerhold Reviewed-by: Ramon Fried --- drivers/serial/serial_msm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index d8c6c2f6b5..d8dd5c1104 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -23,6 +23,7 @@ /* Serial registers - this driver works in uartdm mode*/ #define UARTDM_DMRX 0x34 /* Max RX transfer length */ +#define UARTDM_DMEN 0x3C /* DMA/data-packing mode */ #define UARTDM_NCF_TX 0x40 /* Number of chars to TX */ #define UARTDM_RXFS 0x50 /* RX channel status register */ @@ -197,6 +198,9 @@ static void uart_dm_init(struct msm_serial_data *priv) writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2); writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR); writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR); + + /* Make sure BAM/single character mode is disabled */ + writel(0x0, priv->base + UARTDM_DMEN); } static int msm_serial_probe(struct udevice *dev) { -- cgit v1.2.3