From 58afff43e3a8f31344cbbc6a3f09bd3f7a2a70eb Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 21 Feb 2018 15:06:20 +0100 Subject: clk: zynq: Show watchdog clock rate properly watchdog clock is also connected to cpu 1X clocksource. Zynq> clk dump ... Before: swdt 4294967290 After: swdt 111111110 Signed-off-by: Michal Simek --- drivers/clk/clk_zynq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c index 50f2a65c20..3845e07309 100644 --- a/drivers/clk/clk_zynq.c +++ b/drivers/clk/clk_zynq.c @@ -394,7 +394,7 @@ static ulong zynq_clk_get_rate(struct clk *clk) return zynq_clk_get_peripheral_rate(priv, id, two_divs); case dma_clk: return zynq_clk_get_cpu_rate(priv, cpu_2x_clk); - case usb0_aper_clk ... smc_aper_clk: + case usb0_aper_clk ... swdt_clk: return zynq_clk_get_cpu_rate(priv, cpu_1x_clk); default: return -ENXIO; -- cgit v1.2.3