From 679530c3c6ac99bc4da4dbf73a8e169bc9654e5b Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Tue, 2 Nov 2021 11:36:45 +0100 Subject: board: rename "tqc" vendor to "tq" The subdivision name "TQ Components" hasn't been in use for a long time. Rename the vendor directory to "tq", which also matches our Device Tree vendor prefix. Signed-off-by: Matthias Schiffer --- arch/arm/mach-imx/mx6/Kconfig | 2 +- board/tq/tqma6/Kconfig | 96 ++++++++++++ board/tq/tqma6/MAINTAINERS | 6 + board/tq/tqma6/Makefile | 8 + board/tq/tqma6/README | 38 +++++ board/tq/tqma6/clocks.cfg | 23 +++ board/tq/tqma6/tqma6.c | 306 +++++++++++++++++++++++++++++++++++++ board/tq/tqma6/tqma6_bb.h | 29 ++++ board/tq/tqma6/tqma6_mba6.c | 193 +++++++++++++++++++++++ board/tq/tqma6/tqma6_wru4.c | 347 ++++++++++++++++++++++++++++++++++++++++++ board/tq/tqma6/tqma6dl.cfg | 124 +++++++++++++++ board/tq/tqma6/tqma6q.cfg | 124 +++++++++++++++ board/tq/tqma6/tqma6s.cfg | 124 +++++++++++++++ board/tqc/tqma6/Kconfig | 96 ------------ board/tqc/tqma6/MAINTAINERS | 6 - board/tqc/tqma6/Makefile | 8 - board/tqc/tqma6/README | 38 ----- board/tqc/tqma6/clocks.cfg | 23 --- board/tqc/tqma6/tqma6.c | 306 ------------------------------------- board/tqc/tqma6/tqma6_bb.h | 29 ---- board/tqc/tqma6/tqma6_mba6.c | 193 ----------------------- board/tqc/tqma6/tqma6_wru4.c | 347 ------------------------------------------ board/tqc/tqma6/tqma6dl.cfg | 124 --------------- board/tqc/tqma6/tqma6q.cfg | 124 --------------- board/tqc/tqma6/tqma6s.cfg | 124 --------------- 25 files changed, 1419 insertions(+), 1419 deletions(-) create mode 100644 board/tq/tqma6/Kconfig create mode 100644 board/tq/tqma6/MAINTAINERS create mode 100644 board/tq/tqma6/Makefile create mode 100644 board/tq/tqma6/README create mode 100644 board/tq/tqma6/clocks.cfg create mode 100644 board/tq/tqma6/tqma6.c create mode 100644 board/tq/tqma6/tqma6_bb.h create mode 100644 board/tq/tqma6/tqma6_mba6.c create mode 100644 board/tq/tqma6/tqma6_wru4.c create mode 100644 board/tq/tqma6/tqma6dl.cfg create mode 100644 board/tq/tqma6/tqma6q.cfg create mode 100644 board/tq/tqma6/tqma6s.cfg delete mode 100644 board/tqc/tqma6/Kconfig delete mode 100644 board/tqc/tqma6/MAINTAINERS delete mode 100644 board/tqc/tqma6/Makefile delete mode 100644 board/tqc/tqma6/README delete mode 100644 board/tqc/tqma6/clocks.cfg delete mode 100644 board/tqc/tqma6/tqma6.c delete mode 100644 board/tqc/tqma6/tqma6_bb.h delete mode 100644 board/tqc/tqma6/tqma6_mba6.c delete mode 100644 board/tqc/tqma6/tqma6_wru4.c delete mode 100644 board/tqc/tqma6/tqma6dl.cfg delete mode 100644 board/tqc/tqma6/tqma6q.cfg delete mode 100644 board/tqc/tqma6/tqma6s.cfg diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index b4c8511cb8..d701a46cd6 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -688,7 +688,7 @@ source "board/somlabs/visionsom-6ull/Kconfig" source "board/technexion/pico-imx6/Kconfig" source "board/technexion/pico-imx6ul/Kconfig" source "board/tbs/tbs2910/Kconfig" -source "board/tqc/tqma6/Kconfig" +source "board/tq/tqma6/Kconfig" source "board/toradex/apalis_imx6/Kconfig" source "board/toradex/colibri_imx6/Kconfig" source "board/toradex/colibri-imx6ull/Kconfig" diff --git a/board/tq/tqma6/Kconfig b/board/tq/tqma6/Kconfig new file mode 100644 index 0000000000..cb1b8749ce --- /dev/null +++ b/board/tq/tqma6/Kconfig @@ -0,0 +1,96 @@ +if TARGET_TQMA6 + +config SYS_BOARD + default "tqma6" + +config SYS_VENDOR + default "tq" + +config SYS_CONFIG_NAME + default "tqma6" + +choice + prompt "TQMa6 SoC variant" + default TQMA6Q + help + select the TQMa6 module variant. The variants differing in the used + i.MX6 CPU type and DRAM + +config TQMA6Q + bool "TQMa6Q / TQMa6D" + depends on MX6Q + help + select TQMa6Q / TQMa6D with i.MX6Q/D and 1GiB DRAM + +config TQMA6DL + bool "TQMa6DL" + depends on MX6DL + help + select TQMa6DL with i.MX6DL and 1GiB DRAM + +config TQMA6S + bool "TQMa6S" + depends on MX6S + help + select TQMa6S with i.MX6S and 512 MiB DRAM + +endchoice + +choice + prompt "TQMa6 boot configuration" + default TQMA6X_MMC_BOOT + help + Configure boot device. This is also used to implement environment + location. + +config TQMA6X_MMC_BOOT + bool "MMC / SD Boot" + help + Boot from eMMC / SD Card + +config TQMA6X_SPI_BOOT + bool "SPI NOR Boot" + help + Boot from on board SPI NOR flash + +endchoice + +choice + prompt "TQMa6 base board variant" + default MBA6 + help + Select base board for TQMa6 + +config MBA6 + bool "TQMa6 on MBa6 Starterkit" + select DM_ETH + select USB + select CMD_USB + select USB_STORAGE + select USB_HOST_ETHER + select USB_ETHER_SMSC95XX + select PHYLIB + select PHY_MICREL + select PHY_MICREL_KSZ90X1 + select MXC_UART + help + Select the MBa6 starterkit. This features a GigE Phy, USB, SD-Card + etc. + +config WRU4 + bool "OHB WRU-IV" + help + Select the OHB Systems AG WRU-IV baseboard. + +endchoice + +config SYS_TEXT_BASE + default 0x2fc00000 if TQMA6S + default 0x4fc00000 if TQMA6Q || TQMA6DL + +config IMX_CONFIG + default "board/tq/tqma6/tqma6q.cfg" if TQMA6Q + default "board/tq/tqma6/tqma6dl.cfg" if TQMA6DL + default "board/tq/tqma6/tqma6s.cfg" if TQMA6S + +endif diff --git a/board/tq/tqma6/MAINTAINERS b/board/tq/tqma6/MAINTAINERS new file mode 100644 index 0000000000..dae719f00b --- /dev/null +++ b/board/tq/tqma6/MAINTAINERS @@ -0,0 +1,6 @@ +TQ SYSTEMS TQMA6 BOARD +M: Markus Niebel +S: Maintained +F: board/tq/tqma6/ +F: include/configs/tqma6.h +F: configs/tqma6*_defconfig diff --git a/board/tq/tqma6/Makefile b/board/tq/tqma6/Makefile new file mode 100644 index 0000000000..7271297c70 --- /dev/null +++ b/board/tq/tqma6/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2014, Markus Niebel + +obj-y := tqma6.o + +obj-$(CONFIG_MBA6) += tqma6_mba6.o +obj-$(CONFIG_WRU4) += tqma6_wru4.o diff --git a/board/tq/tqma6/README b/board/tq/tqma6/README new file mode 100644 index 0000000000..c47cb21eeb --- /dev/null +++ b/board/tq/tqma6/README @@ -0,0 +1,38 @@ +U-Boot for the TQ Systems TQMa6 modules + +This file contains information for the port of +U-Boot to the TQ Systems TQMa6 modules. + +1. Boot source +-------------- + +The following boot source is supported: + +- SD/eMMC +- SPI NOR + +2. Building +------------ + +To build U-Boot for the TQ Systems TQMa6 modules: + + make tqma6___config + make + +x is a placeholder for the CPU variant +q - means i.MX6Q/D: TQMa6Q (i.MX6Q) and TQMa6D (i.MX6D) +dl - means i.MX6DL: TQMa6DL (i.MX6DL) +s - means i.MX6S: TQMa6S (i.MX6S) + +baseboard is a placeholder for the boot device +mmc - means eMMC +spi - mean SPI NOR + +This gives the following configurations: + +tqma6q_mba6_mmc_config +tqma6q_mba6_spi_config +tqma6dl_mba6_mmc_config +tqma6dl_mba6_spi_config +tqma6s_mba6_mmc_config +tqma6s_mba6_spi_config diff --git a/board/tq/tqma6/clocks.cfg b/board/tq/tqma6/clocks.cfg new file mode 100644 index 0000000000..1f2001c75f --- /dev/null +++ b/board/tq/tqma6/clocks.cfg @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013, 2014 Markus Niebel + * + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure + * and create imximage boot image + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F diff --git a/board/tq/tqma6/tqma6.c b/board/tq/tqma6/tqma6.c new file mode 100644 index 0000000000..de9c00174a --- /dev/null +++ b/board/tq/tqma6/tqma6.c @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Author: Fabio Estevam + * + * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x) + * Author: Markus Niebel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tqma6_bb.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static const uint16_t tqma6_emmc_dsr = 0x0100; + +#ifndef CONFIG_DM_MMC +/* eMMC on USDHCI3 always present */ +static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = { + NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL), + /* eMMC reset */ + NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL), +}; + +/* + * According to board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 eMMC (SD3) on TQMa6 + * mmc1 .. n optional slots used on baseboard + */ +struct fsl_esdhc_cfg tqma6_usdhc_cfg = { + .esdhc_base = USDHC3_BASE_ADDR, + .max_bus_width = 8, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + /* eMMC/uSDHC3 is always present */ + ret = 1; + else + ret = tqma6_bb_board_mmc_getcd(mmc); + + return ret; +} + +int board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + /* eMMC/uSDHC3 is always present */ + ret = 0; + else + ret = tqma6_bb_board_mmc_getwp(mmc); + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads, + ARRAY_SIZE(tqma6_usdhc3_pads)); + tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) { + puts("Warning: failed to initialize eMMC dev\n"); + } else { + struct mmc *mmc = find_mmc_device(0); + if (mmc) + mmc_set_dsr(mmc, tqma6_emmc_dsr); + } + + tqma6_bb_board_mmc_init(bis); + + return 0; +} +#endif + +#ifndef CONFIG_DM_SPI +static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = { + /* SS1 */ + NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL), +}; + +#define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19) + +static unsigned const tqma6_ecspi1_cs[] = { + TQMA6_SF_CS_GPIO, +}; + +__weak void tqma6_iomuxc_spi(void) +{ + unsigned i; + + for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i) + gpio_direction_output(tqma6_ecspi1_cs[i], 1); + imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads, + ARRAY_SIZE(tqma6_ecspi1_pads)); +} + +#if defined(CONFIG_SF_DEFAULT_BUS) && defined(CONFIG_SF_DEFAULT_CS) +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return ((bus == CONFIG_SF_DEFAULT_BUS) && + (cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1; +} +#endif +#endif + +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) +static struct i2c_pads_info tqma6_i2c3_pads = { + /* I2C3: on board LM75, M24C64, */ + .scl = { + .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL, + I2C_PAD_CTRL), + .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05, + I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(1, 5) + }, + .sda = { + .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA, + I2C_PAD_CTRL), + .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, + I2C_PAD_CTRL), + .gp = IMX_GPIO_NR(1, 6) + } +}; + +static void tqma6_setup_i2c(void) +{ + int ret; + /* + * use logical index for bus, e.g. I2C1 -> 0 + * warn on error + */ + ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads); + if (ret) + printf("setup I2C3 failed: %d\n", ret); +} +#endif + +int board_early_init_f(void) +{ + return tqma6_bb_board_early_init_f(); +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifndef CONFIG_DM_SPI + tqma6_iomuxc_spi(); +#endif +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + tqma6_setup_i2c(); +#endif + + tqma6_bb_board_init(); + + return 0; +} + +static const char *tqma6_get_boardname(void) +{ + u32 cpurev = get_cpu_rev(); + + switch ((cpurev & 0xFF000) >> 12) { + case MXC_CPU_MX6SOLO: + return "TQMa6S"; + break; + case MXC_CPU_MX6DL: + return "TQMa6DL"; + break; + case MXC_CPU_MX6D: + return "TQMa6D"; + break; + case MXC_CPU_MX6Q: + return "TQMa6Q"; + break; + default: + return "??"; + }; +} + +#if CONFIG_IS_ENABLED(POWER_LEGACY) +/* setup board specific PMIC */ +int power_init_board(void) +{ + struct pmic *p; + u32 reg, rev; + + power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS); + p = pmic_get("PFUZE100"); + if (p && !pmic_probe(p)) { + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + pmic_reg_read(p, PFUZE100_REVID, &rev); + printf("PMIC: PFUZE100 ID=0x%02x REV=0x%02x\n", reg, rev); + } + + return 0; +} +#endif + +int board_late_init(void) +{ + env_set("board_name", tqma6_get_boardname()); + + tqma6_bb_board_late_init(); + + return 0; +} + +int checkboard(void) +{ + printf("Board: %s on a %s\n", tqma6_get_boardname(), + tqma6_bb_get_boardname()); + return 0; +} + +/* + * Device Tree Support + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +#define MODELSTRLEN 32u +int ft_board_setup(void *blob, struct bd_info *bd) +{ + char modelstr[MODELSTRLEN]; + + snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(), + tqma6_bb_get_boardname()); + do_fixup_by_path_string(blob, "/", "model", modelstr); + fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size); + /* bring in eMMC dsr settings */ + do_fixup_by_path_u32(blob, + "/soc/aips-bus@02100000/usdhc@02198000", + "dsr", tqma6_emmc_dsr, 2); + tqma6_bb_ft_board_setup(blob, bd); + + return 0; +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tq/tqma6/tqma6_bb.h b/board/tq/tqma6/tqma6_bb.h new file mode 100644 index 0000000000..b0f1f99a83 --- /dev/null +++ b/board/tq/tqma6/tqma6_bb.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013, 2014 TQ Systems + * Author: Markus Niebel + */ + +#ifndef __TQMA6_BB__ +#define __TQMA6_BB__ + +#include + +int tqma6_bb_board_mmc_getwp(struct mmc *mmc); +int tqma6_bb_board_mmc_getcd(struct mmc *mmc); +int tqma6_bb_board_mmc_init(struct bd_info *bis); + +int tqma6_bb_board_early_init_f(void); +int tqma6_bb_board_init(void); +int tqma6_bb_board_late_init(void); +int tqma6_bb_checkboard(void); + +const char *tqma6_bb_get_boardname(void); +/* + * Device Tree Support + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd); +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ + +#endif diff --git a/board/tq/tqma6/tqma6_mba6.c b/board/tq/tqma6/tqma6_mba6.c new file mode 100644 index 0000000000..801619e80b --- /dev/null +++ b/board/tq/tqma6/tqma6_mba6.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Author: Fabio Estevam + * + * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x) + * Author: Markus Niebel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tqma6_bb.h" + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#if defined(CONFIG_TQMA6Q) + +#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790 +#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac + +#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL) + +#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768 +#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788 + +#else + +#error "need to select module" + +#endif + +/* disable on die termination for RGMII */ +#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE 0x00000000 +/* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */ +#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V 0x00080000 +/* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */ +#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V 0x000C0000 + +static void mba6_setup_iomuxc_enet(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* clear gpr1[ENET_CLK_SEL] for externel clock */ + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); + + __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE, + (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM); + __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V, + (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII); +} + +static iomux_v3_cfg_t const mba6_uart2_pads[] = { + NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL), +}; + +static void mba6_setup_iomuxc_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads, + ARRAY_SIZE(mba6_uart2_pads)); +} + +int board_mmc_get_env_dev(int devno) +{ + /* + * This assumes that the baseboard registered + * the boot device first ... + * Note: SDHC3 == idx2 + */ + return (2 == devno) ? 0 : 1; +} + +int board_phy_config(struct phy_device *phydev) +{ +/* + * optimized pad skew values depends on CPU variant on the TQMa6x module: + * CONFIG_TQMA6Q: i.MX6Q/D + * CONFIG_TQMA6S: i.MX6S + * CONFIG_TQMA6DL: i.MX6DL + */ +#if defined(CONFIG_TQMA6Q) +#define MBA6X_KSZ9031_CTRL_SKEW 0x0032 +#define MBA6X_KSZ9031_CLK_SKEW 0x03ff +#define MBA6X_KSZ9031_RX_SKEW 0x3333 +#define MBA6X_KSZ9031_TX_SKEW 0x2036 +#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL) +#define MBA6X_KSZ9031_CTRL_SKEW 0x0030 +#define MBA6X_KSZ9031_CLK_SKEW 0x03ff +#define MBA6X_KSZ9031_RX_SKEW 0x3333 +#define MBA6X_KSZ9031_TX_SKEW 0x2052 +#else +#error +#endif + /* min rx/tx ctrl delay */ + ksz9031_phy_extended_write(phydev, 2, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + MBA6X_KSZ9031_CTRL_SKEW); + /* min rx delay */ + ksz9031_phy_extended_write(phydev, 2, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + MBA6X_KSZ9031_RX_SKEW); + /* max tx delay */ + ksz9031_phy_extended_write(phydev, 2, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + MBA6X_KSZ9031_TX_SKEW); + /* rx/tx clk skew */ + ksz9031_phy_extended_write(phydev, 2, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + MBA6X_KSZ9031_CLK_SKEW); + + phydev->drv->config(phydev); + + return 0; +} + +int tqma6_bb_board_early_init_f(void) +{ + mba6_setup_iomuxc_uart(); + + return 0; +} + +int tqma6_bb_board_init(void) +{ + mba6_setup_iomuxc_enet(); + + return 0; +} + +int tqma6_bb_board_late_init(void) +{ + return 0; +} + +const char *tqma6_bb_get_boardname(void) +{ + return "MBa6x"; +} + +/* + * Device Tree Support + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd) +{ + /* TBD */ +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tq/tqma6/tqma6_wru4.c b/board/tq/tqma6/tqma6_wru4.c new file mode 100644 index 0000000000..3b1bc603ce --- /dev/null +++ b/board/tq/tqma6/tqma6_wru4.c @@ -0,0 +1,347 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Author: Fabio Estevam + * + * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x) + * Author: Markus Niebel + * + * Copyright (C) 2015 Stefan Roese + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tqma6_bb.h" + +/* UART */ +#define UART4_PAD_CTRL ( \ + PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_UP | \ + PAD_CTL_PUE | \ + PAD_CTL_PKE | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_SLOW \ + ) + +static iomux_v3_cfg_t const uart4_pads[] = { + NEW_PAD_CTRL(MX6_PAD_CSI0_DAT17__UART4_CTS_B, UART4_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_CSI0_DAT16__UART4_RTS_B, UART4_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_CSI0_DAT13__UART4_RX_DATA, UART4_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_CSI0_DAT12__UART4_TX_DATA, UART4_PAD_CTRL), +}; + +static void setup_iomuxc_uart4(void) +{ + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); +} + +/* MMC */ +#define USDHC2_PAD_CTRL ( \ + PAD_CTL_HYS | \ + PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST \ + ) + +#define USDHC2_CLK_PAD_CTRL ( \ + PAD_CTL_HYS | \ + PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST \ + ) + +static iomux_v3_cfg_t const usdhc2_pads[] = { + NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC2_CLK_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC2_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC2_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC2_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC2_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC2_PAD_CTRL), + + NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, USDHC2_PAD_CTRL), /* CD */ + NEW_PAD_CTRL(MX6_PAD_GPIO_2__SD2_WP, USDHC2_PAD_CTRL), /* WP */ +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) +#define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2) + +static struct fsl_esdhc_cfg usdhc2_cfg = { + .esdhc_base = USDHC2_BASE_ADDR, + .max_bus_width = 4, +}; + +int tqma6_bb_board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC2_BASE_ADDR) + ret = !gpio_get_value(USDHC2_CD_GPIO); + + return ret; +} + +int tqma6_bb_board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC2_BASE_ADDR) + ret = gpio_get_value(USDHC2_WP_GPIO); + + return ret; +} + +int tqma6_bb_board_mmc_init(struct bd_info *bis) +{ + int ret; + + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + + ret = gpio_request(USDHC2_CD_GPIO, "mmc-cd"); + if (!ret) + gpio_direction_input(USDHC2_CD_GPIO); + ret = gpio_request(USDHC2_WP_GPIO, "mmc-wp"); + if (!ret) + gpio_direction_input(USDHC2_WP_GPIO); + + usdhc2_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + if(fsl_esdhc_initialize(bis, &usdhc2_cfg)) + puts("WARNING: failed to initialize SD\n"); + + return 0; +} + +/* Ethernet */ +#define ENET_PAD_CTRL ( \ + PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_UP | \ + PAD_CTL_PUE | \ + PAD_CTL_PKE | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_SLOW \ + ) + +static iomux_v3_cfg_t const enet_pads[] = { + NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_RXD0__ENET_RX_DATA0, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_RXD1__ENET_RX_DATA1, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__ENET_RX_EN, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_RX_ER__ENET_RX_ER, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_TXD0__ENET_TX_DATA0, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_TXD1__ENET_TX_DATA1, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_ENET_TX_EN__ENET_TX_EN, ENET_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_GPIO_19__ENET_TX_ER, ENET_PAD_CTRL), + + /* ENET1 reset */ + NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, ENET_PAD_CTRL), + /* ENET1 interrupt */ + NEW_PAD_CTRL(MX6_PAD_GPIO_9__GPIO1_IO09, ENET_PAD_CTRL), +}; + +#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 8) + +static void setup_iomuxc_enet(void) +{ + int ret; + + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + /* Reset LAN8720 PHY */ + ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset"); + if (!ret) + gpio_direction_output(ENET_PHY_RESET_GPIO , 0); + udelay(25000); + gpio_set_value(ENET_PHY_RESET_GPIO, 1); +} + +int board_eth_init(struct bd_info *bis) +{ + return cpu_eth_init(bis); +} + +/* GPIO */ +#define GPIO_PAD_CTRL ( \ + PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_UP | \ + PAD_CTL_PUE | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_SLOW \ + ) + +#define GPIO_OD_PAD_CTRL ( \ + PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_UP | \ + PAD_CTL_PUE | \ + PAD_CTL_ODE | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_SLOW \ + ) + +static iomux_v3_cfg_t const gpio_pads[] = { + /* USB_H_PWR */ + NEW_PAD_CTRL(MX6_PAD_GPIO_0__GPIO1_IO00, GPIO_PAD_CTRL), + /* USB_OTG_PWR */ + NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL), + /* PCIE_RST */ + NEW_PAD_CTRL(MX6_PAD_NANDF_CLE__GPIO6_IO07, GPIO_OD_PAD_CTRL), + /* UART1_PWRON */ + NEW_PAD_CTRL(MX6_PAD_DISP0_DAT14__GPIO5_IO08, GPIO_PAD_CTRL), + /* UART2_PWRON */ + NEW_PAD_CTRL(MX6_PAD_DISP0_DAT16__GPIO5_IO10, GPIO_PAD_CTRL), + /* UART3_PWRON */ + NEW_PAD_CTRL(MX6_PAD_DISP0_DAT18__GPIO5_IO12, GPIO_PAD_CTRL), +}; + +#define GPIO_USB_H_PWR IMX_GPIO_NR(1, 0) +#define GPIO_USB_OTG_PWR IMX_GPIO_NR(3, 22) +#define GPIO_PCIE_RST IMX_GPIO_NR(6, 7) +#define GPIO_UART1_PWRON IMX_GPIO_NR(5, 8) +#define GPIO_UART2_PWRON IMX_GPIO_NR(5, 10) +#define GPIO_UART3_PWRON IMX_GPIO_NR(5, 12) + +static void gpio_init(void) +{ + int ret; + + imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); + + ret = gpio_request(GPIO_USB_H_PWR, "usb-h-pwr"); + if (!ret) + gpio_direction_output(GPIO_USB_H_PWR, 1); + ret = gpio_request(GPIO_USB_OTG_PWR, "usb-otg-pwr"); + if (!ret) + gpio_direction_output(GPIO_USB_OTG_PWR, 1); + ret = gpio_request(GPIO_PCIE_RST, "pcie-reset"); + if (!ret) + gpio_direction_output(GPIO_PCIE_RST, 1); + ret = gpio_request(GPIO_UART1_PWRON, "uart1-pwr"); + if (!ret) + gpio_direction_output(GPIO_UART1_PWRON, 0); + ret = gpio_request(GPIO_UART2_PWRON, "uart2-pwr"); + if (!ret) + gpio_direction_output(GPIO_UART2_PWRON, 0); + ret = gpio_request(GPIO_UART3_PWRON, "uart3-pwr"); + if (!ret) + gpio_direction_output(GPIO_UART3_PWRON, 0); +} + +void tqma6_iomuxc_spi(void) +{ + /* No SPI on this baseboard */ +} + +int tqma6_bb_board_early_init_f(void) +{ + setup_iomuxc_uart4(); + + return 0; +} + +int tqma6_bb_board_init(void) +{ + setup_iomuxc_enet(); + + gpio_init(); + + /* Turn the UART-couplers on one-after-another */ + gpio_set_value(GPIO_UART1_PWRON, 1); + mdelay(10); + gpio_set_value(GPIO_UART2_PWRON, 1); + mdelay(10); + gpio_set_value(GPIO_UART3_PWRON, 1); + + return 0; +} + +int tqma6_bb_board_late_init(void) +{ + return 0; +} + +const char *tqma6_bb_get_boardname(void) +{ + return "WRU-IV"; +} + +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + /* 8 bit bus width */ + {"emmc", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + { NULL, 0 }, +}; + +int misc_init_r(void) +{ + add_board_boot_modes(board_boot_modes); + + return 0; +} + +#define WRU4_USB_H1_PWR IMX_GPIO_NR(1, 0) +#define WRU4_USB_OTG_PWR IMX_GPIO_NR(3, 22) + +int board_ehci_hcd_init(int port) +{ + int ret; + + ret = gpio_request(WRU4_USB_H1_PWR, "usb-h1-pwr"); + if (!ret) + gpio_direction_output(WRU4_USB_H1_PWR, 1); + + ret = gpio_request(WRU4_USB_OTG_PWR, "usb-OTG-pwr"); + if (!ret) + gpio_direction_output(WRU4_USB_OTG_PWR, 1); + + return 0; +} + +int board_ehci_power(int port, int on) +{ + if (port) + gpio_set_value(WRU4_USB_OTG_PWR, on); + else + gpio_set_value(WRU4_USB_H1_PWR, on); + + return 0; +} + +/* + * Device Tree Support + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd) +{ + /* TBD */ +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tq/tqma6/tqma6dl.cfg b/board/tq/tqma6/tqma6dl.cfg new file mode 100644 index 0000000000..80c7150316 --- /dev/null +++ b/board/tq/tqma6/tqma6dl.cfg @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 - 2015 Markus Niebel + * + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +#define __ASSEMBLY__ +#include + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +#if defined(CONFIG_TQMA6X_MMC_BOOT) +BOOT_FROM sd +#elif defined(CONFIG_TQMA6X_SPI_BOOT) +BOOT_FROM spi +#endif + +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +/* TQMa6DL DDR config Rev. 0100E */ +/* IOMUX configuration */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 +DATA 4, MX6_IOM_DRAM_CAS, 0x00008030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00008030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 + +/* memory interface calibration values */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00440048 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x003D003F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0029002D +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x002B0043 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x424C0250 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02300234 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4234023C +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0224022C +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x48484C4C +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4C4E4E4C +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36382C36 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x34343630 +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 + +/* configure memory interface */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00408032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D +DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + +#include "clocks.cfg" diff --git a/board/tq/tqma6/tqma6q.cfg b/board/tq/tqma6/tqma6q.cfg new file mode 100644 index 0000000000..82a0a271d4 --- /dev/null +++ b/board/tq/tqma6/tqma6q.cfg @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013, 2014 Markus Niebel + * + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +#define __ASSEMBLY__ +#include + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +#if defined(CONFIG_TQMA6X_MMC_BOOT) +BOOT_FROM sd +#elif defined(CONFIG_TQMA6X_SPI_BOOT) +BOOT_FROM spi +#endif + +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +/* TQMa6Q/D DDR config Rev. 0100B */ +/* IOMUX configuration */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 +DATA 4, MX6_IOM_DRAM_CAS, 0x00008030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00008030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 + +/* memory interface calibration values */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001B0013 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018001B +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001B0016 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012001C +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43400350 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x023E032C +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43400348 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03300304 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x3C323436 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38383242 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3E3C4440 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4236483E +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 + +/* configure memory interface */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x545A79B4 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09308030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025536 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + +#include "clocks.cfg" diff --git a/board/tq/tqma6/tqma6s.cfg b/board/tq/tqma6/tqma6s.cfg new file mode 100644 index 0000000000..9cdbb3c767 --- /dev/null +++ b/board/tq/tqma6/tqma6s.cfg @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013, 2014 Markus Niebel + * + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +#define __ASSEMBLY__ +#include + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +#if defined(CONFIG_TQMA6X_MMC_BOOT) +BOOT_FROM sd +#elif defined(CONFIG_TQMA6X_SPI_BOOT) +BOOT_FROM spi +#endif + +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +/* TQMa6S DDR config Rev. 0100B */ +/* IOMUX configuration */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008000 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 +DATA 4, MX6_IOM_DRAM_CAS, 0x00008030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00008030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000000 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000000 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000000 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000 + +/* memory interface calibration values */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380000 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0014000E +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00120014 +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00000000 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00000000 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x0240023C +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0228022C +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x00000000 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x00000000 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4A4A4E4A +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x00000000 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36362A32 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x00000000 +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x00000000 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x00000000 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x00000000 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x00000000 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000000 + +/* configure memory interface */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 +DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D +DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + +#include "clocks.cfg" diff --git a/board/tqc/tqma6/Kconfig b/board/tqc/tqma6/Kconfig deleted file mode 100644 index a2a5905290..0000000000 --- a/board/tqc/tqma6/Kconfig +++ /dev/null @@ -1,96 +0,0 @@ -if TARGET_TQMA6 - -config SYS_BOARD - default "tqma6" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "tqma6" - -choice - prompt "TQMa6 SoC variant" - default TQMA6Q - help - select the TQMa6 module variant. The variants differing in the used - i.MX6 CPU type and DRAM - -config TQMA6Q - bool "TQMa6Q / TQMa6D" - depends on MX6Q - help - select TQMa6Q / TQMa6D with i.MX6Q/D and 1GiB DRAM - -config TQMA6DL - bool "TQMa6DL" - depends on MX6DL - help - select TQMa6DL with i.MX6DL and 1GiB DRAM - -config TQMA6S - bool "TQMa6S" - depends on MX6S - help - select TQMa6S with i.MX6S and 512 MiB DRAM - -endchoice - -choice - prompt "TQMa6 boot configuration" - default TQMA6X_MMC_BOOT - help - Configure boot device. This is also used to implement environment - location. - -config TQMA6X_MMC_BOOT - bool "MMC / SD Boot" - help - Boot from eMMC / SD Card - -config TQMA6X_SPI_BOOT - bool "SPI NOR Boot" - help - Boot from on board SPI NOR flash - -endchoice - -choice - prompt "TQMa6 base board variant" - default MBA6 - help - Select base board for TQMa6 - -config MBA6 - bool "TQMa6 on MBa6 Starterkit" - select DM_ETH - select USB - select CMD_USB - select USB_STORAGE - select USB_HOST_ETHER - select USB_ETHER_SMSC95XX - select PHYLIB - select PHY_MICREL - select PHY_MICREL_KSZ90X1 - select MXC_UART - help - Select the MBa6 starterkit. This features a GigE Phy, USB, SD-Card - etc. - -config WRU4 - bool "OHB WRU-IV" - help - Select the OHB Systems AG WRU-IV baseboard. - -endchoice - -config SYS_TEXT_BASE - default 0x2fc00000 if TQMA6S - default 0x4fc00000 if TQMA6Q || TQMA6DL - -config IMX_CONFIG - default "board/tqc/tqma6/tqma6q.cfg" if TQMA6Q - default "board/tqc/tqma6/tqma6dl.cfg" if TQMA6DL - default "board/tqc/tqma6/tqma6s.cfg" if TQMA6S - -endif diff --git a/board/tqc/tqma6/MAINTAINERS b/board/tqc/tqma6/MAINTAINERS deleted file mode 100644 index 91cd244499..0000000000 --- a/board/tqc/tqma6/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TQ SYSTEMS TQMA6 BOARD -M: Markus Niebel -S: Maintained -F: board/tqc/tqma6/ -F: include/configs/tqma6.h -F: configs/tqma6*_defconfig diff --git a/board/tqc/tqma6/Makefile b/board/tqc/tqma6/Makefile deleted file mode 100644 index 7271297c70..0000000000 --- a/board/tqc/tqma6/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2014, Markus Niebel - -obj-y := tqma6.o - -obj-$(CONFIG_MBA6) += tqma6_mba6.o -obj-$(CONFIG_WRU4) += tqma6_wru4.o diff --git a/board/tqc/tqma6/README b/board/tqc/tqma6/README deleted file mode 100644 index c47cb21eeb..0000000000 --- a/board/tqc/tqma6/README +++ /dev/null @@ -1,38 +0,0 @@ -U-Boot for the TQ Systems TQMa6 modules - -This file contains information for the port of -U-Boot to the TQ Systems TQMa6 modules. - -1. Boot source --------------- - -The following boot source is supported: - -- SD/eMMC -- SPI NOR - -2. Building ------------- - -To build U-Boot for the TQ Systems TQMa6 modules: - - make tqma6___config - make - -x is a placeholder for the CPU variant -q - means i.MX6Q/D: TQMa6Q (i.MX6Q) and TQMa6D (i.MX6D) -dl - means i.MX6DL: TQMa6DL (i.MX6DL) -s - means i.MX6S: TQMa6S (i.MX6S) - -baseboard is a placeholder for the boot device -mmc - means eMMC -spi - mean SPI NOR - -This gives the following configurations: - -tqma6q_mba6_mmc_config -tqma6q_mba6_spi_config -tqma6dl_mba6_mmc_config -tqma6dl_mba6_spi_config -tqma6s_mba6_mmc_config -tqma6s_mba6_spi_config diff --git a/board/tqc/tqma6/clocks.cfg b/board/tqc/tqma6/clocks.cfg deleted file mode 100644 index 1f2001c75f..0000000000 --- a/board/tqc/tqma6/clocks.cfg +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013, 2014 Markus Niebel - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - */ - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0x00FFF300 -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c deleted file mode 100644 index de9c00174a..0000000000 --- a/board/tqc/tqma6/tqma6.c +++ /dev/null @@ -1,306 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * Author: Fabio Estevam - * - * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x) - * Author: Markus Niebel - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "tqma6_bb.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -static const uint16_t tqma6_emmc_dsr = 0x0100; - -#ifndef CONFIG_DM_MMC -/* eMMC on USDHCI3 always present */ -static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = { - NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL), - /* eMMC reset */ - NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL), -}; - -/* - * According to board_mmc_init() the following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 eMMC (SD3) on TQMa6 - * mmc1 .. n optional slots used on baseboard - */ -struct fsl_esdhc_cfg tqma6_usdhc_cfg = { - .esdhc_base = USDHC3_BASE_ADDR, - .max_bus_width = 8, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - if (cfg->esdhc_base == USDHC3_BASE_ADDR) - /* eMMC/uSDHC3 is always present */ - ret = 1; - else - ret = tqma6_bb_board_mmc_getcd(mmc); - - return ret; -} - -int board_mmc_getwp(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - if (cfg->esdhc_base == USDHC3_BASE_ADDR) - /* eMMC/uSDHC3 is always present */ - ret = 0; - else - ret = tqma6_bb_board_mmc_getwp(mmc); - - return ret; -} - -int board_mmc_init(struct bd_info *bis) -{ - imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads, - ARRAY_SIZE(tqma6_usdhc3_pads)); - tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) { - puts("Warning: failed to initialize eMMC dev\n"); - } else { - struct mmc *mmc = find_mmc_device(0); - if (mmc) - mmc_set_dsr(mmc, tqma6_emmc_dsr); - } - - tqma6_bb_board_mmc_init(bis); - - return 0; -} -#endif - -#ifndef CONFIG_DM_SPI -static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = { - /* SS1 */ - NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL), -}; - -#define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19) - -static unsigned const tqma6_ecspi1_cs[] = { - TQMA6_SF_CS_GPIO, -}; - -__weak void tqma6_iomuxc_spi(void) -{ - unsigned i; - - for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i) - gpio_direction_output(tqma6_ecspi1_cs[i], 1); - imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads, - ARRAY_SIZE(tqma6_ecspi1_pads)); -} - -#if defined(CONFIG_SF_DEFAULT_BUS) && defined(CONFIG_SF_DEFAULT_CS) -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return ((bus == CONFIG_SF_DEFAULT_BUS) && - (cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1; -} -#endif -#endif - -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) -static struct i2c_pads_info tqma6_i2c3_pads = { - /* I2C3: on board LM75, M24C64, */ - .scl = { - .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL, - I2C_PAD_CTRL), - .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05, - I2C_PAD_CTRL), - .gp = IMX_GPIO_NR(1, 5) - }, - .sda = { - .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA, - I2C_PAD_CTRL), - .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, - I2C_PAD_CTRL), - .gp = IMX_GPIO_NR(1, 6) - } -}; - -static void tqma6_setup_i2c(void) -{ - int ret; - /* - * use logical index for bus, e.g. I2C1 -> 0 - * warn on error - */ - ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads); - if (ret) - printf("setup I2C3 failed: %d\n", ret); -} -#endif - -int board_early_init_f(void) -{ - return tqma6_bb_board_early_init_f(); -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - -#ifndef CONFIG_DM_SPI - tqma6_iomuxc_spi(); -#endif -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) - tqma6_setup_i2c(); -#endif - - tqma6_bb_board_init(); - - return 0; -} - -static const char *tqma6_get_boardname(void) -{ - u32 cpurev = get_cpu_rev(); - - switch ((cpurev & 0xFF000) >> 12) { - case MXC_CPU_MX6SOLO: - return "TQMa6S"; - break; - case MXC_CPU_MX6DL: - return "TQMa6DL"; - break; - case MXC_CPU_MX6D: - return "TQMa6D"; - break; - case MXC_CPU_MX6Q: - return "TQMa6Q"; - break; - default: - return "??"; - }; -} - -#if CONFIG_IS_ENABLED(POWER_LEGACY) -/* setup board specific PMIC */ -int power_init_board(void) -{ - struct pmic *p; - u32 reg, rev; - - power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS); - p = pmic_get("PFUZE100"); - if (p && !pmic_probe(p)) { - pmic_reg_read(p, PFUZE100_DEVICEID, ®); - pmic_reg_read(p, PFUZE100_REVID, &rev); - printf("PMIC: PFUZE100 ID=0x%02x REV=0x%02x\n", reg, rev); - } - - return 0; -} -#endif - -int board_late_init(void) -{ - env_set("board_name", tqma6_get_boardname()); - - tqma6_bb_board_late_init(); - - return 0; -} - -int checkboard(void) -{ - printf("Board: %s on a %s\n", tqma6_get_boardname(), - tqma6_bb_get_boardname()); - return 0; -} - -/* - * Device Tree Support - */ -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -#define MODELSTRLEN 32u -int ft_board_setup(void *blob, struct bd_info *bd) -{ - char modelstr[MODELSTRLEN]; - - snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(), - tqma6_bb_get_boardname()); - do_fixup_by_path_string(blob, "/", "model", modelstr); - fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size); - /* bring in eMMC dsr settings */ - do_fixup_by_path_u32(blob, - "/soc/aips-bus@02100000/usdhc@02198000", - "dsr", tqma6_emmc_dsr, 2); - tqma6_bb_ft_board_setup(blob, bd); - - return 0; -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tqc/tqma6/tqma6_bb.h b/board/tqc/tqma6/tqma6_bb.h deleted file mode 100644 index b0f1f99a83..0000000000 --- a/board/tqc/tqma6/tqma6_bb.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013, 2014 TQ Systems - * Author: Markus Niebel - */ - -#ifndef __TQMA6_BB__ -#define __TQMA6_BB__ - -#include - -int tqma6_bb_board_mmc_getwp(struct mmc *mmc); -int tqma6_bb_board_mmc_getcd(struct mmc *mmc); -int tqma6_bb_board_mmc_init(struct bd_info *bis); - -int tqma6_bb_board_early_init_f(void); -int tqma6_bb_board_init(void); -int tqma6_bb_board_late_init(void); -int tqma6_bb_checkboard(void); - -const char *tqma6_bb_get_boardname(void); -/* - * Device Tree Support - */ -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd); -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ - -#endif diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c deleted file mode 100644 index 801619e80b..0000000000 --- a/board/tqc/tqma6/tqma6_mba6.c +++ /dev/null @@ -1,193 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * Author: Fabio Estevam - * - * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x) - * Author: Markus Niebel - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "tqma6_bb.h" - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#if defined(CONFIG_TQMA6Q) - -#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790 -#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac - -#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL) - -#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768 -#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788 - -#else - -#error "need to select module" - -#endif - -/* disable on die termination for RGMII */ -#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE 0x00000000 -/* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */ -#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V 0x00080000 -/* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */ -#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V 0x000C0000 - -static void mba6_setup_iomuxc_enet(void) -{ - struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* clear gpr1[ENET_CLK_SEL] for externel clock */ - clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); - - __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE, - (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM); - __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V, - (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII); -} - -static iomux_v3_cfg_t const mba6_uart2_pads[] = { - NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL), -}; - -static void mba6_setup_iomuxc_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads, - ARRAY_SIZE(mba6_uart2_pads)); -} - -int board_mmc_get_env_dev(int devno) -{ - /* - * This assumes that the baseboard registered - * the boot device first ... - * Note: SDHC3 == idx2 - */ - return (2 == devno) ? 0 : 1; -} - -int board_phy_config(struct phy_device *phydev) -{ -/* - * optimized pad skew values depends on CPU variant on the TQMa6x module: - * CONFIG_TQMA6Q: i.MX6Q/D - * CONFIG_TQMA6S: i.MX6S - * CONFIG_TQMA6DL: i.MX6DL - */ -#if defined(CONFIG_TQMA6Q) -#define MBA6X_KSZ9031_CTRL_SKEW 0x0032 -#define MBA6X_KSZ9031_CLK_SKEW 0x03ff -#define MBA6X_KSZ9031_RX_SKEW 0x3333 -#define MBA6X_KSZ9031_TX_SKEW 0x2036 -#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL) -#define MBA6X_KSZ9031_CTRL_SKEW 0x0030 -#define MBA6X_KSZ9031_CLK_SKEW 0x03ff -#define MBA6X_KSZ9031_RX_SKEW 0x3333 -#define MBA6X_KSZ9031_TX_SKEW 0x2052 -#else -#error -#endif - /* min rx/tx ctrl delay */ - ksz9031_phy_extended_write(phydev, 2, - MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, - MBA6X_KSZ9031_CTRL_SKEW); - /* min rx delay */ - ksz9031_phy_extended_write(phydev, 2, - MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, - MBA6X_KSZ9031_RX_SKEW); - /* max tx delay */ - ksz9031_phy_extended_write(phydev, 2, - MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, - MBA6X_KSZ9031_TX_SKEW); - /* rx/tx clk skew */ - ksz9031_phy_extended_write(phydev, 2, - MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, - MBA6X_KSZ9031_CLK_SKEW); - - phydev->drv->config(phydev); - - return 0; -} - -int tqma6_bb_board_early_init_f(void) -{ - mba6_setup_iomuxc_uart(); - - return 0; -} - -int tqma6_bb_board_init(void) -{ - mba6_setup_iomuxc_enet(); - - return 0; -} - -int tqma6_bb_board_late_init(void) -{ - return 0; -} - -const char *tqma6_bb_get_boardname(void) -{ - return "MBa6x"; -} - -/* - * Device Tree Support - */ -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd) -{ - /* TBD */ -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tqc/tqma6/tqma6_wru4.c b/board/tqc/tqma6/tqma6_wru4.c deleted file mode 100644 index 3b1bc603ce..0000000000 --- a/board/tqc/tqma6/tqma6_wru4.c +++ /dev/null @@ -1,347 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * Author: Fabio Estevam - * - * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x) - * Author: Markus Niebel - * - * Copyright (C) 2015 Stefan Roese - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "tqma6_bb.h" - -/* UART */ -#define UART4_PAD_CTRL ( \ - PAD_CTL_HYS | \ - PAD_CTL_PUS_100K_UP | \ - PAD_CTL_PUE | \ - PAD_CTL_PKE | \ - PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_SLOW \ - ) - -static iomux_v3_cfg_t const uart4_pads[] = { - NEW_PAD_CTRL(MX6_PAD_CSI0_DAT17__UART4_CTS_B, UART4_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_CSI0_DAT16__UART4_RTS_B, UART4_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_CSI0_DAT13__UART4_RX_DATA, UART4_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_CSI0_DAT12__UART4_TX_DATA, UART4_PAD_CTRL), -}; - -static void setup_iomuxc_uart4(void) -{ - imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); -} - -/* MMC */ -#define USDHC2_PAD_CTRL ( \ - PAD_CTL_HYS | \ - PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST \ - ) - -#define USDHC2_CLK_PAD_CTRL ( \ - PAD_CTL_HYS | \ - PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST \ - ) - -static iomux_v3_cfg_t const usdhc2_pads[] = { - NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC2_CLK_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC2_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC2_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC2_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC2_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC2_PAD_CTRL), - - NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, USDHC2_PAD_CTRL), /* CD */ - NEW_PAD_CTRL(MX6_PAD_GPIO_2__SD2_WP, USDHC2_PAD_CTRL), /* WP */ -}; - -#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) -#define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2) - -static struct fsl_esdhc_cfg usdhc2_cfg = { - .esdhc_base = USDHC2_BASE_ADDR, - .max_bus_width = 4, -}; - -int tqma6_bb_board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - if (cfg->esdhc_base == USDHC2_BASE_ADDR) - ret = !gpio_get_value(USDHC2_CD_GPIO); - - return ret; -} - -int tqma6_bb_board_mmc_getwp(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - if (cfg->esdhc_base == USDHC2_BASE_ADDR) - ret = gpio_get_value(USDHC2_WP_GPIO); - - return ret; -} - -int tqma6_bb_board_mmc_init(struct bd_info *bis) -{ - int ret; - - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - - ret = gpio_request(USDHC2_CD_GPIO, "mmc-cd"); - if (!ret) - gpio_direction_input(USDHC2_CD_GPIO); - ret = gpio_request(USDHC2_WP_GPIO, "mmc-wp"); - if (!ret) - gpio_direction_input(USDHC2_WP_GPIO); - - usdhc2_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - if(fsl_esdhc_initialize(bis, &usdhc2_cfg)) - puts("WARNING: failed to initialize SD\n"); - - return 0; -} - -/* Ethernet */ -#define ENET_PAD_CTRL ( \ - PAD_CTL_HYS | \ - PAD_CTL_PUS_100K_UP | \ - PAD_CTL_PUE | \ - PAD_CTL_PKE | \ - PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_SLOW \ - ) - -static iomux_v3_cfg_t const enet_pads[] = { - NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_ENET_RXD0__ENET_RX_DATA0, ENET_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_ENET_RXD1__ENET_RX_DATA1, ENET_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__ENET_RX_EN, ENET_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_ENET_RX_ER__ENET_RX_ER, ENET_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_ENET_TXD0__ENET_TX_DATA0, ENET_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_ENET_TXD1__ENET_TX_DATA1, ENET_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_ENET_TX_EN__ENET_TX_EN, ENET_PAD_CTRL), - NEW_PAD_CTRL(MX6_PAD_GPIO_19__ENET_TX_ER, ENET_PAD_CTRL), - - /* ENET1 reset */ - NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, ENET_PAD_CTRL), - /* ENET1 interrupt */ - NEW_PAD_CTRL(MX6_PAD_GPIO_9__GPIO1_IO09, ENET_PAD_CTRL), -}; - -#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 8) - -static void setup_iomuxc_enet(void) -{ - int ret; - - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); - - /* Reset LAN8720 PHY */ - ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset"); - if (!ret) - gpio_direction_output(ENET_PHY_RESET_GPIO , 0); - udelay(25000); - gpio_set_value(ENET_PHY_RESET_GPIO, 1); -} - -int board_eth_init(struct bd_info *bis) -{ - return cpu_eth_init(bis); -} - -/* GPIO */ -#define GPIO_PAD_CTRL ( \ - PAD_CTL_HYS | \ - PAD_CTL_PUS_100K_UP | \ - PAD_CTL_PUE | \ - PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_SLOW \ - ) - -#define GPIO_OD_PAD_CTRL ( \ - PAD_CTL_HYS | \ - PAD_CTL_PUS_100K_UP | \ - PAD_CTL_PUE | \ - PAD_CTL_ODE | \ - PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_SLOW \ - ) - -static iomux_v3_cfg_t const gpio_pads[] = { - /* USB_H_PWR */ - NEW_PAD_CTRL(MX6_PAD_GPIO_0__GPIO1_IO00, GPIO_PAD_CTRL), - /* USB_OTG_PWR */ - NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL), - /* PCIE_RST */ - NEW_PAD_CTRL(MX6_PAD_NANDF_CLE__GPIO6_IO07, GPIO_OD_PAD_CTRL), - /* UART1_PWRON */ - NEW_PAD_CTRL(MX6_PAD_DISP0_DAT14__GPIO5_IO08, GPIO_PAD_CTRL), - /* UART2_PWRON */ - NEW_PAD_CTRL(MX6_PAD_DISP0_DAT16__GPIO5_IO10, GPIO_PAD_CTRL), - /* UART3_PWRON */ - NEW_PAD_CTRL(MX6_PAD_DISP0_DAT18__GPIO5_IO12, GPIO_PAD_CTRL), -}; - -#define GPIO_USB_H_PWR IMX_GPIO_NR(1, 0) -#define GPIO_USB_OTG_PWR IMX_GPIO_NR(3, 22) -#define GPIO_PCIE_RST IMX_GPIO_NR(6, 7) -#define GPIO_UART1_PWRON IMX_GPIO_NR(5, 8) -#define GPIO_UART2_PWRON IMX_GPIO_NR(5, 10) -#define GPIO_UART3_PWRON IMX_GPIO_NR(5, 12) - -static void gpio_init(void) -{ - int ret; - - imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); - - ret = gpio_request(GPIO_USB_H_PWR, "usb-h-pwr"); - if (!ret) - gpio_direction_output(GPIO_USB_H_PWR, 1); - ret = gpio_request(GPIO_USB_OTG_PWR, "usb-otg-pwr"); - if (!ret) - gpio_direction_output(GPIO_USB_OTG_PWR, 1); - ret = gpio_request(GPIO_PCIE_RST, "pcie-reset"); - if (!ret) - gpio_direction_output(GPIO_PCIE_RST, 1); - ret = gpio_request(GPIO_UART1_PWRON, "uart1-pwr"); - if (!ret) - gpio_direction_output(GPIO_UART1_PWRON, 0); - ret = gpio_request(GPIO_UART2_PWRON, "uart2-pwr"); - if (!ret) - gpio_direction_output(GPIO_UART2_PWRON, 0); - ret = gpio_request(GPIO_UART3_PWRON, "uart3-pwr"); - if (!ret) - gpio_direction_output(GPIO_UART3_PWRON, 0); -} - -void tqma6_iomuxc_spi(void) -{ - /* No SPI on this baseboard */ -} - -int tqma6_bb_board_early_init_f(void) -{ - setup_iomuxc_uart4(); - - return 0; -} - -int tqma6_bb_board_init(void) -{ - setup_iomuxc_enet(); - - gpio_init(); - - /* Turn the UART-couplers on one-after-another */ - gpio_set_value(GPIO_UART1_PWRON, 1); - mdelay(10); - gpio_set_value(GPIO_UART2_PWRON, 1); - mdelay(10); - gpio_set_value(GPIO_UART3_PWRON, 1); - - return 0; -} - -int tqma6_bb_board_late_init(void) -{ - return 0; -} - -const char *tqma6_bb_get_boardname(void) -{ - return "WRU-IV"; -} - -static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ - {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, - /* 8 bit bus width */ - {"emmc", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, - { NULL, 0 }, -}; - -int misc_init_r(void) -{ - add_board_boot_modes(board_boot_modes); - - return 0; -} - -#define WRU4_USB_H1_PWR IMX_GPIO_NR(1, 0) -#define WRU4_USB_OTG_PWR IMX_GPIO_NR(3, 22) - -int board_ehci_hcd_init(int port) -{ - int ret; - - ret = gpio_request(WRU4_USB_H1_PWR, "usb-h1-pwr"); - if (!ret) - gpio_direction_output(WRU4_USB_H1_PWR, 1); - - ret = gpio_request(WRU4_USB_OTG_PWR, "usb-OTG-pwr"); - if (!ret) - gpio_direction_output(WRU4_USB_OTG_PWR, 1); - - return 0; -} - -int board_ehci_power(int port, int on) -{ - if (port) - gpio_set_value(WRU4_USB_OTG_PWR, on); - else - gpio_set_value(WRU4_USB_H1_PWR, on); - - return 0; -} - -/* - * Device Tree Support - */ -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd) -{ - /* TBD */ -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tqc/tqma6/tqma6dl.cfg b/board/tqc/tqma6/tqma6dl.cfg deleted file mode 100644 index 80c7150316..0000000000 --- a/board/tqc/tqma6/tqma6dl.cfg +++ /dev/null @@ -1,124 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 - 2015 Markus Niebel - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -#define __ASSEMBLY__ -#include - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -#if defined(CONFIG_TQMA6X_MMC_BOOT) -BOOT_FROM sd -#elif defined(CONFIG_TQMA6X_SPI_BOOT) -BOOT_FROM spi -#endif - -#include "asm/arch/mx6-ddr.h" -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -/* TQMa6DL DDR config Rev. 0100E */ -/* IOMUX configuration */ -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030 -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 -DATA 4, MX6_IOM_DRAM_CAS, 0x00008030 -DATA 4, MX6_IOM_DRAM_RAS, 0x00008030 -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 -DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 -DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 -DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 - -/* memory interface calibration values */ -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00440048 -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x003D003F -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0029002D -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x002B0043 -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x424C0250 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02300234 -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4234023C -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0224022C -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x48484C4C -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4C4E4E4C -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36382C36 -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x34343630 -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 - -/* configure memory interface */ -DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D -DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 -DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 -DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 -DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00408032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222 -DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D -DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 - -#include "clocks.cfg" diff --git a/board/tqc/tqma6/tqma6q.cfg b/board/tqc/tqma6/tqma6q.cfg deleted file mode 100644 index 82a0a271d4..0000000000 --- a/board/tqc/tqma6/tqma6q.cfg +++ /dev/null @@ -1,124 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013, 2014 Markus Niebel - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -#define __ASSEMBLY__ -#include - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -#if defined(CONFIG_TQMA6X_MMC_BOOT) -BOOT_FROM sd -#elif defined(CONFIG_TQMA6X_SPI_BOOT) -BOOT_FROM spi -#endif - -#include "asm/arch/mx6-ddr.h" -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -/* TQMa6Q/D DDR config Rev. 0100B */ -/* IOMUX configuration */ -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030 -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 -DATA 4, MX6_IOM_DRAM_CAS, 0x00008030 -DATA 4, MX6_IOM_DRAM_RAS, 0x00008030 -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 -DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 -DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 -DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 - -/* memory interface calibration values */ -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001B0013 -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018001B -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001B0016 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012001C -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43400350 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x023E032C -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43400348 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03300304 -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x3C323436 -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38383242 -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3E3C4440 -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4236483E -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 - -/* configure memory interface */ -DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 -DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 -DATA 4, MX6_MMDC_P0_MDCFG0, 0x545A79B4 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023 -DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 -DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00088032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x09308030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222 -DATA 4, MX6_MMDC_P0_MDPDC, 0x00025536 -DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 - -#include "clocks.cfg" diff --git a/board/tqc/tqma6/tqma6s.cfg b/board/tqc/tqma6/tqma6s.cfg deleted file mode 100644 index 9cdbb3c767..0000000000 --- a/board/tqc/tqma6/tqma6s.cfg +++ /dev/null @@ -1,124 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013, 2014 Markus Niebel - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -#define __ASSEMBLY__ -#include - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -#if defined(CONFIG_TQMA6X_MMC_BOOT) -BOOT_FROM sd -#elif defined(CONFIG_TQMA6X_SPI_BOOT) -BOOT_FROM spi -#endif - -#include "asm/arch/mx6-ddr.h" -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -/* TQMa6S DDR config Rev. 0100B */ -/* IOMUX configuration */ -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008000 -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 -DATA 4, MX6_IOM_DRAM_CAS, 0x00008030 -DATA 4, MX6_IOM_DRAM_RAS, 0x00008030 -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 -DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 -DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 -DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000 -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B4DS, 0x00000000 -DATA 4, MX6_IOM_GRP_B5DS, 0x00000000 -DATA 4, MX6_IOM_GRP_B6DS, 0x00000000 -DATA 4, MX6_IOM_GRP_B7DS, 0x00000000 -DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000 -DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000 -DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000 -DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000 - -/* memory interface calibration values */ -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380000 -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0014000E -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00120014 -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00000000 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00000000 -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x0240023C -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0228022C -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x00000000 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x00000000 -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4A4A4E4A -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x00000000 -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36362A32 -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x00000000 -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x00000000 -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x00000000 -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x00000000 -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x00000000 -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000000 - -/* configure memory interface */ -DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D -DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 -DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 -DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 -DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000 -DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D -DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 - -#include "clocks.cfg" -- cgit v1.2.3