From 7bf446101651767e3a2de7227889004166ec34d6 Mon Sep 17 00:00:00 2001 From: Wei Liang Lim Date: Thu, 19 Oct 2023 18:09:08 +0800 Subject: riscv: dubhe: Set SYS_CACHELINE_SIZE 64 Signed-off-by: Wei Liang Lim --- arch/riscv/cpu/dubhe/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/cpu/dubhe/Kconfig b/arch/riscv/cpu/dubhe/Kconfig index 38e94c96a4..7f0ce08a39 100644 --- a/arch/riscv/cpu/dubhe/Kconfig +++ b/arch/riscv/cpu/dubhe/Kconfig @@ -16,3 +16,6 @@ config STARFIVE_DUBHE imply SPL_OPENSBI imply SPL_LOAD_FIT imply MII + +config SYS_CACHELINE_SIZE + default 64 -- cgit v1.2.3