From 496d25d55c6e90cabe38395f8faa5ff5d7d9473a Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Fri, 16 Jun 2023 10:05:59 +0800 Subject: dram: jh7110: Add resize DDR info from EEPROM. sync from vf2 and add resize DDR info from EEPROM Signed-off-by: Samin Guo --- arch/riscv/cpu/jh7110/dram.c | 49 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 2 deletions(-) diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c index 1dc77efeca..ad8baeba93 100644 --- a/arch/riscv/cpu/jh7110/dram.c +++ b/arch/riscv/cpu/jh7110/dram.c @@ -4,20 +4,65 @@ */ #include +#include #include #include #include DECLARE_GLOBAL_DATA_PTR; +static bool check_eeprom_dram_info(phys_size_t size) +{ + switch (size) { + case 0x80000000: + case 0x100000000: + case 0x200000000: + case 0x400000000: + return true; + default: + return false; + } +} + int dram_init(void) { - return fdtdec_setup_mem_size_base(); + int ret; + u8 data; + u32 len; + u32 offset; + phys_size_t size; + + data = 0; + len = 1; + offset = 91; /*offset of memory size stored in eeprom*/ + ret = fdtdec_setup_mem_size_base(); + if (ret) + goto err; + + /*read memory size info*/ + ret = get_data_from_eeprom(offset, len, &data); + if (ret == len) { + size = ((phys_size_t)hextoul(&data, NULL)) << 30; + if (check_eeprom_dram_info(size)) + gd->ram_size = size; + } + + ret = 0; +err: + return ret; } int dram_init_banksize(void) { - return fdtdec_setup_memory_banksize(); + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; } ulong board_get_usable_ram_top(ulong total_size) -- cgit v1.2.3 From b354251c68d6ee4404ec08159a3d7a7bc948f78e Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Fri, 7 Jul 2023 15:22:36 +0800 Subject: dram: jh7110: Macro definitions STARFIVE_JH7110_EEPROM_DDRINFO_OFFSET In order to read DDR info from eeprom. Signed-off-by: Samin Guo --- arch/riscv/cpu/jh7110/dram.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c index ad8baeba93..ddcb3da64e 100644 --- a/arch/riscv/cpu/jh7110/dram.c +++ b/arch/riscv/cpu/jh7110/dram.c @@ -10,6 +10,7 @@ #include DECLARE_GLOBAL_DATA_PTR; +#define STARFIVE_JH7110_EEPROM_DDRINFO_OFFSET 91 static bool check_eeprom_dram_info(phys_size_t size) { @@ -34,7 +35,7 @@ int dram_init(void) data = 0; len = 1; - offset = 91; /*offset of memory size stored in eeprom*/ + offset = STARFIVE_JH7110_EEPROM_DDRINFO_OFFSET; /*offset of memory size stored in eeprom*/ ret = fdtdec_setup_mem_size_base(); if (ret) goto err; -- cgit v1.2.3 From 7eb47f1ce4fb5ee18155fa3fa4679aed4d01a16d Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Fri, 16 Jun 2023 09:55:38 +0800 Subject: dram: jh7110: Add CONFIG_ID_EEPROM to determine if EEPROM is available When eeprom reads, you need to determine whether eeprom supports it. Signed-off-by: Samin Guo --- arch/riscv/cpu/jh7110/dram.c | 44 ++++++++++++++++++++++++++------------------ 1 file changed, 26 insertions(+), 18 deletions(-) diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c index ddcb3da64e..b5d1934f35 100644 --- a/arch/riscv/cpu/jh7110/dram.c +++ b/arch/riscv/cpu/jh7110/dram.c @@ -2,16 +2,19 @@ /* * Copyright (C) 2018, Bin Meng */ - #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_ID_EEPROM +#include #define STARFIVE_JH7110_EEPROM_DDRINFO_OFFSET 91 +#endif + +DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_ID_EEPROM static bool check_eeprom_dram_info(phys_size_t size) { switch (size) { @@ -25,22 +28,15 @@ static bool check_eeprom_dram_info(phys_size_t size) } } -int dram_init(void) +static void resize_ddr_from_eeprom(void) { - int ret; - u8 data; - u32 len; - u32 offset; + u32 offset = STARFIVE_JH7110_EEPROM_DDRINFO_OFFSET; phys_size_t size; + u32 len = 1; + u8 data = 0; + int ret; - data = 0; - len = 1; - offset = STARFIVE_JH7110_EEPROM_DDRINFO_OFFSET; /*offset of memory size stored in eeprom*/ - ret = fdtdec_setup_mem_size_base(); - if (ret) - goto err; - - /*read memory size info*/ + /* read memory size info */ ret = get_data_from_eeprom(offset, len, &data); if (ret == len) { size = ((phys_size_t)hextoul(&data, NULL)) << 30; @@ -48,9 +44,21 @@ int dram_init(void) gd->ram_size = size; } - ret = 0; -err: +} +#endif /* CONFIG_ID_EEPROM */ + +int dram_init(void) +{ + int ret; + + ret = fdtdec_setup_mem_size_base(); + if (ret) return ret; + +#ifdef CONFIG_ID_EEPROM + resize_ddr_from_eeprom(); +#endif + return 0; } int dram_init_banksize(void) -- cgit v1.2.3 From a76fba9179fa794ef7de7e7d49526f8da3ef219f Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Wed, 14 Jun 2023 11:00:03 +0800 Subject: dram: starfive: jh7110: Add 1G support add 1G DDR tuning cfg Signed-off-by: Samin Guo --- arch/riscv/cpu/jh7110/dram.c | 1 + drivers/ram/starfive/ddrcsr_boot.c | 38 ++++++++++++++++++++++--------------- drivers/ram/starfive/ddrphy_start.c | 22 ++++++++++++--------- drivers/ram/starfive/starfive_ddr.c | 5 ++++- drivers/ram/starfive/starfive_ddr.h | 10 ++++++---- 5 files changed, 47 insertions(+), 29 deletions(-) diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c index b5d1934f35..e141f87d41 100644 --- a/arch/riscv/cpu/jh7110/dram.c +++ b/arch/riscv/cpu/jh7110/dram.c @@ -18,6 +18,7 @@ DECLARE_GLOBAL_DATA_PTR; static bool check_eeprom_dram_info(phys_size_t size) { switch (size) { + case 0x40000000: case 0x80000000: case 0x100000000: case 0x200000000: diff --git a/drivers/ram/starfive/ddrcsr_boot.c b/drivers/ram/starfive/ddrcsr_boot.c index 048b838b3d..469e280938 100644 --- a/drivers/ram/starfive/ddrcsr_boot.c +++ b/drivers/ram/starfive/ddrcsr_boot.c @@ -15,13 +15,15 @@ static struct ddr_reg_cfg ddr_csr_cfg[] = { {0x0, 0x0, 0x00000001, REGSETALL}, {0xf00, 0x0, 0x40001030, (OFFSET_SEL | F_SET | REG4G | REG8G)}, - {0xf00, 0x0, 0x40001030, (OFFSET_SEL | F_SET | REG2G)}, + {0xf00, 0x0, 0x40001010, (OFFSET_SEL | F_SET | REG2G)}, + {0xf00, 0x0, 0x40001010, (OFFSET_SEL | F_SET | REG1G)}, {0xf04, 0x0, 0x00000001, (OFFSET_SEL | F_SET | REG4G | REG8G)}, - {0xf04, 0x0, 0x00800001, (OFFSET_SEL | F_SET | REG2G)}, + {0xf04, 0x0, 0x00800001, (OFFSET_SEL | F_SET | REG1G | REG2G)}, {0xf10, 0x0, 0x00400000, (OFFSET_SEL | REGSETALL)}, {0xf14, 0x0, 0x043fffff, (OFFSET_SEL | REGSETALL)}, {0xf18, 0x0, 0x00000000, (OFFSET_SEL | REGSETALL)}, - {0xf30, 0x0, 0x1f000041, (OFFSET_SEL | REGSETALL)}, + {0xf30, 0x0, 0x1f000041, (OFFSET_SEL | F_SET | REG2G | REG4G | REG8G)}, + {0xf30, 0x0, 0x07000021, (OFFSET_SEL | F_SET | REG1G)}, {0xf34, 0x0, 0x1f000041, (OFFSET_SEL | F_SET | REG4G | REG8G)}, {0x110, 0x0, 0xc0000001, (OFFSET_SEL | REGSETALL)}, {0x114, 0x0, 0xffffffff, (OFFSET_SEL | REGSETALL)}, @@ -74,19 +76,19 @@ static struct ddr_reg_cfg ddr_csr_cfg1[] = { {0x6a4, 0x0, 0x20240c00, REGSETALL}, {0x6a8, 0x0, 0x00040000, REGSETALL}, {0x4, 0x0, 0x30010006, (F_SET | REG4G | REG8G)}, - {0x4, 0x0, 0x10010006, (F_SET | REG2G)}, + {0x4, 0x0, 0x10010006, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x4, 0x0, 0x30020000, (F_SET | REG4G | REG8G)}, - {0x4, 0x0, 0x10020000, (F_SET | REG2G)}, + {0x4, 0x0, 0x10020000, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x4, 0x0, 0x30030031, (F_SET | REG4G | REG8G)}, - {0x4, 0x0, 0x10030031, (F_SET | REG2G)}, + {0x4, 0x0, 0x10030031, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x4, 0x0, 0x300b0033, (F_SET | REG4G | REG8G)}, - {0x4, 0x0, 0x100b0033, (F_SET | REG2G)}, + {0x4, 0x0, 0x100b0033, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x4, 0x0, 0x30160016, (F_SET | REG4G | REG8G)}, - {0x4, 0x0, 0x10160016, (F_SET | REG2G)}, + {0x4, 0x0, 0x10160016, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x10, 0x0, 0x00000010, REGSETALL}, {0x14, 0x0, 0x00000001, REGSETALL}, @@ -153,20 +155,20 @@ static struct ddr_reg_cfg ddr_csr_cfg3[] = { {0x6a4, 0x0, 0x202c0c00, REGSETALL}, {0x6a8, 0x0, 0x00040000, REGSETALL}, {0x4, 0x0, 0x30010036, (F_SET | REG4G | REG8G)}, - {0x4, 0x0, 0x10010036, (F_SET | REG2G)}, + {0x4, 0x0, 0x10010036, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x4, 0x0, 0x3002001b, (F_SET | REG4G | REG8G)}, - {0x4, 0x0, 0x10010036, (F_SET | REG2G)}, + {0x4, 0x0, 0x1002001b, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x4, 0x0, 0x30030031, (F_SET | REG4G | REG8G)}, - {0x4, 0x0, 0x10030031, (F_SET | REG2G)}, + {0x4, 0x0, 0x10030031, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x4, 0x0, 0x300b0066, (F_SET | REG4G)}, {0x4, 0x0, 0x300b0036, (F_SET | REG8G)}, - {0x4, 0x0, 0x100b0066, (F_SET | REG2G)}, + {0x4, 0x0, 0x100b0066, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x4, 0x0, 0x30160016, (F_SET | REG4G | REG8G)}, - {0x4, 0x0, 0x10160016, (F_SET | REG2G)}, + {0x4, 0x0, 0x10160016, (F_SET | REG1G | REG2G)}, {0xc, 0x0, 0x00000002, REGSETALL}, {0x410, 0x0, 0x00101010, REGSETALL}, {0x420, 0x0, 0x0c181006, REGSETALL}, @@ -176,9 +178,9 @@ static struct ddr_reg_cfg ddr_csr_cfg3[] = { {0x108, 0x0, 0x00003000, REGSETALL}, {0x704, 0x0, 0x00000007, REGSETALL | OFFSET_SEL}, {0x330, 0x0, 0x09313fff, (F_SET | REG4G | REG8G)}, - {0x330, 0x0, 0x09311fff, (F_SET | REG2G)}, + {0x330, 0x0, 0x09311fff, (F_SET | REG1G | REG2G)}, {0x508, 0x0, 0x00000033, (F_SET | REG4G | REG8G)}, - {0x508, 0x0, 0x00000013, (F_SET | REG2G)}, + {0x508, 0x0, 0x00000013, (F_SET | REG1G | REG2G)}, {0x324, 0x0, 0x00002000, REGSETALL}, {0x104, 0x0, 0x90000000, REGSETALL}, {0x510, 0x0, 0x00000100, REGSETALL}, @@ -217,6 +219,10 @@ void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size) u32 mask; switch (size) { + case DDR_SIZE_1G: + mask = REG1G; + break; + case DDR_SIZE_2G: mask = REG2G; break; @@ -249,6 +255,7 @@ void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size) udelay(3000); switch (size) { + case DDR_SIZE_1G: case DDR_SIZE_2G: out_le32(csrreg + REGOFFSET(0x10), 0x0000001c); break; @@ -279,6 +286,7 @@ void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size) out_le32(csrreg + REGOFFSET(0x10), 0x00000021); out_le32(csrreg + REGOFFSET(0x14), 0x00000001); break; + case DDR_SIZE_1G: case DDR_SIZE_2G: case DDR_SIZE_16G: default: diff --git a/drivers/ram/starfive/ddrphy_start.c b/drivers/ram/starfive/ddrphy_start.c index 58165e427c..3ec587276d 100644 --- a/drivers/ram/starfive/ddrphy_start.c +++ b/drivers/ram/starfive/ddrphy_start.c @@ -79,7 +79,7 @@ static struct ddr_reg_cfg ddr_start_cfg[] = { {185, 0x80ffffff, 0x20000000, REGCLRSETALL}, {10, 0xffffffe0, 0x00000002, REGCLRSETALL}, {0, 0xfffffffe, 0x00000001, REGCLRSETALL}, - {11, 0xfffffff0, 0x00000005, (F_CLRSET | REG2G)}, + {11, 0xfffffff0, 0x00000005, (F_CLRSET | REG1G | REG2G)}, {247, 0xffffffff, 0x00000008, REGCLRSETALL}, {249, 0xffffffff, 0x00000800, REGCLRSETALL}, {252, 0xffffffff, 0x00000008, REGCLRSETALL}, @@ -92,10 +92,10 @@ static struct ddr_reg_cfg ddr_start_cfg[] = { {313, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)}, {337, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)}, {361, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)}, - {289, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, - {313, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, - {337, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, - {361, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, + {289, 0xffffffff, 0x66000000, (F_CLRSET | REG1G | REG2G | REG4G)}, + {313, 0xffffffff, 0x66000000, (F_CLRSET | REG1G | REG2G | REG4G)}, + {337, 0xffffffff, 0x66000000, (F_CLRSET | REG1G | REG2G | REG4G)}, + {361, 0xffffffff, 0x66000000, (F_CLRSET | REG1G | REG2G | REG4G)}, {282, 0xffffffff, 0x00160000, REGCLRSETALL}, {306, 0xffffffff, 0x00160000, REGCLRSETALL}, {330, 0xffffffff, 0x00160000, REGCLRSETALL}, @@ -162,7 +162,7 @@ static struct ddr_reg_cfg ddr_start_cfg[] = { {1915, 0x0, 0xc3c37ff, (OFFSET_SEL | REGSETALL)}, {1916, 0x0, 0x1fffff10, (OFFSET_SEL | REGSETALL)}, {1917, 0x0, 0x230070, (OFFSET_SEL | REGSETALL)}, - {1918, 0x0, 0x3ff7ffff, (OFFSET_SEL | REG4G | REG2G | F_SET)}, + {1918, 0x0, 0x3ff7ffff, (OFFSET_SEL | REG4G | REG1G | REG2G | F_SET)}, {1918, 0x0, 0x3ff7ffff, (OFFSET_SEL | REG8G | F_SET)}, {1919, 0x0, 0xe10, (OFFSET_SEL | REGSETALL)}, {1920, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)}, @@ -186,9 +186,9 @@ static struct ddr_reg_cfg ddr_start_cfg[] = { {333, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)}, {589, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)}, {845, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)}, - {1062, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)}, - {1318, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)}, - {1574, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)}, + {1062, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG1G | REG2G | F_CLRSET)}, + {1318, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG1G | REG2G | F_CLRSET)}, + {1574, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG1G | REG2G | F_CLRSET)}, {1062, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)}, {1318, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)}, {1574, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)}, @@ -256,6 +256,10 @@ void ddr_phy_start(u32 *phyreg, enum ddr_size_t size) u32 mask; switch (size) { + case DDR_SIZE_1G: + mask = REG1G; + break; + case DDR_SIZE_2G: mask = REG2G; break; diff --git a/drivers/ram/starfive/starfive_ddr.c b/drivers/ram/starfive/starfive_ddr.c index 5773d57927..a5c567da38 100644 --- a/drivers/ram/starfive/starfive_ddr.c +++ b/drivers/ram/starfive/starfive_ddr.c @@ -38,6 +38,9 @@ static int starfive_ddr_setup(struct udevice *dev, struct starfive_ddr_priv *pri enum ddr_size_t size; switch (priv->info.size) { + case 0x40000000: + size = DDR_SIZE_1G; + break; case 0x80000000: size = DDR_SIZE_2G; break; @@ -123,7 +126,7 @@ static int starfive_ddr_probe(struct udevice *dev) reset_deassert(&priv->rst_axi); ret = starfive_ddr_setup(dev, priv); - printf("DDR version: dc2e84f0.\n"); + printf("DDR: %ldG version: g8ad50857.\n", priv->info.size/1024/1024/1024); goto init_end; err_osc: reset_free(&priv->rst_osc); diff --git a/drivers/ram/starfive/starfive_ddr.h b/drivers/ram/starfive/starfive_ddr.h index d63e7e4c83..aa7ee988e4 100644 --- a/drivers/ram/starfive/starfive_ddr.h +++ b/drivers/ram/starfive/starfive_ddr.h @@ -27,13 +27,14 @@ #define DDR_AXI_ENABLE 1 #define OFFSET_SEL BIT(31) -#define REG2G BIT(30) -#define REG4G BIT(29) -#define REG8G BIT(28) +#define REG1G BIT(30) +#define REG2G BIT(29) +#define REG4G BIT(28) +#define REG8G BIT(27) #define F_ADDSET BIT(2) #define F_SET BIT(1) #define F_CLRSET BIT(0) -#define REGALL (REG2G | REG4G | REG8G) +#define REGALL (REG1G | REG2G | REG4G | REG8G) #define REGSETALL (F_SET | REGALL) #define REGCLRSETALL (F_CLRSET | REGALL) #define REGADDSETALL (F_ADDSET | REGALL) @@ -46,6 +47,7 @@ struct ddr_reg_cfg { }; enum ddr_size_t { + DDR_SIZE_1G, DDR_SIZE_2G, DDR_SIZE_4G, DDR_SIZE_8G, -- cgit v1.2.3 From 8e4d0d56493b4897d1010893ea5b69b1f0f934a0 Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Fri, 16 Jun 2023 10:28:34 +0800 Subject: riscv: jh7110: set SPL_OPENSBI_LOAD_ADDR set SPL_OPENSBI_LOAD_ADDR to 0x40000000 Signed-off-by: Samin Guo --- configs/starfive_evb_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/starfive_evb_defconfig b/configs/starfive_evb_defconfig index 9e2d6bc515..55d68eb557 100644 --- a/configs/starfive_evb_defconfig +++ b/configs/starfive_evb_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_BUILD_TARGET="" CONFIG_TARGET_STARFIVE_EVB=y +CONFIG_SPL_OPENSBI_LOAD_ADDR=0x40000000 CONFIG_NR_CPUS=5 CONFIG_FPGA_GMAC_SPEED_AUTO=y CONFIG_STARFIVE_JH7110_L2CC_FLUSH=y -- cgit v1.2.3 From de7517bdbe830ed5457780f579bcca798419a497 Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Sun, 25 Jun 2023 10:32:54 +0800 Subject: riscv: jh7110: add spi nor flash SPI_FLASH_MACRONIX support Radxa uses macronix spi flash, so enable it. Signed-off-by: Samin Guo --- configs/starfive_evb_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/starfive_evb_defconfig b/configs/starfive_evb_defconfig index 55d68eb557..6070d0bc44 100644 --- a/configs/starfive_evb_defconfig +++ b/configs/starfive_evb_defconfig @@ -77,6 +77,7 @@ CONFIG_MMC_DW_SNPS=y CONFIG_SF_DEFAULT_MODE=0x0 CONFIG_SF_DEFAULT_SPEED=100000000 CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_MICREL=y -- cgit v1.2.3 From 618eb7825344a7821bc731e94e12766c89529ee7 Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Fri, 16 Jun 2023 11:01:35 +0800 Subject: borad: starfive: evb: Resize the address space Readjust the address space for 1G DDR Signed-off-by: Samin Guo --- include/configs/starfive-evb.h | 28 ++++++++-------------------- 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/include/configs/starfive-evb.h b/include/configs/starfive-evb.h index 362a5fe7de..6d0559f861 100644 --- a/include/configs/starfive-evb.h +++ b/include/configs/starfive-evb.h @@ -16,23 +16,22 @@ #define CONFIG_SPL_MAX_SIZE 0x00040000 #define CONFIG_SPL_BSS_START_ADDR 0x08040000 #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000 -#define CONFIG_SYS_SPL_MALLOC_START (0x80000000) +#define CONFIG_SYS_SPL_MALLOC_START 0x42000000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00800000 -#define CONFIG_SPL_STACK (0x08000000 + 0x00180000 - \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SPL_STACK (0x08000000 + 0x00180000 - \ + GENERATED_GBL_DATA_SIZE) -#define STARFIVE_SPL_BOOT_LOAD_ADDR 0xa0000000 +#define STARFIVE_SPL_BOOT_LOAD_ADDR 0x60000000 #endif - #define CONFIG_SYS_CACHELINE_SIZE 64 /* * Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BOOTM_LEN (32 << 20) /* 32MB */ +#define CONFIG_SYS_BOOTM_LEN SZ_64M /* * Print Buffer Size @@ -56,19 +55,13 @@ */ #define CONFIG_SYS_MALLOC_LEN SZ_8M -#define CONFIG_NR_DRAM_BANKS 1 - -#define PHYS_SDRAM_0 0x40000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_0_SIZE 0x100000000 /* 8 GB */ - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_0) - +#define CONFIG_SYS_SDRAM_BASE 0x40000000 /* Init Stack Pointer */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_8M) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_16M) -#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000 +#define CONFIG_STANDALONE_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_16M) #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ @@ -206,11 +199,6 @@ BOOTENV \ BOOTENV_SF -/* - * memtest works on 1.9 MB in DRAM - */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600} #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -- cgit v1.2.3 From 9a582173ba11765aac1cd64a02ddebba1e7d7095 Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Tue, 27 Jun 2023 10:22:29 +0800 Subject: borad: starfive: evb: Synchronize environment variables from vf2 loadaddr fdtoverlay_addr_r kernel_comp_addr_r/kernel_comp_size Signed-off-by: Samin Guo --- include/configs/starfive-evb.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/starfive-evb.h b/include/configs/starfive-evb.h index 6d0559f861..c183e0599a 100644 --- a/include/configs/starfive-evb.h +++ b/include/configs/starfive-evb.h @@ -177,12 +177,16 @@ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_addr_r=0x40200000\0" \ + "kernel_comp_addr_r=0x5a000000\0" \ + "kernel_comp_size=0x4000000\0" \ "fdt_addr_r=0x46000000\0" \ "scriptaddr=0x43900000\0" \ "script_offset_f=0x1fff000\0" \ "script_size_f=0x1000\0" \ "pxefile_addr_r=0x45900000\0" \ "ramdisk_addr_r=0x46100000\0" \ + "fdtoverlay_addr_r=0x4f000000\0" \ + "loadaddr=0x60000000\0" \ CHIPA_GMAC_SET \ CHIPA_SET \ EVB_BOOTENV_NVME \ -- cgit v1.2.3