From d2e38f5a9b740307d8f4ed1ca4594121e2fae6e8 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 23 Oct 2019 11:08:53 -0300 Subject: mx7ulp_evk: Disable CONFIG_NET Currently the following build warning is seen: ===================== WARNING ====================== This board does not use CONFIG_DM_ETH (Driver Model for Ethernet drivers). Please update the board to use CONFIG_DM_ETH before the v2020.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. =================================================== Since the mx7ulp-evk board does not have networking support, explicitly disable networking. Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan --- configs/mx7ulp_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index 3cf90155d1..8c17477872 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -19,6 +19,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk" CONFIG_ENV_IS_IN_MMC=y +# CONFIG_NET is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_DM_GPIO=y -- cgit v1.2.3 From a44083c0532260657d1871f5732be81d727abf9d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 23 Oct 2019 11:08:54 -0300 Subject: mx7ulp_evk: Remove unneeded SDHC definitions As we use the driver model for ESDHC there is no need for defining CONFIG_SYS_FSL_USDHC_NUM and CONFIG_SYS_FSL_ESDHC_ADDR, so simply remove them. Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan --- include/configs/mx7ulp_evk.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index cdc1a487c4..f5583054a3 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -18,9 +18,6 @@ #define IRAM_BASE_ADDR OCRAM_0_BASE #define IOMUXC_BASE_ADDR IOMUXC1_RBASE -#define CONFIG_SYS_FSL_USDHC_NUM 1 - -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ -- cgit v1.2.3 From 9c27310ac23ce1966f9629d73973c458412a0085 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 23 Oct 2019 11:08:55 -0300 Subject: mx7ulp: Move SoC base address to a common file SoC base addresses should better go into a common SoC file instead of repeating the definition in each board file. Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan --- arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 4 ++++ include/configs/mx7ulp_evk.h | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index 3c82e9921e..9a420dc30b 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -946,6 +946,10 @@ #define SNVS_LPCR_DPEN (0x20) #define SNVS_LPCR_SRTC_ENV (0x1) +#define SRC_BASE_ADDR CMC1_RBASE +#define IRAM_BASE_ADDR OCRAM_0_BASE +#define IOMUXC_BASE_ADDR IOMUXC1_RBASE + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index f5583054a3..c1b379bdea 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -14,10 +14,6 @@ #define CONFIG_BOARD_POSTCLK_INIT #define CONFIG_SYS_BOOTM_LEN 0x1000000 -#define SRC_BASE_ADDR CMC1_RBASE -#define IRAM_BASE_ADDR OCRAM_0_BASE -#define IOMUXC_BASE_ADDR IOMUXC1_RBASE - #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ -- cgit v1.2.3 From 625bbd38a6cc4aa7a3e445c46bbd8a0eef0ceaba Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 15 Jan 2020 11:27:30 +0100 Subject: ARM: imx: vining2000: Clean up uSDHC4 setup Simplify the uSDHC4 eMMC controller setup. This is the only eMMC present on the system and only controller that is used, so drop the extra logic. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Silvio Fricke Cc: Stefano Babic Reviewed-by: Stefano Babic --- board/softing/vining_2000/vining_2000.c | 27 ++++----------------------- 1 file changed, 4 insertions(+), 23 deletions(-) diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c index ef914b13a1..6dc3fc8b50 100644 --- a/board/softing/vining_2000/vining_2000.c +++ b/board/softing/vining_2000/vining_2000.c @@ -427,8 +427,6 @@ void board_preboot_os(void) #include #include -static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR }; - static iomux_v3_cfg_t const pcie_pads[] = { MX6_PAD_NAND_DATA02__GPIO4_IO_6 | MUX_PAD_CTRL(GPIO_PAD_CTRL), }; @@ -461,30 +459,13 @@ static void vining2000_spl_setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); } +static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR }; + int board_mmc_init(bd_t *bis) { - struct src *src_regs = (struct src *)SRC_BASE_ADDR; - u32 val; - u32 port; - - val = readl(&src_regs->sbmr1); - - if ((val & 0xc0) != 0x40) { - printf("Not boot from USDHC!\n"); - return -EINVAL; - } - - port = (val >> 11) & 0x3; - printf("port %d\n", port); - switch (port) { - case 3: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - usdhc_cfg.esdhc_base = USDHC4_BASE_ADDR; - break; - } + imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk; return fsl_esdhc_initialize(bis, &usdhc_cfg); } -- cgit v1.2.3 From f3284e401e95e7e8f285d5596236c183aef8abd0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 15 Jan 2020 11:27:31 +0100 Subject: ARM: imx: vining2000: Properly discern PFUZE100 and PFUZE200 The PFUZE100 and PFUZE200 PMICs can be discerned by bit 0 in DeviceID register. Print the correct identification of the PMICs. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Silvio Fricke Cc: Stefano Babic --- board/softing/vining_2000/vining_2000.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c index 6dc3fc8b50..c74c06eaee 100644 --- a/board/softing/vining_2000/vining_2000.c +++ b/board/softing/vining_2000/vining_2000.c @@ -146,7 +146,7 @@ static struct pmic *pfuze_init(unsigned char i2cbus) return NULL; pmic_reg_read(p, PFUZE100_DEVICEID, ®); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + printf("PMIC: PFUZE%i00 ID=0x%02x\n", (reg & 1) ? 2 : 1, reg); /* Set SW1AB stanby volage to 0.975V */ pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); -- cgit v1.2.3 From 9d1230332208b260c23adba2298e5dab9b23a358 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 15 Jan 2020 11:27:32 +0100 Subject: ARM: imx: vining2000: Enable SPL SDP by default Enable SPL SDP fallback boot option in default build. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Silvio Fricke Cc: Stefano Babic --- configs/vining_2000_defconfig | 9 +++++++++ include/configs/vining_2000.h | 2 -- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index c1542fe5d3..34b49ce972 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -26,6 +26,9 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -74,5 +77,11 @@ CONFIG_MXC_UART=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Softing" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 0c0baf2738..61d9c62068 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -66,12 +66,10 @@ #define CONFIG_PHY_ATHEROS -#ifdef CONFIG_CMD_USB #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif #ifdef CONFIG_CMD_PCI #define CONFIG_PCI_SCAN_SHOW -- cgit v1.2.3 From 5b6f8f3083557569c5fdd9823f50fe14f27dcaef Mon Sep 17 00:00:00 2001 From: Arkadiusz Karas Date: Thu, 2 Jan 2020 19:31:21 +0100 Subject: ARM: imx: mx6ull: Add iMX6ULL VisionSOM SoM and EVK Add iMX6ULL VisionSOM SoM and VisionCB-RT-STD evaluation board support. The SoM has an iMX6ULL, 512 MiB of DRAM and microSD slot. The carrier board has Ethernet, USB host port, USB OTG port. Signed-off-by: Arkadiusz Karas Signed-off-by: Marek Vasut Cc: Stefano Babic --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx6ull-somlabs-visionsom.dts | 276 ++++++++++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 13 ++ board/somlabs/visionsom-6ull/Kconfig | 12 ++ board/somlabs/visionsom-6ull/MAINTAINERS | 6 + board/somlabs/visionsom-6ull/Makefile | 4 + board/somlabs/visionsom-6ull/imximage.cfg | 107 ++++++++++ board/somlabs/visionsom-6ull/visionsom-6ull.c | 146 ++++++++++++++ configs/somlabs_visionsom_6ull_defconfig | 49 +++++ include/configs/somlabs_visionsom_6ull.h | 116 +++++++++++ 10 files changed, 730 insertions(+) create mode 100644 arch/arm/dts/imx6ull-somlabs-visionsom.dts create mode 100644 board/somlabs/visionsom-6ull/Kconfig create mode 100644 board/somlabs/visionsom-6ull/MAINTAINERS create mode 100644 board/somlabs/visionsom-6ull/Makefile create mode 100644 board/somlabs/visionsom-6ull/imximage.cfg create mode 100644 board/somlabs/visionsom-6ull/visionsom-6ull.c create mode 100644 configs/somlabs_visionsom_6ull_defconfig create mode 100644 include/configs/somlabs_visionsom_6ull.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 04a8cccda5..b2f127d398 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -676,6 +676,7 @@ dtb-$(CONFIG_MX6ULL) += \ imx6ull-colibri.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-dart-6ul.dtb \ + imx6ull-somlabs-visionsom.dtb \ imx6ulz-14x14-evk.dtb dtb-$(CONFIG_ARCH_MX6) += \ diff --git a/arch/arm/dts/imx6ull-somlabs-visionsom.dts b/arch/arm/dts/imx6ull-somlabs-visionsom.dts new file mode 100644 index 0000000000..868f3f8440 --- /dev/null +++ b/arch/arm/dts/imx6ull-somlabs-visionsom.dts @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017-2019 SoMLabs + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +/dts-v1/; + +#include +#include "imx6ull.dtsi" + +/ { + model = "SoMLabs VisionSOM-6ULL"; + compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + + usr0 { + label = "usr0"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + usr1 { + label = "usr1"; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + usr2 { + label = "usr2"; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + }; + + usr3 { + label = "usr3"; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + }; +}; + +&cpu0 { + arm-supply = <®_arm>; + soc-supply = <®_soc>; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; + +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x1>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */ +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + /* 32kHz low power reference clock for WiFi */ + MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x17099 + /* LED 0..3 */ + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x17099 + MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x17099 + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x17099 + MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x17099 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1F829 + + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400010a9 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x30b0 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x10b0 + >; + }; + + pinctrl_usb_otg2: usbotg2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x10b0 + >; + }; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure-delay-time = <0xffff>; + pre-charge-time = <0xfff>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usbphy1 { + tx-d-cal = <0x5>; +}; + +&usbphy2 { + tx-d-cal = <0x5>; +}; + +&usdhc2 { + non-removable; + disable-wp; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,wdog_b; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index f1a1021f10..9d91f9ab44 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -540,6 +540,18 @@ config TARGET_SKSIMX6 bool "sks-imx6" select SUPPORT_SPL +config TARGET_SOMLABS_VISIONSOM_6ULL + bool "visionsom-6ull" + select MX6ULL + select BOARD_LATE_INIT + select DM + select DM_ETH + select DM_GPIO + select DM_MMC + select DM_SERIAL + select DM_THERMAL + imply CMD_DM + config TARGET_TBS2910 bool "TBS2910 Matrix ARM mini PC" @@ -694,6 +706,7 @@ source "board/logicpd/imx6/Kconfig" source "board/seco/Kconfig" source "board/sks-kinkel/sksimx6/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig" +source "board/somlabs/visionsom-6ull/Kconfig" source "board/technexion/pico-imx6/Kconfig" source "board/technexion/pico-imx6ul/Kconfig" source "board/tbs/tbs2910/Kconfig" diff --git a/board/somlabs/visionsom-6ull/Kconfig b/board/somlabs/visionsom-6ull/Kconfig new file mode 100644 index 0000000000..37408aa798 --- /dev/null +++ b/board/somlabs/visionsom-6ull/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SOMLABS_VISIONSOM_6ULL + +config SYS_BOARD + default "visionsom-6ull" + +config SYS_VENDOR + default "somlabs" + +config SYS_CONFIG_NAME + default "somlabs_visionsom_6ull" + +endif diff --git a/board/somlabs/visionsom-6ull/MAINTAINERS b/board/somlabs/visionsom-6ull/MAINTAINERS new file mode 100644 index 0000000000..905c000bc4 --- /dev/null +++ b/board/somlabs/visionsom-6ull/MAINTAINERS @@ -0,0 +1,6 @@ +VISIONSOM-6ULL BOARD +M: Arkadiusz Karas +S: Maintained +F: board/somlabs/visionsom-6ull/ +F: include/configs/somlabs_visionsom_6ull.h +F: configs/somlabs_visionsom_6ull_defconfig diff --git a/board/somlabs/visionsom-6ull/Makefile b/board/somlabs/visionsom-6ull/Makefile new file mode 100644 index 0000000000..9c3768aa45 --- /dev/null +++ b/board/somlabs/visionsom-6ull/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2019 Arkadiusz Karas + +obj-y := visionsom-6ull.o diff --git a/board/somlabs/visionsom-6ull/imximage.cfg b/board/somlabs/visionsom-6ull/imximage.cfg new file mode 100644 index 0000000000..b49a2df6dd --- /dev/null +++ b/board/somlabs/visionsom-6ull/imximage.cfg @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 A. Karas + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : sd + */ + +BOOT_FROM sd + +/* + * Secure boot support + */ +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Micron MT41K256M16TW-107 */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000000 +DATA 4 0x021B083C 0x41570155 +DATA 4 0x021B0848 0x4040474A +DATA 4 0x021B0850 0x40405550 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00921012 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D0B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B0890 0x23400A38 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 diff --git a/board/somlabs/visionsom-6ull/visionsom-6ull.c b/board/somlabs/visionsom-6ull/visionsom-6ull.c new file mode 100644 index 0000000000..bc7257be40 --- /dev/null +++ b/board/somlabs/visionsom-6ull/visionsom-6ull.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017-2019 A. Karas, SomLabs + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FEC_MXC +static int setup_fec(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(0, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int mmc_map_to_kernel_blk(int devno) +{ + return devno; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + if (is_cpu_type(MXC_CPU_MX6ULL)) + env_set("board", "visionsom-6ull"); + else + env_set("board", "visionsom-6ul"); + + return 0; +} + +int checkboard(void) +{ + printf("Board: SoMLabs VisionSOM-6UL%s\n", + is_cpu_type(MXC_CPU_MX6ULL) ? "L" : ""); + + return 0; +} diff --git a/configs/somlabs_visionsom_6ull_defconfig b/configs/somlabs_visionsom_6ull_defconfig new file mode 100644 index 0000000000..e39c03573a --- /dev/null +++ b/configs/somlabs_visionsom_6ull_defconfig @@ -0,0 +1,49 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_TARGET_SOMLABS_VISIONSOM_6ULL=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xC0000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/somlabs/visionsom-6ull/imximage.cfg" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +# CONFIG_CMD_MDIO is not set +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-somlabs-visionsom" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_LZO=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h new file mode 100644 index 0000000000..6759f24c08 --- /dev/null +++ b/include/configs/somlabs_visionsom_6ull.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017-2019 A. Karas, SomLabs + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the SoMlabs VisionSOM 6ULL board. + */ +#ifndef __SOMLABS_VISIONSOM_6ULL_H +#define __SOMLABS_VISIONSOM_6ULL_H + +#include +#include +#include "mx6_common.h" +#include + +/* SPL options */ +#include "imx6_spl.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#ifdef CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#endif /* CONFIG_FSL_USDHC */ + +#define CONFIG_CMD_READ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "console=ttymxc0\0" \ + "initrd_addr=0x86800000\0" \ + "fdt_addr=0x83000000\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "splashimage=0x80000000\0" \ + "splashfile=/boot/splash.bmp\0" \ + "mmcdev=1\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk1p1 rootwait rw\0" \ + "setrootmmc=setenv rootspec root=${mmcroot}\0" \ + "setbootscriptmmc=setenv loadbootscript " \ + "load mmc ${mmcdev}:${mmcpart} " \ + "${loadaddr} /boot/${script};\0" \ + "setloadmmc=setenv loadimage load mmc ${mmcdev}:${mmcpart} " \ + "${loadaddr} /boot/${image}; " \ + "setenv loadfdt load mmc ${mmcdev}:${mmcpart} " \ + "${fdt_addr} /boot/${fdt_file};\0" \ + "setbootargs=setenv bootargs console=${console},${baudrate} " \ + "${rootspec}\0" \ + "execbootscript=echo Running bootscript...; source\0" \ + "setfdtfile=setenv fdt_file somlabs-visionsom-6ull.dtb\0" \ + "checkbootdev=run setbootscriptmmc; " \ + "run setrootmmc; " \ + "run setloadmmc; " \ + +#define CONFIG_BOOTCOMMAND \ + "run setfdtfile; " \ + "run checkbootdev; " \ + "run loadfdt;" \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run setbootargs; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "fi; " \ + "fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* environment organization */ +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth0" +#endif + +#define CONFIG_IMX_THERMAL + +#endif -- cgit v1.2.3 From 68b49056e6b0574d04cb6aa69f7fa7a070aa1d30 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Sat, 18 Jan 2020 16:12:41 +0100 Subject: arm: dts: i.mx8x: add #cooling-cells properties Fix dtb building warnings: Warning (cooling_device_property): /thermal-zones/cpu-thermal0/cooling-maps/map0: Missing property '#cooling-cells' in node /cpus/cpu@0 or bad phandle (referred from cooling-device[0]) Signed-off-by: Anatolij Gustschin Reviewed-by: Stefano Babic Reviewed-by: Fabio Estevam --- arch/arm/dts/fsl-imx8-ca35.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/fsl-imx8-ca35.dtsi b/arch/arm/dts/fsl-imx8-ca35.dtsi index 28bc32c8b7..9af8b1511c 100644 --- a/arch/arm/dts/fsl-imx8-ca35.dtsi +++ b/arch/arm/dts/fsl-imx8-ca35.dtsi @@ -18,6 +18,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&A35_L2>; + #cooling-cells = <2>; }; A35_1: cpu@1 { @@ -26,6 +27,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&A35_L2>; + #cooling-cells = <2>; }; A35_2: cpu@2 { @@ -34,6 +36,7 @@ reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&A35_L2>; + #cooling-cells = <2>; }; A35_3: cpu@3 { @@ -42,6 +45,7 @@ reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&A35_L2>; + #cooling-cells = <2>; }; A35_L2: l2-cache0 { -- cgit v1.2.3 From d7e5d97207392106426fe1b84e95533737f922cc Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 17 Jan 2020 08:58:46 -0300 Subject: mx7ulp_evk_plugin: Disable CONFIG_NET Currently the following build warning is seen: ===================== WARNING ====================== This board does not use CONFIG_DM_ETH (Driver Model for Ethernet drivers). Please update the board to use CONFIG_DM_ETH before the v2020.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. =================================================== Since the mx7ulp-evk board does not have networking support, explicitly disable networking. Signed-off-by: Fabio Estevam --- configs/mx7ulp_evk_plugin_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig index 1c37d6bc02..54ff93ea5e 100644 --- a/configs/mx7ulp_evk_plugin_defconfig +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -17,6 +17,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk" CONFIG_ENV_IS_IN_MMC=y +# CONFIG_NET is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_DM_GPIO=y -- cgit v1.2.3 From 30b8eb5ee684013ce1b3e9fc50b4bf7adec95817 Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Fri, 17 Jan 2020 10:50:25 +0100 Subject: mx7ulp: soc: s_init should only be executed once On SPL enabled systems, the current s_init code (wdog, clock and ldo init) is executed twice (by SPL and u-boot). This is not necessary and might lead to boot issues (ie, starting PMC1 when it is already running). Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Fabio Estevam --- arch/arm/mach-imx/mx7ulp/soc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 8345b01398..316262f71b 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -117,6 +117,7 @@ void init_wdog(void) disable_wdog(WDG2_RBASE); } +#if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD)) #if defined(CONFIG_LDO_ENABLED_MODE) static void init_ldo_mode(void) { @@ -174,6 +175,7 @@ void s_init(void) #endif return; } +#endif #ifndef CONFIG_ULP_WATCHDOG void reset_cpu(ulong addr) -- cgit v1.2.3 From e2b14bf4ba0a151956e89c8243c10b08485a875f Mon Sep 17 00:00:00 2001 From: Joris Offouga Date: Thu, 16 Jan 2020 17:41:43 +0100 Subject: mx7dsabre: Fix dm probe pmic With commit 0d52bab4621 ("mx7dsabre: Enable DM_ETH") Device Tree has been update and change pfuze3000 node Signed-off-by: Joris Offouga Reviewed-by: Fabio Estevam --- board/freescale/mx7dsabresd/mx7dsabresd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 835eed3316..41c620795c 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -264,7 +264,7 @@ int power_init_board(void) struct udevice *dev; int ret, dev_id, rev_id; - ret = pmic_get("pfuze3000@08", &dev); + ret = pmic_get("pfuze3000@8", &dev); if (ret == -ENODEV) return 0; if (ret != 0) -- cgit v1.2.3 From 11c04aa6715b90bb59c196e810a2e883455c4598 Mon Sep 17 00:00:00 2001 From: Flavio Suligoi Date: Thu, 16 Jan 2020 09:29:38 +0100 Subject: imx: imx8mm_evk: remove hdmi fw info from README The imx8mm doesn't require the hdmi firmware. Update also the fw version. Signed-off-by: Flavio Suligoi Reviewed-by: Peng Fan --- board/freescale/imx8mm_evk/README | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/imx8mm_evk/README b/board/freescale/imx8mm_evk/README index c908c0adc4..9921b35989 100644 --- a/board/freescale/imx8mm_evk/README +++ b/board/freescale/imx8mm_evk/README @@ -15,12 +15,12 @@ branch: imx_4.19.35_1.0.0 $ make PLAT=imx8mm bl31 $ cp build/imx8mm/release/bl31.bin $(builddir) -Get the ddr and hdmi firmware +Get the ddr firmware ============================= $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin $ chmod +x firmware-imx-8.0.bin $ ./firmware-imx-8.0 -$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir) +$ cp firmware-imx-8.0/firmware/ddr/synopsys/lpddr4*.bin $(builddir) Build U-Boot ============ -- cgit v1.2.3 From 4cd1f979b2b4dfd799131ba21366b905a8600914 Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Wed, 15 Jan 2020 18:50:04 +0100 Subject: arm: dts: imx7ulp-evk: remove mux value from pad configuration The mux mode is embedded in the PAD definition and therefore there is no need to repeat it in the PAD configuration value (more over since this information will be masked out when the configuration value is applied). Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Fabio Estevam --- arch/arm/dts/imx7ulp-evk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/imx7ulp-evk.dts b/arch/arm/dts/imx7ulp-evk.dts index 08a682f314..8f6a935e24 100644 --- a/arch/arm/dts/imx7ulp-evk.dts +++ b/arch/arm/dts/imx7ulp-evk.dts @@ -156,7 +156,7 @@ pinctrl_backlight: backlight_grp { fsl,pins = < - IMX7ULP_PAD_PTF2__PTF2 0x20100 + IMX7ULP_PAD_PTF2__PTF2 0x20000 >; }; -- cgit v1.2.3 From 5255f85c6efb62ec962e216a6d908f800622d60e Mon Sep 17 00:00:00 2001 From: Alifer Moraes Date: Tue, 14 Jan 2020 11:22:57 -0300 Subject: imx8mm_evk: Include sys_proto.h header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add sys_proto.h header file to fix the following sparse warning: board/freescale/imx8mm_evk/imx8mm_evk.c:59:5: warning: no previous prototype for ‘board_mmc_get_env_dev’ [-Wmissing-prototypes] Signed-off-by: Alifer Moraes --- board/freescale/imx8mm_evk/imx8mm_evk.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c index a0af550f5e..c5fd940eeb 100644 --- a/board/freescale/imx8mm_evk/imx8mm_evk.c +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c @@ -8,6 +8,7 @@ #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; -- cgit v1.2.3 From 1e994e2f3ddb458743b43235b5d201e635d0126b Mon Sep 17 00:00:00 2001 From: Flavio Suligoi Date: Thu, 16 Jan 2020 11:32:17 +0100 Subject: fsl: fix typo in header file Signed-off-by: Flavio Suligoi --- include/fsl_validate.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/fsl_validate.h b/include/fsl_validate.h index c7b3ffc67c..06951fccf4 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -212,7 +212,7 @@ struct fsl_secboot_sg_table { /* ESBC global structure. * Data to be used across verification of different images. - * Stores follwoing Data: + * Stores following Data: * IE Table */ struct fsl_secboot_glb { -- cgit v1.2.3 From 7132d38cbe45015ac5a4b099b2b1f4b656a5d854 Mon Sep 17 00:00:00 2001 From: Flavio Suligoi Date: Thu, 16 Jan 2020 11:32:18 +0100 Subject: imx: fix typo in header file Signed-off-by: Flavio Suligoi --- include/imximage.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/imximage.h b/include/imximage.h index ace5cf8601..1ed3284f15 100644 --- a/include/imximage.h +++ b/include/imximage.h @@ -73,7 +73,7 @@ enum imximage_cmd { CMD_CHECK_BITS_CLR, CMD_CSF, CMD_PLUGIN, - /* Follwoing on i.MX8MQ/MM */ + /* Following on i.MX8MQ/MM */ CMD_FIT, CMD_SIGNED_HDMI, CMD_LOADER, -- cgit v1.2.3 From c27483fcb0b525df45f33160300dda1149a6c69a Mon Sep 17 00:00:00 2001 From: Alifer Moraes Date: Tue, 14 Jan 2020 15:54:59 -0300 Subject: imx8m: clock_imx8mm: Staticize functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Functions fracpll_configure(), decode_intpll(), decode_fracpll(), get_root_src_clk() and get_root_clk() are used only in the scope of this file, so make them static to fix the following sparse warnings: arch/arm/mach-imx/imx8m/clock_imx8mm.c:50:5: warning: no previous prototype for ‘fracpll_configure’ [-Wmissing-prototypes] arch/arm/mach-imx/imx8m/clock_imx8mm.c:271:5: warning: no previous prototype for ‘decode_intpll’ [-Wmissing-prototypes] arch/arm/mach-imx/imx8m/clock_imx8mm.c:418:5: warning: no previous prototype for ‘decode_fracpll’ [-Wmissing-prototypes] arch/arm/mach-imx/imx8m/clock_imx8mm.c:483:5: warning: no previous prototype for ‘get_root_src_clk’ [-Wmissing-prototypes] arch/arm/mach-imx/imx8m/clock_imx8mm.c:527:5: warning: no previous prototype for ‘get_root_clk’ [-Wmissing-prototypes] Signed-off-by: Alifer Moraes --- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index ca4b4c05ab..c423ac0058 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -47,7 +47,7 @@ static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { PLL_1443X_RATE(100000000U, 300, 9, 3, 0), }; -int fracpll_configure(enum pll_clocks pll, u32 freq) +static int fracpll_configure(enum pll_clocks pll, u32 freq) { int i; u32 tmp, div_val; @@ -268,7 +268,7 @@ u32 imx_get_uartclk(void) return 24000000U; } -u32 decode_intpll(enum clk_root_src intpll) +static u32 decode_intpll(enum clk_root_src intpll) { u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask; u32 main_div, pre_div, post_div, div; @@ -415,7 +415,7 @@ u32 decode_intpll(enum clk_root_src intpll) return lldiv(freq, pre_div * (1 << post_div) * div); } -u32 decode_fracpll(enum clk_root_src frac_pll) +static u32 decode_fracpll(enum clk_root_src frac_pll) { u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1; u32 main_div, pre_div, post_div, k; @@ -480,7 +480,7 @@ u32 decode_fracpll(enum clk_root_src frac_pll) 65536 * pre_div * (1 << post_div)); } -u32 get_root_src_clk(enum clk_root_src root_src) +static u32 get_root_src_clk(enum clk_root_src root_src) { switch (root_src) { case OSC_24M_CLK: @@ -524,7 +524,7 @@ u32 get_root_src_clk(enum clk_root_src root_src) return 0; } -u32 get_root_clk(enum clk_root_index clock_id) +static u32 get_root_clk(enum clk_root_index clock_id) { enum clk_root_src root_src; u32 post_podf, pre_podf, root_src_clk; -- cgit v1.2.3 From 62cdfdcc81dc0af1ebabbf589ddb1ecc36351a47 Mon Sep 17 00:00:00 2001 From: Alifer Moraes Date: Tue, 14 Jan 2020 15:55:00 -0300 Subject: mx8mm_evk: spl: Staticize functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Functions spl_dram_init() and power_init_board() are used only in the scope of this file, so make them static to fix the following sparse warnings: board/freescale/imx8mm_evk/spl.c:40:6: warning: no previous prototype for ‘spl_dram_init’ [-Wmissing-prototypes] board/freescale/imx8mm_evk/spl.c:85:5: warning: no previous prototype for ‘power_init_board’ [-Wmissing-prototypes] Signed-off-by: Alifer Moraes --- board/freescale/imx8mm_evk/spl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c index 2d08f9a563..e28f795676 100644 --- a/board/freescale/imx8mm_evk/spl.c +++ b/board/freescale/imx8mm_evk/spl.c @@ -37,7 +37,7 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) } } -void spl_dram_init(void) +static void spl_dram_init(void) { ddr_init(&dram_timing); } @@ -82,7 +82,7 @@ int board_early_init_f(void) return 0; } -int power_init_board(void) +static int power_init_board(void) { struct udevice *dev; int ret; -- cgit v1.2.3 From 40eeb9c412572b8f7adf6155d5e6f4ef138fd376 Mon Sep 17 00:00:00 2001 From: Alifer Moraes Date: Tue, 14 Jan 2020 15:55:01 -0300 Subject: spl: Add prototype to function spl_board_boot_device() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add prototype to function spl_board_boot_device to fix the following sparse warning: board/freescale/imx8mm_evk/spl.c:26:5: warning: no previous prototype for ‘spl_board_boot_device’ [-Wmissing-prototypes] Signed-off-by: Alifer Moraes --- include/spl.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/spl.h b/include/spl.h index cd4669f5aa..6087cd793c 100644 --- a/include/spl.h +++ b/include/spl.h @@ -269,6 +269,7 @@ int spl_parse_image_header(struct spl_image_info *spl_image, void spl_board_prepare_for_linux(void); void spl_board_prepare_for_boot(void); int spl_board_ubi_load_image(u32 boot_device); +int spl_board_boot_device(u32 boot_device); /** * jump_to_image_linux() - Jump to a Linux kernel from SPL -- cgit v1.2.3 From 09f0c5069066a8332e419c5f5052c2900819eb47 Mon Sep 17 00:00:00 2001 From: Alifer Moraes Date: Thu, 16 Jan 2020 12:43:06 -0300 Subject: imx8qxp_mek: Include fdt_support.h header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Include fdt_support.h header file to fix the following sparse warning: board/freescale/imx8qxp_mek/imx8qxp_mek.c:129:5: warning: no previous prototype for ‘ft_board_setup’ [-Wmissing-prototypes] Signed-off-by: Alifer Moraes --- board/freescale/imx8qxp_mek/imx8qxp_mek.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c index 194eb60cd3..8e731ec32e 100644 --- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c +++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include -- cgit v1.2.3 From c83c00ae675ca5815ca04d7cad411f4900efff5e Mon Sep 17 00:00:00 2001 From: Alifer Moraes Date: Thu, 16 Jan 2020 12:43:07 -0300 Subject: imx8qm_mek: Include fdt_support.h header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Include fdt_support.h header file to fix the following sparse warning: board/freescale/imx8qm_mek/imx8qm_mek.c:116:5: warning: no previous prototype for ‘ft_board_setup’ [-Wmissing-prototypes] Signed-off-by: Alifer Moraes --- board/freescale/imx8qm_mek/imx8qm_mek.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c index 667a2743a6..139f416d1f 100644 --- a/board/freescale/imx8qm_mek/imx8qm_mek.c +++ b/board/freescale/imx8qm_mek/imx8qm_mek.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include -- cgit v1.2.3 From f04887f73b0dc711d8c01efdf6c6bb53e597cde6 Mon Sep 17 00:00:00 2001 From: Alifer Moraes Date: Thu, 16 Jan 2020 12:45:33 -0300 Subject: imx8qm_rom7720_a1: Remove unused function detail_board_ddr_info() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit detail_board_ddr_info() is not used anywhere, so simply remove it. This function is only used by Layerscape, not by i.MX. This was detected by the following sparse warning: board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c:110:6: warning: no previous prototype for ‘detail_board_ddr_info’ [-Wmissing-prototypes] Signed-off-by: Alifer Moraes Reviewed-by: Oliver Graute --- board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c index 2f97d5ce96..8bcbcc0e3f 100644 --- a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c +++ b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c @@ -107,11 +107,6 @@ int board_init(void) return 0; } -void detail_board_ddr_info(void) -{ - puts("\nDDR "); -} - /* * Board specific reset that is system reset. */ -- cgit v1.2.3 From 8edd0f8a7a5bcdb1495b5e4d7b4b905f6397dfe8 Mon Sep 17 00:00:00 2001 From: Alifer Moraes Date: Thu, 16 Jan 2020 12:43:08 -0300 Subject: imx8qm_mek: Remove unused function detail_board_ddr_info() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit detail_board_ddr_info() is not used anywhere, so simply remove it. This function is only used by Layerscape, not by i.MX. This was detected by the following sparse warning: board/freescale/imx8qm_mek/imx8qm_mek.c:102:6: warning: no previous prototype for ‘detail_board_ddr_info’ [-Wmissing-prototypes] --- board/freescale/imx8qm_mek/imx8qm_mek.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c index 139f416d1f..3f6a183157 100644 --- a/board/freescale/imx8qm_mek/imx8qm_mek.c +++ b/board/freescale/imx8qm_mek/imx8qm_mek.c @@ -100,11 +100,6 @@ int board_init(void) return 0; } -void detail_board_ddr_info(void) -{ - puts("\nDDR "); -} - /* * Board specific reset that is system reset. */ -- cgit v1.2.3 From 122fbf469a2e33c3c88f59e23bbff999a6906d26 Mon Sep 17 00:00:00 2001 From: Alifer Moraes Date: Thu, 16 Jan 2020 12:43:09 -0300 Subject: imx8qxp_mek: Remove unused function detail_board_ddr_info() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit detail_board_ddr_info() is not used anywhere, so simply remove it. This function is only used by Layerscape, not by i.MX. This was detected by the following sparse warning: board/freescale/imx8qxp_mek/imx8qxp_mek.c:115:6: warning: no previous prototype for ‘detail_board_ddr_info’ [-Wmissing-prototypes] Signed-off-by: Alifer Moraes --- board/freescale/imx8qxp_mek/imx8qxp_mek.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c index 8e731ec32e..f8dd6d0bb0 100644 --- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c +++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c @@ -113,11 +113,6 @@ int board_init(void) return 0; } -void detail_board_ddr_info(void) -{ - puts("\nDDR "); -} - /* * Board specific reset that is system reset. */ -- cgit v1.2.3 From 96159bef6fd86a399e7734c6ca38ba9e535da5f0 Mon Sep 17 00:00:00 2001 From: Alifer Moraes Date: Thu, 16 Jan 2020 12:46:48 -0300 Subject: apalis-imx8: Remove unused function detail_board_ddr_info() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit detail_board_ddr_info() is not used anywhere, so simply remove it. This function is only used by Layerscape, not by i.MX. This was detected by the following sparse warning: board/toradex/apalis-imx8/apalis-imx8.c:92:6: warning: no previous prototype for ‘detail_board_ddr_info’ [-Wmissing-prototypes] Signed-off-by: Alifer Moraes --- board/toradex/apalis-imx8/apalis-imx8.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index 0483041187..a42fbb722a 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -89,11 +89,6 @@ int board_init(void) return 0; } -void detail_board_ddr_info(void) -{ - puts("\nDDR "); -} - /* * Board specific reset that is system reset. */ -- cgit v1.2.3 From 419603ca2d7a8065029a838cb0227ad7bfc5e1d3 Mon Sep 17 00:00:00 2001 From: Alifer Moraes Date: Thu, 16 Jan 2020 12:46:49 -0300 Subject: colibri-imx8x: Remove unused function detail_board_ddr_info() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit detail_board_ddr_info() is not used anywhere, so simply remove it. This function is only used by Layerscape, not by i.MX. This was detected by the following sparse warning: board/toradex/colibri-imx8x/colibri-imx8x.c:104:6: warning: no previous prototype for ‘detail_board_ddr_info’ [-Wmissing-prototypes] Signed-off-by: Alifer Moraes --- board/toradex/colibri-imx8x/colibri-imx8x.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index adeee67643..f9e947eede 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -101,11 +101,6 @@ int board_init(void) return 0; } -void detail_board_ddr_info(void) -{ - puts("\nDDR "); -} - /* * Board specific reset that is system reset. */ -- cgit v1.2.3