From e9cef6c8ce31ff51099f23e2d628483cf762d728 Mon Sep 17 00:00:00 2001 From: "yanhong.wang" Date: Mon, 11 Apr 2022 15:24:56 +0800 Subject: clk:starfive-jh7110: Add clock driver for JH7110 Add a clock driver for StarFive JH7110 Soc platform. Signed-off-by: yanhong.wang --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/starfive/Kconfig | 15 + drivers/clk/starfive/Makefile | 3 + drivers/clk/starfive/clk-jh7110.c | 688 +++++++++++++++++++++ include/dt-bindings/clock/starfive-jh7110-clkgen.h | 393 ++++++++++++ include/dt-bindings/clock/starfive-jh7110-vout.h | 66 ++ 7 files changed, 1167 insertions(+) create mode 100644 drivers/clk/starfive/Kconfig create mode 100644 drivers/clk/starfive/Makefile create mode 100644 drivers/clk/starfive/clk-jh7110.c create mode 100644 include/dt-bindings/clock/starfive-jh7110-clkgen.h create mode 100644 include/dt-bindings/clock/starfive-jh7110-vout.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index baac8d281e..67569c1595 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -194,6 +194,7 @@ source "drivers/clk/owl/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/sunxi/Kconfig" source "drivers/clk/sifive/Kconfig" +source "drivers/clk/starfive/Kconfig" source "drivers/clk/tegra/Kconfig" source "drivers/clk/ti/Kconfig" source "drivers/clk/uniphier/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 711ae5bc29..9ce429831c 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -53,3 +53,4 @@ obj-$(CONFIG_STM32H7) += clk_stm32h7.o obj-$(CONFIG_CLK_VERSAL) += clk_versal.o obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o +obj-$(CONFIG_CLK_JH7110) += starfive/ diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig new file mode 100644 index 0000000000..93fa380772 --- /dev/null +++ b/drivers/clk/starfive/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0 + +config SPL_CLK_JH7110 + bool "SPL clock support for JH7110" + depends on TARGET_STARFIVE_VISIONFIVE && SPL + select SPL_CLK + select SPL_CLK_CCF + help + This enables SPL DM/DTS support for clock driver in JH7110 + +config CLK_JH7110 + bool "Starfive JH7110 clock support" + depends on CLK && CLK_CCF && TARGET_STARFIVE_VISIONFIVE + help + This enables support clock driver for Starfive JH7110 SoC platform. diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile new file mode 100644 index 0000000000..64ce31b747 --- /dev/null +++ b/drivers/clk/starfive/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_$(SPL_TPL_)CLK_JH7110) += clk-jh7110.o diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c new file mode 100644 index 0000000000..fb717b09f6 --- /dev/null +++ b/drivers/clk/starfive/clk-jh7110.c @@ -0,0 +1,688 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: yanhong + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define STARFIVE_CLK_ENABLE_SHIFT 31 /*[31]*/ +#define STARFIVE_CLK_INVERT_SHIFT 30 /*[30]*/ +#define STARFIVE_CLK_MUX_SHIFT 24 /*[29:24]*/ +#define STARFIVE_CLK_DIV_SHIFT 0 /*[23:0]*/ + +#define SYS_OFFSET(id) (id * 4) +#define STG_OFFSET(id) ((id - JH7110_CLK_SYS_REG_END) * 4) +#define AON_OFFSET(id) ((id - JH7110_CLK_STG_REG_END) * 4) + +#define JH7110_PLL0 (JH7110_CLK_RTC+1) +#define JH7110_PLL1 (JH7110_CLK_RTC+2) +#define JH7110_PLL2 (JH7110_CLK_RTC+3) + +struct jh7110_clk_priv { + void __iomem *sys; + void __iomem *stg; + void __iomem *aon; +}; + +static const char *cpu_root_sels[2] = { + [0] = "osc", + [1] = "pll0_out", +}; + +static const char *perh_root_sels[2] = { + [0] = "pll0_out", + [1] = "pll2_out", +}; + +static const char *bus_root_sels[2] = { + [0] = "osc", + [1] = "pll2_out", +}; + +static const char *qspi_ref_sels[2] = { + [0] = "osc", + [1] = "clk_qspi_ref_src", +}; + +static const char *gmac5_tx_sels[2] = { + [0] = "gmac1_gtxclk", + [1] = "gmac1_rmii_rtx", +}; + +static const char *aon_apb_func_sels[2] = { + [0] = "osc_div4", + [1] = "osc", +}; + +static const char *u0_dw_gmac5_axi64_clk_tx_sels[2] = { + [0] = "gmac0_gtxclk", + [1] = "gmac0_rmii_rtx", +}; + +static ulong starfive_clk_get_rate(struct clk *clk) +{ + struct clk *c; + int ret; + + debug("%s(#%lu)\n", __func__, clk->id); + + ret = clk_get_by_id(clk->id, &c); + if (ret) + return ret; + + return clk_get_rate(c); +} + +static ulong starfive_clk_set_rate(struct clk *clk, unsigned long rate) +{ + struct clk *c; + int ret; + + debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate); + + ret = clk_get_by_id(clk->id, &c); + if (ret) + return ret; + + return clk_set_rate(c, rate); +} + +static int __starfive_clk_enable(struct clk *clk, bool enable) +{ + struct clk *c; + int ret; + + debug("%s(#%lu) en: %d\n", __func__, clk->id, enable); + + ret = clk_get_by_id(clk->id, &c); + if (ret) + return ret; + + if (enable) + ret = clk_enable(c); + else + ret = clk_disable(c); + + return ret; +} + +static int starfive_clk_disable(struct clk *clk) +{ + return __starfive_clk_enable(clk, 0); +} + +static int starfive_clk_enable(struct clk *clk) +{ + return __starfive_clk_enable(clk, 1); +} + +static int starfive_clk_set_parent(struct clk *clk, struct clk *parent) +{ + struct clk *c, *cp; + int ret; + + debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id); + + ret = clk_get_by_id(clk->id, &c); + if (ret) + return ret; + + ret = clk_get_by_id(parent->id, &cp); + if (ret) + return ret; + + ret = clk_set_parent(c, cp); + c->dev->parent = cp->dev; + + return ret; +} + +static const struct clk_ops starfive_clk_ops = { + .set_rate = starfive_clk_set_rate, + .get_rate = starfive_clk_get_rate, + .enable = starfive_clk_enable, + .disable = starfive_clk_disable, + .set_parent = starfive_clk_set_parent, +}; + +static struct clk *starfive_clk_mux(void __iomem *reg, + const char *name, + unsigned int offset, + u8 width, + const char * const *parent_names, + u8 num_parents) +{ + return clk_register_mux(NULL, name, parent_names, num_parents, 0, + reg + offset, STARFIVE_CLK_MUX_SHIFT, width, 0); +} + +static struct clk *starfive_clk_gate(void __iomem *reg, + const char *name, + const char *parent_name, + unsigned int offset) +{ + return clk_register_gate(NULL, name, parent_name, 0, reg+offset, + STARFIVE_CLK_ENABLE_SHIFT, 0, NULL); +} + +static struct clk *starfive_clk_fix_factor(void __iomem *reg, + const char *name, + const char *parent_name, + unsigned int mult, + unsigned int div) +{ + return clk_register_fixed_factor(NULL, name, parent_name, + 0, mult, div); + +} + +static struct clk *starfive_clk_divider(void __iomem *reg, + const char *name, + const char *parent_name, + unsigned int offset, + u8 width) +{ + return clk_register_divider(NULL, name, parent_name, 0, reg+offset, 0, + width, CLK_DIVIDER_ONE_BASED); +} + + +static struct clk *starfive_clk_composite(void __iomem *reg, + const char *name, + const char * const *parent_names, + unsigned int num_parents, + unsigned int offset, + unsigned int mux_width, + unsigned int gate_width, + unsigned int div_width) +{ + struct clk *clk = ERR_PTR(-ENOMEM); + struct clk_divider *div = NULL; + struct clk_gate *gate = NULL; + struct clk_mux *mux = NULL; + int mask_arry[4] = {0x1, 0x3, 0x7, 0xF}; + int mask; + + if (mux_width) { + if (mux_width > 4) + goto fail; + else + mask = mask_arry[mux_width-1]; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + goto fail; + + mux->reg = reg + offset; + mux->mask = mask; + mux->shift = STARFIVE_CLK_MUX_SHIFT; + mux->num_parents = num_parents; + mux->flags = 0; + mux->parent_names = parent_names; + } + + if (gate_width) { + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + + if (!gate) + goto fail; + + gate->reg = reg + offset; + gate->bit_idx = STARFIVE_CLK_ENABLE_SHIFT; + gate->flags = 0; + } + + if (div_width) { + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + goto fail; + + div->reg = reg + offset; + div->shift = STARFIVE_CLK_DIV_SHIFT; + div->width = div_width; + div->flags = CLK_DIVIDER_ONE_BASED; + div->table = NULL; + } + + clk = clk_register_composite(NULL, name, + parent_names, num_parents, + &mux->clk, &clk_mux_ops, + &div->clk, &clk_divider_ops, + &gate->clk, &clk_gate_ops, 0); + + if (IS_ERR(clk)) + goto fail; + + return clk; + +fail: + kfree(gate); + kfree(div); + kfree(mux); + return ERR_CAST(clk); +} + +static struct clk *starfive_clk_fix_parent_composite(void __iomem *reg, + const char *name, + const char *parent_names, + unsigned int offset, + unsigned int mux_width, + unsigned int gate_width, + unsigned int div_width) +{ + const char * const *parents; + + parents = &parent_names; + + return starfive_clk_composite(reg, name, parents, 1, offset, + mux_width, gate_width, div_width); +} + +static struct clk *starfive_clk_gate_divider(void __iomem *reg, + const char *name, + const char *parent, + unsigned int offset, + unsigned int width) +{ + const char * const *parent_names; + + parent_names = &parent; + + return starfive_clk_composite(reg, name, parent_names, 1, + offset, 0, 1, width); +} + +static struct clk *starfive_clk_gate_dis(void __iomem *reg, + const char *name, + const char *parent_name, + unsigned int offset) +{ + return clk_register_gate(NULL, name, parent_name, 0, reg+offset, + STARFIVE_CLK_ENABLE_SHIFT, + CLK_GATE_SET_TO_DISABLE, NULL); +} + +static int jh7110_clk_init(struct udevice *dev) +{ + struct jh7110_clk_priv *priv = dev_get_priv(dev); + + clk_dm(JH7110_PLL0, + starfive_clk_fix_factor(priv->sys, + "pll0_out", "osc", 52, 1)); + clk_dm(JH7110_PLL1, + starfive_clk_fix_factor(priv->sys, + "pll1_out", "osc", 44, 1)); + clk_dm(JH7110_PLL2, + starfive_clk_fix_factor(priv->sys, + "pll2_out", "osc", 51, 1)); + + /*root*/ + clk_dm(JH7110_CPU_ROOT, + starfive_clk_mux(priv->sys, "cpu_root", + SYS_OFFSET(JH7110_CPU_ROOT), 1, + cpu_root_sels, ARRAY_SIZE(cpu_root_sels))); + clk_dm(JH7110_CPU_CORE, + starfive_clk_divider(priv->sys, + "cpu_core", "cpu_root", + SYS_OFFSET(JH7110_CPU_CORE), 3)); + clk_dm(JH7110_CPU_BUS, + starfive_clk_divider(priv->sys, + "cpu_bus", "cpu_core", + SYS_OFFSET(JH7110_CPU_BUS), 2)); + clk_dm(JH7110_DDR_ROOT, + starfive_clk_fix_factor(priv->sys, + "ddr_root", "pll1_out", 1, 1)); + clk_dm(JH7110_GMACUSB_ROOT, + starfive_clk_fix_factor(priv->sys, + "gmacusb_root", "pll0_out", 1, 1)); + clk_dm(JH7110_PERH_ROOT, + starfive_clk_mux(priv->sys, "perh_root", + SYS_OFFSET(JH7110_PERH_ROOT), 1, + perh_root_sels, ARRAY_SIZE(perh_root_sels))); + + clk_dm(JH7110_BUS_ROOT, + starfive_clk_mux(priv->sys, "bus_root", + SYS_OFFSET(JH7110_BUS_ROOT), 1, + bus_root_sels, ARRAY_SIZE(bus_root_sels))); + clk_dm(JH7110_AXI_CFG0, + starfive_clk_divider(priv->sys, + "axi_cfg0", "bus_root", + SYS_OFFSET(JH7110_AXI_CFG0), 2)); + clk_dm(JH7110_STG_AXIAHB, + starfive_clk_divider(priv->sys, + "stg_axiahb", "axi_cfg0", + SYS_OFFSET(JH7110_STG_AXIAHB), 2)); + clk_dm(JH7110_AHB0, + starfive_clk_gate(priv->sys, + "ahb0", "stg_axiahb", + SYS_OFFSET(JH7110_AHB0))); + clk_dm(JH7110_AHB1, + starfive_clk_gate(priv->sys, + "ahb1", "stg_axiahb", + SYS_OFFSET(JH7110_AHB1))); + clk_dm(JH7110_APB_BUS_FUNC, + starfive_clk_divider(priv->sys, + "apb_bus_func", "stg_axiahb", + SYS_OFFSET(JH7110_APB_BUS_FUNC), 4)); + + clk_dm(JH7110_OSC_DIV4, + starfive_clk_divider(priv->aon, + "osc_div4", "osc", + AON_OFFSET(JH7110_OSC_DIV4), 3)); + clk_dm(JH7110_AON_APB_FUNC, + starfive_clk_mux(priv->aon, "aon_apb_func", + AON_OFFSET(JH7110_AON_APB_FUNC), 1, + aon_apb_func_sels, ARRAY_SIZE(aon_apb_func_sels))); + + clk_dm(JH7110_APB_BUS, + starfive_clk_fix_factor(priv->sys, + "apb_bus", "aon_apb_func", 1, 1)); + clk_dm(JH7110_APB0, + starfive_clk_gate(priv->sys, + "apb0", "apb_bus", + SYS_OFFSET(JH7110_APB0))); + clk_dm(JH7110_APB12, + starfive_clk_fix_factor(priv->sys, + "apb12", "apb_bus", 1, 1)); + clk_dm(JH7110_AON_APB, + starfive_clk_fix_factor(priv->sys, + "aon_apb", "apb_bus_func", 1, 1)); + + /*hifi4*/ + clk_dm(JH7110_HIFI4_CORE, + starfive_clk_divider(priv->sys, + "hifi4_core", "bus_root", + SYS_OFFSET(JH7110_HIFI4_CORE), 4)); + + /*QSPI*/ + clk_dm(JH7110_QSPI_CLK_AHB, + starfive_clk_gate(priv->sys, + "u0_cdns_qspi_clk_ahb", "ahb1", + SYS_OFFSET(JH7110_QSPI_CLK_AHB))); + clk_dm(JH7110_QSPI_CLK_APB, + starfive_clk_gate(priv->sys, + "u0_cdns_qspi_clk_apb", "apb12", + SYS_OFFSET(JH7110_QSPI_CLK_APB))); + clk_dm(JH7110_QSPI_REF_SRC, + starfive_clk_divider(priv->sys, + "u0_cdns_qspi_ref_src", "gmacusb_root", + SYS_OFFSET(JH7110_QSPI_REF_SRC), 5)); + clk_dm(JH7110_QSPI_CLK_REF, + starfive_clk_composite(priv->sys, + "u0_cdns_qspi_clk_ref", + qspi_ref_sels, ARRAY_SIZE(qspi_ref_sels), + SYS_OFFSET(JH7110_QSPI_CLK_REF), 1, 1, 0)); + + /*SDIO*/ + clk_dm(JH7110_SDIO0_CLK_AHB, + starfive_clk_gate(priv->sys, + "u0_dw_sdio_clk_ahb", "ahb0", + SYS_OFFSET(JH7110_SDIO0_CLK_AHB))); + clk_dm(JH7110_SDIO1_CLK_AHB, + starfive_clk_gate(priv->sys, + "u1_dw_sdio_clk_ahb", "ahb0", + SYS_OFFSET(JH7110_SDIO1_CLK_AHB))); + clk_dm(JH7110_SDIO0_CLK_SDCARD, + starfive_clk_fix_parent_composite(priv->sys, + "u0_dw_sdio_clk_sdcard", "axi_cfg0", + SYS_OFFSET(JH7110_SDIO0_CLK_SDCARD), 0, 1, 4)); + clk_dm(JH7110_SDIO1_CLK_SDCARD, + starfive_clk_fix_parent_composite(priv->sys, + "u1_dw_sdio_clk_sdcard", "axi_cfg0", + SYS_OFFSET(JH7110_SDIO1_CLK_SDCARD), 0, 1, 4)); + + /*STG*/ + clk_dm(JH7110_USB_125M, + starfive_clk_divider(priv->sys, + "usb_125m", "gmacusb_root", + SYS_OFFSET(JH7110_USB_125M), 4)); + + /*GMAC1*/ + clk_dm(JH7110_GMAC5_CLK_AHB, + starfive_clk_gate(priv->sys, + "u1_dw_gmac5_axi64_clk_ahb", "ahb0", + SYS_OFFSET(JH7110_GMAC5_CLK_AHB))); + clk_dm(JH7110_GMAC5_CLK_AXI, + starfive_clk_gate(priv->sys, + "u1_dw_gmac5_axi64_clk_axi", "stg_axiahb", + SYS_OFFSET(JH7110_GMAC5_CLK_AXI))); + clk_dm(JH7110_GMAC_SRC, + starfive_clk_divider(priv->sys, + "gmac_src", "gmacusb_root", + SYS_OFFSET(JH7110_GMAC_SRC), 3)); + clk_dm(JH7110_GMAC1_GTXCLK, + starfive_clk_divider(priv->sys, + "gmac1_gtxclk", "gmacusb_root", + SYS_OFFSET(JH7110_GMAC1_GTXCLK), 4)); + clk_dm(JH7110_GMAC1_RMII_RTX, + starfive_clk_divider(priv->sys, + "gmac1_rmii_rtx", "gmac1_rmii_refin", + SYS_OFFSET(JH7110_GMAC1_RMII_RTX), 5)); + clk_dm(JH7110_GMAC5_CLK_PTP, + starfive_clk_gate_divider(priv->sys, + "u1_dw_gmac5_axi64_clk_ptp", "gmac_src", + SYS_OFFSET(JH7110_GMAC5_CLK_PTP), 5)); + + clk_dm(JH7110_GMAC5_CLK_RMII, + starfive_clk_fix_factor(priv->sys, + "u1_dw_gmac5_axi64_clk_rmii", + "gmac1_rmii_refin", 1, 1)); + + clk_dm(JH7110_GMAC5_CLK_TX, + starfive_clk_composite(priv->sys, + "u1_dw_gmac5_axi64_clk_tx", + gmac5_tx_sels, ARRAY_SIZE(gmac5_tx_sels), + SYS_OFFSET(JH7110_GMAC5_CLK_TX), 1, 1, 0)); + clk_dm(JH7110_GMAC5_CLK_TX_INV, + starfive_clk_gate_dis(priv->sys, + "u1_dw_gmac5_axi64_clk_tx_inv", + "u1_dw_gmac5_axi64_clk_tx", + SYS_OFFSET(JH7110_GMAC5_CLK_TX_INV))); + clk_dm(JH7110_GMAC1_GTXC, + starfive_clk_gate_divider(priv->sys, + "gmac1_gtxc", "gmac1_gtxclk", + SYS_OFFSET(JH7110_GMAC1_GTXC), 6)); + + /*GMAC0*/ + clk_dm(JH7110_AON_AHB, + starfive_clk_fix_factor(priv->sys, "aon_ahb", + "stg_axiahb", 1, 1)); + clk_dm(JH7110_GMAC0_GTXCLK, + starfive_clk_gate_divider(priv->sys, "gmac0_gtxclk", + "gmacusb_root", SYS_OFFSET(JH7110_GMAC0_GTXCLK), 4)); + clk_dm(JH7110_GMAC0_PTP, + starfive_clk_gate_divider(priv->sys, "gmac0_ptp", + "gmac_src", SYS_OFFSET(JH7110_GMAC0_PTP), 5)); + clk_dm(JH7110_GMAC_PHY, + starfive_clk_gate_divider(priv->sys, "gmac_phy", + "gmac_src", SYS_OFFSET(JH7110_GMAC_PHY), 5)); + clk_dm(JH7110_GMAC0_GTXC, + starfive_clk_gate_divider(priv->sys, "gmac0_gtxc", + "gmac0_gtxclk", SYS_OFFSET(JH7110_GMAC0_GTXC), 5)); + + /*UART0*/ + clk_dm(JH7110_UART0_CLK_APB, + starfive_clk_gate(priv->sys, + "u0_dw_uart_clk_apb", "apb0", + SYS_OFFSET(JH7110_UART0_CLK_APB))); + clk_dm(JH7110_UART0_CLK_CORE, + starfive_clk_gate(priv->sys, + "u0_dw_uart_clk_core", "osc", + SYS_OFFSET(JH7110_UART0_CLK_CORE))); + + /*UART1*/ + clk_dm(JH7110_UART1_CLK_APB, + starfive_clk_gate(priv->sys, + "u1_dw_uart_clk_apb", "apb0", + SYS_OFFSET(JH7110_UART1_CLK_APB))); + clk_dm(JH7110_UART1_CLK_CORE, + starfive_clk_gate(priv->sys, + "u1_dw_uart_clk_core", "osc", + SYS_OFFSET(JH7110_UART1_CLK_CORE))); + + /*UART2*/ + clk_dm(JH7110_UART2_CLK_APB, + starfive_clk_gate(priv->sys, + "u2_dw_uart_clk_apb", "apb0", + SYS_OFFSET(JH7110_UART2_CLK_APB))); + clk_dm(JH7110_UART2_CLK_CORE, + starfive_clk_gate(priv->sys, + "u2_dw_uart_clk_core", "osc", + SYS_OFFSET(JH7110_UART2_CLK_CORE))); + + /*UART3*/ + clk_dm(JH7110_UART3_CLK_APB, + starfive_clk_gate(priv->sys, + "u3_dw_uart_clk_apb", "apb0", + SYS_OFFSET(JH7110_UART3_CLK_APB))); + clk_dm(JH7110_UART3_CLK_CORE, + starfive_clk_gate(priv->sys, + "u3_dw_uart_clk_core", "perh_root", + SYS_OFFSET(JH7110_UART3_CLK_CORE))); + + /*UART4*/ + clk_dm(JH7110_UART4_CLK_APB, + starfive_clk_gate(priv->sys, + "u4_dw_uart_clk_apb", "apb0", + SYS_OFFSET(JH7110_UART4_CLK_APB))); + clk_dm(JH7110_UART4_CLK_CORE, + starfive_clk_gate(priv->sys, + "u4_dw_uart_clk_core", "perh_root", + SYS_OFFSET(JH7110_UART4_CLK_CORE))); + + /*UART5*/ + clk_dm(JH7110_UART5_CLK_APB, + starfive_clk_gate(priv->sys, + "u5_dw_uart_clk_apb", "apb0", + SYS_OFFSET(JH7110_UART5_CLK_APB))); + clk_dm(JH7110_UART5_CLK_CORE, + starfive_clk_gate(priv->sys, + "u5_dw_uart_clk_core", "perh_root", + SYS_OFFSET(JH7110_UART5_CLK_CORE))); + + clk_dm(JH7110_STG_APB, + starfive_clk_fix_factor(priv->stg, + "stg_apb", "apb_bus", 1, 1)); + + clk_dm(JH7110_HIFI4_CLK_CORE, + starfive_clk_gate(priv->stg, + "u0_hifi4_clk_core", "hifi4_core", + STG_OFFSET(JH7110_HIFI4_CLK_CORE))); + + clk_dm(JH7110_USB0_CLK_USB_APB, + starfive_clk_gate(priv->stg, + "u0_cdn_usb_clk_usb_apb", "stg_apb", + STG_OFFSET(JH7110_USB0_CLK_USB_APB))); + clk_dm(JH7110_USB0_CLK_UTMI_APB, + starfive_clk_gate(priv->stg, + "u0_cdn_usb_clk_utmi_apb", "stg_apb", + STG_OFFSET(JH7110_USB0_CLK_UTMI_APB))); + clk_dm(JH7110_USB0_CLK_AXI, + starfive_clk_gate(priv->stg, + "u0_cdn_usb_clk_axi", "stg_axiahb", + STG_OFFSET(JH7110_USB0_CLK_AXI))); + clk_dm(JH7110_USB0_CLK_LPM, + starfive_clk_gate_divider(priv->stg, + "u0_cdn_usb_clk_lpm", "osc", + STG_OFFSET(JH7110_USB0_CLK_LPM), 2)); + clk_dm(JH7110_USB0_CLK_STB, + starfive_clk_gate_divider(priv->stg, + "u0_cdn_usb_clk_stb", "osc", + STG_OFFSET(JH7110_USB0_CLK_STB), 3)); + clk_dm(JH7110_USB0_CLK_APP_125, + starfive_clk_gate(priv->stg, + "u0_cdn_usb_clk_app_125", "usb_125m", + STG_OFFSET(JH7110_USB0_CLK_APP_125))); + clk_dm(JH7110_USB0_REFCLK, + starfive_clk_divider(priv->stg, + "u0_cdn_usb_refclk", "osc", + STG_OFFSET(JH7110_USB0_REFCLK), 2)); + + /*GMAC1*/ + clk_dm(JH7110_U0_GMAC5_CLK_AHB, + starfive_clk_gate(priv->aon, + "u0_dw_gmac5_axi64_clk_ahb", "aon_ahb", + AON_OFFSET(JH7110_U0_GMAC5_CLK_AHB))); + clk_dm(JH7110_U0_GMAC5_CLK_AXI, + starfive_clk_gate(priv->aon, + "u0_dw_gmac5_axi64_clk_axi", "aon_ahb", + AON_OFFSET(JH7110_U0_GMAC5_CLK_AXI))); + clk_dm(JH7110_GMAC0_RMII_RTX, + starfive_clk_divider(priv->aon, + "gmac0_rmii_rtx", "gmac0_rmii_refin", + AON_OFFSET(JH7110_GMAC0_RMII_RTX), 5)); + clk_dm(JH7110_U0_GMAC5_CLK_PTP, + starfive_clk_fix_factor(priv->aon, + "u0_dw_gmac5_axi64_clk_ptp", + "gmac0_ptp", 1, 1)); + clk_dm(JH7110_U0_GMAC5_CLK_TX, + starfive_clk_composite(priv->aon, + "u0_dw_gmac5_axi64_clk_tx", + u0_dw_gmac5_axi64_clk_tx_sels, + ARRAY_SIZE(u0_dw_gmac5_axi64_clk_tx_sels), + AON_OFFSET(JH7110_U0_GMAC5_CLK_TX), 1, 1, 0)); + clk_dm(JH7110_U0_GMAC5_CLK_TX_INV, + starfive_clk_gate_dis(priv->aon, + "u0_dw_gmac5_axi64_clk_tx_inv", + "u0_dw_gmac5_axi64_clk_tx", + AON_OFFSET(JH7110_U0_GMAC5_CLK_TX_INV))); + clk_dm(JH7110_U0_GMAC5_CLK_RMII, + starfive_clk_fix_factor(priv->aon, + "u0_dw_gmac5_axi64_clk_rmii", + "gmac0_rmii_refin", 1, 1)); + + /*otp*/ + clk_dm(JH7110_OTPC_CLK_APB, + starfive_clk_gate(priv->aon, + "u0_otpc_clk_apb", "aon_apb", + AON_OFFSET(JH7110_OTPC_CLK_APB))); + + return 0; +} + +static int jh7110_clk_probe(struct udevice *dev) +{ + struct jh7110_clk_priv *priv = dev_get_priv(dev); + + priv->aon = dev_remap_addr_name(dev, "aon"); + if (!priv->aon) + return -EINVAL; + + priv->sys = dev_remap_addr_name(dev, "sys"); + if (!priv->sys) + return -EINVAL; + + priv->stg = dev_remap_addr_name(dev, "stg"); + if (!priv->stg) + return -EINVAL; + + return jh7110_clk_init(dev); +} + +static const struct udevice_id jh7110_clk_of_match[] = { + { .compatible = "starfive,jh7110-clkgen" }, + { } +}; + +U_BOOT_DRIVER(jh7110_clk) = { + .name = "jh7110_clk", + .id = UCLASS_CLK, + .of_match = jh7110_clk_of_match, + .probe = jh7110_clk_probe, + .ops = &starfive_clk_ops, + .priv_auto = sizeof(struct jh7110_clk_priv), + .flags = DM_FLAG_PRE_RELOC, +}; + diff --git a/include/dt-bindings/clock/starfive-jh7110-clkgen.h b/include/dt-bindings/clock/starfive-jh7110-clkgen.h new file mode 100644 index 0000000000..b8ba0237db --- /dev/null +++ b/include/dt-bindings/clock/starfive-jh7110-clkgen.h @@ -0,0 +1,393 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright 2022 StarFive, Inc + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CLKGEN_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CLKGEN_H__ + +/* sys regisger */ +#define JH7110_CPU_ROOT 0 +#define JH7110_CPU_CORE 1 +#define JH7110_CPU_BUS 2 +#define JH7110_GPU_ROOT 3 +#define JH7110_PERH_ROOT 4 +#define JH7110_BUS_ROOT 5 +#define JH7110_NOCSTG_BUS 6 +#define JH7110_AXI_CFG0 7 +#define JH7110_STG_AXIAHB 8 +#define JH7110_AHB0 9 +#define JH7110_AHB1 10 +#define JH7110_APB_BUS_FUNC 11 +#define JH7110_APB0 12 +#define JH7110_PLL0_DIV2 13 +#define JH7110_PLL1_DIV2 14 +#define JH7110_PLL2_DIV2 15 +#define JH7110_AUDIO_ROOT 16 +#define JH7110_MCLK_INNER 17 +#define JH7110_MCLK 18 +#define JH7110_MCLK_OUT 19 +#define JH7110_ISP_2X 20 +#define JH7110_ISP_AXI 21 +#define JH7110_GCLK0 22 +#define JH7110_GCLK1 23 +#define JH7110_GCLK2 24 +#define JH7110_U7_CORE_CLK 25 +#define JH7110_U7_CORE_CLK1 26 +#define JH7110_U7_CORE_CLK2 27 +#define JH7110_U7_CORE_CLK3 28 +#define JH7110_U7_CORE_CLK4 29 +#define JH7110_U7_DEBUG_CLK 30 +#define JH7110_U7_RTC_TOGGLE 31 +#define JH7110_U7_TRACE_CLK0 32 +#define JH7110_U7_TRACE_CLK1 33 +#define JH7110_U7_TRACE_CLK2 34 +#define JH7110_U7_TRACE_CLK3 35 +#define JH7110_U7_TRACE_CLK4 36 +#define JH7110_U7_TRACE_COM_CLK 37 +#define JH7110_NOC_BUS_CLK_CPU_AXI 38 +#define JH7110_NOC_BUS_CLK_AXICFG0_AXI 39 +#define JH7110_OSC_DIV2 40 +#define JH7110_PLL1_DIV4 41 +#define JH7110_PLL1_DIV8 42 +#define JH7110_DDR_BUS 43 +#define JH7110_DDR_CLK_AXI 44 +#define JH7110_GPU_CORE 45 +#define JH7110_GPU_CORE_CLK 46 +#define JH7110_GPU_SYS_CLK 47 +#define JH7110_GPU_CLK_APB 48 +#define JH7110_GPU_RTC_TOGGLE 49 +#define JH7110_NOC_BUS_CLK_GPU_AXI 50 +#define JH7110_ISP_TOP_CLK_ISPCORE_2X 51 +#define JH7110_ISP_TOP_CLK_ISP_AXI 52 +#define JH7110_NOC_BUS_CLK_ISP_AXI 53 +#define JH7110_HIFI4_CORE 54 +#define JH7110_HIFI4_AXI 55 +#define JH7110_AXI_CFG1_DEC_CLK_MAIN 56 +#define JH7110_AXI_CFG1_DEC_CLK_AHB 57 +#define JH7110_VOUT_SRC 58 +#define JH7110_VOUT_AXI 59 +#define JH7110_NOC_BUS_CLK_DISP_AXI 60 +#define JH7110_VOUT_TOP_CLK_VOUT_AHB 61 +#define JH7110_VOUT_TOP_CLK_VOUT_AXI 62 +#define JH7110_VOUT_TOP_CLK_HDMITX0_MCLK 63 +#define JH7110_VOUT_TOP_CLK_MIPIPHY_REF 64 +#define JH7110_JPEGC_AXI 65 +#define JH7110_CODAJ12_CLK_AXI 66 +#define JH7110_CODAJ12_CLK_CORE 67 +#define JH7110_CODAJ12_CLK_APB 68 +#define JH7110_VDEC_AXI 69 +#define JH7110_WAVE511_CLK_AXI 70 +#define JH7110_WAVE511_CLK_BPU 71 +#define JH7110_WAVE511_CLK_VCE 72 +#define JH7110_WAVE511_CLK_APB 73 +#define JH7110_VDEC_JPG_ARB_JPGCLK 74 +#define JH7110_VDEC_JPG_ARB_MAINCLK 75 +#define JH7110_NOC_BUS_CLK_VDEC_AXI 76 +#define JH7110_VENC_AXI 77 +#define JH7110_WAVE420L_CLK_AXI 78 +#define JH7110_WAVE420L_CLK_BPU 79 +#define JH7110_WAVE420L_CLK_VCE 80 +#define JH7110_WAVE420L_CLK_APB 81 +#define JH7110_NOC_BUS_CLK_VENC_AXI 82 +#define JH7110_AXI_CFG0_DEC_CLK_MAIN_DIV 83 +#define JH7110_AXI_CFG0_DEC_CLK_MAIN 84 +#define JH7110_AXI_CFG0_DEC_CLK_HIFI4 85 +#define JH7110_AXIMEM2_128B_CLK_AXI 86 +#define JH7110_QSPI_CLK_AHB 87 +#define JH7110_QSPI_CLK_APB 88 +#define JH7110_QSPI_REF_SRC 89 +#define JH7110_QSPI_CLK_REF 90 +#define JH7110_SDIO0_CLK_AHB 91 +#define JH7110_SDIO1_CLK_AHB 92 +#define JH7110_SDIO0_CLK_SDCARD 93 +#define JH7110_SDIO1_CLK_SDCARD 94 +#define JH7110_USB_125M 95 +#define JH7110_NOC_BUS_CLK_STG_AXI 96 +#define JH7110_GMAC5_CLK_AHB 97 +#define JH7110_GMAC5_CLK_AXI 98 +#define JH7110_GMAC_SRC 99 +#define JH7110_GMAC1_GTXCLK 100 +#define JH7110_GMAC1_RMII_RTX 101 +#define JH7110_GMAC5_CLK_PTP 102 +#define JH7110_GMAC5_CLK_RX 103 +#define JH7110_GMAC5_CLK_RX_INV 104 +#define JH7110_GMAC5_CLK_TX 105 +#define JH7110_GMAC5_CLK_TX_INV 106 +#define JH7110_GMAC1_GTXC 107 +#define JH7110_GMAC0_GTXCLK 108 +#define JH7110_GMAC0_PTP 109 +#define JH7110_GMAC_PHY 110 +#define JH7110_GMAC0_GTXC 111 +#define JH7110_SYS_IOMUX_PCLK 112 +#define JH7110_MAILBOX_CLK_APB 113 +#define JH7110_INT_CTRL_CLK_APB 114 +#define JH7110_CAN0_CTRL_CLK_APB 115 +#define JH7110_CAN0_CTRL_CLK_TIMER 116 +#define JH7110_CAN0_CTRL_CLK_CAN 117 +#define JH7110_CAN1_CTRL_CLK_APB 118 +#define JH7110_CAN1_CTRL_CLK_TIMER 119 +#define JH7110_CAN1_CTRL_CLK_CAN 120 +#define JH7110_PWM_CLK_APB 121 +#define JH7110_DSKIT_WDT_CLK_APB 122 +#define JH7110_DSKIT_WDT_CLK_WDT 123 +#define JH7110_TIMER_CLK_APB 124 +#define JH7110_TIMER_CLK_TIMER0 125 +#define JH7110_TIMER_CLK_TIMER1 126 +#define JH7110_TIMER_CLK_TIMER2 127 +#define JH7110_TIMER_CLK_TIMER3 128 +#define JH7110_TEMP_SENSOR_CLK_APB 129 +#define JH7110_TEMP_SENSOR_CLK_TEMP 130 +#define JH7110_SPI0_CLK_APB 131 +#define JH7110_SPI1_CLK_APB 132 +#define JH7110_SPI2_CLK_APB 133 +#define JH7110_SPI3_CLK_APB 134 +#define JH7110_SPI4_CLK_APB 135 +#define JH7110_SPI5_CLK_APB 136 +#define JH7110_SPI6_CLK_APB 137 +#define JH7110_I2C0_CLK_APB 138 +#define JH7110_I2C1_CLK_APB 139 +#define JH7110_I2C2_CLK_APB 140 +#define JH7110_I2C3_CLK_APB 141 +#define JH7110_I2C4_CLK_APB 142 +#define JH7110_I2C5_CLK_APB 143 +#define JH7110_I2C6_CLK_APB 144 +#define JH7110_UART0_CLK_APB 145 +#define JH7110_UART0_CLK_CORE 146 +#define JH7110_UART1_CLK_APB 147 +#define JH7110_UART1_CLK_CORE 148 +#define JH7110_UART2_CLK_APB 149 +#define JH7110_UART2_CLK_CORE 150 +#define JH7110_UART3_CLK_APB 151 +#define JH7110_UART3_CLK_CORE 152 +#define JH7110_UART4_CLK_APB 153 +#define JH7110_UART4_CLK_CORE 154 +#define JH7110_UART5_CLK_APB 155 +#define JH7110_UART5_CLK_CORE 156 +#define JH7110_PWMDAC_CLK_APB 157 +#define JH7110_PWMDAC_CLK_CORE 158 +#define JH7110_SPDIF_CLK_APB 159 +#define JH7110_SPDIF_CLK_CORE 160 +#define JH7110_I2STX0_4CHCLK_APB 161 +#define JH7110_I2STX_4CH0_BCLK_MST 162 +#define JH7110_I2STX_4CH0_BCLK_MST_INV 163 +#define JH7110_I2STX_4CH0_LRCK_MST 164 +#define JH7110_I2STX0_4CHBCLK 165 +#define JH7110_I2STX0_4CHBCLK_N 166 +#define JH7110_I2STX0_4CHLRCK 167 +#define JH7110_I2STX1_4CHCLK_APB 168 +#define JH7110_I2STX_4CH1_BCLK_MST 169 +#define JH7110_I2STX_4CH1_BCLK_MST_INV 170 +#define JH7110_I2STX_4CH1_LRCK_MST 171 +#define JH7110_I2STX1_4CHBCLK 172 +#define JH7110_I2STX1_4CHBCLK_N 173 +#define JH7110_I2STX1_4CHLRCK 174 +#define JH7110_I2SRX0_3CH_CLK_APB 175 +#define JH7110_I2SRX_3CH_BCLK_MST 176 +#define JH7110_I2SRX_3CH_BCLK_MST_INV 177 +#define JH7110_I2SRX_3CH_LRCK_MST 178 +#define JH7110_I2SRX0_3CH_BCLK 179 +#define JH7110_I2SRX0_3CH_BCLK_N 180 +#define JH7110_I2SRX0_3CH_LRCK 181 +#define JH7110_PDM_CLK_DMIC 182 +#define JH7110_PDM_CLK_APB 183 +#define JH7110_TDM_CLK_AHB 184 +#define JH7110_TDM_CLK_APB 185 +#define JH7110_TDM_INTERNAL 186 +#define JH7110_TDM_CLK_TDM 187 +#define JH7110_TDM_CLK_TDM_N 188 +#define JH7110_JTAG_CERTIFICATION_TRNG_CLK 189 + +#define JH7110_CLK_SYS_REG_END 190 + +/* stg regisger */ +#define JH7110_HIFI4_CLK_CORE 190 +#define JH7110_USB0_CLK_USB_APB 191 +#define JH7110_USB0_CLK_UTMI_APB 192 +#define JH7110_USB0_CLK_AXI 193 +#define JH7110_USB0_CLK_LPM 194 +#define JH7110_USB0_CLK_STB 195 +#define JH7110_USB0_CLK_APP_125 196 +#define JH7110_USB0_REFCLK 197 +#define JH7110_PCIE0_CLK_AXI_MST0 198 +#define JH7110_PCIE0_CLK_APB 199 +#define JH7110_PCIE0_CLK_TL 200 +#define JH7110_PCIE1_CLK_AXI_MST0 201 +#define JH7110_PCIE1_CLK_APB 202 +#define JH7110_PCIE1_CLK_TL 203 +#define JH7110_PCIE01_SLV_DEC_MAINCLK 204 +#define JH7110_SEC_HCLK 205 +#define JH7110_SEC_MISCAHB_CLK 206 +#define JH7110_STG_MTRX_GRP0_CLK_MAIN 207 +#define JH7110_STG_MTRX_GRP0_CLK_BUS 208 +#define JH7110_STG_MTRX_GRP0_CLK_STG 209 +#define JH7110_STG_MTRX_GRP1_CLK_MAIN 210 +#define JH7110_STG_MTRX_GRP1_CLK_BUS 211 +#define JH7110_STG_MTRX_GRP1_CLK_STG 212 +#define JH7110_STG_MTRX_GRP1_CLK_HIFI 213 +#define JH7110_E2_RTC_CLK 214 +#define JH7110_E2_CLK_CORE 215 +#define JH7110_E2_CLK_DBG 216 +#define JH7110_DMA1P_CLK_AXI 217 +#define JH7110_DMA1P_CLK_AHB 218 + +#define JH7110_CLK_STG_REG_END 219 + +/* aon regisger */ +#define JH7110_OSC_DIV4 219 +#define JH7110_AON_APB_FUNC 220 +#define JH7110_U0_GMAC5_CLK_AHB 221 +#define JH7110_U0_GMAC5_CLK_AXI 222 +#define JH7110_GMAC0_RMII_RTX 223 +#define JH7110_U0_GMAC5_CLK_TX 224 +#define JH7110_U0_GMAC5_CLK_TX_INV 225 +#define JH7110_U0_GMAC5_CLK_RX 226 +#define JH7110_U0_GMAC5_CLK_RX_INV 227 +#define JH7110_OTPC_CLK_APB 228 +#define JH7110_RTC_HMS_CLK_APB 229 +#define JH7110_RTC_INTERNAL 230 +#define JH7110_RTC_HMS_CLK_OSC32K 231 +#define JH7110_RTC_HMS_CLK_CAL 232 + +#define JH7110_CLK_AON_REG_END 233 + +/* sys other */ +#define JH7110_PLL0_OUT 233 +#define JH7110_PLL1_OUT 234 +#define JH7110_PLL2_OUT 235 +#define JH7110_AON_APB 236 +#define JH7110_RESET1_CTRL_CLK_SRC 237 +#define JH7110_DDR_ROOT 238 +#define JH7110_VDEC_ROOT 239 +#define JH7110_VENC_ROOT 240 +#define JH7110_VOUT_ROOT 241 +#define JH7110_GMACUSB_ROOT 242 +#define JH7110_PCLK2_MUX_FUNC_PCLK 243 +#define JH7110_PCLK2_MUX_BIST_PCLK 244 +#define JH7110_APB_BUS 245 +#define JH7110_APB12 246 +#define JH7110_AXI_CFG1 247 +#define JH7110_PLL_WRAP_CRG_GCLK0 248 +#define JH7110_PLL_WRAP_CRG_GCLK1 249 +#define JH7110_PLL_WRAP_CRG_GCLK2 250 +#define JH7110_JTAG2APB_PCLK 251 +#define JH7110_U7_BUS_CLK 252 +#define JH7110_U7_IRQ_SYNC_BUS_CLK 253 +#define JH7110_NOC_BUS_CLK2_CPU_AXI 254 +#define JH7110_NOC_BUS_CLK_APB_BUS 255 +#define JH7110_NOC_BUS_CLK2_APB_BUS 256 +#define JH7110_NOC_BUS_CLK2_AXICFG0_AXI 257 +#define JH7110_DDR_CLK_DDRPHY_PLL_BYPASS 258 +#define JH7110_DDR_CLK_OSC 259 +#define JH7110_DDR_CLK_APB 260 +#define JH7110_NOC_BUS_CLK_DDRC 261 +#define JH7110_NOC_BUS_CLK2_DDRC 262 +#define JH7110_SYS_AHB_DEC_CLK_AHB 263 +#define JH7110_STG_AHB_DEC_CLK_AHB 264 +#define JH7110_NOC_BUS_CLK2_GPU_AXI 265 +#define JH7110_ISP_TOP_CLK_DVP 266 +#define JH7110_NOC_BUS_CLK2_ISP_AXI 267 +#define JH7110_ISP_TOP_CLK_BIST_APB 268 +#define JH7110_NOC_BUS_CLK2_DISP_AXI 269 +#define JH7110_VOUT_TOP_CLK_HDMITX0_BCLK 270 +#define JH7110_VOUT_TOP_U0_HDMI_TX_PIN_WS 271 +#define JH7110_VOUT_TOP_CLK_HDMIPHY_REF 272 +#define JH7110_VOUT_TOP_BIST_PCLK 273 +#define JH7110_AXIMEM0_128B_CLK_AXI 274 +#define JH7110_VDEC_INTSRAM_CLK_VDEC_AXI 275 +#define JH7110_NOC_BUS_CLK2_VDEC_AXI 276 +#define JH7110_AXIMEM1_128B_CLK_AXI 277 +#define JH7110_VENC_INTSRAM_CLK_VENC_AXI 278 +#define JH7110_NOC_BUS_CLK2_VENC_AXI 279 +#define JH7110_SRAM_CLK_ROM 280 +#define JH7110_NOC_BUS_CLK2_STG_AXI 281 +#define JH7110_GMAC5_CLK_RMII 282 +#define JH7110_AON_AHB 283 +#define JH7110_SYS_CRG_PCLK 284 +#define JH7110_SYS_SYSCON_PCLK 285 +#define JH7110_SPI0_CLK_CORE 286 +#define JH7110_SPI1_CLK_CORE 287 +#define JH7110_SPI2_CLK_CORE 288 +#define JH7110_SPI3_CLK_CORE 289 +#define JH7110_SPI4_CLK_CORE 290 +#define JH7110_SPI5_CLK_CORE 291 +#define JH7110_SPI6_CLK_CORE 292 +#define JH7110_I2C0_CLK_CORE 293 +#define JH7110_I2C1_CLK_CORE 294 +#define JH7110_I2C2_CLK_CORE 295 +#define JH7110_I2C3_CLK_CORE 296 +#define JH7110_I2C4_CLK_CORE 297 +#define JH7110_I2C5_CLK_CORE 298 +#define JH7110_I2C6_CLK_CORE 299 +#define JH7110_I2STX_BCLK_MST 300 +#define JH7110_I2STX_LRCK_MST 301 +#define JH7110_I2SRX_BCLK_MST 302 +#define JH7110_I2SRX_LRCK_MST 303 +#define JH7110_PDM_CLK_DMIC0_BCLK_SLV 304 +#define JH7110_PDM_CLK_DMIC0_LRCK_SLV 305 +#define JH7110_PDM_CLK_DMIC1_BCLK_SLV 306 +#define JH7110_PDM_CLK_DMIC1_LRCK_SLV 307 +#define JH7110_TDM_CLK_MST 308 +#define JH7110_AHB2APB_CLK_AHB 309 +#define JH7110_P2P_ASYNC_CLK_APBS 310 +#define JH7110_P2P_ASYNC_CLK_APBM 311 +#define JH7110_JTAG_DAISY_CHAIN_JTAG_TCK 312 +#define JH7110_U7_DEBUG_SYSTEMJTAG_JTAG_TCK 313 +#define JH7110_E2_DEBUG_SYSTEMJTAG_TCK 314 +#define JH7110_JTAG_CERTIFICATION_TCK 315 +#define JH7110_SEC_SKP_CLK 316 + +#define JH7110_CLK_SYS_END 317 + +/* stg other */ +#define JH7110_PCIE0_CLK_AXI_SLV0 317 +#define JH7110_PCIE0_CLK_AXI_SLV 318 +#define JH7110_PCIE0_CLK_OSC 319 +#define JH7110_PCIE1_CLK_AXI_SLV0 320 +#define JH7110_PCIE1_CLK_AXI_SLV 321 +#define JH7110_PCIE1_CLK_OSC 322 +#define JH7110_E2_IRQ_SYNC_CLK_CORE 323 +#define JH7110_STG_CRG_PCLK 324 +#define JH7110_STG_SYSCON_PCLK 325 + +#define JH7110_CLK_STG_END 326 + +/* aon other */ +#define JH7110_U0_GMAC5_CLK_PTP 326 +#define JH7110_U0_GMAC5_CLK_RMII 327 +#define JH7110_AON_SYSCON_PCLK 328 +#define JH7110_AON_IOMUX_PCLK 329 +#define JH7110_AON_CRG_PCLK 330 +#define JH7110_PMU_CLK_APB 331 +#define JH7110_PMU_CLK_WKUP 332 +#define JH7110_RTC_HMS_CLK_OSC32K_G 333 +#define JH7110_32K_OUT 334 +#define JH7110_RESET0_CTRL_CLK_SRC 335 +/* aon other and source */ +#define JH7110_PCLK_MUX_FUNC_PCLK 336 +#define JH7110_PCLK_MUX_BIST_PCLK 337 + +#define JH7110_CLK_END 338 + +/* sys external clocks */ +#define JH7110_OSC (JH7110_CLK_END + 0) +#define JH7110_GMAC1_RMII_REFIN (JH7110_CLK_END + 1) +#define JH7110_GMAC1_RGMII_RXIN (JH7110_CLK_END + 2) +#define JH7110_I2STX_BCLK_EXT (JH7110_CLK_END + 3) +#define JH7110_I2STX_LRCK_EXT (JH7110_CLK_END + 4) +#define JH7110_I2SRX_BCLK_EXT (JH7110_CLK_END + 5) +#define JH7110_I2SRX_LRCK_EXT (JH7110_CLK_END + 6) +#define JH7110_TDM_EXT (JH7110_CLK_END + 7) +#define JH7110_MCLK_EXT (JH7110_CLK_END + 8) +#define JH7110_JTAG_TCK_INNER (JH7110_CLK_END + 9) +#define JH7110_BIST_APB (JH7110_CLK_END + 10) + +/* stg external clocks */ +#define JH7110_STG_APB (JH7110_CLK_END + 11) + +/* aon external clocks */ +#define JH7110_GMAC0_RMII_REFIN (JH7110_CLK_END + 12) +#define JH7110_GMAC0_RGMII_RXIN (JH7110_CLK_END + 13) +#define JH7110_CLK_RTC (JH7110_CLK_END + 14) + +#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */ diff --git a/include/dt-bindings/clock/starfive-jh7110-vout.h b/include/dt-bindings/clock/starfive-jh7110-vout.h new file mode 100644 index 0000000000..e76a80a5f1 --- /dev/null +++ b/include/dt-bindings/clock/starfive-jh7110-vout.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright 2022 StarFive, Inc + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_VOUT_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_VOUT_H__ + +/* regisger */ +#define JH7110_APB 0 +#define JH7110_DC8200_PIX0 1 +#define JH7110_DSI_SYS 2 +#define JH7110_TX_ESC 3 +#define JH7110_U0_DC8200_CLK_AXI 4 +#define JH7110_U0_DC8200_CLK_CORE 5 +#define JH7110_U0_DC8200_CLK_AHB 6 +#define JH7110_U0_DC8200_CLK_PIX0 7 +#define JH7110_U0_DC8200_CLK_PIX1 8 +#define JH7110_DOM_VOUT_TOP_LCD_CLK 9 +#define JH7110_U0_CDNS_DSITX_CLK_APB 10 +#define JH7110_U0_CDNS_DSITX_CLK_SYS 11 +#define JH7110_U0_CDNS_DSITX_CLK_DPI 12 +#define JH7110_U0_CDNS_DSITX_CLK_TXESC 13 +#define JH7110_U0_MIPITX_DPHY_CLK_TXESC 14 +#define JH7110_U0_HDMI_TX_CLK_MCLK 15 +#define JH7110_U0_HDMI_TX_CLK_BCLK 16 +#define JH7110_U0_HDMI_TX_CLK_SYS 17 + +#define JH7110_CLK_VOUT_REG_END 18 + +/* other */ +#define JH7110_DISP_ROOT 18 +#define JH7110_DISP_AXI 19 +#define JH7110_DISP_AHB 20 +#define JH7110_HDMI_PHY_REF 21 +#define JH7110_HDMITX0_MCLK 22 +#define JH7110_HDMITX0_SCK 23 + +#define JH7110_MIPI_DPHY_REF 24 +#define JH7110_U0_PCLK_MUX_BIST_PCLK 25 +#define JH7110_DISP_APB 26 +#define JH7110_U0_PCLK_MUX_FUNC_PCLK 27 +#define JH7110_U0_DOM_VOUT_CRG_PCLK 28 +#define JH7110_U0_DOM_VOUT_SYSCON_PCLK 29 +#define JH7110_U0_SAIF_AMBA_DOM_VOUT_AHB_DEC_CLK_AHB 30 +#define JH7110_U0_AHB2APB_CLK_AHB 31 +#define JH7110_U0_P2P_ASYNC_CLK_APBS 32 +#define JH7110_U0_CDNS_DSITX_CLK_RXESC 33 +#define JH7110_U0_CDNS_DSITX_CLK_TXBYTEHS 34 +#define JH7110_U0_MIPITX_DPHY_CLK_SYS 35 +#define JH7110_U0_MIPITX_DPHY_CLK_DPHY_REF 36 +#define JH7110_U0_MIPITX_APBIF_PCLK 37 +#define JH7110_HDMI_TX_CLK_REF 38 +#define JH7110_U0_DC8200_CLK_PIX0_OUT 39 +#define JH7110_U0_DC8200_CLK_PIX1_OUT 40 + +#define JH7110_CLK_VOUT_END 41 + +/* external clocks */ +#define JH7110_HDMITX0_PIXELCLK (JH7110_CLK_VOUT_END + 0) +#define JH7110_MIPITX_DPHY_RXESC (JH7110_CLK_VOUT_END + 1) +#define JH7110_MIPITX_DPHY_TXBYTEHS (JH7110_CLK_VOUT_END + 2) + + + +#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */ -- cgit v1.2.3