From 2a70e4bec3fc432e833536c148c212a75704d1e5 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Thu, 27 Aug 2020 19:18:21 +0530 Subject: configs: Enable NVME support for Layerscape platforms Enable CONFIG_NVME and CONFIG_CMD_NVME for Layerscape platforms Signed-off-by: Wasim Khan Reviewed-by: Priyanka Jain --- configs/ls1012afrdm_qspi_defconfig | 2 ++ configs/ls1012afrdm_tfa_defconfig | 2 ++ configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1012afrwy_qspi_defconfig | 2 ++ configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1012afrwy_tfa_defconfig | 2 ++ configs/ls1012aqds_qspi_defconfig | 2 ++ configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1012aqds_tfa_defconfig | 2 ++ configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1012ardb_qspi_defconfig | 2 ++ configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1012ardb_tfa_defconfig | 2 ++ configs/ls1021aiot_qspi_defconfig | 2 ++ configs/ls1021aiot_sdcard_defconfig | 2 ++ configs/ls1021aqds_ddr4_nor_defconfig | 2 ++ configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 2 ++ configs/ls1021aqds_nand_defconfig | 2 ++ configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 2 ++ configs/ls1021aqds_nor_defconfig | 2 ++ configs/ls1021aqds_nor_lpuart_defconfig | 2 ++ configs/ls1021aqds_qspi_defconfig | 2 ++ configs/ls1021aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1021aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1021atsn_qspi_defconfig | 2 ++ configs/ls1021atsn_sdcard_defconfig | 2 ++ configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 ++ configs/ls1021atwr_nor_defconfig | 2 ++ configs/ls1021atwr_nor_lpuart_defconfig | 2 ++ configs/ls1021atwr_qspi_defconfig | 2 ++ configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 ++ configs/ls1021atwr_sdcard_ifc_defconfig | 2 ++ configs/ls1021atwr_sdcard_qspi_defconfig | 2 ++ configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1028aqds_tfa_defconfig | 2 ++ configs/ls1028aqds_tfa_lpuart_defconfig | 2 ++ configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1028ardb_tfa_defconfig | 2 ++ configs/ls1043aqds_defconfig | 2 ++ configs/ls1043aqds_lpuart_defconfig | 2 ++ configs/ls1043aqds_nand_defconfig | 2 ++ configs/ls1043aqds_nor_ddr3_defconfig | 2 ++ configs/ls1043aqds_qspi_defconfig | 2 ++ configs/ls1043aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1043aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1043aqds_tfa_defconfig | 2 ++ configs/ls1043ardb_SECURE_BOOT_defconfig | 2 ++ configs/ls1043ardb_defconfig | 2 ++ configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 2 ++ configs/ls1043ardb_nand_defconfig | 2 ++ configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 2 ++ configs/ls1043ardb_sdcard_defconfig | 2 ++ configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1043ardb_tfa_defconfig | 2 ++ configs/ls1046afrwy_tfa_defconfig | 2 ++ configs/ls1046aqds_SECURE_BOOT_defconfig | 2 ++ configs/ls1046aqds_defconfig | 2 ++ configs/ls1046aqds_lpuart_defconfig | 2 ++ configs/ls1046aqds_nand_defconfig | 2 ++ configs/ls1046aqds_qspi_defconfig | 2 ++ configs/ls1046aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1046aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1046aqds_tfa_defconfig | 2 ++ configs/ls1046ardb_emmc_defconfig | 2 ++ configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1046ardb_qspi_defconfig | 2 ++ configs/ls1046ardb_qspi_spl_defconfig | 2 ++ configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 2 ++ configs/ls1046ardb_sdcard_defconfig | 2 ++ configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1046ardb_tfa_defconfig | 2 ++ configs/ls1088aqds_defconfig | 2 ++ configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1088aqds_qspi_defconfig | 2 ++ configs/ls1088aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1088aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1088aqds_tfa_defconfig | 2 ++ configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1088ardb_qspi_defconfig | 2 ++ configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1088ardb_sdcard_qspi_defconfig | 2 ++ configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1088ardb_tfa_defconfig | 2 ++ configs/ls2080aqds_SECURE_BOOT_defconfig | 2 ++ configs/ls2080aqds_defconfig | 2 ++ configs/ls2080aqds_nand_defconfig | 2 ++ configs/ls2080aqds_qspi_defconfig | 2 ++ configs/ls2080aqds_sdcard_defconfig | 2 ++ configs/ls2080ardb_SECURE_BOOT_defconfig | 2 ++ configs/ls2080ardb_defconfig | 2 ++ configs/ls2080ardb_nand_defconfig | 2 ++ configs/ls2081ardb_defconfig | 2 ++ configs/ls2088aqds_tfa_defconfig | 2 ++ configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls2088ardb_qspi_defconfig | 2 ++ configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls2088ardb_tfa_defconfig | 2 ++ configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/lx2160aqds_tfa_defconfig | 2 ++ configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/lx2160ardb_tfa_defconfig | 2 ++ configs/lx2160ardb_tfa_stmm_defconfig | 2 ++ 104 files changed, 208 insertions(+) diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index 1af77dca3d..6a95dd582a 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -61,3 +61,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index a94887d649..95fdc0fc11 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -61,3 +61,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index 78e1f66673..f73b7919c3 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -62,3 +62,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index bdd4dbee57..5740a1fce8 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -63,3 +63,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index 5a58f7ce1e..be8c9fdd6d 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -62,3 +62,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index 7a15c8f0ad..cdb8bf5685 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -68,3 +68,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_RTL8152=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 1e8e3110f3..9fdaf79f00 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -84,3 +84,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index dc405c725a..3216e18dd5 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -75,3 +75,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index bf03216202..829eb2f1b4 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -84,3 +84,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index 552364a5aa..40f37cc5fc 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -66,3 +66,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index f50047933a..99e80d6c21 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -68,3 +68,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index cf4324355d..d8d2cfaa0b 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -67,3 +67,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 1bcf80cf6e..705ed2f661 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -67,3 +67,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index 78c4d61242..b258217a61 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -55,3 +55,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index bb4b9dd8d4..bb063197d7 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -60,3 +60,5 @@ CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 6687fc2630..789bb5a05e 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -73,3 +73,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index 555d4e9843..9c36d2a461 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -73,3 +73,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 9478ed52a6..f6adc529b1 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -88,3 +88,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index c5e93dac60..91fb32a3bb 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -72,3 +72,5 @@ CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_RSA=y CONFIG_SPL_RSA=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index 10060a10ac..4e7e25abc0 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -74,3 +74,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 3dc0baafe3..b50946c48a 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -74,3 +74,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index db5b571ea2..e470e63b0c 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -73,3 +73,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 0d0fa68e83..58775c0162 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -87,3 +87,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index c322ee8ca4..0be05b641b 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -85,3 +85,5 @@ CONFIG_USB_STORAGE=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index 43f9e511cc..e060f148f5 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -61,3 +61,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index 49197eeed4..c611995d0b 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -72,3 +72,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index d62dcfa751..b67a636734 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -66,3 +66,5 @@ CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_RSA=y CONFIG_SPL_RSA=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index f49a882e0a..b53185e5f8 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -68,3 +68,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index e75c7b43d2..028cc239ae 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -69,3 +69,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 767c364b3e..2899d1bdd3 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -71,3 +71,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 5b3ac2a348..f8a1635617 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -80,3 +80,5 @@ CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_RSA=y CONFIG_SPL_RSA=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 5cc0b90aa7..15d9203bbd 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -81,3 +81,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index e3e64f9790..4edfdb58bb 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -82,3 +82,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 1dc9d310fe..c31bb06435 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -84,3 +84,5 @@ CONFIG_WDT_SP805=y CONFIG_RSA=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index bf9fee9f7b..374eacb897 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -89,3 +89,5 @@ CONFIG_WDT=y CONFIG_WDT_SP805=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig index 3fccd4b2b7..3f58f17c26 100644 --- a/configs/ls1028aqds_tfa_lpuart_defconfig +++ b/configs/ls1028aqds_tfa_lpuart_defconfig @@ -91,3 +91,5 @@ CONFIG_WDT=y CONFIG_WDT_SP805=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index 5257080eb2..11e61d9081 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -81,3 +81,5 @@ CONFIG_WDT_SP805=y CONFIG_RSA=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 9435e705ad..9ccbb7a67a 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -90,3 +90,5 @@ CONFIG_WDT=y CONFIG_WDT_SP805=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 4846dddcd6..e839e5fa6b 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -68,3 +68,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 6d8b6f34d5..86692bb102 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -70,3 +70,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 98a9af5790..9185c8c36f 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -84,3 +84,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 87651a7504..fd84464f0d 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -69,3 +69,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 2e2d4db1b2..ec1b10ec51 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -65,3 +65,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index ca825d7d78..e814935442 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -85,3 +85,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 3b24e1927b..2c3923da72 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -79,3 +79,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index 1aa657a04b..d89ca73d95 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -71,3 +71,5 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index d306773f3e..2b1d9588e7 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -78,3 +78,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index bd723a5eca..3e9460241f 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -61,3 +61,5 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 59e88fdd71..63f1bb88e1 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -61,3 +61,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index a535109184..da1861de66 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -81,3 +81,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 9a43ea856d..fbc57c7d25 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -80,3 +80,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index 34cbd24d0b..903c4bbcb0 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -81,3 +81,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index cf5b5975c1..54a7d22f9d 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -80,3 +80,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index aac3175d2c..b7194443b6 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -62,3 +62,5 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index d15869f70d..6da10c3115 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -65,3 +65,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index 2d76b35f79..1f70bc6746 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -68,3 +68,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_RTL8152=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index 26b42fabec..0e18f14174 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -69,3 +69,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index dfa1882279..d759681060 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -71,3 +71,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index f37cdf7eba..de21e30fa8 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -73,3 +73,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index 5256f30960..a65760d991 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -79,3 +79,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index 466d7ca6c8..b47998881d 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -69,3 +69,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 959b8ffee9..9f99cce4d1 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -89,3 +89,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 527eb0887b..34a6d0b1b4 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -84,3 +84,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 6860e48d51..14fbcc1015 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -71,3 +71,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index f481add1fb..8730315766 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -81,3 +81,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index cd0ba8fbe5..9ec38c8b15 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -81,3 +81,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index d7ee89c636..3e168a4985 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -64,3 +64,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index 481c42c928..876b775e3b 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -67,3 +67,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index 327028619b..398faa85e7 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -86,3 +86,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_SPL_GZIP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 525caa6881..c353c03fde 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -78,3 +78,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index d5e519f705..f431b09e60 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -80,3 +80,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index 6ef4e24f18..7190c65150 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -63,3 +63,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index d123a8df43..711e21ffa9 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -68,3 +68,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index 9642de2b4f..ddc4ed848f 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -72,3 +72,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index 0d35e91fed..9943666ff6 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -74,3 +74,5 @@ CONFIG_USB_GADGET=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index fcb7678585..3627792b18 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -75,3 +75,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index 1f8398cc83..99a51305cb 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -80,3 +80,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index 6558c165fe..52dd94e195 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -84,3 +84,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index 582cd85765..328173574e 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -100,3 +100,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index 40f66fa63f..5542914179 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -76,3 +76,5 @@ CONFIG_USB_GADGET=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index d7ecff2f9e..b3cd9b5399 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -77,3 +77,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index ffc4588e60..417c813f3a 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -85,3 +85,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_RSA=y CONFIG_SPL_RSA=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index 6adfadf990..27a7674c20 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -86,3 +86,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 767715986d..9f8e3123e3 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -86,3 +86,5 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index c6c860c723..573a85955f 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -92,3 +92,5 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_RTL8152=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index bb421db3a0..fc238236bb 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -68,3 +68,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index 76ee054b67..0010bb886d 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -69,3 +69,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index abc16a274b..217e9829db 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -76,3 +76,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index 2604ac26fc..08a7bd2635 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -68,3 +68,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index 908a548115..ed3bfe21d4 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -75,3 +75,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 4341e61e3f..231d420ebb 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -66,3 +66,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index 4cf27d1cfc..1d7559c18b 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -67,3 +67,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 19436bdc89..8f933d9d54 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -72,3 +72,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index 39e5d7d421..a76e7805d5 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -65,3 +65,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 6127e98bf6..bde3755f41 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -89,3 +89,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index d3f8d53063..30984f4cb4 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -65,3 +65,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 972e7f892e..129aa2aa6e 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -70,3 +70,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index c5da5a32cd..59162990aa 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -82,3 +82,5 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index faecc7b644..1fe0c1f74d 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -87,3 +87,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 461d719d3e..1be2231082 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -84,3 +84,5 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index 6dde0937c4..a6ac66d8b0 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -90,3 +90,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_WDT=y CONFIG_WDT_SBSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index 159ae9d97f..d339ab240b 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -75,3 +75,5 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 8a4e6efc90..90b66e1376 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -81,3 +81,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_WDT=y CONFIG_WDT_SBSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index bd9c1e9bf0..69eb4dbb7d 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -84,3 +84,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_MM_COMM_TEE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_CMD_NVME=y +CONFIG_NVME=y -- cgit v1.2.3 From 1f46e6790ad95dc22fbbeeafebf902eb1b2c6998 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Fri, 23 Oct 2020 13:35:27 +0530 Subject: pci: layerscape: move per-pci device fdt fixup in a function Move the pci device related fdt fixup in a function in order to re-use it in a following patch. While at it, improve the error handling. Signed-off-by: Laurentiu Tudor [Rebased] Signed-off-by: Priyanka Jain --- drivers/pci/pcie_layerscape_fixup.c | 60 +++++++++++++++++++++---------------- 1 file changed, 34 insertions(+), 26 deletions(-) diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index 1709cd3d23..db2b0e2277 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -174,12 +174,41 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob, } } +static int fdt_fixup_pcie_device_ls(void *blob, pci_dev_t bdf, + struct ls_pcie_rc *pcie_rc) +{ + int streamid, index; + + streamid = pcie_next_streamid(pcie_rc->stream_id_cur, + pcie_rc->pcie->idx); + if (streamid < 0) { + printf("ERROR: out of stream ids for BDF %d.%d.%d\n", + PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); + return -ENOENT; + } + pcie_rc->stream_id_cur++; + + index = ls_pcie_next_lut_index(pcie_rc); + if (index < 0) { + printf("ERROR: out of LUT indexes for BDF %d.%d.%d\n", + PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); + return -ENOENT; + } + + /* map PCI b.d.f to streamID in LUT */ + ls_pcie_lut_set_mapping(pcie_rc, index, bdf >> 8, streamid); + /* update msi-map in device tree */ + fdt_pcie_set_msi_map_entry_ls(blob, pcie_rc, bdf >> 8, streamid); + /* update iommu-map in device tree */ + fdt_pcie_set_iommu_map_entry_ls(blob, pcie_rc, bdf >> 8, streamid); + + return 0; +} + static void fdt_fixup_pcie_ls(void *blob) { struct udevice *dev, *bus; struct ls_pcie_rc *pcie_rc; - int streamid; - int index; pci_dev_t bdf; /* Scan all known buses */ @@ -196,32 +225,11 @@ static void fdt_fixup_pcie_ls(void *blob) pcie_rc = dev_get_priv(bus); - streamid = pcie_next_streamid(pcie_rc->stream_id_cur, - pcie_rc->pcie->idx); - if (streamid < 0) { - debug("ERROR: no stream ids free\n"); - continue; - } else { - pcie_rc->stream_id_cur++; - } - - index = ls_pcie_next_lut_index(pcie_rc); - if (index < 0) { - debug("ERROR: no LUT indexes free\n"); - continue; - } - /* the DT fixup must be relative to the hose first_busno */ bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0); - /* map PCI b.d.f to streamID in LUT */ - ls_pcie_lut_set_mapping(pcie_rc, index, bdf >> 8, - streamid); - /* update msi-map in device tree */ - fdt_pcie_set_msi_map_entry_ls(blob, pcie_rc, bdf >> 8, - streamid); - /* update iommu-map in device tree */ - fdt_pcie_set_iommu_map_entry_ls(blob, pcie_rc, bdf >> 8, - streamid); + + if (fdt_fixup_pcie_device_ls(blob, bdf, pcie_rc) < 0) + break; } pcie_board_fix_fdt(blob); } -- cgit v1.2.3 From f4cd963325d2ed73a928ddf096da2471fdceeb55 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Thu, 10 Sep 2020 12:42:17 +0300 Subject: pci: layerscape: move pci node search in a common function Fix duplication of this code by placing it in a common function. Furthermore, the resulting function will be re-used in upcoming patches. Signed-off-by: Laurentiu Tudor Reviewed-by: Priyanka Jain --- drivers/pci/pcie_layerscape_fixup.c | 76 +++++++++++++++++-------------------- 1 file changed, 34 insertions(+), 42 deletions(-) diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index db2b0e2277..9f8ad09f6a 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -22,6 +22,34 @@ #include "pcie_layerscape.h" #include "pcie_layerscape_fixup_common.h" +static int fdt_pcie_get_nodeoffset(void *blob, struct ls_pcie_rc *pcie_rc) +{ + int nodeoffset; + uint svr; + char *compat = NULL; + + /* find pci controller node */ + nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", + pcie_rc->dbi_res.start); + if (nodeoffset < 0) { +#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ + svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; + if (svr == SVR_LS2088A || svr == SVR_LS2084A || + svr == SVR_LS2048A || svr == SVR_LS2044A || + svr == SVR_LS2081A || svr == SVR_LS2041A) + compat = "fsl,ls2088a-pcie"; + else + compat = CONFIG_FSL_PCIE_COMPAT; + + nodeoffset = + fdt_node_offset_by_compat_reg(blob, compat, + pcie_rc->dbi_res.start); +#endif + } + + return nodeoffset; +} + #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2) /* * Return next available LUT index. @@ -127,30 +155,11 @@ static void fdt_pcie_set_iommu_map_entry_ls(void *blob, u32 iommu_map[4]; int nodeoffset; int lenp; - uint svr; - char *compat = NULL; struct ls_pcie *pcie = pcie_rc->pcie; - /* find pci controller node */ - nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", - pcie_rc->dbi_res.start); - if (nodeoffset < 0) { -#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ - svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; - if (svr == SVR_LS2088A || svr == SVR_LS2084A || - svr == SVR_LS2048A || svr == SVR_LS2044A || - svr == SVR_LS2081A || svr == SVR_LS2041A) - compat = "fsl,ls2088a-pcie"; - else - compat = CONFIG_FSL_PCIE_COMPAT; - - if (compat) - nodeoffset = fdt_node_offset_by_compat_reg(blob, - compat, pcie_rc->dbi_res.start); -#endif - if (nodeoffset < 0) - return; - } + nodeoffset = fdt_pcie_get_nodeoffset(blob, pcie_rc); + if (nodeoffset < 0) + return; /* get phandle to iommu controller */ prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp); @@ -238,28 +247,11 @@ static void fdt_fixup_pcie_ls(void *blob) static void ft_pcie_rc_fix(void *blob, struct ls_pcie_rc *pcie_rc) { int off; - uint svr; - char *compat = NULL; struct ls_pcie *pcie = pcie_rc->pcie; - off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", - pcie_rc->dbi_res.start); - if (off < 0) { -#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ - svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; - if (svr == SVR_LS2088A || svr == SVR_LS2084A || - svr == SVR_LS2048A || svr == SVR_LS2044A || - svr == SVR_LS2081A || svr == SVR_LS2041A) - compat = "fsl,ls2088a-pcie"; - else - compat = CONFIG_FSL_PCIE_COMPAT; - if (compat) - off = fdt_node_offset_by_compat_reg(blob, - compat, pcie_rc->dbi_res.start); -#endif - if (off < 0) - return; - } + off = fdt_pcie_get_nodeoffset(blob, pcie_rc); + if (off < 0) + return; if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE) fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0); -- cgit v1.2.3 From 284d062ef1edda752eadd5aa8cb1df37c76dd272 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Thu, 10 Sep 2020 12:42:18 +0300 Subject: pci: add a few ARI related defines Add a few defines related to PCI ARI configuration. Signed-off-by: Laurentiu Tudor Reviewed-by: Priyanka Jain --- include/pci.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/pci.h b/include/pci.h index 1c5b36617e..d1ccf6c963 100644 --- a/include/pci.h +++ b/include/pci.h @@ -495,12 +495,18 @@ #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ +#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ +#define PCI_EXP_DEVCAP2_ARI 0x00000020 /* ARI Forwarding Supported */ +#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ +#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ + #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ /* Single Root I/O Virtualization Registers */ #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ #define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */ #define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */ +#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */ #define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ #define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ #define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ -- cgit v1.2.3 From 2a5bbb13cc39102a68fcc31056925427ab44b591 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Thu, 10 Sep 2020 12:42:19 +0300 Subject: pci: layerscape: add a way of specifying additional iommu mappings In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add an u-boot env var and a device tree property (to be used for example in more static scenarios such as hardwired PCI endpoints that get initialized later in the system setup) that would allow two things: - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number of VFs that will ever be created for it - for hot-plug case, specify the B.D.F with which the device will show up on the PCI bus More details can be found in the included documentation: arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra Signed-off-by: Laurentiu Tudor Reviewed-by: Priyanka Jain --- .../fsl-layerscape/doc/README.pci_iommu_extra | 67 +++++ drivers/pci/Kconfig | 12 + drivers/pci/pcie_layerscape_fixup.c | 328 +++++++++++++++++++++ 3 files changed, 407 insertions(+) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra new file mode 100644 index 0000000000..43db4d8e94 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra @@ -0,0 +1,67 @@ +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +Specifying extra IOMMU mappings for PCI controllers + +This feature can be enabled through the PCI_IOMMU_EXTRA_MAPPINGS Kconfig option. + +The "pci_iommu_extra" env var or "pci-iommu-extra" device tree property (to be +used for example in more static scenarios such as hardwired PCI endpoints that +get initialized later in the system setup) allows two things: + - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number + of VFs that will ever be created for it + - for hot-plug case, specify the B.D.F with which the device will show up on + the PCI bus + +The env var consists of a list of , pairs for a certain pci bus +identified by its controller's base register address, as defined in the "reg" +property in the device tree. + +pci_iommu_extra = pci@,,,,, + pci@,,,,,... + +where: + is the base register address of the pci controller for which the + subsequent , pairs apply + identifies to which B.D.F the action applies to + can be: + - "vfs=" to specify that for the PCI EP identified previously by + the to include mappings for of VFs. + The variant "noari_vfs=" is available to disable taking ARI into + account. + - "hp" to specify that on this there will be a hot-plugged device so + it needs a mapping +The device tree property must be placed under the correct pci controller node +and only the bdf and action pairs need to be specified, like this: + +pci-iommu-extra = ",,,,..."; + +Note: the env var has priority over the device tree property. + +For example, given this configuration on bus 6: + +=> pci 6 +Scanning PCI devices on bus 6 +BusDevFun VendorId DeviceId Device Class Sub-Class +_____________________________________________________________ +06.00.00 0x8086 0x1572 Network controller 0x00 +06.00.01 0x8086 0x1572 Network controller 0x00 + +The following u-boot env var will create iommu mappings for 3 VFs for each PF: + +=> setenv pci_iommu_extra pci@0x3800000,6.0.0,vfs=3,6.0.1,vfs=3 + +For the device tree case, this would be specified like this: + +pci-iommu-extra = "6.0.0,vfs=3,6.0.1,vfs=3"; + +To add an iommu mapping for a hot-plugged device, please see following example: + +=> setenv pci_iommu_extra pci@0x3800000,2.16.0,hp + +For the device tree case, this would be specified like this: + +pci-iommu-extra = "2.16.0,hp"; diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index dd1cc65229..af92784950 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -179,6 +179,18 @@ config PCIE_LAYERSCAPE_RC configured to Root Complex mode by clearing the corresponding bit of RCW[HOST_AGT_PEX]. +config PCI_IOMMU_EXTRA_MAPPINGS + bool "Support for specifying extra IOMMU mappings for PCI" + depends on PCIE_LAYERSCAPE_RC + help + Enable support for specifying extra IOMMU mappings for PCI + controllers through a special env var called "pci_iommu_extra" or + through a device tree property named "pci-iommu-extra" placed in + the node describing the PCI controller. + The intent is to cover SR-IOV scenarios which need mappings for VFs + and PCI hot-plug scenarios. More documentation can be found under: + arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra + config PCIE_LAYERSCAPE_EP bool "Layerscape PCIe Endpoint mode support" depends on DM_PCI diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index 9f8ad09f6a..c75cf26e0a 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -19,6 +19,8 @@ #ifdef CONFIG_ARM #include #endif +#include +#include #include "pcie_layerscape.h" #include "pcie_layerscape_fixup_common.h" @@ -214,11 +216,292 @@ static int fdt_fixup_pcie_device_ls(void *blob, pci_dev_t bdf, return 0; } +struct extra_iommu_entry { + int action; + pci_dev_t bdf; + int num_vfs; + bool noari; +}; + +#define EXTRA_IOMMU_ENTRY_HOTPLUG 1 +#define EXTRA_IOMMU_ENTRY_VFS 2 + +static struct extra_iommu_entry *get_extra_iommu_ents(void *blob, + int nodeoffset, + phys_addr_t addr, + int *cnt) +{ + const char *s, *p, *tok; + struct extra_iommu_entry *entries; + int i = 0, b, d, f; + + /* + * Retrieve extra IOMMU configuration from env var or from device tree. + * Env var is given priority. + */ + s = env_get("pci_iommu_extra"); + if (!s) { + s = fdt_getprop(blob, nodeoffset, "pci-iommu-extra", NULL); + } else { + phys_addr_t pci_base; + char *endp; + + /* + * In env var case the config string has "pci@0x..." in + * addition. Parse this part and match it by address against + * the input pci controller's registers base address. + */ + tok = s; + p = strchrnul(s + 1, ','); + s = NULL; + do { + if (!strncmp(tok, "pci", 3)) { + pci_base = simple_strtoul(tok + 4, &endp, 0); + if (pci_base == addr) { + s = endp + 1; + break; + } + } + p = strchrnul(p + 1, ','); + tok = p + 1; + } while (*p); + } + + /* + * If no env var or device tree property found or pci register base + * address mismatches, bail out + */ + if (!s) + return NULL; + + /* + * In order to find how many action entries to allocate, count number + * of actions by interating through the pairs of bdfs and actions. + */ + *cnt = 0; + p = s; + while (*p && strncmp(p, "pci", 3)) { + if (*p == ',') + (*cnt)++; + p++; + } + if (!(*p)) + (*cnt)++; + + if (!(*cnt) || (*cnt) % 2) { + printf("ERROR: invalid or odd extra iommu token count %d\n", + *cnt); + return NULL; + } + *cnt = (*cnt) / 2; + + entries = malloc((*cnt) * sizeof(*entries)); + if (!entries) { + printf("ERROR: fail to allocate extra iommu entries\n"); + return NULL; + } + + /* + * Parse action entries one by one and store the information in the + * newly allocated actions array. + */ + p = s; + while (p) { + /* Extract BDF */ + b = simple_strtoul(p, (char **)&p, 0); p++; + d = simple_strtoul(p, (char **)&p, 0); p++; + f = simple_strtoul(p, (char **)&p, 0); p++; + entries[i].bdf = PCI_BDF(b, d, f); + + /* Parse action */ + if (!strncmp(p, "hp", 2)) { + /* Hot-plug entry */ + entries[i].action = EXTRA_IOMMU_ENTRY_HOTPLUG; + p += 2; + } else if (!strncmp(p, "vfs", 3) || + !strncmp(p, "noari_vfs", 9)) { + /* VFs or VFs with ARI disabled entry */ + entries[i].action = EXTRA_IOMMU_ENTRY_VFS; + entries[i].noari = !strncmp(p, "noari_vfs", 9); + + /* + * Parse and store total number of VFs to allocate + * IOMMU entries for. + */ + p = strchr(p, '='); + entries[i].num_vfs = simple_strtoul(p + 1, (char **)&p, + 0); + if (*p) + p++; + } else { + printf("ERROR: invalid action in extra iommu entry\n"); + free(entries); + + return NULL; + } + + if (!(*p) || !strncmp(p, "pci", 3)) + break; + + i++; + } + + return entries; +} + +static void get_vf_offset_and_stride(struct udevice *dev, int sriov_pos, + struct extra_iommu_entry *entry, + u16 *offset, u16 *stride) +{ + u16 tmp16; + u32 tmp32; + bool have_ari = false; + int pos; + struct udevice *pf_dev; + + dm_pci_read_config16(dev, sriov_pos + PCI_SRIOV_TOTAL_VF, &tmp16); + if (entry->num_vfs > tmp16) { + printf("WARN: requested no. of VFs %d exceeds total of %d\n", + entry->num_vfs, tmp16); + } + + /* + * The code below implements the VF Discovery recomandations specified + * in PCIe base spec "9.2.1.2 VF Discovery", quoted below: + * + * VF Discovery + * + * The First VF Offset and VF Stride fields in the SR-IOV extended + * capability are 16-bit Routing ID offsets. These offsets are used to + * compute the Routing IDs for the VFs with the following restrictions: + * - The value in NumVFs in a PF (Section 9.3.3.7) may affect the + * values in First VF Offset (Section 9.3.3.9) and VF Stride + * (Section 9.3.3.10) of that PF. + * - The value in ARI Capable Hierarchy (Section 9.3.3.3.5) in the + * lowest-numbered PF of the Device (for example PF0) may affect + * the values in First VF Offset and VF Stride in all PFs of the + * Device. + * - NumVFs of a PF may only be changed when VF Enable + * (Section 9.3.3.3.1) of that PF is Clear. + * - ARI Capable Hierarchy (Section 9.3.3.3.5) may only be changed + * when VF Enable is Clear in all PFs of a Device. + */ + + /* Clear VF enable for all PFs */ + device_foreach_child(pf_dev, dev->parent) { + dm_pci_read_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, + &tmp16); + tmp16 &= ~PCI_SRIOV_CTRL_VFE; + dm_pci_write_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, + tmp16); + } + + /* Obtain a reference to PF0 device */ + if (dm_pci_bus_find_bdf(PCI_BDF(PCI_BUS(entry->bdf), + PCI_DEV(entry->bdf), 0), &pf_dev)) { + printf("WARN: failed to get PF0\n"); + } + + if (entry->noari) + goto skip_ari; + + /* Check that connected downstream port supports ARI Forwarding */ + pos = dm_pci_find_capability(dev->parent, PCI_CAP_ID_EXP); + dm_pci_read_config32(dev->parent, pos + PCI_EXP_DEVCAP2, &tmp32); + if (!(tmp32 & PCI_EXP_DEVCAP2_ARI)) + goto skip_ari; + + /* Check that PF supports Alternate Routing ID */ + if (!dm_pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) + goto skip_ari; + + /* Set ARI Capable Hierarcy for PF0 */ + dm_pci_read_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, &tmp16); + tmp16 |= PCI_SRIOV_CTRL_ARI; + dm_pci_write_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, tmp16); + have_ari = true; + +skip_ari: + if (!have_ari) { + /* + * No ARI support or disabled so clear ARI Capable Hierarcy + * for PF0 + */ + dm_pci_read_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, + &tmp16); + tmp16 &= ~PCI_SRIOV_CTRL_ARI; + dm_pci_write_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, + tmp16); + } + + /* Set requested number of VFs */ + dm_pci_write_config16(dev, sriov_pos + PCI_SRIOV_NUM_VF, + entry->num_vfs); + + /* Read VF stride and offset with the configs just made */ + dm_pci_read_config16(dev, sriov_pos + PCI_SRIOV_VF_OFFSET, offset); + dm_pci_read_config16(dev, sriov_pos + PCI_SRIOV_VF_STRIDE, stride); + + if (have_ari) { + /* Reset to default ARI Capable Hierarcy bit for PF0 */ + dm_pci_read_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, + &tmp16); + tmp16 &= ~PCI_SRIOV_CTRL_ARI; + dm_pci_write_config16(pf_dev, sriov_pos + PCI_SRIOV_CTRL, + tmp16); + } + /* Reset to default the number of VFs */ + dm_pci_write_config16(dev, sriov_pos + PCI_SRIOV_NUM_VF, 0); +} + +static int fdt_fixup_pci_vfs(void *blob, struct extra_iommu_entry *entry, + struct ls_pcie_rc *pcie_rc) +{ + struct udevice *dev, *bus; + u16 vf_offset, vf_stride; + int i, sriov_pos; + pci_dev_t bdf; + + if (dm_pci_bus_find_bdf(entry->bdf, &dev)) { + printf("ERROR: BDF %d.%d.%d not found\n", PCI_BUS(entry->bdf), + PCI_DEV(entry->bdf), PCI_FUNC(entry->bdf)); + return 0; + } + + sriov_pos = dm_pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV); + if (!sriov_pos) { + printf("WARN: trying to set VFs on non-SRIOV dev\n"); + return 0; + } + + get_vf_offset_and_stride(dev, sriov_pos, entry, &vf_offset, &vf_stride); + + for (bus = dev; device_is_on_pci_bus(bus);) + bus = bus->parent; + + bdf = entry->bdf - PCI_BDF(bus->seq, 0, 0) + (vf_offset << 8); + + for (i = 0; i < entry->num_vfs; i++) { + if (fdt_fixup_pcie_device_ls(blob, bdf, pcie_rc) < 0) + return -1; + bdf += vf_stride << 8; + } + + printf("Added %d iommu VF mappings for PF %d.%d.%d\n", + entry->num_vfs, PCI_BUS(entry->bdf), + PCI_DEV(entry->bdf), PCI_FUNC(entry->bdf)); + + return 0; +} + static void fdt_fixup_pcie_ls(void *blob) { struct udevice *dev, *bus; struct ls_pcie_rc *pcie_rc; pci_dev_t bdf; + struct extra_iommu_entry *entries; + int i, cnt, nodeoffset; + /* Scan all known buses */ for (pci_find_first_device(&dev); @@ -240,6 +523,51 @@ static void fdt_fixup_pcie_ls(void *blob) if (fdt_fixup_pcie_device_ls(blob, bdf, pcie_rc) < 0) break; } + + if (!IS_ENABLED(CONFIG_PCI_IOMMU_EXTRA_MAPPINGS)) + goto skip; + + list_for_each_entry(pcie_rc, &ls_pcie_list, list) { + nodeoffset = fdt_pcie_get_nodeoffset(blob, pcie_rc); + if (nodeoffset < 0) { + printf("ERROR: couldn't find pci node\n"); + continue; + } + + entries = get_extra_iommu_ents(blob, nodeoffset, + pcie_rc->dbi_res.start, &cnt); + if (!entries) + continue; + + for (i = 0; i < cnt; i++) { + if (entries[i].action == EXTRA_IOMMU_ENTRY_HOTPLUG) { + bdf = entries[i].bdf; + printf("Added iommu map for hotplug %d.%d.%d\n", + PCI_BUS(bdf), PCI_DEV(bdf), + PCI_FUNC(bdf)); + if (fdt_fixup_pcie_device_ls(blob, bdf, + pcie_rc) < 0) { + free(entries); + return; + } + } else if (entries[i].action == EXTRA_IOMMU_ENTRY_VFS) { + if (fdt_fixup_pci_vfs(blob, &entries[i], + pcie_rc) < 0) { + free(entries); + return; + } + } else { + printf("Invalid action %d for BDF %d.%d.%d\n", + entries[i].action, + PCI_BUS(entries[i].bdf), + PCI_DEV(entries[i].bdf), + PCI_FUNC(entries[i].bdf)); + } + } + free(entries); + } + +skip: pcie_board_fix_fdt(blob); } #endif -- cgit v1.2.3 From bcc6c574525caa36cd863b7fd78a037d741d622d Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Fri, 23 Oct 2020 13:39:33 +0530 Subject: cmd: optee_rpmb command for read/write of rpmb from optee Enable "optee_rpmb" command to write/read named persistent values created on RPMB by opening session with OPTEE AVB TA. This provides easy test for establishing a session with OPTEE TA and storage of persistent data in MMC RPMB. It includes following subcommands: optee_rpmb read_pvalue:read persistent values on rpmb via OPTEE AVB TA optee_rpmb write_pvalue:write persistent values on rpmb via OPTEE AVB TA Signed-off-by: Ruchika Gupta [Rebased] Signed-off-by: Priyanka Jain --- cmd/Kconfig | 8 ++ cmd/Makefile | 1 + cmd/optee_rpmb.c | 272 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 281 insertions(+) create mode 100644 cmd/optee_rpmb.c diff --git a/cmd/Kconfig b/cmd/Kconfig index a3166e4f31..860c00ff62 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1066,6 +1066,14 @@ config CMD_CLONE initial flashing by external block device without network or usb support. +config CMD_OPTEE_RPMB + bool "Enable read/write support on RPMB via OPTEE" + depends on SUPPORT_EMMC_RPMB && OPTEE + help + Enable the commands for reading, writing persistent named values + in the Replay Protection Memory Block partition in eMMC by + using Persistent Objects in OPTEE + config CMD_MTD bool "mtd" depends on MTD diff --git a/cmd/Makefile b/cmd/Makefile index 19a891633f..a1eee43599 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -97,6 +97,7 @@ obj-$(CONFIG_CMD_MII) += mii.o obj-$(CONFIG_CMD_MDIO) += mdio.o obj-$(CONFIG_CMD_MISC) += misc.o obj-$(CONFIG_CMD_MMC) += mmc.o +obj-$(CONFIG_CMD_OPTEE_RPMB) += optee_rpmb.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_CMD_MTD) += mtd.o obj-$(CONFIG_CMD_MTDPARTS) += mtdparts.o diff --git a/cmd/optee_rpmb.c b/cmd/optee_rpmb.c new file mode 100644 index 0000000000..0d6b1cb1d8 --- /dev/null +++ b/cmd/optee_rpmb.c @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct udevice *tee; +static u32 session; + +static int avb_ta_open_session(void) +{ + const struct tee_optee_ta_uuid uuid = TA_AVB_UUID; + struct tee_open_session_arg arg; + int rc; + + tee = tee_find_device(tee, NULL, NULL, NULL); + if (!tee) + return -ENODEV; + + memset(&arg, 0, sizeof(arg)); + tee_optee_ta_uuid_to_octets(arg.uuid, &uuid); + rc = tee_open_session(tee, &arg, 0, NULL); + if (!rc) + session = arg.session; + + return 0; +} + +static int invoke_func(u32 func, ulong num_param, struct tee_param *param) +{ + struct tee_invoke_arg arg; + + if (!tee) + if (avb_ta_open_session()) + return -ENODEV; + + memset(&arg, 0, sizeof(arg)); + arg.func = func; + arg.session = session; + + if (tee_invoke_func(tee, &arg, num_param, param)) + return -EFAULT; + switch (arg.ret) { + case TEE_SUCCESS: + return 0; + case TEE_ERROR_OUT_OF_MEMORY: + case TEE_ERROR_STORAGE_NO_SPACE: + return -ENOSPC; + case TEE_ERROR_ITEM_NOT_FOUND: + return -EIO; + case TEE_ERROR_TARGET_DEAD: + /* + * The TA has paniced, close the session to reload the TA + * for the next request. + */ + tee_close_session(tee, session); + tee = NULL; + return -EIO; + default: + return -EIO; + } +} + +static int read_persistent_value(const char *name, + size_t buffer_size, + u8 *out_buffer, + size_t *out_num_bytes_read) +{ + int rc = 0; + struct tee_shm *shm_name; + struct tee_shm *shm_buf; + struct tee_param param[2]; + size_t name_size = strlen(name) + 1; + + if (!tee) + if (avb_ta_open_session()) + return -ENODEV; + + rc = tee_shm_alloc(tee, name_size, + TEE_SHM_ALLOC, &shm_name); + if (rc) + return -ENOMEM; + + rc = tee_shm_alloc(tee, buffer_size, + TEE_SHM_ALLOC, &shm_buf); + if (rc) { + rc = -ENOMEM; + goto free_name; + } + + memcpy(shm_name->addr, name, name_size); + + memset(param, 0, sizeof(param)); + param[0].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT; + param[0].u.memref.shm = shm_name; + param[0].u.memref.size = name_size; + param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INOUT; + param[1].u.memref.shm = shm_buf; + param[1].u.memref.size = buffer_size; + + rc = invoke_func(TA_AVB_CMD_READ_PERSIST_VALUE, + 2, param); + if (rc) + goto out; + + if (param[1].u.memref.size > buffer_size) { + rc = -EINVAL; + goto out; + } + + *out_num_bytes_read = param[1].u.memref.size; + + memcpy(out_buffer, shm_buf->addr, *out_num_bytes_read); + +out: + tee_shm_free(shm_buf); +free_name: + tee_shm_free(shm_name); + + return rc; +} + +static int write_persistent_value(const char *name, + size_t value_size, + const u8 *value) +{ + int rc = 0; + struct tee_shm *shm_name; + struct tee_shm *shm_buf; + struct tee_param param[2]; + size_t name_size = strlen(name) + 1; + + if (!tee) { + if (avb_ta_open_session()) + return -ENODEV; + } + if (!value_size) + return -EINVAL; + + rc = tee_shm_alloc(tee, name_size, + TEE_SHM_ALLOC, &shm_name); + if (rc) + return -ENOMEM; + + rc = tee_shm_alloc(tee, value_size, + TEE_SHM_ALLOC, &shm_buf); + if (rc) { + rc = -ENOMEM; + goto free_name; + } + + memcpy(shm_name->addr, name, name_size); + memcpy(shm_buf->addr, value, value_size); + + memset(param, 0, sizeof(param)); + param[0].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT; + param[0].u.memref.shm = shm_name; + param[0].u.memref.size = name_size; + param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT; + param[1].u.memref.shm = shm_buf; + param[1].u.memref.size = value_size; + + rc = invoke_func(TA_AVB_CMD_WRITE_PERSIST_VALUE, + 2, param); + if (rc) + goto out; + +out: + tee_shm_free(shm_buf); +free_name: + tee_shm_free(shm_name); + + return rc; +} + +int do_optee_rpmb_read(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + const char *name; + size_t bytes; + size_t bytes_read; + void *buffer; + char *endp; + + if (argc != 3) + return CMD_RET_USAGE; + + name = argv[1]; + bytes = simple_strtoul(argv[2], &endp, 10); + if (*endp && *endp != '\n') + return CMD_RET_USAGE; + + buffer = malloc(bytes); + if (!buffer) + return CMD_RET_FAILURE; + + if (read_persistent_value(name, bytes, buffer, &bytes_read) == 0) { + printf("Read %zu bytes, value = %s\n", bytes_read, + (char *)buffer); + free(buffer); + return CMD_RET_SUCCESS; + } + + printf("Failed to read persistent value\n"); + + free(buffer); + + return CMD_RET_FAILURE; +} + +int do_optee_rpmb_write(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + const char *name; + const char *value; + + if (argc != 3) + return CMD_RET_USAGE; + + name = argv[1]; + value = argv[2]; + + if (write_persistent_value(name, strlen(value) + 1, + (const uint8_t *)value) == 0) { + printf("Wrote %zu bytes\n", strlen(value) + 1); + return CMD_RET_SUCCESS; + } + + printf("Failed to write persistent value\n"); + + return CMD_RET_FAILURE; +} + +static struct cmd_tbl cmd_optee_rpmb[] = { + U_BOOT_CMD_MKENT(read_pvalue, 3, 0, do_optee_rpmb_read, "", ""), + U_BOOT_CMD_MKENT(write_pvalue, 3, 0, do_optee_rpmb_write, "", ""), +}; + +static int do_optee_rpmb(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct cmd_tbl *cp; + + cp = find_cmd_tbl(argv[1], cmd_optee_rpmb, ARRAY_SIZE(cmd_optee_rpmb)); + + argc--; + argv++; + + if (!cp || argc > cp->maxargs) + return CMD_RET_USAGE; + + if (flag == CMD_FLAG_REPEAT) + return CMD_RET_FAILURE; + + return cp->cmd(cmdtp, flag, argc, argv); +} + +U_BOOT_CMD ( + optee_rpmb, 29, 0, do_optee_rpmb, + "Provides commands for testing secure storage on RPMB on OPTEE", + "read_pvalue - read a persistent value \n" + "optee_rpmb write_pvalue - write a persistent value \n" + ); -- cgit v1.2.3 From 52c7c1cc153b6fb049f1bc415c97675dae468396 Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Fri, 23 Oct 2020 13:43:57 +0530 Subject: configs: lx2160a: Enable OPTEE support Enable support to compile OPTEE driver, access AVB TA and RPMB API's access via RPC from OPTEE for lx2160 Signed-off-by: Ruchika Gupta [Rebased] Signed-off-by: Priyanka Jain --- configs/lx2160ardb_tfa_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 90b66e1376..81bbebd9e7 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -83,3 +83,8 @@ CONFIG_WDT_SBSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y CONFIG_CMD_NVME=y CONFIG_NVME=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_OPTEE_TA_AVB=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_CMD_OPTEE_RPMB=y -- cgit v1.2.3 From d5d6b548d950385cb66e1fa97ad5f6790bbca3ad Mon Sep 17 00:00:00 2001 From: "hui.song" Date: Thu, 24 Sep 2020 21:40:50 +0800 Subject: gpio: mpc8xxx: support fsl-layerscape platform Make the MPC8XXX gpio driver to support the fsl-layerscape. Signed-off-by: hui.song Reviewed-by: Priyanka Jain --- drivers/gpio/mpc8xxx_gpio.c | 108 +++++++++++++++++++++++++++++++++++--------- 1 file changed, 87 insertions(+), 21 deletions(-) diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c index 1dfd22522c..27881a7322 100644 --- a/drivers/gpio/mpc8xxx_gpio.c +++ b/drivers/gpio/mpc8xxx_gpio.c @@ -6,12 +6,15 @@ * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is * * Copyright 2010 eXMeritus, A Boeing Company + * Copyright 2020 NXP */ #include #include #include #include +#include +#include struct ccsr_gpio { u32 gpdir; @@ -20,6 +23,7 @@ struct ccsr_gpio { u32 gpier; u32 gpimr; u32 gpicr; + u32 gpibe; }; struct mpc8xxx_gpio_data { @@ -35,6 +39,7 @@ struct mpc8xxx_gpio_data { */ u32 dat_shadow; ulong type; + bool little_endian; }; enum { @@ -47,33 +52,56 @@ inline u32 gpio_mask(uint gpio) return (1U << (31 - (gpio))); } -static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask) +static inline u32 mpc8xxx_gpio_get_val(struct udevice *dev, u32 mask) { - return in_be32(&base->gpdat) & mask; + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); + + if (data->little_endian) + return in_le32(&data->base->gpdat) & mask; + else + return in_be32(&data->base->gpdat) & mask; } -static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask) +static inline u32 mpc8xxx_gpio_get_dir(struct udevice *dev, u32 mask) { - return in_be32(&base->gpdir) & mask; + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); + + if (data->little_endian) + return in_le32(&data->base->gpdir) & mask; + else + return in_be32(&data->base->gpdir) & mask; } -static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask) +static inline int mpc8xxx_gpio_open_drain_val(struct udevice *dev, u32 mask) { - return in_be32(&base->gpodr) & mask; + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); + + if (data->little_endian) + return in_le32(&data->base->gpodr) & mask; + else + return in_be32(&data->base->gpodr) & mask; } -static inline void mpc8xxx_gpio_open_drain_on(struct ccsr_gpio *base, u32 +static inline void mpc8xxx_gpio_open_drain_on(struct udevice *dev, u32 gpios) { + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); /* GPODR register 1 -> open drain on */ - setbits_be32(&base->gpodr, gpios); + if (data->little_endian) + setbits_le32(&data->base->gpodr, gpios); + else + setbits_be32(&data->base->gpodr, gpios); } -static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base, +static inline void mpc8xxx_gpio_open_drain_off(struct udevice *dev, u32 gpios) { + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); /* GPODR register 0 -> open drain off (actively driven) */ - clrbits_be32(&base->gpodr, gpios); + if (data->little_endian) + clrbits_le32(&data->base->gpodr, gpios); + else + clrbits_be32(&data->base->gpodr, gpios); } static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio) @@ -82,7 +110,10 @@ static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio) u32 mask = gpio_mask(gpio); /* GPDIR register 0 -> input */ - clrbits_be32(&data->base->gpdir, mask); + if (data->little_endian) + clrbits_le32(&data->base->gpdir, mask); + else + clrbits_be32(&data->base->gpdir, mask); return 0; } @@ -100,10 +131,20 @@ static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value) data->dat_shadow &= ~mask; } - gpdir = in_be32(&base->gpdir); + if (data->little_endian) + gpdir = in_le32(&base->gpdir); + else + gpdir = in_be32(&base->gpdir); + gpdir |= gpio_mask(gpio); - out_be32(&base->gpdat, gpdir & data->dat_shadow); - out_be32(&base->gpdir, gpdir); + + if (data->little_endian) { + out_le32(&base->gpdat, gpdir & data->dat_shadow); + out_le32(&base->gpdir, gpdir); + } else { + out_be32(&base->gpdat, gpdir & data->dat_shadow); + out_be32(&base->gpdir, gpdir); + } return 0; } @@ -124,21 +165,20 @@ static int mpc8xxx_gpio_get_value(struct udevice *dev, uint gpio) { struct mpc8xxx_gpio_data *data = dev_get_priv(dev); - if (!!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio))) { + if (!!mpc8xxx_gpio_get_dir(dev, gpio_mask(gpio))) { /* Output -> use shadowed value */ return !!(data->dat_shadow & gpio_mask(gpio)); } /* Input -> read value from GPDAT register */ - return !!mpc8xxx_gpio_get_val(data->base, gpio_mask(gpio)); + return !!mpc8xxx_gpio_get_val(dev, gpio_mask(gpio)); } static int mpc8xxx_gpio_get_function(struct udevice *dev, uint gpio) { - struct mpc8xxx_gpio_data *data = dev_get_priv(dev); int dir; - dir = !!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio)); + dir = !!mpc8xxx_gpio_get_dir(dev, gpio_mask(gpio)); return dir ? GPIOF_OUTPUT : GPIOF_INPUT; } @@ -146,14 +186,33 @@ static int mpc8xxx_gpio_get_function(struct udevice *dev, uint gpio) static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev) { struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev); + struct mpc8xxx_gpio_data *data = dev_get_priv(dev); fdt_addr_t addr; - u32 reg[2]; + u32 i; + u32 reg[4]; + + if (ofnode_read_bool(dev->node, "little-endian")) + data->little_endian = true; + + if (data->little_endian) + dev_read_u32_array(dev, "reg", reg, 4); + else + dev_read_u32_array(dev, "reg", reg, 2); + + if (data->little_endian) { + for (i = 0; i < 2; i++) + reg[i] = be32_to_cpu(reg[i]); + } - dev_read_u32_array(dev, "reg", reg, 2); addr = dev_translate_address(dev, reg); plat->addr = addr; - plat->size = reg[1]; + + if (data->little_endian) + plat->size = reg[3]; + else + plat->size = reg[1]; + plat->ngpios = dev_read_u32_default(dev, "ngpios", 32); return 0; @@ -198,6 +257,13 @@ static int mpc8xxx_gpio_probe(struct udevice *dev) if (!str) return -ENOMEM; + if (ofnode_device_is_compatible(dev->node, "fsl,qoriq-gpio")) { + unsigned long gpibe = data->addr + sizeof(struct ccsr_gpio) + - sizeof(u32); + + out_be32((unsigned int *)gpibe, 0xffffffff); + } + uc_priv->bank_name = str; uc_priv->gpio_count = data->gpio_count; -- cgit v1.2.3 From c760095adbf222aefba00404b38a25bf5dee0909 Mon Sep 17 00:00:00 2001 From: Razvan Ionut Cirjan Date: Fri, 23 Oct 2020 16:20:38 +0530 Subject: net: lx2160a.c: Update to set ECx_PMUX precedence As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan [Rebased] Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 16 ++++++++-------- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 +- drivers/net/ldpaa_eth/lx2160a.c | 4 ++-- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index e610528544..596b88d3e2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1147,15 +1147,15 @@ int arch_early_init_r(void) * EC*_PMUX(rgmii) bits in RCW. * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits - * Now if a dpmac is enabled by serdes bits then it takes precedence - * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol - * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, - * then the dpmac is SGMII and not RGMII. + * Now if a dpmac is enabled as RGMII through ECx_PMUX then it takes + * precedence over SerDes protocol. i.e. in LX2160A if we select serdes + * protocol that configures dpmac17 as SGMII and set the EC1_PMUX as + * RGMII, then the dpmac is RGMII and not SGMII. * - * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in - * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled - * or not? if it is (fsl_serdes_init has already enabled the dpmac), - * then don't enable it. + * Therefore, even thought fsl_rgmii_init is after fsl_serdes_init + * function of SOC, the dpmac will be enabled as RGMII even if it was + * also enabled before as SGMII. If ECx_PMUX is not configured for + * RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init(). */ fsl_rgmii_init(); #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index baa9fa8529..24a64b7575 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -396,7 +396,7 @@ struct ccsr_gur { #define FSL_CHASSIS3_EC2_REGSR 27 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT 0 -#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x00000007 +#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x0000000C #define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT 2 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c index 1e62c64203..e57f1a19a5 100644 --- a/drivers/net/ldpaa_eth/lx2160a.c +++ b/drivers/net/ldpaa_eth/lx2160a.c @@ -92,7 +92,7 @@ void fsl_rgmii_init(void) & FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK; ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT; - if (!ec && (wriop_is_enabled_dpmac(17) == -ENODEV)) + if (!ec) wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID); #endif @@ -101,7 +101,7 @@ void fsl_rgmii_init(void) & FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK; ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT; - if (!ec && (wriop_is_enabled_dpmac(18) == -ENODEV)) + if (!ec) wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID); #endif } -- cgit v1.2.3 From 0205beb15612a63c365f7729af92fa32e6281987 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Thu, 15 Oct 2020 14:54:34 +0800 Subject: dm: pci: fsl: Correct the workaround of erratum A-007815 The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang Reviewed-by: Priyanka Jain --- drivers/pci/pcie_fsl.c | 20 ++++++++++++++++---- drivers/pci/pcie_fsl.h | 2 ++ 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index ab33459e28..fb50b8f518 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -396,6 +396,19 @@ static int fsl_pcie_init_atmu(struct fsl_pcie *pcie) return 0; } +static void fsl_pcie_dbi_read_only_reg_write_enable(struct fsl_pcie *pcie, + bool enable) +{ + u32 val; + + fsl_pcie_hose_read_config_dword(pcie, DBI_RO_WR_EN, &val); + if (enable) + val |= 1; + else + val &= ~1; + fsl_pcie_hose_write_config_dword(pcie, DBI_RO_WR_EN, val); +} + static int fsl_pcie_init_port(struct fsl_pcie *pcie) { ccsr_fsl_pci_t *regs = pcie->regs; @@ -470,7 +483,7 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie) * Set to 0 to protect the read-only registers. */ #ifdef CONFIG_SYS_FSL_ERRATUM_A007815 - clrbits_be32(®s->dbi_ro_wr_en, 0x01); + fsl_pcie_dbi_read_only_reg_write_enable(pcie, false); #endif /* @@ -504,13 +517,12 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie) static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie) { - ccsr_fsl_pci_t *regs = pcie->regs; u32 classcode_reg; u32 val; if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { classcode_reg = PCI_CLASS_REVISION; - setbits_be32(®s->dbi_ro_wr_en, 0x01); + fsl_pcie_dbi_read_only_reg_write_enable(pcie, true); } else { classcode_reg = CSR_CLASSCODE; } @@ -521,7 +533,7 @@ static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie) fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val); if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) - clrbits_be32(®s->dbi_ro_wr_en, 0x01); + fsl_pcie_dbi_read_only_reg_write_enable(pcie, false); return 0; } diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h index dc8368d559..70c5f4e4cf 100644 --- a/drivers/pci/pcie_fsl.h +++ b/drivers/pci/pcie_fsl.h @@ -26,6 +26,8 @@ /* PCIe Link Status Register */ #define PCI_LSR (FSL_PCIE_CAP_ID + 0x12) +#define DBI_RO_WR_EN 0x8bc + #ifndef CONFIG_SYS_PCI_MEMORY_BUS #define CONFIG_SYS_PCI_MEMORY_BUS 0 #endif -- cgit v1.2.3 From 4ceb5c6db2f4080042e5c3e036ab06b0178e32c4 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 15 Oct 2020 23:08:57 +0200 Subject: board: kontron: add sl28 support Add basic support for the Kontron SMARC-sAL28 board. This includes just the bare minimum to be able to bring up the board and boot linux. For now, the Single and Dual PHY variant is supported. Other variants will fall back to the basic variant. In particular, there is no watchdog support for now. This means that you have to disable the default watchdog, otherwise you'll end up in the recovery bootloader. See the board README for details. Signed-off-by: Michael Walle Reviewed-by: Tom Rini Tested-by: Heiko Thiery Reviewed-by: Priyanka Jain --- arch/arm/Kconfig | 11 ++ arch/arm/dts/Makefile | 3 + arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 135 +++++++++++++++ .../dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi | 2 + arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts | 15 ++ .../dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi | 2 + arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts | 48 ++++++ arch/arm/dts/fsl-ls1028a-kontron-sl28.dts | 189 +++++++++++++++++++++ board/kontron/sl28/Kconfig | 18 ++ board/kontron/sl28/MAINTAINERS | 7 + board/kontron/sl28/Makefile | 8 + board/kontron/sl28/common.c | 10 ++ board/kontron/sl28/ddr.c | 98 +++++++++++ board/kontron/sl28/sl28.c | 68 ++++++++ board/kontron/sl28/spl.c | 32 ++++ configs/kontron_sl28_defconfig | 107 ++++++++++++ doc/board/index.rst | 1 + doc/board/kontron/index.rst | 9 + doc/board/kontron/sl28.rst | 160 +++++++++++++++++ include/configs/kontron_sl28.h | 108 ++++++++++++ 20 files changed, 1031 insertions(+) create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28.dts create mode 100644 board/kontron/sl28/Kconfig create mode 100644 board/kontron/sl28/MAINTAINERS create mode 100644 board/kontron/sl28/Makefile create mode 100644 board/kontron/sl28/common.c create mode 100644 board/kontron/sl28/ddr.c create mode 100644 board/kontron/sl28/sl28.c create mode 100644 board/kontron/sl28/spl.c create mode 100644 configs/kontron_sl28_defconfig create mode 100644 doc/board/kontron/index.rst create mode 100644 doc/board/kontron/sl28.rst create mode 100644 include/configs/kontron_sl28.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 80f09601e4..b2f7fcbd6e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1620,6 +1620,16 @@ config TARGET_LS1046AFRWY development platform that supports the QorIQ LS1046A Layerscape Architecture processor. +config TARGET_SL28 + bool "Support sl28" + select ARCH_LS1028A + select ARM64 + select ARMV8_MULTIENTRY + select SUPPORT_SPL + select BINMAN + help + Support for Kontron SMARC-sAL28 board. + config TARGET_COLIBRI_PXA270 bool "Support colibri_pxa270" select CPU_PXA @@ -1998,6 +2008,7 @@ source "board/hisilicon/hikey/Kconfig" source "board/hisilicon/hikey960/Kconfig" source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" +source "board/kontron/sl28/Kconfig" source "board/myir/mys_6ulx/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b195723f16..d8b0a913be 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -424,6 +424,9 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1012a-2g5rdb.dtb \ fsl-ls1012a-frdm.dtb \ fsl-ls1012a-frwy.dtb +dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \ + fsl-ls1028a-kontron-sl28-var3.dtb \ + fsl-ls1028a-kontron-sl28-var4.dtb \ dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi new file mode 100644 index 0000000000..2375549c6e --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include + +/ { + aliases { + mmc0 = &esdhc0; + mmc1 = &esdhc1; + i2c0 = &i2c0; + i2c1 = &i2c3; + i2c2 = &i2c4; + rtc0 = &rtc; + ethernet0 = &enetc0; + ethernet1 = &enetc1; + ethernet2 = &enetc2; + ethernet3 = &enetc6; + }; + + binman { + filename = "u-boot.rom"; + pad-byte = <0xff>; + + u-boot-spl { + }; + + fit { + offset = ; + description = "FIT image with multiple configurations"; + + images { + uboot { + description = "U-Boot"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compression = "none"; + load = ; + + u-boot-nodtb { + }; + }; + + fdt-1 { + description = "fsl-ls1028a-kontron-sl28"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + blob { + filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28.dtb"; + }; + }; + + fdt-2 { + description = "fsl-ls1028a-kontron-sl28-var3"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + blob { + filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dtb"; + }; + }; + + fdt-3 { + description = "fsl-ls1028a-kontron-sl28-var4"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + blob { + filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dtb"; + }; + }; + }; + + configurations { + default = "conf-1"; + + conf-1 { + description = "fsl-ls1028a-kontron-sl28"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-1"; + }; + + conf-2 { + description = "fsl-ls1028a-kontron-sl28-var3"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-2"; + }; + + conf-3 { + description = "fsl-ls1028a-kontron-sl28-var4"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-3"; + }; + }; + }; + }; +}; + +&i2c0 { + rtc: rtc@32 { + }; +}; + +&fspi { + u-boot,dm-pre-reloc; + flash@0 { + u-boot,dm-pre-reloc; + }; +}; + +&dspi2 { + u-boot,dm-pre-reloc; +}; + +&esdhc0 { + u-boot,dm-pre-reloc; +}; + +&esdhc1 { + u-boot,dm-pre-reloc; +}; + +&serial0 { + u-boot,dm-pre-reloc; +}; + +&sysclk { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi new file mode 100644 index 0000000000..79b771e074 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi" diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts new file mode 100644 index 0000000000..0c8b2af41a --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the Kontron SMARC-sAL28 board. + * + * Copyright (C) 2019 Michael Walle + * + */ + +/dts-v1/; +#include "fsl-ls1028a-kontron-sl28.dts" + +/ { + model = "Kontron SMARC-sAL28 (Single PHY)"; + compatible = "kontron,sl28-var3", "kontron,sl28", "fsl,ls1028a"; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi new file mode 100644 index 0000000000..79b771e074 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi" diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts new file mode 100644 index 0000000000..33b16303ad --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the Kontron SMARC-sAL28 board. + * + * This is for the network variant 4 which has two ethernet ports. It + * extends the base and provides one more port connected via RGMII. + * + * Copyright (C) 2019 Michael Walle + * + */ + +/dts-v1/; +#include "fsl-ls1028a-kontron-sl28.dts" +#include + +/ { + model = "Kontron SMARC-sAL28 (Dual PHY)"; + compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a"; +}; + +&enetc1 { + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&mdio0 { + phy1: ethernet-phy@4 { + reg = <0x4>; + eee-broken-1000t; + eee-broken-100tx; + + qca,clk-out-frequency = <125000000>; + qca,clk-out-strength = ; + + vddio-supply = <&vddh>; + + vddio: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddh: vddh-regulator { + regulator-name = "VDDH"; + }; + }; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts new file mode 100644 index 0000000000..9561a58562 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the Kontron SMARC-sAL28 board. + * + * Copyright (C) 2019 Michael Walle + * + */ + +/dts-v1/; +#include "fsl-ls1028a.dtsi" + +/ { + model = "Kontron SMARC-sAL28"; + compatible = "kontron,sl28", "fsl,ls1028a"; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &lpuart1; + spi0 = &fspi; + spi1 = &dspi2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&dspi2 { + status = "okay"; +}; + +&enetc0 { + phy-handle = <&phy0>; + phy-mode = "sgmii"; + status = "okay"; +}; + +&enetc2 { + status = "disabled"; +}; + +&enetc6 { + status = "disabled"; +}; + +&esdhc0 { + sd-uhs-sdr104; + sd-uhs-sdr50; + sd-uhs-sdr25; + sd-uhs-sdr12; + status = "okay"; +}; + +&esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; + status = "okay"; +}; + +&fspi { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + m25p,fast-read; + spi-max-frequency = <133000000>; + reg = <0>; + /* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */ + spi-rx-bus-width = <2>; /* 2 SPI Rx lines */ + spi-tx-bus-width = <1>; /* 1 SPI Tx line */ + + partition@0 { + reg = <0x000000 0x010000>; + label = "rcw"; + read-only; + }; + + partition@10000 { + reg = <0x010000 0x0f0000>; + label = "failsafe bootloader"; + read-only; + }; + + partition@100000 { + reg = <0x100000 0x040000>; + label = "failsafe DP firmware"; + read-only; + }; + + partition@140000 { + reg = <0x140000 0x0a0000>; + label = "failsafe trusted firmware"; + read-only; + }; + + partition@1e0000 { + reg = <0x1e0000 0x020000>; + label = "reserved"; + read-only; + }; + + partition@200000 { + reg = <0x200000 0x010000>; + label = "configuration store"; + }; + + partition@210000 { + reg = <0x210000 0x0f0000>; + label = "bootloader"; + }; + + partition@300000 { + reg = <0x300000 0x040000>; + label = "DP firmware"; + }; + + partition@340000 { + reg = <0x340000 0x0a0000>; + label = "trusted firmware"; + }; + + partition@3e0000 { + reg = <0x3e0000 0x020000>; + label = "bootloader environment"; + }; + }; +}; + +&i2c0 { + status = "okay"; + + rtc@32 { + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +&lpuart1 { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + phy0: ethernet-phy@5 { + reg = <0x5>; + eee-broken-1000t; + eee-broken-100tx; + }; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/board/kontron/sl28/Kconfig b/board/kontron/sl28/Kconfig new file mode 100644 index 0000000000..cdec39be01 --- /dev/null +++ b/board/kontron/sl28/Kconfig @@ -0,0 +1,18 @@ +if TARGET_SL28 + +config SYS_BOARD + default "sl28" + +config SYS_VENDOR + default "kontron" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "kontron_sl28" + +config SYS_TEXT_BASE + default 0x96000000 + +endif diff --git a/board/kontron/sl28/MAINTAINERS b/board/kontron/sl28/MAINTAINERS new file mode 100644 index 0000000000..a7b0fbbdd1 --- /dev/null +++ b/board/kontron/sl28/MAINTAINERS @@ -0,0 +1,7 @@ +Kontron SMARC-sAL28 board +M: Michael Walle +S: Maintained +F: arch/arm/dts/fsl-ls1028a-kontron-sl28-* +F: board/kontron/sl28/ +F: configs/kontron_sl28_defconfig +F: include/configs/kontron_sl28.h diff --git a/board/kontron/sl28/Makefile b/board/kontron/sl28/Makefile new file mode 100644 index 0000000000..0f1866c874 --- /dev/null +++ b/board/kontron/sl28/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ + +ifndef CONFIG_SPL_BUILD +obj-y += sl28.o +endif + +obj-y += common.o ddr.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/kontron/sl28/common.c b/board/kontron/sl28/common.c new file mode 100644 index 0000000000..14704f7051 --- /dev/null +++ b/board/kontron/sl28/common.c @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include + +int board_early_init_f(void) +{ + fsl_lsch3_early_init_f(); + return 0; +} diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c new file mode 100644 index 0000000000..d111b6d4c3 --- /dev/null +++ b/board/kontron/sl28/ddr.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define DCFG_GPPORCR1 0x20 + +#define GPPORCR1_MEM_MASK (0x7 << 5) +#define GPPORCR1_MEM_512MB_CS0 (0x0 << 5) +#define GPPORCR1_MEM_1GB_CS0 (0x1 << 5) +#define GPPORCR1_MEM_2GB_CS0 (0x2 << 5) +#define GPPORCR1_MEM_4GB_CS0_1 (0x3 << 5) +#define GPPORCR1_MEM_4GB_CS0_2 (0x4 << 5) +#define GPPORCR1_MEM_8GB_CS0_1_2_3 (0x5 << 5) +#define GPPORCR1_MEM_8GB_CS0_1 (0x6 << 5) + +static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = { + .cs[0].bnds = 0x0000007f, + .cs[0].config = 0x80044402, + .cs[1].bnds = 0x008000ff, + .cs[1].config = 0x80004402, + + .timing_cfg_0 = 0x9011010c, + .timing_cfg_3 = 0x010c1000, + .timing_cfg_1 = 0xbcb48c66, + .timing_cfg_2 = 0x0fc0d118, + .ddr_sdram_cfg = 0xe70c000c, + .ddr_sdram_cfg_2 = 0x24401111, + .ddr_sdram_mode = 0x00441c70, + .ddr_sdram_mode_3 = 0x00001c70, + .ddr_sdram_mode_5 = 0x00001c70, + .ddr_sdram_mode_7 = 0x00001c70, + .ddr_sdram_mode_2 = 0x00180000, + .ddr_sdram_mode_4 = 0x00180000, + .ddr_sdram_mode_6 = 0x00180000, + .ddr_sdram_mode_8 = 0x00180000, + + .ddr_sdram_interval = 0x0c30030c, + .ddr_data_init = 0xdeadbeef, + + .ddr_sdram_clk_cntl = 0x02400000, + + .timing_cfg_4 = 0x00000001, + .timing_cfg_5 = 0x04401400, + + .ddr_zq_cntl = 0x89080600, + .ddr_wrlvl_cntl = 0x8675f606, + .ddr_wrlvl_cntl_2 = 0x04080700, + .ddr_wrlvl_cntl_3 = 0x00000009, + + .ddr_cdr1 = 0x80040000, + .ddr_cdr2 = 0x0000bc01, +}; + +int fsl_initdram(void) +{ + u32 gpporcr1 = in_le32(DCFG_BASE + DCFG_GPPORCR1); + phys_size_t dram_size; + + switch (gpporcr1 & GPPORCR1_MEM_MASK) { + case GPPORCR1_MEM_2GB_CS0: + dram_size = 0x80000000; + ddr_cfg_regs.cs[1].bnds = 0; + ddr_cfg_regs.cs[1].config = 0; + ddr_cfg_regs.cs[1].config_2 = 0; + break; + case GPPORCR1_MEM_4GB_CS0_1: + dram_size = 0x100000000ULL; + break; + case GPPORCR1_MEM_512MB_CS0: + dram_size = 0x20000000; + fallthrough; /* for now */ + case GPPORCR1_MEM_1GB_CS0: + dram_size = 0x40000000; + fallthrough; /* for now */ + case GPPORCR1_MEM_4GB_CS0_2: + dram_size = 0x100000000ULL; + fallthrough; /* for now */ + case GPPORCR1_MEM_8GB_CS0_1: + case GPPORCR1_MEM_8GB_CS0_1_2_3: + dram_size = 0x200000000ULL; + fallthrough; /* for now */ + default: + panic("Unsupported memory configuration (%08x)\n", + gpporcr1 & GPPORCR1_MEM_MASK); + break; + } + + if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); + + gd->ram_size = dram_size; + + return 0; +} diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c new file mode 100644 index 0000000000..b18127c4d1 --- /dev/null +++ b/board/kontron/sl28/sl28.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + if (CONFIG_IS_ENABLED(FSL_CAAM)) + sec_init(); + + return 0; +} + +int board_eth_init(struct bd_info *bis) +{ + return pci_eth_init(bis); +} + +int checkboard(void) +{ + printf("EL: %d\n", current_el()); + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); + print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_ddr_info(0); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int nbanks = CONFIG_NR_DRAM_BANKS; + int i; + + ft_cpu_setup(blob, bd); + + /* fixup DT for the two GPP DDR banks */ + for (i = 0; i < nbanks; i++) { + base[i] = gd->bd->bi_dram[i].start; + size[i] = gd->bd->bi_dram[i].size; + } + + fdt_fixup_memory_banks(blob, base, size, nbanks); + + fdt_fixup_icid(blob); + + return 0; +} diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c new file mode 100644 index 0000000000..fa5829eee0 --- /dev/null +++ b/board/kontron/sl28/spl.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include + +#define DCFG_RCWSR25 0x160 +#define GPINFO_HW_VARIANT_MASK 0xff + +int sl28_variant(void) +{ + return in_le32(DCFG_BASE + DCFG_RCWSR25) & GPINFO_HW_VARIANT_MASK; +} + +int board_fit_config_name_match(const char *name) +{ + int variant = sl28_variant(); + + switch (variant) { + case 3: + return strcmp(name, "fsl-ls1028a-kontron-sl28-var3"); + case 4: + return strcmp(name, "fsl-ls1028a-kontron-sl28-var4"); + default: + return strcmp(name, "fsl-ls1028a-kontron-sl28"); + } +} + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = BOOT_DEVICE_SPI; +} diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig new file mode 100644 index 0000000000..c1a096799c --- /dev/null +++ b/configs/kontron_sl28_defconfig @@ -0,0 +1,107 @@ +CONFIG_ARM=y +CONFIG_TARGET_SL28=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x3e0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000 +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_TEXT_BASE=0x18010000 +CONFIG_SYS_FSL_SDHC_CLK_DIV=1 +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SIZE_LIMIT=0x20000 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x3f0000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +# CONFIG_PSCI_RESET is not set +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-kontron-sl28" +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_PCI_INIT_R=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RNG=y +CONFIG_MP=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIST="" +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_FSL_CAAM=y +CONFIG_SYS_FSL_DDR3=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_I2C_MUX=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_FSL_ENETC=y +CONFIG_NVME=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_DM_RNG=y +CONFIG_DM_RTC=y +CONFIG_RTC_RV8803=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_NXP_FSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_OF_LIBFDT_ASSUME_MASK=0x0 +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/doc/board/index.rst b/doc/board/index.rst index 63935abcd7..4b6a996eb1 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -15,6 +15,7 @@ Board-specific doc freescale/index google/index intel/index + kontron/index renesas/index rockchip/index sifive/index diff --git a/doc/board/kontron/index.rst b/doc/board/kontron/index.rst new file mode 100644 index 0000000000..543b22e2f5 --- /dev/null +++ b/doc/board/kontron/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Kontron +======= + +.. toctree:: + :maxdepth: 2 + + sl28 diff --git a/doc/board/kontron/sl28.rst b/doc/board/kontron/sl28.rst new file mode 100644 index 0000000000..e458fbc607 --- /dev/null +++ b/doc/board/kontron/sl28.rst @@ -0,0 +1,160 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Summary +======= + +The Kontron SMARC-sAL28 board is a TSN-enabled dual-core ARM A72 +processor module with an on-chip 6-port TSN switch and a 3D GPU. + + +Quickstart +========== + +Compile U-Boot +-------------- + +Configure and compile the binary:: + + $ make kontron_sl28_defconfig + $ CROSS_COMPILE=aarch64-linux-gnu make + +Copy u-boot.rom to a TFTP server. + +Install the bootloader on the board +----------------------------------- + +Please note, this bootloader doesn't support the builtin watchdog (yet), +therefore you have to disable it, see below. Otherwise you'll end up in +the failsafe bootloader on every reset:: + + > tftp path/to/u-boot.rom + > sf probe 0 + > sf update $fileaddr 0x210000 $filesize + +The board is fully failsafe, you can't break anything. But because you've +disabled the builtin watchdog you might have to manually enter failsafe +mode by asserting the ``FORCE_RECOV#`` line during board reset. + +Disable the builtin watchdog +---------------------------- + +- boot into the failsafe bootloader, either by asserting the + ``FORCE_RECOV#`` line or if you still have the original bootloader + installed you can use the command:: + + > wdt dev cpld_watchdog@4a; wdt expire 1 + +- in the failsafe bootloader use the "sl28 nvm" command to disable + the automatic start of the builtin watchdog:: + + > sl28 nvm 0008 + +- power-cycle the board + + +Useful I2C tricks +================= + +The board has a board management controller which is not supported in +u-boot (yet). But you can use the i2c command to access it. + +- reset into failsafe bootloader:: + + > i2c mw 4a 5.1 0; i2c mw 4a 6.1 6b; i2c mw 4a 4.1 42 + +- read board management controller version:: + + > i2c md 4a 3.1 1 + + +Non-volatile Board Configuration Bits +===================================== + +The board has 16 configuration bits which are stored in the CPLD and are +non-volatile. These can be changed by the `sl28 nvm` command. + +=== =============================================================== +Bit Description +=== =============================================================== + 0 Power-on inhibit + 1 Enable eMMC boot + 2 Enable watchdog by default + 3 Disable failsafe watchdog by default + 4 Clock generator selection bit 0 + 5 Clock generator selection bit 1 + 6 Disable CPU SerDes clock #2 and PCIe-A clock output + 7 Disable PCIe-B and PCIe-C clock output + 8 Keep onboard PHYs in reset + 9 Keep USB hub in reset + 10 Keep eDP-to-LVDS converter in reset + 11 Enable I2C stuck recovery on I2C PM and I2C GP busses + 12 Enable automatic onboard PHY H/W reset + 13 reserved + 14 Used by the RCW to determine boot source + 15 Used by the RCW to determine boot source +=== =============================================================== + +Please note, that if the board is in failsafe mode, the bits will have the +factory defaults, ie. all bits are off. + +Power-On Inhibit +---------------- + +If this is set, the board doesn't automatically turn on when power is +applied. Instead, the user has to either toggle the ``PWR_BTN#`` line or +use any other wake-up source such as RTC alarm or Wake-on-LAN. + +eMMC Boot +--------- + +If this is set, the RCW will be fetched from the on-board eMMC at offset +1MiB. For further details, have a look at the `Reset Configuration Word +Documentation`_. + +Watchdog +-------- + +By default, the CPLD watchdog is enabled in failsafe mode. Using bits 2 and +3, the user can change its mode or disable it altogether. + +===== ===== =============================== +Bit 2 Bit 3 Description +===== ===== =============================== + 0 0 Watchdog enabled, failsafe mode + 0 1 Watchdog disabled + 1 0 Watchdog enabled, failsafe mode + 1 1 Watchdog enabled, normal mode +===== ===== =============================== + +Clock Generator Select +---------------------- + +The board is prepared to supply different SerDes clock speeds. But for now, +only setting 0 is supported, otherwise the CPU will hang because the PLL +will not lock. + +Clock Output Disable And Keep Devices In Reset +---------------------------------------------- + +To safe power, the user might disable different devices and clock output of +the board. It is not supported to disable the "CPU SerDes clock #2" for +now, otherwise the CPU will hang because the PLL will not lock. + +Automatic reset of the onboard PHYs +----------------------------------- + +By default, there is no hardware reset of the onboard PHY. This is because +for Wake-on-LAN, some registers have to retain their values. If you don't +use the WOL feature and a soft reset of the PHY is not enough you can +enable the hardware reset. The onboard PHY hardware reset follows the +power-on reset. + + +Further documentation +===================== + +- `Vendor Documentation`_ +- `Reset Configuration Word Documentation`_ + +.. _Reset Configuration Word Documentation: https://raw.githubusercontent.com/kontron/rcw-smarc-sal28/master/README.md +.. _Vendor Documentation: https://raw.githubusercontent.com/kontron/u-boot-smarc-sal28/master/board/kontron/sl28/README.md diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h new file mode 100644 index 0000000000..afe512a8c7 --- /dev/null +++ b/include/configs/kontron_sl28.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __SL28_H +#define __SL28_H + +#include +#include +#include + +/* we don't use hwconfig but this has to be defined.. */ +#define HWCONFIG_BUFFER_SIZE 256 + +/* we don't have secure memory unless we have a BL31 */ +#ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#undef CONFIG_SYS_MEM_RESERVE_SECURE +#endif + +/* DDR */ +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef + +#define CONFIG_VERY_BIG_RAM +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 + +/* early stack pointer */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xeff0) + +/* memtest command */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +/* SMP */ +#define CPU_RELEASE_ADDR secondary_boot_addr + +/* generic timer */ +#define COUNTER_FREQUENCY 25000000 + +/* size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) + +/* early heap for SPL DM */ +#define CONFIG_MALLOC_F_ADDR CONFIG_SYS_FSL_OCRAM_BASE + +/* serial port */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) + +/* MMC */ +#ifdef CONFIG_MMC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#endif + +/* ethernet */ +#define CONFIG_SYS_RX_ETH_BUFFER 8 + +/* SPL */ +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SPL_MAX_SIZE 0x20000 +#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) + +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) + +/* environment */ +/* see include/configs/ti_armv7_common.h */ +#define CONFIG_SYS_LOAD_ADDR 0x82000000 +#define ENV_MEM_LAYOUT_SETTINGS \ + "loadaddr=0x82000000\0" \ + "kernel_addr_r=0x82000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "bootm_size=0x10000000\0" \ + "pxefile_addr_r=0x80100000\0" \ + "scriptaddr=0x80000000\0" \ + "ramdisk_addr_r=0x88080000\0" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(NVME, nvme, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, 0) \ + func(PXE, pxe, 0) +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "env_addr=0x203e0004\0" \ + "envload=env import -d -b ${env_addr}\0" \ + "install_rcw=source 20200000\0" \ + "fdtfile=freescale/fsl-ls1028a-kontron-sl28.dtb\0" \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV + +#endif /* __SL28_H */ -- cgit v1.2.3 From 66d00ebdeaa967b56438ac3c7352a377174742d6 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 15 Oct 2020 23:08:58 +0200 Subject: board: sl28: add board specific nvm command The board supports 16 configuration bits which can be manipulated with this command. See the board's README for a detailed explanation on each bit. Signed-off-by: Michael Walle Tested-by: Heiko Thiery Reviewed-by: Priyanka Jain --- board/kontron/sl28/Makefile | 2 +- board/kontron/sl28/cmds.c | 178 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 179 insertions(+), 1 deletion(-) create mode 100644 board/kontron/sl28/cmds.c diff --git a/board/kontron/sl28/Makefile b/board/kontron/sl28/Makefile index 0f1866c874..74d8012f0f 100644 --- a/board/kontron/sl28/Makefile +++ b/board/kontron/sl28/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ ifndef CONFIG_SPL_BUILD -obj-y += sl28.o +obj-y += sl28.o cmds.o endif obj-y += common.o ddr.o diff --git a/board/kontron/sl28/cmds.c b/board/kontron/sl28/cmds.c new file mode 100644 index 0000000000..046d3b4903 --- /dev/null +++ b/board/kontron/sl28/cmds.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * sl28 extension commands + * + * Copyright (c) 2020 Kontron Europe GmbH + */ + +#include +#include +#include +#include + +#define CPLD_I2C_ADDR 0x4a +#define REG_UFM_CTRL 0x02 +#define UFM_CTRL_DCLK BIT(1) +#define UFM_CTRL_DIN BIT(2) +#define UFM_CTRL_PROGRAM BIT(3) +#define UFM_CTRL_ERASE BIT(4) +#define UFM_CTRL_DSHIFT BIT(5) +#define UFM_CTRL_DOUT BIT(6) +#define UFM_CTRL_BUSY BIT(7) + +static int ufm_shift_data(struct udevice *dev, u16 data_in, u16 *data_out) +{ + int i; + int ret; + u16 data = 0; + + /* latch data */ + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, 0); + if (ret < 0) + return ret; + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK); + if (ret < 0) + return ret; + + /* assert drshift */ + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, + UFM_CTRL_DSHIFT | UFM_CTRL_DCLK); + if (ret < 0) + return ret; + + /* clock 16 data bits, reverse order */ + for (i = 15; i >= 0; i--) { + u8 din = (data_in & (1 << i)) ? UFM_CTRL_DIN : 0; + + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DSHIFT + | din); + if (ret < 0) + return ret; + if (data_out) { + ret = dm_i2c_reg_read(dev, REG_UFM_CTRL); + if (ret < 0) + return ret; + if (ret & UFM_CTRL_DOUT) + data |= (1 << i); + } + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, + UFM_CTRL_DSHIFT | UFM_CTRL_DCLK | din); + if (ret < 0) + return ret; + } + + /* deassert drshift */ + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK); + if (ret < 0) + return ret; + + if (data_out) + *data_out = data; + + return ret; +} + +static int ufm_erase(struct udevice *dev) +{ + int ret; + + /* erase, tEPMX is 500ms */ + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, + UFM_CTRL_DCLK | UFM_CTRL_ERASE); + if (ret < 0) + return ret; + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK); + if (ret < 0) + return ret; + mdelay(500); + + return 0; +} + +static int ufm_program(struct udevice *dev) +{ + int ret; + + /* program, tPPMX is 100us */ + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, + UFM_CTRL_DCLK | UFM_CTRL_PROGRAM); + if (ret < 0) + return ret; + ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK); + if (ret < 0) + return ret; + udelay(100); + + return 0; +} + +static int ufm_write(struct udevice *dev, u16 data) +{ + int ret; + + ret = ufm_shift_data(dev, data, NULL); + if (ret < 0) + return ret; + + ret = ufm_erase(dev); + if (ret < 0) + return ret; + + return ufm_program(dev); +} + +static int ufm_read(struct udevice *dev, u16 *data) +{ + return ufm_shift_data(dev, 0, data); +} + +static int do_sl28_nvm(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct udevice *dev; + u16 nvm; + int ret; + char *endp; + + if (i2c_get_chip_for_busnum(0, CPLD_I2C_ADDR, 1, &dev)) + return CMD_RET_FAILURE; + + if (argc > 1) { + nvm = simple_strtoul(argv[1], &endp, 16); + if (*endp != '\0') { + printf("ERROR: argument is not a valid number\n"); + ret = -EINVAL; + goto out; + } + + /* + * We swap all bits, because the a zero bit in hardware means the + * feature is enabled. But this is hard for the user. + */ + nvm ^= 0xffff; + + ret = ufm_write(dev, nvm); + if (ret) + goto out; + printf("New settings will be activated after the next power cycle!\n"); + } else { + ret = ufm_read(dev, &nvm); + if (ret) + goto out; + nvm ^= 0xffff; + + printf("%04hx\n", nvm); + } + + return CMD_RET_SUCCESS; + +out: + printf("command failed (%d)\n", ret); + return CMD_RET_FAILURE; +} + +static char sl28_help_text[] = + "nvm [] - display/set the 16 non-volatile bits\n"; + +U_BOOT_CMD_WITH_SUBCMDS(sl28, "SMARC-sAL28 specific", sl28_help_text, + U_BOOT_SUBCMD_MKENT(nvm, 2, 1, do_sl28_nvm)); -- cgit v1.2.3 From f3555bd2854c8bda719e48e8013064ac578b5642 Mon Sep 17 00:00:00 2001 From: Priyanka Singh Date: Fri, 16 Oct 2020 14:45:44 +0530 Subject: board: freescale: vid.c: Initialize variable 'i2caddress' Initialize variable 'i2caddress' in print_vdd() to zero Signed-off-by: Priyanka Singh Reviewed-by: Priyanka Jain --- board/freescale/common/vid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 20c97aa1ef..bf8a5d893f 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -892,7 +892,7 @@ exit: static int print_vdd(void) { - int vdd_last, ret, i2caddress; + int vdd_last, ret, i2caddress = 0; ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); if (ret) { -- cgit v1.2.3 From 026703174a2cf8cd9c83a7c797b96b95af5af69b Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Mon, 12 Oct 2020 20:07:35 +0800 Subject: board/freescale/vid: enables writes to all commands for LTC3882 Enable writes to all commands for LTC3882 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- board/freescale/common/vid.c | 42 +++++++++++++++++++++++++++++++++++++++--- board/freescale/common/vid.h | 19 +++++++++++++++++++ 2 files changed, 58 insertions(+), 3 deletions(-) diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index bf8a5d893f..9c51f50260 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -379,6 +379,7 @@ static int set_voltage_to_LTC(int i2caddress, int vdd) { int ret, vdd_last, vdd_target = vdd; int count = 100, temp = 0; + unsigned char value; /* Scale up to the LTC resolution is 1/4096V */ vdd = (vdd * 4096) / 1000; @@ -391,16 +392,51 @@ static int set_voltage_to_LTC(int i2caddress, int vdd) /* Write the desired voltage code to the regulator */ #ifndef CONFIG_DM_I2C + /* Check write protect state */ + ret = i2c_read(I2C_VOL_MONITOR_ADDR, + PMBUS_CMD_WRITE_PROTECT, 1, + (void *)&value, sizeof(value)); + if (ret) + goto exit; + + if (value != EN_WRITE_ALL_CMD) { + value = EN_WRITE_ALL_CMD; + ret = i2c_write(I2C_VOL_MONITOR_ADDR, + PMBUS_CMD_WRITE_PROTECT, 1, + (void *)&value, sizeof(value)); + if (ret) + goto exit; + } + ret = i2c_write(I2C_VOL_MONITOR_ADDR, - PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); + PMBUS_CMD_PAGE_PLUS_WRITE, 1, + (void *)&buff, sizeof(buff)); #else struct udevice *dev; ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev); - if (!ret) + if (!ret) { + /* Check write protect state */ + ret = dm_i2c_read(dev, + PMBUS_CMD_WRITE_PROTECT, + (void *)&value, sizeof(value)); + if (ret) + goto exit; + + if (value != EN_WRITE_ALL_CMD) { + value = EN_WRITE_ALL_CMD; + ret = dm_i2c_write(dev, + PMBUS_CMD_WRITE_PROTECT, + (void *)&value, sizeof(value)); + if (ret) + goto exit; + } + ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE, - (void *)&buff, 5); + (void *)&buff, sizeof(buff)); + } #endif +exit: if (ret) { printf("VID: I2C failed to write to the volatge regulator\n"); return -1; diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h index 99778e9a93..65b348ee42 100644 --- a/board/freescale/common/vid.h +++ b/board/freescale/common/vid.h @@ -18,6 +18,25 @@ /* step the IR regulator in 5mV increments */ #define IR_VDD_STEP_DOWN 5 #define IR_VDD_STEP_UP 5 + +/* LTC3882 */ +#define PMBUS_CMD_WRITE_PROTECT 0x10 +/* + * WRITE_PROTECT command supported values + * 0x80: Disable all writes except WRITE_PROTECT, PAGE, + * STORE_USER_ALL and MFR_EE_UNLOCK commands. + * 0x40: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ALL, + * MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS and CLEAR_FAULTS commands. + * Individual faults can also be cleared by writing a 1 to the + * respective status bit. + * 0x20: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ ALL, + * MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS, CLEAR_FAULTS, ON_OFF_CONFIG + * and VOUT_COMMAND commands. Individual faults can be cleared by + * writing a 1 to the respective status bit. + * 0x00: Enables write to all commands + */ +#define EN_WRITE_ALL_CMD (0) + int adjust_vdd(ulong vdd_override); #endif /* __VID_H_ */ -- cgit v1.2.3 From 4eecc6f1a104b5f3737c7e1bbaaa022e5d3bac53 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 16 Oct 2020 19:38:18 +0200 Subject: armv8: layerscape: don't remove crypto node if just partially disabled On all newer Layerscape SoCs, only the export-controlled ciphers of the crypto module are disabled on non-E parts. Thus it doesn't make sense to completely remove the node. Linux will figure out what is there and what is not. Just remove it for older SoCs, where the module is indeed completely disabled on non-E parts. Signed-off-by: Michael Walle Reviewed-by: Horia Geanta Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 41 ++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 7400b2cf29..6d3391db3b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -437,13 +437,52 @@ __weak void fdt_fixup_ecam(void *blob) } #endif +/* + * If it is a non-E part the crypto is disabled on the following SoCs: + * - LS1043A + * - LS1088A + * - LS2080A + * - LS2088A + * and their personalities. + * + * On all other SoCs just the export-controlled ciphers are disabled, that + * means that the following is still working: + * - hashing (using MDHA - message digest hash accelerator) + * - random number generation (using RNG4) + * - cyclic redundancy checking (using CRCA) + * - runtime integrity checker (RTIC) + * + * The linux driver will figure out what is available and what is not. + * Therefore, we just remove the crypto node on the SoCs which have no crypto + * support at all. + */ +static bool crypto_is_disabled(unsigned int svr) +{ + if (IS_E_PROCESSOR(svr)) + return false; + + if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS1043A))) + return true; + + if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS1088A))) + return true; + + if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS2080A))) + return true; + + if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS2088A))) + return true; + + return false; +} + void ft_cpu_setup(void *blob, struct bd_info *bd) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); unsigned int svr = gur_in32(&gur->svr); /* delete crypto node if not on an E-processor */ - if (!IS_E_PROCESSOR(svr)) + if (crypto_is_disabled(svr)) fdt_fixup_crypto_node(blob, 0); #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 else { -- cgit v1.2.3 From 78a8bca5e4971e4be0c3ba438f7386462507ad6a Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Tue, 20 Oct 2020 12:09:58 +0300 Subject: configs: ls1088a: enable CMD_MDIO Enable the CMD_MDIO Kconfig option by removing the "is not set" indication from all the defconfigs for this SoC. Signed-off-by: Ioana Ciornei Reviewed-by: Priyanka Jain --- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 1 - configs/ls1088aqds_qspi_defconfig | 1 - configs/ls1088aqds_sdcard_qspi_defconfig | 1 - configs/ls1088aqds_tfa_defconfig | 1 - configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 1 - configs/ls1088ardb_qspi_defconfig | 1 - configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 1 - configs/ls1088ardb_sdcard_qspi_defconfig | 1 - configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 1 - configs/ls1088ardb_tfa_defconfig | 1 - 10 files changed, 10 deletions(-) diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index 9943666ff6..d4b9f58340 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -31,7 +31,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index 3627792b18..6c089e418f 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -32,7 +32,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index 52dd94e195..da14230e8d 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -42,7 +42,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index 328173574e..07b385fb90 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -36,7 +36,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index 5542914179..b698d7621a 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -33,7 +33,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index b3cd9b5399..a9d29f6ea5 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -34,7 +34,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 417c813f3a..db6c59cc69 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -45,7 +45,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index 27a7674c20..cd07f9e5a0 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -44,7 +44,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 9f8e3123e3..f4eee9e24a 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index 573a85955f..cacbe40c9e 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -37,7 +37,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y -- cgit v1.2.3