From c055cee1951a01a3306f54f20bcfb85adf28721a Mon Sep 17 00:00:00 2001
From: Ashish Kumar <Ashish.Kumar@nxp.com>
Date: Fri, 18 Aug 2017 10:54:36 +0530
Subject: armv8: fsl-lsch3: Make CCN-504 related code conditional

LS2080 family has CCN-504 cache coherent interconnet. Other SoCs
in LSCH3 family may have differnt interconnect.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
---
 README | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'README')

diff --git a/README b/README
index c0c8b559f9..ca07f7a3f9 100644
--- a/README
+++ b/README
@@ -322,6 +322,10 @@ build a config tool - later.
 		Defined For SoC that has cache coherent interconnect
 		CCN-400
 
+		CONFIG_SYS_FSL_HAS_CCN504
+
+		Defined for SoC that has cache coherent interconnect CCN-504
+
 The following options need to be configured:
 
 - CPU Type:	Define exactly one, e.g. CONFIG_MPC85XX.
-- 
cgit v1.2.3