From 19a4d31c12bac4c68078683ffff3a222e0385fae Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Nov 2021 23:08:20 +0530 Subject: arm64: dts: rockchip: Sync px30 from linux-next Sync the px30 devicetree files from linux-next tree. commit <14ce8069f48b> ("lib/stackdepot: allow optional init and stack_table allocation by kvmalloc() - fixup3") Note, this path even sync rk3326 files as it depends on px30. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts | 43 ++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts (limited to 'arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts') diff --git a/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts new file mode 100644 index 0000000000..d759478e1c --- /dev/null +++ b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "px30.dtsi" +#include "px30-engicam-edimm2.2.dtsi" +#include "px30-engicam-px30-core.dtsi" + +/ { + model = "Engicam PX30.Core EDIMM2.2 Starter Kit"; + compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core", + "rockchip,px30"; + + chosen { + stdout-path = "serial2:115200n8"; + }; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdio_pwrseq { + reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; +}; + +&vcc3v3_btreg { + enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; +}; -- cgit v1.2.3