From 185f812c419f1b4f0d10d9787d59cf9f11a2a600 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 19 Jan 2022 18:05:50 +0100 Subject: doc: replace @return by Return: Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt --- arch/arm/mach-tegra/clock.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm/mach-tegra/clock.c') diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 18c19dbf60..77c8ad978e 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -243,7 +243,7 @@ void clock_ll_set_source(enum periph_id periph_id, unsigned source) * @param divider_bits number of divider bits (8 or 16) * @param parent_rate clock rate of parent clock in Hz * @param rate required clock rate for this clock - * @return divider which should be used + * Return: divider which should be used */ static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate, unsigned long rate) @@ -297,7 +297,7 @@ int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate) * * @param parent_rate clock rate of parent clock in Hz * @param divider which should be used in 7.1 format - * @return effective clock rate of peripheral + * Return: effective clock rate of peripheral */ static unsigned long get_rate_from_divider(unsigned long parent_rate, int divider) @@ -365,7 +365,7 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id, * @param rate required clock rate for this clock * @param extra_div value for the second-stage divisor (not set if this * function returns -1. - * @return divider which should be used, or -1 if nothing is valid + * Return: divider which should be used, or -1 if nothing is valid * */ static int find_best_divider(unsigned divider_bits, unsigned long parent_rate, @@ -403,7 +403,7 @@ static int find_best_divider(unsigned divider_bits, unsigned long parent_rate, * @param source Source number (0-3 or 0-7) * @param mux_bits Number of mux bits (2 or 4) * @param divider Required divider in 7.1 or 15.1 format - * @return 0 if ok, -1 on error (requesting a parent clock which is not valid + * Return: 0 if ok, -1 on error (requesting a parent clock which is not valid * for this peripheral) */ static int adjust_periph_pll(enum periph_id periph_id, int source, @@ -586,7 +586,7 @@ unsigned clock_get_rate(enum clock_id clkid) * @param m PLL input divider(DIVN) * @param p post divider(DIVP) * @param cpcon base PLL charge pump(CPCON) - * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot + * Return: 0 if ok, -1 on error (the requested PLL is incorrect and cannot * be overridden), 1 if PLL is already correct */ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) -- cgit v1.2.3