From c93ad777b86c40497cf29d88e3a91381fc8ebe5c Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Tue, 12 May 2020 12:54:07 +0530 Subject: treewide: Remove unused FSL QSPI config options for Layerscape platforms Some of these options are not used by the driver anymore and some of them are obsolete as the information is gathered from the dt. Also consolidating defines in common headers. Signed-off-by: Frieder Schrempf Signed-off-by: Ashish Kumar Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 - arch/arm/include/asm/arch-ls102xa/config.h | 1 - 2 files changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index ddd9390df4..cf2abda133 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -306,7 +306,6 @@ #define CONFIG_SYS_FSL_ESDHC_BE #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE -#define CONFIG_SYS_FSL_QSPI_BE #define CONFIG_SYS_FSL_CCSR_GUR_BE #define CONFIG_SYS_FSL_PEX_LUT_BE diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 970537870d..3884948a2c 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -94,7 +94,6 @@ #define CONFIG_SYS_FSL_ESDHC_BE #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE -#define CONFIG_SYS_FSL_QSPI_BE #define CONFIG_SYS_FSL_DCU_BE #define CONFIG_SYS_FSL_SEC_MON_LE #define CONFIG_SYS_FSL_SFP_VER_3_2 -- cgit v1.2.3 From b480bcca805c350bf875f026ee816db502c88765 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 12 Dec 2019 11:49:24 +0530 Subject: treewide: Update fsl qspi node dt properties as per spi-mem driver According to new qspi driver, some properties like "bus-num, num-cs, big-endian" are no longer used. Device endiannes can be determined from device-type data in driver. Now use board specific compatibles, generic node names and specific labels to align with linux device-tree properties. Also consolidate spi-max-frequency to 50Mhz treewide. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1012a-2g5rdb.dts | 5 ++--- arch/arm/dts/fsl-ls1012a-frdm.dtsi | 5 ++--- arch/arm/dts/fsl-ls1012a-qds.dtsi | 5 ++--- arch/arm/dts/fsl-ls1012a-rdb.dtsi | 5 ++--- arch/arm/dts/fsl-ls1012a.dtsi | 4 +--- arch/arm/dts/fsl-ls1043a-qds.dtsi | 5 ++--- arch/arm/dts/fsl-ls1043a.dtsi | 6 ++---- arch/arm/dts/fsl-ls1046a-frwy.dts | 5 ++--- arch/arm/dts/fsl-ls1046a-qds.dtsi | 5 ++--- arch/arm/dts/fsl-ls1046a-rdb.dts | 5 ++--- arch/arm/dts/fsl-ls1046a.dtsi | 4 +--- arch/arm/dts/fsl-ls1088a-qds.dts | 5 ++--- arch/arm/dts/fsl-ls1088a-rdb.dts | 5 ++--- arch/arm/dts/fsl-ls1088a.dtsi | 2 +- arch/arm/dts/fsl-ls2080a-qds.dts | 5 ++--- arch/arm/dts/fsl-ls2080a.dtsi | 4 ++-- arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 5 ++--- arch/arm/dts/ls1021a-twr.dtsi | 5 ++--- arch/arm/dts/ls1021a.dtsi | 6 ++---- 19 files changed, 35 insertions(+), 56 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts index fecef88e08..6402cf5aca 100644 --- a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts +++ b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts @@ -21,14 +21,13 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fl128s@0 { + s25fs512s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; + spi-max-frequency = <50000000>; reg = <0>; }; }; diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi b/arch/arm/dts/fsl-ls1012a-frdm.dtsi index a357793bfa..88aa24a6d2 100644 --- a/arch/arm/dts/fsl-ls1012a-frdm.dtsi +++ b/arch/arm/dts/fsl-ls1012a-frdm.dtsi @@ -15,14 +15,13 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fl128s@0 { + s25fs512s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; + spi-max-frequency = <50000000>; reg = <0>; }; }; diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi index a330597b6c..910d2a5c77 100644 --- a/arch/arm/dts/fsl-ls1012a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi @@ -43,14 +43,13 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fl128s@0 { + s25fs512s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; + spi-max-frequency = <50000000>; reg = <0>; }; }; diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi index 55155fd321..3757051b78 100644 --- a/arch/arm/dts/fsl-ls1012a-rdb.dtsi +++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi @@ -19,14 +19,13 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fl128s@0 { + s25fs512s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; + spi-max-frequency = <50000000>; reg = <0>; }; }; diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index 1125e5753b..2d70c82a72 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -107,14 +107,12 @@ }; qspi: quadspi@1550000 { - compatible = "fsl,vf610-qspi"; + compatible = "fsl,ls1021a-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x1550000 0x0 0x10000>, <0x0 0x40000000 0x0 0x4000000>; reg-names = "QuadSPI", "QuadSPI-memory"; - num-cs = <1>; - big-endian; status = "disabled"; }; diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi b/arch/arm/dts/fsl-ls1043a-qds.dtsi index 70e1a6a53f..884bdad196 100644 --- a/arch/arm/dts/fsl-ls1043a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi @@ -53,14 +53,13 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fl128s@0 { + s25fl128s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; + spi-max-frequency = <50000000>; reg = <0>; }; }; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index 0a959f0f2d..f7db44c0fa 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -210,14 +210,12 @@ status = "disabled"; }; qspi: quadspi@1550000 { - compatible = "fsl,vf610-qspi"; + compatible = "fsl,ls1021a-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x1550000 0x0 0x10000>, - <0x0 0x40000000 0x0 0x4000000>; + <0x0 0x40000000 0x0 0x1000000>; reg-names = "QuadSPI", "QuadSPI-memory"; - num-cs = <2>; - big-endian; status = "disabled"; }; diff --git a/arch/arm/dts/fsl-ls1046a-frwy.dts b/arch/arm/dts/fsl-ls1046a-frwy.dts index d39159322a..cda05411d8 100644 --- a/arch/arm/dts/fsl-ls1046a-frwy.dts +++ b/arch/arm/dts/fsl-ls1046a-frwy.dts @@ -19,13 +19,12 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: mt25qu512abb8esf@0 { + mt25qu512a0: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; }; diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi index 76dc397328..fec5c8ddb2 100644 --- a/arch/arm/dts/fsl-ls1046a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi @@ -53,14 +53,13 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fl128s@0 { + s25fs512s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; + spi-max-frequency = <50000000>; reg = <0>; }; }; diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts index cac65a7afa..464129291c 100644 --- a/arch/arm/dts/fsl-ls1046a-rdb.dts +++ b/arch/arm/dts/fsl-ls1046a-rdb.dts @@ -21,10 +21,9 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fs512s@0 { + s25fs512s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -32,7 +31,7 @@ reg = <0>; }; - qflash1: s25fs512s@1 { + s25fs512s1: flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 4e91d5c995..8673a5db2a 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -211,14 +211,12 @@ }; qspi: quadspi@1550000 { - compatible = "fsl,vf610-qspi"; + compatible = "fsl,ls1021a-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x1550000 0x0 0x10000>, <0x0 0x40000000 0x0 0x10000000>; reg-names = "QuadSPI", "QuadSPI-memory"; - num-cs = <4>; - big-endian; status = "disabled"; }; diff --git a/arch/arm/dts/fsl-ls1088a-qds.dts b/arch/arm/dts/fsl-ls1088a-qds.dts index f07d0c6f27..4f37a28992 100644 --- a/arch/arm/dts/fsl-ls1088a-qds.dts +++ b/arch/arm/dts/fsl-ls1088a-qds.dts @@ -108,10 +108,9 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fs512s@0 { + s25fs512s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -119,7 +118,7 @@ reg = <0>; }; - qflash1: s25fs512s@1 { + s25fs512s1: flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls1088a-rdb.dts b/arch/arm/dts/fsl-ls1088a-rdb.dts index 46a5780547..de92bf22e2 100644 --- a/arch/arm/dts/fsl-ls1088a-rdb.dts +++ b/arch/arm/dts/fsl-ls1088a-rdb.dts @@ -143,10 +143,9 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fs512s@0 { + s25fs512s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -154,7 +153,7 @@ reg = <0>; }; - qflash1: s25fs512s@1 { + s25fs512s1: flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 133cacb93e..bf303c6ad3 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -92,7 +92,7 @@ }; qspi: quadspi@1550000 { - compatible = "fsl,vf610-qspi"; + compatible = "fsl,ls1088a-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x20c0000 0x0 0x10000>, diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts index 13461b5c45..f91a48d9fd 100644 --- a/arch/arm/dts/fsl-ls2080a-qds.dts +++ b/arch/arm/dts/fsl-ls2080a-qds.dts @@ -72,14 +72,13 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fs256s@0 { + s25fs256s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; + spi-max-frequency = <50000000>; reg = <0>; }; }; diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index fb5777e268..90a0a3f8fb 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -96,13 +96,13 @@ }; qspi: quadspi@1550000 { - compatible = "fsl,vf610-qspi"; + compatible = "fsl,ls2080a-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x20c0000 0x0 0x10000>, <0x0 0x20000000 0x0 0x10000000>; reg-names = "QuadSPI", "QuadSPI-memory"; - num-cs = <4>; + status = "disabled"; }; esdhc: esdhc@0 { diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts index 16b9aeec96..179ed19bf2 100644 --- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts +++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts @@ -125,10 +125,9 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fs512s@0 { + s25fs512s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -136,7 +135,7 @@ reg = <0>; }; - qflash1: s25fs512s@1 { + s25fs512s1: flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/ls1021a-twr.dtsi b/arch/arm/dts/ls1021a-twr.dtsi index 27c96f9540..bf96af7e36 100644 --- a/arch/arm/dts/ls1021a-twr.dtsi +++ b/arch/arm/dts/ls1021a-twr.dtsi @@ -24,14 +24,13 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: n25q128a13@0 { + n25q128a130: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; + spi-max-frequency = <50000000>; reg = <0>; }; }; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index e419d9c44f..0eeec43ccc 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -169,14 +169,12 @@ }; qspi: quadspi@1550000 { - compatible = "fsl,vf610-qspi"; + compatible = "fsl,ls1021a-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x1550000 0x10000>, - <0x40000000 0x4000000>; + <0x40000000 0x1000000>; reg-names = "QuadSPI", "QuadSPI-memory"; - num-cs = <2>; - big-endian; status = "disabled"; }; -- cgit v1.2.3 From 237b26200964c4d0ff34d1bffc70127274a68571 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Mon, 27 Apr 2020 15:21:12 +0300 Subject: arm: dts: lx2160a: add noted for dpmacs 1, 2, 5-6 Add nodes for DPMACs 1, 2 and 5-6 which were missing from the description. These will be later used on the LX2160AQDS specific DTS. Signed-off-by: Ioana Ciornei Reviewed-by: Razvan Ionut Cirjan Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-lx2160a.dtsi | 86 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 73d04db7e4..1789da8638 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -2,7 +2,7 @@ /* * NXP lx2160a SOC common device tree source * - * Copyright 2018 NXP + * Copyright 2018-2020 NXP * */ @@ -383,6 +383,18 @@ #address-cells = <1>; #size-cells = <0>; + dpmac1: dpmac@1 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x1>; + status = "disabled"; + }; + + dpmac2: dpmac@2 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x2>; + status = "disabled"; + }; + dpmac3: dpmac@3 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x3>; @@ -395,6 +407,78 @@ status = "disabled"; }; + dpmac5: dpmac@5 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x5>; + status = "disabled"; + }; + + dpmac6: dpmac@6 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x6>; + status = "disabled"; + }; + + dpmac7: dpmac@7 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x7>; + status = "disabled"; + }; + + dpmac8: dpmac@8 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x8>; + status = "disabled"; + }; + + dpmac9: dpmac@9 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x9>; + status = "disabled"; + }; + + dpmac10: dpmac@a { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xa>; + status = "disabled"; + }; + + dpmac11: dpmac@b { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xb>; + status = "disabled"; + }; + + dpmac12: dpmac@c { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xc>; + status = "disabled"; + }; + + dpmac13: dpmac@d { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xd>; + status = "disabled"; + }; + + dpmac14: dpmac@e { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xe>; + status = "disabled"; + }; + + dpmac15: dpmac@f { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xf>; + status = "disabled"; + }; + + dpmac16: dpmac@10 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x10>; + status = "disabled"; + }; + dpmac17: dpmac@11 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x11>; -- cgit v1.2.3 From 3695e4ccfdd3baa29a0d64e4ed08ff1f0d602d09 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Mon, 27 Apr 2020 15:21:13 +0300 Subject: arm: dts: lx2160aqds: add MDIO slots The LX2160A processor has two external MDIO interfaces, described in the DTS as emdio1 and emdio2. On the LX2160AQDS board EMDIO1 is used with two onboard RGMII PHYs (Realtek RTL8211FD-CG), as well as eight input/output connectors for mezzanine cards. Configuration signals from the Qixis FPGA control the routing of the external MDIOs. Register 0x54 of the Qixis FPGA controls the routing of the EMDIO1 one of the 8 IO slots. As a consequence, a new node is added to describe register 0x54 as a MDIO mux controlled with child nodes describing all the IO slots as MDIO buses. Also, DPMAC 17 and 18 are updated to reference the on-board PHYs. Signed-off-by: Ioana Ciornei Reviewed-by: Razvan Ionut Cirjan Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-lx2160a-qds.dts | 115 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 114 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts index 592fd5977e..4946ce8dfb 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -2,7 +2,7 @@ /* * NXP LX2160AQDS device tree source * - * Copyright 2018-2019 NXP + * Copyright 2018-2020 NXP * */ @@ -18,6 +18,26 @@ }; }; +&dpmac17 { + status = "okay"; + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; +}; + +&dpmac18 { + status = "okay"; + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-id"; +}; + +&emdio1 { + status = "okay"; +}; + +&emdio2 { + status = "okay"; +}; + &esdhc0 { status = "okay"; }; @@ -30,6 +50,99 @@ status = "okay"; u-boot,dm-pre-reloc; + fpga@66 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-mfd"; + reg = <0x66>; + + mux-mdio@54 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mdio-mux-i2creg"; + reg = <0x54>; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3 + mdio-parent-bus = <&emdio1>; + + mdio@00 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + }; + mdio@08 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40>; + + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + }; + + emdio1_slot1: mdio@c0 { /* I/O Slot #1 */ + reg = <0xC0>; + device-name = "emdio1_slot1"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot2: mdio@c8 { /* I/O Slot #2 */ + reg = <0xC8>; + device-name = "emdio1_slot2"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot3: mdio@d0 { /* I/O Slot #3 */ + reg = <0xD0>; + device-name = "emdio1_slot3"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot4: mdio@d8 { /* I/O Slot #4 */ + reg = <0xD8>; + device-name = "emdio1_slot4"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot5: mdio@e0 { /* I/O Slot #5 */ + reg = <0xE0>; + device-name = "emdio1_slot5"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot6: mdio@e8 { /* I/O Slot #6 */ + reg = <0xE8>; + device-name = "emdio1_slot6"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot7: mdio@f0 { /* I/O Slot #7 */ + reg = <0xF0>; + device-name = "emdio1_slot7"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot8: mdio@f8 { /* I/O Slot #8 */ + reg = <0xF8>; + device-name = "emdio1_slot8"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + }; + i2c-mux@77 { compatible = "nxp,pca9547"; reg = <0x77>; -- cgit v1.2.3 From 74f04490f22428531f9fd5fcd9ca61b6e145a12b Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Mon, 27 Apr 2020 15:21:14 +0300 Subject: arm: dts: lx2160aqds: add nodes describing possible mezzanine cards Add device trees describing possible uses of mezzanine cards depending on the SERDES protocol employed. This patch adds DPAA2 networking support for the following protocols on each SERDES block: * SD #1: 3, 7, 19, 20 * SD #2: 11 Each SERDES block has a different device tree file per protocol supported, where the IO SLOTs used are enabled and PHYs located on the mezzanine cards are described. Also, dpmac nodes are edited and their associated phy-connection-type and phy-handle are added. Top DTS files are also added for each combination of protocol on the 3 SERDES blocks. Signed-off-by: Ioana Ciornei Reviewed-by: Razvan Ionut Cirjan [Rebased] Signed-off-by: Priyanka Jain --- arch/arm/dts/Makefile | 10 +- arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts | 19 ++++ arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts | 17 +++ arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts | 19 ++++ arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts | 17 +++ arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts | 19 ++++ arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts | 17 +++ arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts | 19 ++++ arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts | 17 +++ arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi | 75 +++++++++++++ arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi | 39 +++++++ arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi | 55 ++++++++++ arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi | 100 +++++++++++++++++ arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi | 76 +++++++++++++ arch/arm/dts/fsl-lx2160a-qds.dts | 180 +------------------------------ arch/arm/dts/fsl-lx2160a-qds.dtsi | 169 +++++++++++++++++++++++++++++ 16 files changed, 670 insertions(+), 178 deletions(-) create mode 100644 arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds.dtsi (limited to 'arch/arm') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ca663a86f2..f28fc371c3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -383,7 +383,15 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls1028a-qds-duart.dtb \ fsl-ls1028a-qds-lpuart.dtb \ fsl-lx2160a-rdb.dtb \ - fsl-lx2160a-qds.dtb + fsl-lx2160a-qds.dtb \ + fsl-lx2160a-qds-3-x-x.dtb \ + fsl-lx2160a-qds-3-11-x.dtb \ + fsl-lx2160a-qds-7-x-x.dtb \ + fsl-lx2160a-qds-7-11-x.dtb \ + fsl-lx2160a-qds-19-x-x.dtb \ + fsl-lx2160a-qds-19-11-x.dtb \ + fsl-lx2160a-qds-20-x-x.dtb \ + fsl-lx2160a-qds-20-11-x.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ diff --git a/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts b/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts new file mode 100644 index 0000000000..585759162f --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 19.11.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-19.dtsi" + +#include "fsl-lx2160a-qds-sd2-11.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 19.11.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts b/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts new file mode 100644 index 0000000000..ebe11396a6 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 19.x.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-19.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 19.x.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts b/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts new file mode 100644 index 0000000000..d9f0918967 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 20.11.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-20.dtsi" + +#include "fsl-lx2160a-qds-sd2-11.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 20.11.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts b/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts new file mode 100644 index 0000000000..735d440d37 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 20.x.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-20.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 20.x.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts b/arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts new file mode 100644 index 0000000000..3b21c87b93 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 3.11.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-3.dtsi" + +#include "fsl-lx2160a-qds-sd2-11.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 3.11.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts b/arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts new file mode 100644 index 0000000000..ede40563f7 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 3.x.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-3.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 3.x.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts b/arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts new file mode 100644 index 0000000000..8100af4727 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 7.11.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-7.dtsi" + +#include "fsl-lx2160a-qds-sd2-11.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 7.11.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts b/arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts new file mode 100644 index 0000000000..15dee3587f --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 7.x.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-7.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 7-x-x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi new file mode 100644 index 0000000000..a31ff8a1bd --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 19 + * + * Some assumptions are made: + * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4) + * * mezzanine card M13 is connected to IO SLOT6 (25g-aui for DPMAC 5,6) + * * mezzanine card M7 is connected to IO SLOT2 (xlaui4 for DPMAC 2) + * + * Copyright 2020 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac2 { + status = "okay"; + phy-handle = <&cortina_phy0>; + phy-connection-type = "xlaui4"; +}; + +&dpmac3 { + status = "okay"; + phy-handle = <&aquantia_phy1>; + phy-connection-type = "usxgmii"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&aquantia_phy2>; + phy-connection-type = "usxgmii"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&inphi_phy0>; + phy-connection-type = "25g-aui"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&inphi_phy1>; + phy-connection-type = "25g-aui"; +}; + +&emdio1_slot1 { + aquantia_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + + aquantia_phy2: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; +}; + +&emdio1_slot2 { + cortina_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; +}; + +&emdio1_slot6 { + inphi_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x0>; + }; + + inphi_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x1>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi new file mode 100644 index 0000000000..42e149691d --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 20 + * + * Some assumptions are made: + * * 2 mezzanine cards M13 are connected to IO SLOT1 and IO SLOT2 + * (xlaui4 for DPMAC 1,2) + * + * Copyright 2020 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac1 { + status = "okay"; + phy-handle = <&cortina_phy1_0>; + phy-connection-type = "xlaui4"; +}; + +&dpmac2 { + status = "okay"; + phy-handle = <&cortina_phy2_0>; + phy-connection-type = "xlaui4"; +}; + +&emdio1_slot1 { + cortina_phy1_0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; +}; + +&emdio1_slot2 { + cortina_phy2_0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi new file mode 100644 index 0000000000..256d784aca --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 3 + * + * Some assumptions are made: + * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4,5,6) + * + * Copyright 2020 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac3 { + status = "okay"; + phy-handle = <&aquantia_phy1>; + phy-connection-type = "usxgmii"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&aquantia_phy2>; + phy-connection-type = "usxgmii"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&aquantia_phy3>; + phy-connection-type = "usxgmii"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&aquantia_phy4>; + phy-connection-type = "usxgmii"; +}; + +&emdio1_slot1 { + aquantia_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + aquantia_phy2: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + aquantia_phy3: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x2>; + }; + aquantia_phy4: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x3>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi new file mode 100644 index 0000000000..5fcf846c10 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 7 + * + * Some assumptions are made: + * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4,5,6) + * * mezzanine card M1/M4 is connected to IO SLOT2 (sgmii for DPMAC 7,8,9,10) + * + * Copyright 2020 NXP + * + */ +#include "fsl-lx2160a-qds.dtsi" + +&dpmac3 { + status = "okay"; + phy-handle = <&aquantia_phy1>; + phy-connection-type = "usxgmii"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&aquantia_phy2>; + phy-connection-type = "usxgmii"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&aquantia_phy3>; + phy-connection-type = "usxgmii"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&aquantia_phy4>; + phy-connection-type = "usxgmii"; +}; + +&dpmac7 { + status = "okay"; + phy-handle = <&sgmii_phy1>; + phy-connection-type = "sgmii"; +}; + +&dpmac8 { + status = "okay"; + phy-handle = <&sgmii_phy2>; + phy-connection-type = "sgmii"; +}; + +&dpmac9 { + status = "okay"; + phy-handle = <&sgmii_phy3>; + phy-connection-type = "sgmii"; +}; + +&dpmac10 { + status = "okay"; + phy-handle = <&sgmii_phy4>; + phy-connection-type = "sgmii"; +}; + +&emdio1_slot1 { + aquantia_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + + aquantia_phy2: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + + aquantia_phy3: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x2>; + }; + + aquantia_phy4: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x3>; + }; +}; + +&emdio1_slot2 { + sgmii_phy1: ethernet-phy@1c { + reg = <0x1c>; + }; + + sgmii_phy2: ethernet-phy@1d { + reg = <0x1d>; + }; + + sgmii_phy3: ethernet-phy@1e { + reg = <0x1e>; + }; + + sgmii_phy4: ethernet-phy@1f { + reg = <0x1f>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi new file mode 100644 index 0000000000..cf09f98aa6 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for the SERDES block #2 - protocol 11 + * + * Some assumptions are made: + * * 2 mezzanine cards M1/M4 are connected to IO SLOT 7 and IO SLOT 8 + * (sgmii for DPMAC 12, 13, 14, 16, 17, 18) + * + * Copyright 2020 NXP + * + */ +#include "fsl-lx2160a-qds.dtsi" + +&dpmac12 { + status = "okay"; + phy-handle = <&sgmii_phy7_2>; + phy-connection-type = "sgmii"; +}; + +&dpmac17 { + status = "okay"; + phy-handle = <&sgmii_phy7_3>; + phy-connection-type = "sgmii"; +}; + +&dpmac18 { + status = "okay"; + phy-handle = <&sgmii_phy7_4>; + phy-connection-type = "sgmii"; +}; + +&dpmac16 { + status = "okay"; + phy-handle = <&sgmii_phy8_2>; + phy-connection-type = "sgmii"; +}; + +&dpmac13 { + status = "okay"; + phy-handle = <&sgmii_phy8_3>; + phy-connection-type = "sgmii"; +}; + +&dpmac14 { + status = "okay"; + phy-handle = <&sgmii_phy8_4>; + phy-connection-type = "sgmii"; +}; + +&emdio1_slot7 { + sgmii_phy7_2: ethernet-phy@1d { + reg = <0x1d>; + }; + + sgmii_phy7_3: ethernet-phy@1e { + reg = <0x1e>; + }; + + sgmii_phy7_4: ethernet-phy@1f { + reg = <0x1f>; + }; +}; + +&emdio1_slot8 { + sgmii_phy8_2: ethernet-phy@1d { + reg = <0x1d>; + }; + + sgmii_phy8_3: ethernet-phy@1e { + reg = <0x1e>; + }; + + sgmii_phy8_4: ethernet-phy@1f { + reg = <0x1f>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts index 4946ce8dfb..e0f5d5e2d3 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -1,14 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * NXP LX2160AQDS device tree source + * NXP LX2160AQDS default device tree source * - * Copyright 2018-2020 NXP + * Copyright 2020 NXP * */ /dts-v1/; -#include "fsl-lx2160a.dtsi" +#include "fsl-lx2160a-qds.dtsi" / { model = "NXP Layerscape LX2160AQDS Board"; @@ -17,177 +17,3 @@ spi0 = &fspi; }; }; - -&dpmac17 { - status = "okay"; - phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii-id"; -}; - -&dpmac18 { - status = "okay"; - phy-handle = <&rgmii_phy2>; - phy-connection-type = "rgmii-id"; -}; - -&emdio1 { - status = "okay"; -}; - -&emdio2 { - status = "okay"; -}; - -&esdhc0 { - status = "okay"; -}; - -&esdhc1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - u-boot,dm-pre-reloc; - - fpga@66 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-mfd"; - reg = <0x66>; - - mux-mdio@54 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "mdio-mux-i2creg"; - reg = <0x54>; - #mux-control-cells = <1>; - mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3 - mdio-parent-bus = <&emdio1>; - - mdio@00 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x00>; - - rgmii_phy1: ethernet-phy@1 { - reg = <0x1>; - }; - }; - mdio@08 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x40>; - - rgmii_phy2: ethernet-phy@2 { - reg = <0x2>; - }; - }; - - emdio1_slot1: mdio@c0 { /* I/O Slot #1 */ - reg = <0xC0>; - device-name = "emdio1_slot1"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot2: mdio@c8 { /* I/O Slot #2 */ - reg = <0xC8>; - device-name = "emdio1_slot2"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot3: mdio@d0 { /* I/O Slot #3 */ - reg = <0xD0>; - device-name = "emdio1_slot3"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot4: mdio@d8 { /* I/O Slot #4 */ - reg = <0xD8>; - device-name = "emdio1_slot4"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot5: mdio@e0 { /* I/O Slot #5 */ - reg = <0xE0>; - device-name = "emdio1_slot5"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot6: mdio@e8 { /* I/O Slot #6 */ - reg = <0xE8>; - device-name = "emdio1_slot6"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot7: mdio@f0 { /* I/O Slot #7 */ - reg = <0xF0>; - device-name = "emdio1_slot7"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot8: mdio@f8 { /* I/O Slot #8 */ - reg = <0xF8>; - device-name = "emdio1_slot8"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - }; - - i2c-mux@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - rtc@51 { - compatible = "pcf2127-rtc"; - reg = <0x51>; - }; - }; - }; -}; - -&fspi { - status = "okay"; - - mt35xu512aba0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - spi-rx-bus-width = <8>; - spi-tx-bus-width = <1>; - }; -}; - -&sata0 { - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&sata2 { - status = "okay"; -}; - -&sata3 { - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi b/arch/arm/dts/fsl-lx2160a-qds.dtsi new file mode 100644 index 0000000000..129cf82a8f --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS common device tree source + * + * Copyright 2018-2019 NXP + * + */ + +#include "fsl-lx2160a.dtsi" + +&dpmac17 { + status = "okay"; + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; +}; + +&dpmac18 { + status = "okay"; + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-id"; +}; + +&emdio1 { + status = "okay"; +}; + +&emdio2 { + status = "okay"; +}; + +&esdhc0 { + status = "okay"; +}; + +&esdhc1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + u-boot,dm-pre-reloc; + + fpga@66 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-mfd"; + reg = <0x66>; + + mux-mdio@54 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mdio-mux-i2creg"; + reg = <0x54>; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3 + mdio-parent-bus = <&emdio1>; + + mdio@00 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + }; + mdio@08 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40>; + + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + }; + + emdio1_slot1: mdio@c0 { /* I/O Slot #1 */ + reg = <0xC0>; + device-name = "emdio1_slot1"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot2: mdio@c8 { /* I/O Slot #2 */ + reg = <0xC8>; + device-name = "emdio1_slot2"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot3: mdio@d0 { /* I/O Slot #3 */ + reg = <0xD0>; + device-name = "emdio1_slot3"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot4: mdio@d8 { /* I/O Slot #4 */ + reg = <0xD8>; + device-name = "emdio1_slot4"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot5: mdio@e0 { /* I/O Slot #5 */ + reg = <0xE0>; + device-name = "emdio1_slot5"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot6: mdio@e8 { /* I/O Slot #6 */ + reg = <0xE8>; + device-name = "emdio1_slot6"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot7: mdio@f0 { /* I/O Slot #7 */ + reg = <0xF0>; + device-name = "emdio1_slot7"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot8: mdio@f8 { /* I/O Slot #8 */ + reg = <0xF8>; + device-name = "emdio1_slot8"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + }; + + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + rtc@51 { + compatible = "pcf2127-rtc"; + reg = <0x51>; + }; + }; + }; +}; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sata3 { + status = "okay"; +}; -- cgit v1.2.3 From b62526282ab2e505148d8c962dfb888f155ec7e9 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 15 May 2020 09:56:48 +0300 Subject: arm: dts: ls1088aqds: add CONFIG_MULTI_DTB_FIT support Add support for selecting the appropriate DTS file depending on the SERDES protocol used. The fsl-ls2088a-qds DTS will be used by default if there isn't a DTS file specifically made for the current SERDES protocol. This patch adds support for the on-board ports (DPMAC 1,2 and 4,5) found on the SERDES protocols 21(0x15) and 29(0x1d) for SD#1. On the LS1088AQDS board EMDIO1 is used with two onboard RGMII PHYs (Realtek RTL8211FD-CG), as well as 2 input/output connectors for mezzanine cards. Configuration signals from the Qixis FPGA control the routing of the external MDIOs. Register 0x54 of the Qixis FPGA controls the routing of the EMDIO1 one of the 2 IO slots. As a consequence, a new node is added to describe register 0x54 as a MDIO mux controlled with child nodes describing all the IO slots as MDIO buses. Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS. Signed-off-by: Ioana Ciornei Signed-off-by: Priyanka Jain --- arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-ls1088a-qds-21-x.dts | 16 +++ arch/arm/dts/fsl-ls1088a-qds-29-x.dts | 16 +++ arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi | 30 +++++ arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi | 18 +++ arch/arm/dts/fsl-ls1088a-qds.dts | 123 +------------------- arch/arm/dts/fsl-ls1088a-qds.dtsi | 186 +++++++++++++++++++++++++++++++ board/freescale/ls1088a/eth_ls1088aqds.c | 87 +++++++++++++++ 8 files changed, 358 insertions(+), 120 deletions(-) create mode 100644 arch/arm/dts/fsl-ls1088a-qds-21-x.dts create mode 100644 arch/arm/dts/fsl-ls1088a-qds-29-x.dts create mode 100644 arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi create mode 100644 arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi create mode 100644 arch/arm/dts/fsl-ls1088a-qds.dtsi (limited to 'arch/arm') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f28fc371c3..d6f799635d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -379,6 +379,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2088a-rdb-qspi.dtb \ fsl-ls1088a-rdb.dtb \ fsl-ls1088a-qds.dtb \ + fsl-ls1088a-qds-21-x.dtb \ + fsl-ls1088a-qds-29-x.dtb \ fsl-ls1028a-rdb.dtb \ fsl-ls1028a-qds-duart.dtb \ fsl-ls1028a-qds-lpuart.dtb \ diff --git a/arch/arm/dts/fsl-ls1088a-qds-21-x.dts b/arch/arm/dts/fsl-ls1088a-qds-21-x.dts new file mode 100644 index 0000000000..a877964511 --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds-21-x.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1088AQDS device tree source for SERDES protocol 21.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-ls1088a-qds-sd1-21.dtsi" + +/ { + model = "NXP Layerscape 1088a QDS Board (DTS 21-x)"; + compatible = "fsl,ls1088a-qds", "fsl,ls1088a"; +}; diff --git a/arch/arm/dts/fsl-ls1088a-qds-29-x.dts b/arch/arm/dts/fsl-ls1088a-qds-29-x.dts new file mode 100644 index 0000000000..29c4ec59fe --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds-29-x.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1088AQDS device tree source for SERDES protocol 29.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-ls1088a-qds-sd1-29.dtsi" + +/ { + model = "NXP Layerscape 1088a QDS Board (DTS 29-x)"; + compatible = "fsl,ls1088a-qds", "fsl,ls1088a"; +}; diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi new file mode 100644 index 0000000000..e0a6c04835 --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1088AQDS device tree source for SERDES block #1 - protocol 21 (0x15) + * + * Copyright 2020 NXP + */ + +#include "fsl-ls1088a-qds.dtsi" + +&dpmac1 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac2 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-id"; +}; diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi new file mode 100644 index 0000000000..65e95300ab --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1088AQDS device tree source for SERDES block #1 - protocol 29 (0x1d) + * + * Copyright 2020 NXP + */ + +#include "fsl-ls1088a-qds.dtsi" + +&dpmac1 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac2 { + status = "okay"; + phy-connection-type = "xfi"; +}; diff --git a/arch/arm/dts/fsl-ls1088a-qds.dts b/arch/arm/dts/fsl-ls1088a-qds.dts index 4f37a28992..8e64e713aa 100644 --- a/arch/arm/dts/fsl-ls1088a-qds.dts +++ b/arch/arm/dts/fsl-ls1088a-qds.dts @@ -1,132 +1,15 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * NXP ls1088a QDS board device tree source + * NXP ls1088a QDS default board device tree source * - * Copyright 2017 NXP + * Copyright 2020 NXP */ /dts-v1/; -#include "fsl-ls1088a.dtsi" +#include "fsl-ls1088a-qds.dtsi" / { model = "NXP Layerscape 1088a QDS Board"; compatible = "fsl,ls1088a-qds", "fsl,ls1088a"; - aliases { - spi0 = &qspi; - spi1 = &dspi; - }; -}; - -&i2c0 { - status = "okay"; - u-boot,dm-pre-reloc; - - i2c-mux@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - rtc@51 { - compatible = "pcf2127-rtc"; - reg = <0x51>; - }; - }; - }; -}; - -&ifc { - #address-cells = <2>; - #size-cells = <1>; - /* NOR, NAND Flashes and FPGA on board */ - ranges = <0 0 0x5 0x80000000 0x08000000 - 2 0 0x5 0x30000000 0x00010000 - 3 0 0x5 0x20000000 0x00010000>; - status = "okay"; - - nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - bank-width = <2>; - device-width = <1>; - }; - - nand@2,0 { - compatible = "fsl,ifc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x1 0x0 0x10000>; - }; - - fpga: board-control@3,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus", "fsl,ls1088aqds-fpga", - "fsl,fpga-qixis"; - reg = <0x2 0x0 0x0000100>; - bank-width = <1>; - device-width = <1>; - ranges = <0 2 0 0x100>; - }; -}; - -&dspi { - bus-num = <0>; - status = "okay"; - - dflash0: n25q128a { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <1000000>; /* input clock */ - }; - - dflash1: sst25wf040b { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3500000>; - reg = <1>; - }; - - dflash2: en25s64 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3500000>; - reg = <2>; - }; -}; - -&qspi { - status = "okay"; - - s25fs512s0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - - s25fs512s1: flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <1>; - }; -}; - -&sata { - status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1088a-qds.dtsi b/arch/arm/dts/fsl-ls1088a-qds.dtsi new file mode 100644 index 0000000000..a7d0edcf0a --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds.dtsi @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP ls1088a QDS common board device tree source + * + * Copyright 2017-2020 NXP + */ + +#include "fsl-ls1088a.dtsi" + +/ { + aliases { + spi0 = &qspi; + spi1 = &dspi; + }; +}; + +&emdio1 { + status = "okay"; +}; + +&emdio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + u-boot,dm-pre-reloc; + + fpga@66 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-mfd"; + reg = <0x66>; + + mux-mdio@54 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mdio-mux-i2creg"; + reg = <0x54>; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xe0>; // reg 0x54, bits 7:5 + mdio-parent-bus = <&emdio1>; + + mdio@00 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + }; + mdio@20 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x20>; + + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + }; + + emdio1_slot1: mdio@40 { /* I/O Slot #1 */ + reg = <0x40>; + device-name = "emdio1_slot1"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot3: mdio@60 { /* I/O Slot #3 */ + reg = <0x60>; + device-name = "emdio1_slot3"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + rtc@51 { + compatible = "pcf2127-rtc"; + reg = <0x51>; + }; + }; + }; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0 0 0x5 0x80000000 0x08000000 + 2 0 0x5 0x30000000 0x00010000 + 3 0 0x5 0x20000000 0x00010000>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + nand@2,0 { + compatible = "fsl,ifc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1 0x0 0x10000>; + }; + + fpga: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus", "fsl,ls1088aqds-fpga", + "fsl,fpga-qixis"; + reg = <0x2 0x0 0x0000100>; + bank-width = <1>; + device-width = <1>; + ranges = <0 2 0 0x100>; + }; +}; + +&dspi { + bus-num = <0>; + status = "okay"; + + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; /* input clock */ + }; + + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3500000>; + reg = <1>; + }; + + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3500000>; + reg = <2>; + }; +}; + +&qspi { + status = "okay"; + + s25fs512s0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + + s25fs512s1: flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <1>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c index 54ef75347f..c0bcf71299 100644 --- a/board/freescale/ls1088a/eth_ls1088aqds.c +++ b/board/freescale/ls1088a/eth_ls1088aqds.c @@ -742,3 +742,90 @@ void reset_phy(void) mc_env_boot(); } #endif /* CONFIG_RESET_PHY_R */ + +#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT) + +/* Structure to hold SERDES protocols supported in case of + * CONFIG_DM_ETH enabled (network interfaces are described in the DTS). + * + * @serdes_block: the index of the SERDES block + * @serdes_protocol: the decimal value of the protocol supported + * @dts_needed: DTS notes describing the current configuration are needed + * + * When dts_needed is true, the board_fit_config_name_match() function + * will try to exactly match the current configuration of the block with a DTS + * name provided. + */ +static struct serdes_configuration { + u8 serdes_block; + u32 serdes_protocol; + bool dts_needed; +} supported_protocols[] = { + /* Serdes block #1 */ + {1, 21, true}, + {1, 29, true}, +}; + +#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) + +static bool protocol_supported(u8 serdes_block, u32 protocol) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) + return true; + } + + return false; +} + +static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) { + if (serdes_conf.dts_needed == true) + sprintf(str, "%u", protocol); + else + sprintf(str, "x"); + return; + } + } +} + +int board_fit_config_name_match(const char *name) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + char expected_dts[100]; + char srds_s1_str[2]; + u32 srds_s1, cfg; + + cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & + FSL_CHASSIS3_SRDS1_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; + srds_s1 = serdes_get_number(FSL_SRDS_1, cfg); + + /* Check for supported protocols. The default DTS will be used + * in this case + */ + if (!protocol_supported(1, srds_s1)) + return -1; + + get_str_protocol(1, srds_s1, srds_s1_str); + + sprintf(expected_dts, "fsl-ls1088a-qds-%s-x", srds_s1_str); + + if (!strcmp(name, expected_dts)) + return 0; + + return -1; +} +#endif -- cgit v1.2.3 From 020ed9c666748b103e0740622ca4128a2bd40f29 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Mon, 18 May 2020 14:48:36 +0300 Subject: arm: dts: ls2080aqds: add CONFIG_MULTI_DTB_FIT support Add support for selecting the appropriate DTS file depending on the SERDES protocol used. The fsl-ls2080a-qds DTS will be used by default if there isn't a DTS file specifically made for the current SERDES protocol. This patch adds the necessary DPMAC nodes (DPMAC 1-8) for protocol 42 (0x2A) on SD#1. Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS. Signed-off-by: Ioana Ciornei Reviewed-by: Priyanka Jain --- arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-ls2080a-qds-42-x.dts | 16 ++++++ arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi | 48 ++++++++++++++++ arch/arm/dts/fsl-ls2080a-qds.dts | 72 +----------------------- arch/arm/dts/fsl-ls2080a-qds.dtsi | 77 +++++++++++++++++++++++++ board/freescale/ls2080aqds/eth.c | 97 ++++++++++++++++++++++++++++++++ 6 files changed, 241 insertions(+), 70 deletions(-) create mode 100644 arch/arm/dts/fsl-ls2080a-qds-42-x.dts create mode 100644 arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi create mode 100644 arch/arm/dts/fsl-ls2080a-qds.dtsi (limited to 'arch/arm') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d6f799635d..2404eaa5ee 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -374,6 +374,7 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ ls1021a-iot-duart.dtb ls1021a-tsn.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ + fsl-ls2080a-qds-42-x.dtb \ fsl-ls2080a-rdb.dtb \ fsl-ls2081a-rdb.dtb \ fsl-ls2088a-rdb-qspi.dtb \ diff --git a/arch/arm/dts/fsl-ls2080a-qds-42-x.dts b/arch/arm/dts/fsl-ls2080a-qds-42-x.dts new file mode 100644 index 0000000000..bd46c395d4 --- /dev/null +++ b/arch/arm/dts/fsl-ls2080a-qds-42-x.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS2080AQDS device tree source for SERDES protocol 42.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-ls2080a-qds-sd1-42.dtsi" + +/ { + model = "NXP Layerscape LS2080AQDS Board (DTS 42-x)"; + compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; +}; diff --git a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi new file mode 100644 index 0000000000..ccbb5de1ea --- /dev/null +++ b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS2080aQDS device tree source for SERDES block #1 - protocol 42 (0x2a) + * + * Copyright 2020 NXP + */ + +#include "fsl-ls2080a-qds.dtsi" + +&dpmac1 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac2 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac3 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac4 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac5 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac6 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac7 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac8 { + status = "okay"; + phy-connection-type = "xfi"; +}; diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts index f91a48d9fd..a1196f9292 100644 --- a/arch/arm/dts/fsl-ls2080a-qds.dts +++ b/arch/arm/dts/fsl-ls2080a-qds.dts @@ -1,13 +1,13 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Freescale ls2080a QDS board device tree source + * Freescale ls2080a QDS defaul board device tree source * * Copyright 2013-2015 Freescale Semiconductor, Inc. */ /dts-v1/; -#include "fsl-ls2080a.dtsi" +#include "fsl-ls2080a-qds.dtsi" / { model = "Freescale Layerscape 2080a QDS Board"; @@ -18,71 +18,3 @@ spi1 = &dspi; }; }; - -&i2c0 { - status = "okay"; - pca9547@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x00>; - rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; - }; - }; - }; -}; - -&dspi { - bus-num = <0>; - status = "okay"; - - dflash0: n25q128a { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <0>; - }; - dflash1: sst25wf040b { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <1>; - }; - dflash2: en25s64 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <2>; - }; -}; - -&qspi { - status = "okay"; - - s25fs256s0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-ls2080a-qds.dtsi b/arch/arm/dts/fsl-ls2080a-qds.dtsi new file mode 100644 index 0000000000..cb7851f2cc --- /dev/null +++ b/arch/arm/dts/fsl-ls2080a-qds.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Freescale ls2080a QDS common device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + */ + +#include "fsl-ls2080a.dtsi" + +&i2c0 { + status = "okay"; + pca9547@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + }; + }; + }; +}; + +&dspi { + bus-num = <0>; + status = "okay"; + + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; + +&qspi { + status = "okay"; + + s25fs256s0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 2b1b106b07..0d6eec377f 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -989,3 +989,100 @@ void reset_phy(void) mc_env_boot(); } #endif /* CONFIG_RESET_PHY_R */ + +#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT) + +/* Structure to hold SERDES protocols supported in case of + * CONFIG_DM_ETH enabled (network interfaces are described in the DTS). + * + * @serdes_block: the index of the SERDES block + * @serdes_protocol: the decimal value of the protocol supported + * @dts_needed: DTS notes describing the current configuration are needed + * + * When dts_needed is true, the board_fit_config_name_match() function + * will try to exactly match the current configuration of the block with a DTS + * name provided. + */ +static struct serdes_configuration { + u8 serdes_block; + u32 serdes_protocol; + bool dts_needed; +} supported_protocols[] = { + /* Serdes block #1 */ + {1, 42, true}, + + /* Serdes block #2 */ + {2, 65, false}, +}; + +#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) + +static bool protocol_supported(u8 serdes_block, u32 protocol) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) + return true; + } + + return false; +} + +static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) { + if (serdes_conf.dts_needed == true) + sprintf(str, "%u", protocol); + else + sprintf(str, "x"); + return; + } + } +} + +int board_fit_config_name_match(const char *name) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 rcw_status = in_le32(&gur->rcwsr[28]); + char srds_s1_str[2], srds_s2_str[2]; + u32 srds_s1, srds_s2; + char expected_dts[100]; + + srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + + /* Check for supported protocols. The default DTS will be used + * in this case + */ + if (!protocol_supported(1, srds_s1) || + !protocol_supported(2, srds_s2)) + return -1; + + get_str_protocol(1, srds_s1, srds_s1_str); + get_str_protocol(2, srds_s2, srds_s2_str); + + printf("expected_dts %s\n", expected_dts); + sprintf(expected_dts, "fsl-ls2080a-qds-%s-%s", + srds_s1_str, srds_s2_str); + + if (!strcmp(name, expected_dts)) + return 0; + + printf("this is not!\n"); + return -1; +} + +#endif -- cgit v1.2.3