From 93557bd260506c9965ad592d05b610268ab59a3f Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Mon, 6 May 2019 11:21:12 +0800 Subject: rockchip: add common header boot0.h and gpio.h for soc boot0.h and gpio.h will be used by system and include by 'asm/arch/', each of them need of a copy from 'asm/arch-rockchip'. Signed-off-by: Kever Yang Reviewed-by: Tom Rini --- arch/arm/include/asm/arch-rk3036/boot0.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3036/gpio.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3128/boot0.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3128/gpio.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3188/boot0.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3188/gpio.h | 11 +++++++++++ arch/arm/include/asm/arch-rk322x/boot0.h | 11 +++++++++++ arch/arm/include/asm/arch-rk322x/gpio.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3288/boot0.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3288/gpio.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3328/boot0.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3328/gpio.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3368/boot0.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3368/gpio.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3399/boot0.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3399/gpio.h | 11 +++++++++++ arch/arm/include/asm/arch-rv1108/boot0.h | 11 +++++++++++ arch/arm/include/asm/arch-rv1108/gpio.h | 11 +++++++++++ 18 files changed, 198 insertions(+) create mode 100644 arch/arm/include/asm/arch-rk3036/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3036/gpio.h create mode 100644 arch/arm/include/asm/arch-rk3128/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3128/gpio.h create mode 100644 arch/arm/include/asm/arch-rk3188/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3188/gpio.h create mode 100644 arch/arm/include/asm/arch-rk322x/boot0.h create mode 100644 arch/arm/include/asm/arch-rk322x/gpio.h create mode 100644 arch/arm/include/asm/arch-rk3288/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3288/gpio.h create mode 100644 arch/arm/include/asm/arch-rk3328/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3328/gpio.h create mode 100644 arch/arm/include/asm/arch-rk3368/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3368/gpio.h create mode 100644 arch/arm/include/asm/arch-rk3399/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3399/gpio.h create mode 100644 arch/arm/include/asm/arch-rv1108/boot0.h create mode 100644 arch/arm/include/asm/arch-rv1108/gpio.h (limited to 'arch/arm') diff --git a/arch/arm/include/asm/arch-rk3036/boot0.h b/arch/arm/include/asm/arch-rk3036/boot0.h new file mode 100644 index 0000000000..2e78b074ad --- /dev/null +++ b/arch/arm/include/asm/arch-rk3036/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3036/gpio.h b/arch/arm/include/asm/arch-rk3036/gpio.h new file mode 100644 index 0000000000..eca79d5159 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3036/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3128/boot0.h b/arch/arm/include/asm/arch-rk3128/boot0.h new file mode 100644 index 0000000000..2e78b074ad --- /dev/null +++ b/arch/arm/include/asm/arch-rk3128/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3128/gpio.h b/arch/arm/include/asm/arch-rk3128/gpio.h new file mode 100644 index 0000000000..eca79d5159 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3128/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3188/boot0.h b/arch/arm/include/asm/arch-rk3188/boot0.h new file mode 100644 index 0000000000..2e78b074ad --- /dev/null +++ b/arch/arm/include/asm/arch-rk3188/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3188/gpio.h b/arch/arm/include/asm/arch-rk3188/gpio.h new file mode 100644 index 0000000000..eca79d5159 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3188/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk322x/boot0.h b/arch/arm/include/asm/arch-rk322x/boot0.h new file mode 100644 index 0000000000..2e78b074ad --- /dev/null +++ b/arch/arm/include/asm/arch-rk322x/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk322x/gpio.h b/arch/arm/include/asm/arch-rk322x/gpio.h new file mode 100644 index 0000000000..eca79d5159 --- /dev/null +++ b/arch/arm/include/asm/arch-rk322x/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3288/boot0.h b/arch/arm/include/asm/arch-rk3288/boot0.h new file mode 100644 index 0000000000..2e78b074ad --- /dev/null +++ b/arch/arm/include/asm/arch-rk3288/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3288/gpio.h b/arch/arm/include/asm/arch-rk3288/gpio.h new file mode 100644 index 0000000000..eca79d5159 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3288/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3328/boot0.h b/arch/arm/include/asm/arch-rk3328/boot0.h new file mode 100644 index 0000000000..2e78b074ad --- /dev/null +++ b/arch/arm/include/asm/arch-rk3328/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3328/gpio.h b/arch/arm/include/asm/arch-rk3328/gpio.h new file mode 100644 index 0000000000..eca79d5159 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3328/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3368/boot0.h b/arch/arm/include/asm/arch-rk3368/boot0.h new file mode 100644 index 0000000000..2e78b074ad --- /dev/null +++ b/arch/arm/include/asm/arch-rk3368/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3368/gpio.h b/arch/arm/include/asm/arch-rk3368/gpio.h new file mode 100644 index 0000000000..eca79d5159 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3368/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3399/boot0.h b/arch/arm/include/asm/arch-rk3399/boot0.h new file mode 100644 index 0000000000..2e78b074ad --- /dev/null +++ b/arch/arm/include/asm/arch-rk3399/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3399/gpio.h b/arch/arm/include/asm/arch-rk3399/gpio.h new file mode 100644 index 0000000000..eca79d5159 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3399/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rv1108/boot0.h b/arch/arm/include/asm/arch-rv1108/boot0.h new file mode 100644 index 0000000000..2e78b074ad --- /dev/null +++ b/arch/arm/include/asm/arch-rv1108/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rv1108/gpio.h b/arch/arm/include/asm/arch-rv1108/gpio.h new file mode 100644 index 0000000000..eca79d5159 --- /dev/null +++ b/arch/arm/include/asm/arch-rv1108/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif -- cgit v1.2.3 From dc23c27aa5ac7672bc8206e0f46e9aceab1f0bb7 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Mon, 6 May 2019 11:21:13 +0800 Subject: arm: remove ARCH_ROCKCHIP macro in common code This is fix to: e2a12f590d rockchip: use 'arch-rockchip' as header file path The V2 of origin patch set has fix this, but we merge V1 by mistake, so lets correct it. Signed-off-by: Kever Yang --- arch/arm/cpu/armv8/start.S | 4 ---- arch/arm/lib/vectors.S | 4 ---- 2 files changed, 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index ecee9e37a5..fe52166e28 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -26,11 +26,7 @@ _start: * order to boot, allow them to set that in their boot0.h file and then * use it here. */ -#ifdef CONFIG_ARCH_ROCKCHIP -#include -#else #include -#endif #else b reset #endif diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index 20f485142e..56f3681558 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -67,11 +67,7 @@ * (1) defines '_start:' as appropriate * (2) inserts the vector table using ARM_VECTORS as appropriate */ -#ifdef CONFIG_ARCH_ROCKCHIP -#include -#else #include -#endif #else /* -- cgit v1.2.3 From 1e32c5194fabebd6f1b4742e56b1660c9d9b1a57 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 2 Apr 2019 20:41:20 +0800 Subject: arm: add option for TPL support in arm 32bit Some options like TPL_SYS_THUMB_BUILD, TPL_USE_ARCH_MEMCPY and TPL_USE_ARCH_MEMCPY are needed for TPL build in 32bit arm. Signed-off-by: Kever Yang --- arch/arm/Kconfig | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f91c590f6d..a3d67e43f0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -338,6 +338,17 @@ config SPL_SYS_THUMB_BUILD density. For ARM architectures that support Thumb2 this flag will result in Thumb2 code generated by GCC. +config TPL_SYS_THUMB_BUILD + bool "Build TPL using the Thumb instruction set" + default y if SYS_THUMB_BUILD + depends on TPL && !ARM64 + help + Use this flag to build SPL using the Thumb instruction set for + ARM architectures. Thumb instruction set provides better code + density. For ARM architectures that support Thumb2 this flag will + result in Thumb2 code generated by GCC. + + config SYS_L2CACHE_OFF bool "L2cache off" help @@ -373,6 +384,15 @@ config SPL_USE_ARCH_MEMCPY Such implementation may be faster under some conditions but may increase the binary size. +config TPL_USE_ARCH_MEMCPY + bool "Use an assembly optimized implementation of memcpy for TPL" + default y if USE_ARCH_MEMCPY + depends on !ARM64 + help + Enable the generation of an optimized version of memcpy. + Such implementation may be faster under some conditions + but may increase the binary size. + config USE_ARCH_MEMSET bool "Use an assembly optimized implementation of memset" default y @@ -391,6 +411,15 @@ config SPL_USE_ARCH_MEMSET Such implementation may be faster under some conditions but may increase the binary size. +config TPL_USE_ARCH_MEMSET + bool "Use an assembly optimized implementation of memset for TPL" + default y if USE_ARCH_MEMSET + depends on !ARM64 + help + Enable the generation of an optimized version of memset. + Such implementation may be faster under some conditions + but may increase the binary size. + config ARM64_SUPPORT_AARCH32 bool "ARM64 system support AArch32 execution state" default y if ARM64 && !TARGET_THUNDERX_88XX -- cgit v1.2.3 From a0a0d04f3218507aaa29b4fdd45f37d819fb0a32 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 2 Apr 2019 20:41:21 +0800 Subject: arm: add a separate stack for TPL TPL stack may different from SPL and sys stack, add support for separate one when the board defines it. Signed-off-by: Kever Yang --- arch/arm/lib/crt0.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index fe312db690..30fba20e1b 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -67,7 +67,9 @@ ENTRY(_main) * Set up initial C runtime environment and call board_init_f(0). */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK) + ldr r0, =(CONFIG_TPL_STACK) +#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) ldr r0, =(CONFIG_SPL_STACK) #else ldr r0, =(CONFIG_SYS_INIT_SP_ADDR) -- cgit v1.2.3 From c34643e0db40bbcfaea8a0df8b6f4d0be7b0f71f Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 2 Apr 2019 20:41:24 +0800 Subject: rockchip: rk322x: add tpl support Move original spl to tpl, and add spl to load next stage firmware, adapt all the address and option for them. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 26 +++++++++++++++ arch/arm/mach-rockchip/Makefile | 3 +- arch/arm/mach-rockchip/rk322x-board-spl.c | 46 ++++++++++----------------- arch/arm/mach-rockchip/rk322x-board-tpl.c | 53 +++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/u-boot-tpl.lds | 12 +++++++ include/configs/rk322x_common.h | 6 ++-- 6 files changed, 113 insertions(+), 33 deletions(-) create mode 100644 arch/arm/mach-rockchip/rk322x-board-tpl.c create mode 100644 arch/arm/mach-rockchip/u-boot-tpl.lds (limited to 'arch/arm') diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 282d728b82..48e364e127 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -47,14 +47,40 @@ config ROCKCHIP_RK322X bool "Support Rockchip RK3228/RK3229" select CPU_V7A select SUPPORT_SPL + select SUPPORT_TPL select SPL + select SPL_DM + select SPL_OF_LIBFDT + select TPL + select TPL_DM + select TPL_OF_LIBFDT + select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL + select TPL_NEEDS_SEPARATE_STACK if TPL + select SPL_DRIVERS_MISC_SUPPORT + imply SPL_SERIAL_SUPPORT + imply TPL_SERIAL_SUPPORT select ROCKCHIP_BROM_HELPER + select TPL_LIBCOMMON_SUPPORT + select TPL_LIBGENERIC_SUPPORT help The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7 including NEON and GPU, Mali-400 graphics, several DDR3 options and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. +if ROCKCHIP_RK322X + +config TPL_TEXT_BASE + default 0x10081000 + +config TPL_MAX_SIZE + default 28672 + +config TPL_STACK + default 0x10088000 + +endif + config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" select CPU_V7A diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 368302e1da..fd62a693fe 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -11,10 +11,11 @@ obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o +obj-tpl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o -obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c index 888310efbe..c9b41c62c0 100644 --- a/arch/arm/mach-rockchip/rk322x-board-spl.c +++ b/arch/arm/mach-rockchip/rk322x-board-spl.c @@ -4,55 +4,43 @@ */ #include -#include #include -#include #include #include -#include #include -#include u32 spl_boot_device(void) { return BOOT_DEVICE_MMC1; } +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + #define SGRF_DDR_CON0 0x10150000 void board_init_f(ulong dummy) { - struct udevice *dev; int ret; -#ifdef CONFIG_DEBUG_UART - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - printascii("SPL Init"); -#endif ret = spl_early_init(); if (ret) { - debug("spl_early_init() failed: %d\n", ret); + printf("spl_early_init() failed: %d\n", ret); hang(); } - - rockchip_timer_init(); - printf("timer init done\n"); - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - printf("DRAM init failed: %d\n", ret); - return; - } + preloader_console_init(); /* Disable the ddr secure region setting to make it non-secure */ rk_clrreg(SGRF_DDR_CON0, 0x4000); -#if defined(CONFIG_SPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -#endif } + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rk322x-board-tpl.c b/arch/arm/mach-rockchip/rk322x-board-tpl.c new file mode 100644 index 0000000000..92d40ee43a --- /dev/null +++ b/arch/arm/mach-rockchip/rk322x-board-tpl.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + printascii("TPL Init"); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + rockchip_timer_init(); + printf("timer init done\n"); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("DRAM init failed: %d\n", ret); + return; + } + +#if defined(CONFIG_TPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_TPL_BOARD_INIT) + back_to_bootrom(BROM_BOOT_NEXTSTAGE); +#endif +} diff --git a/arch/arm/mach-rockchip/u-boot-tpl.lds b/arch/arm/mach-rockchip/u-boot-tpl.lds new file mode 100644 index 0000000000..f5a89721ce --- /dev/null +++ b/arch/arm/mach-rockchip/u-boot-tpl.lds @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Rockchip Electronic Co.,Ltd + */ + +#undef CONFIG_SPL_TEXT_BASE +#define CONFIG_SPL_TEXT_BASE CONFIG_TPL_TEXT_BASE + +#undef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_MAX_SIZE CONFIG_TPL_MAX_SIZE + +#include "../cpu/u-boot-spl.lds" diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 3a96748f6b..15bb8d63b8 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -17,9 +17,9 @@ #define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */ #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) -#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 -#define CONFIG_SYS_LOAD_ADDR 0x60800800 -#define CONFIG_SPL_STACK 0x10088000 +#define CONFIG_SYS_INIT_SP_ADDR 0x61100000 +#define CONFIG_SYS_LOAD_ADDR 0x61800800 +#define CONFIG_SPL_MAX_SIZE 0x100000 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10) #define CONFIG_ROCKCHIP_CHIP_TAG "RK32" -- cgit v1.2.3 From 09259fce1e8b4ac34a47d4590f42878a38b42826 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 2 Apr 2019 20:41:25 +0800 Subject: sysreset: enable driver support in SPL/TPL SPL/TPL also need use sysreset for some feature like panic callback. Signed-off-by: Kever Yang --- arch/Kconfig | 1 + arch/arm/Kconfig | 1 + configs/am65x_evm_a53_defconfig | 1 + configs/am65x_evm_r5_defconfig | 1 + configs/am65x_hs_evm_a53_defconfig | 1 + configs/am65x_hs_evm_r5_defconfig | 1 + configs/mt7629_rfb_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + drivers/sysreset/Kconfig | 18 ++++++++++++++++++ drivers/sysreset/Makefile | 2 +- 10 files changed, 27 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/Kconfig b/arch/Kconfig index 760023b19a..03277dd2c1 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -158,6 +158,7 @@ config X86 imply DM_USB imply DM_VIDEO imply SYSRESET + imply SPL_SYSRESET imply SYSRESET_X86 imply USB_ETHER_ASIX imply USB_ETHER_SMSC95XX diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a3d67e43f0..3c4af1f299 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1436,6 +1436,7 @@ config ARCH_STM32MP select SYSCON select SYSRESET select SYS_THUMB_BUILD + imply SPL_SYSRESET imply CMD_DM imply CMD_POWEROFF imply ENV_VARS_UBOOT_RUNTIME_CONFIG diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 101fae1456..41cf0100fa 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -72,4 +72,5 @@ CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_TI=y CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index 8dce577cf7..3814872ec7 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -83,6 +83,7 @@ CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig index 7af0046ee3..9c55cd37f6 100644 --- a/configs/am65x_hs_evm_a53_defconfig +++ b/configs/am65x_hs_evm_a53_defconfig @@ -75,4 +75,5 @@ CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_TI=y CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y diff --git a/configs/am65x_hs_evm_r5_defconfig b/configs/am65x_hs_evm_r5_defconfig index 8d5d3590b2..0b12f15782 100644 --- a/configs/am65x_hs_evm_r5_defconfig +++ b/configs/am65x_hs_evm_r5_defconfig @@ -85,6 +85,7 @@ CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig index 01b952fc15..0dceafdaa6 100644 --- a/configs/mt7629_rfb_defconfig +++ b/configs/mt7629_rfb_defconfig @@ -65,6 +65,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MTK_QSPI=y CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index a46edee634..e2826a6a95 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -174,6 +174,7 @@ CONFIG_SANDBOX_SPI=y CONFIG_SPMI=y CONFIG_SPMI_SANDBOX=y CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y CONFIG_TIMER=y CONFIG_TIMER_EARLY=y CONFIG_SANDBOX_TIMER=y diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 8ce3e2e207..d456f0ce36 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -13,6 +13,24 @@ config SYSRESET to effect a reset. The uclass will try all available drivers when reset_walk() is called. +config SPL_SYSRESET + bool "Enable support for system reset drivers in SPL mode" + depends on SYSRESET && SPL_DM + help + Enable system reset drivers which can be used to reset the CPU or + board. Each driver can provide a reset method which will be called + to effect a reset. The uclass will try all available drivers when + reset_walk() is called. + +config TPL_SYSRESET + bool "Enable support for system reset drivers in TPL mode" + depends on SYSRESET && TPL_DM + help + Enable system reset drivers which can be used to reset the CPU or + board. Each driver can provide a reset method which will be called + to effect a reset. The uclass will try all available drivers when + reset_walk() is called. + if SYSRESET config SYSRESET_GPIO diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index b3728ac17f..8e1c845dfe 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -2,7 +2,7 @@ # # (C) Copyright 2016 Cadence Design Systems Inc. -obj-$(CONFIG_SYSRESET) += sysreset-uclass.o +obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset-uclass.o obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o obj-$(CONFIG_ARCH_STI) += sysreset_sti.o -- cgit v1.2.3 From d55dbfed1677dc35bc29e1a297695e63eaf37a13 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 2 Apr 2019 20:41:26 +0800 Subject: rockchip: rk322x: dts: enable uart2 for SPL/TPL When we use DM_SERIAL for serial driver, we need enable the dts node for the debug console. Signed-off-by: Kever Yang --- arch/arm/dts/rk3229-evb.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts index bfb367ac99..632cdc9bc3 100644 --- a/arch/arm/dts/rk3229-evb.dts +++ b/arch/arm/dts/rk3229-evb.dts @@ -82,6 +82,7 @@ }; &uart2 { + u-boot,dm-pre-reloc; status = "okay"; }; -- cgit v1.2.3 From 579a1684663c6c7d440aead9b16525ae72fca8c8 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 29 Mar 2019 22:48:24 +0800 Subject: rockchip: rk3368: support UART2/4 in board_debug_uart_init() evb-rk3368 is using UART2 and PX5 evb is using UART4 Signed-off-by: Kever Yang Tested-by: Andy Yan --- arch/arm/mach-rockchip/rk3368/rk3368.c | 40 ++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index 1ed06c5352..f06d27717d 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -124,6 +124,46 @@ void board_debug_uart_init(void) GPIO2D0_MASK, GPIO2D0_UART0_SIN); rk_clrsetreg(&grf->gpio2d_iomux, GPIO2D1_MASK, GPIO2D1_UART0_SOUT); +#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1c0000) + struct rk3368_pmu_grf * const pmugrf __maybe_unused = + (struct rk3368_pmu_grf * const)0xff738000; + + enum { + /* UART4 */ + GPIO0D2_MASK = GENMASK(5, 4), + GPIO0D2_GPIO = 0, + GPIO0D2_UART4_SOUT = (3 << 4), + + GPIO0D3_MASK = GENMASK(7, 6), + GPIO0D3_GPIO = 0, + GPIO0D3_UART4_SIN = (3 << 6), + }; + + /* Enable early UART4 on the PX5 */ + rk_clrsetreg(&pmugrf->gpio0d_iomux, + GPIO0D2_MASK | GPIO0D3_MASK, + GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN); +#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000) + struct rk3368_grf * const grf = + (struct rk3368_grf * const)0xff770000; + + enum { + GPIO2A6_SHIFT = 12, + GPIO2A6_MASK = GENMASK(13, 12), + GPIO2A6_GPIO = 0, + GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT), + + GPIO2A5_SHIFT = 10, + GPIO2A5_MASK = GENMASK(11, 10), + GPIO2A5_GPIO = 0, + GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT), + }; + + /* Enable early UART2 on the RK3368 */ + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A6_MASK, GPIO2A6_UART2_SIN); + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A5_MASK, GPIO2A5_UART2_SOUT); #endif } #endif -- cgit v1.2.3 From 4d9dd40d68e4d1fbe170ade90e36753ff259ffca Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 29 Mar 2019 22:48:25 +0800 Subject: rockchip: px5 update dts for spl/tpl TPL need dmc to init ddr sdram, and emmc, boot-order. Signed-off-by: Kever Yang Tested-by: Andy Yan --- arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi index 7495781454..18b841864c 100644 --- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi @@ -2,6 +2,27 @@ /* * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ +/ { + chosen { + u-boot,spl-boot-order = &emmc; + }; +}; + +&dmc { + u-boot,dm-pre-reloc; + + /* + * PX5-evb(2GB) need to use CBRD mode, or else the dram is not correct + * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for + * details on the 'rockchip,memory-schedule' property and how it + * affects the physical-address to device-address mapping. + */ + rockchip,memory-schedule = ; + rockchip,ddr-frequency = <800000000>; + rockchip,ddr-speed-bin = ; + + status = "okay"; +}; &pinctrl { u-boot,dm-pre-reloc; @@ -20,6 +41,10 @@ u-boot,dm-pre-reloc; }; +&sgrf { + u-boot,dm-pre-reloc; +}; + &cru { u-boot,dm-pre-reloc; }; @@ -31,3 +56,7 @@ &uart4 { u-boot,dm-pre-reloc; }; + +&emmc { + u-boot,dm-pre-reloc; +}; -- cgit v1.2.3 From 6b780e441b807f7340e6b2f250f40c9f19e02355 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 29 Mar 2019 22:48:28 +0800 Subject: rockchip: boot0: update CONFIG_ROCKCHIP_SPL_RESERVE_IRAM for SPL only The CONFIG_ROCKCHIP_SPL_RESERVE_IRAM is for SPL only, add condition to limit it not affect TPL. Signed-off-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/boot0.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h index 9ea4708ada..0c375e543a 100644 --- a/arch/arm/include/asm/arch-rockchip/boot0.h +++ b/arch/arm/include/asm/arch-rockchip/boot0.h @@ -54,6 +54,7 @@ _start: ARM_VECTORS #endif -#if defined(CONFIG_SPL_BUILD) && (CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0) +#if !defined(CONFIG_TPL_BUILD) && defined(CONFIG_SPL_BUILD) && \ + (CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0) .space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */ #endif -- cgit v1.2.3 From 6459e7f5880f48f38b64989b166bde44f150e465 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 29 Mar 2019 22:48:30 +0800 Subject: rockchip: rk3368: remove uart iomux init in SPL The iomux should have been set in board_debug_uart_init(), do not set in board_init_f(), remove it. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3368-board-spl.c | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c index b055ed4aee..c651193712 100644 --- a/arch/arm/mach-rockchip/rk3368-board-spl.c +++ b/arch/arm/mach-rockchip/rk3368-board-spl.c @@ -10,11 +10,9 @@ #include #include #include -#include void board_init_f(ulong dummy) { - struct udevice *pinctrl; struct udevice *dev; int ret; @@ -24,19 +22,6 @@ void board_init_f(ulong dummy) hang(); } - /* Set up our preloader console */ - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - pr_err("%s: pinctrl init failed: %d\n", __func__, ret); - hang(); - } - - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0); - if (ret) { - pr_err("%s: failed to set up console UART\n", __func__); - hang(); - } - preloader_console_init(); ret = uclass_get_device(UCLASS_RAM, 0, &dev); -- cgit v1.2.3 From 615e9b3ccef450cb03a2346a4e505bf6dd2944e5 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 29 Mar 2019 22:48:31 +0800 Subject: rockchip: px5: add timer0 dts node as tick timer Let's use rockchip timer before stimer patches can be merged. Signed-off-by: Kever Yang --- arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi index 18b841864c..f5406d4c7e 100644 --- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi @@ -5,6 +5,7 @@ / { chosen { u-boot,spl-boot-order = &emmc; + tick-timer = "/timer@ff810000"; }; }; @@ -60,3 +61,9 @@ &emmc { u-boot,dm-pre-reloc; }; + +&timer0 { + u-boot,dm-pre-reloc; + clock-frequency = <24000000>; + status = "okay"; +}; -- cgit v1.2.3 From 3cbec0ad090f11006415b191f4a25367f82255c3 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Mon, 1 Apr 2019 17:15:53 +0800 Subject: rockchip: add u-boot-tpl-v8.lds We don't have both sram and sdram in TPL, so update from: arch/arm/cpu/armv8/u-boot-spl.lds Signed-off-by: Kever Yang Reviewed-by: Simon Glass --- arch/arm/mach-rockchip/u-boot-tpl-v8.lds | 94 ++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 arch/arm/mach-rockchip/u-boot-tpl-v8.lds (limited to 'arch/arm') diff --git a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds new file mode 100644 index 0000000000..9869972e22 --- /dev/null +++ b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 + * Rockchip Electronics Co., Ltd + * Kever Yang + * + * (C) Copyright 2013 + * David Feng + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2010 + * Texas Instruments, + * Aneesh V + */ + +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + .text : { + . = ALIGN(8); + *(.__image_copy_start) + CPUDIR/start.o (.text*) + *(.text*) + } + + .rodata : { + . = ALIGN(8); + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + .data : { + . = ALIGN(8); + *(.data*) + } + + .u_boot_list : { + . = ALIGN(8); + KEEP(*(SORT(.u_boot_list*))); + } + + .image_copy_end : { + . = ALIGN(8); + *(.__image_copy_end) + } + + .end : { + . = ALIGN(8); + *(.__end) + } + + _image_binary_end = .; + + .bss_start (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.__bss_start)); + } + + .bss (NOLOAD) : { + *(.bss*) + . = ALIGN(8); + } + + .bss_end (NOLOAD) : { + KEEP(*(.__bss_end)); + } + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} + +#if defined(CONFIG_TPL_MAX_SIZE) +ASSERT(__image_copy_end - __image_copy_start < (CONFIG_TPL_MAX_SIZE), \ + "TPL image too big"); +#endif + +#if defined(CONFIG_TPL_BSS_MAX_SIZE) +ASSERT(__bss_end - __bss_start < (CONFIG_TPL_BSS_MAX_SIZE), \ + "TPL image BSS too big"); +#endif + +#if defined(CONFIG_TPL_MAX_FOOTPRINT) +ASSERT(__bss_end - _start < (CONFIG_TPL_MAX_FOOTPRINT), \ + "TPL image plus BSS too big"); +#endif -- cgit v1.2.3 From 6bbf5e1a9480004139f543c4717bf95f22b1b5b3 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 9 Nov 2018 11:18:15 +0800 Subject: rockchip: rk3399: add tpl support Rockchip platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size. This patch add rk3399-board-tpl.c and its common configs. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 34 ++++++++++++- arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3399-board-tpl.c | 84 +++++++++++++++++++++++++++++++ include/configs/rk3399_common.h | 8 +++ 4 files changed, 126 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-rockchip/rk3399-board-tpl.c (limited to 'arch/arm') diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 48e364e127..f5c3329750 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -154,12 +154,28 @@ config ROCKCHIP_RK3399 bool "Support Rockchip RK3399" select ARM64 select SUPPORT_SPL + select SUPPORT_TPL select SPL + select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL + select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_SEPARATE_BSS select SPL_SERIAL_SUPPORT select SPL_DRIVERS_MISC_SUPPORT select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER + imply TPL_SERIAL_SUPPORT + imply TPL_LIBCOMMON_SUPPORT + imply TPL_LIBGENERIC_SUPPORT + imply TPL_SYS_MALLOC_SIMPLE + imply TPL_BOOTROM_SUPPORT + imply TPL_DRIVERS_MISC_SUPPORT + imply TPL_OF_CONTROL + imply TPL_DM + imply TPL_REGMAP + imply TPL_SYSCON + imply TPL_RAM + imply TPL_CLK + imply TPL_TINY_MEMSET help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. @@ -168,6 +184,22 @@ config ROCKCHIP_RK3399 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +if ROCKCHIP_RK3399 + +config TPL_LDSCRIPT + default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" + +config TPL_TEXT_BASE + default 0xff8c2000 + +config TPL_MAX_SIZE + default 188416 + +config TPL_STACK + default 0xff8effff + +endif + config ROCKCHIP_RV1108 bool "Support Rockchip RV1108" select CPU_V7A @@ -195,7 +227,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM config TPL_ROCKCHIP_BACK_TO_BROM bool "TPL returns to bootrom" - default y if ROCKCHIP_RK3368 + default y select ROCKCHIP_BROM_HELPER depends on TPL help diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index fd62a693fe..846c82d70a 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -12,6 +12,7 @@ obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-tpl.o +obj-tpl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o diff --git a/arch/arm/mach-rockchip/rk3399-board-tpl.c b/arch/arm/mach-rockchip/rk3399-board-tpl.c new file mode 100644 index 0000000000..86d3ffe97c --- /dev/null +++ b/arch/arm/mach-rockchip/rk3399-board-tpl.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include +#include + +#define TIMER_CHN10_BASE 0xff8680a0 +#define TIMER_END_COUNT_L 0x00 +#define TIMER_END_COUNT_H 0x04 +#define TIMER_INIT_COUNT_L 0x10 +#define TIMER_INIT_COUNT_H 0x14 +#define TIMER_CONTROL_REG 0x1c + +#define TIMER_EN 0x1 +#define TIMER_FMODE (0 << 1) +#define TIMER_RMODE (1 << 1) + +void secure_timer_init(void) +{ + writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L); + writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H); + writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L); + writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H); + writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + printascii("U-Boot TPL board init\n"); +#endif + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + secure_timer_init(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + pr_err("DRAM init failed: %d\n", ret); + return; + } +} + +void board_return_to_bootrom(void) +{ + back_to_bootrom(BROM_BOOT_NEXTSTAGE); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOOTROM; +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index e7ae2c4640..f31f2658bb 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -18,11 +18,19 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_MAX_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x00400000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 +#else #define CONFIG_SPL_STACK 0xff8effff #define CONFIG_SPL_MAX_SIZE 0x30000 - 0x2000 /* BSS setup */ #define CONFIG_SPL_BSS_START_ADDR 0xff8e0000 #define CONFIG_SPL_BSS_MAX_SIZE 0x10000 +#endif #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ -- cgit v1.2.3 From ec107f04b6198933287e85041ff804dd00c11fa3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 26 Apr 2019 19:03:39 -0600 Subject: rockchip: chromebook_minnie: Enable sound Enable sound for this board, which has the same codec as jerry. Signed-off-by: Simon Glass Signed-off-by: Kever Yang --- arch/arm/dts/rk3288-veyron-minnie.dts | 12 ++++++++++++ configs/chromebook_minnie_defconfig | 5 +++++ 2 files changed, 17 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/rk3288-veyron-minnie.dts b/arch/arm/dts/rk3288-veyron-minnie.dts index 0a2915fba0..646f6ae742 100644 --- a/arch/arm/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/dts/rk3288-veyron-minnie.dts @@ -85,6 +85,18 @@ regulator-boot-on; vin-supply = <&vcc18_wl>; }; + + sound { + compatible = "rockchip,audio-max98090-jerry"; + + cpu { + sound-dai = <&i2s 0>; + }; + + codec { + sound-dai = <&max98090 0>; + }; + }; }; &backlight { diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 216f5dcf90..17c1ea6453 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -32,6 +32,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_SOUND=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set @@ -74,6 +75,10 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SOUND=y +CONFIG_I2S=y +CONFIG_I2S_ROCKCHIP=y +CONFIG_SOUND_MAX98090=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y -- cgit v1.2.3 From 82d08de9c5dba1b5dd0689570c74698aae307599 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 7 May 2019 23:51:49 +0530 Subject: dts: Makefile: Build rockchip dtbs based on SoC types - Sometimes u-boot specific dtsi files are included automatically which would build for entire rockchip SoC, even-though the respective dtsi should used it for specific family of rockchip SoC. - Sometimes u-boot specific dts nodes or properties can use config macros from respective rockchip family include/configs files, example CONFIG_SPL_PAD_TO. So, it's better to compile the dtbs based on the respective rockchip family types rather than rockchip itself to avoid compilation issues. This patch organize the existing dtb's based on the rockchip family types. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 35 ++++++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a199f3f988..b76e0ba726 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -65,16 +65,23 @@ dtb-$(CONFIG_KIRKWOOD) += \ dtb-$(CONFIG_ARCH_OWL) += \ bubblegum_96.dtb -dtb-$(CONFIG_ARCH_ROCKCHIP) += \ - rk3036-sdk.dtb \ - rk3128-evb.dtb \ - rk3188-radxarock.dtb \ - rk3229-evb.dtb \ +dtb-$(CONFIG_ROCKCHIP_RK3036) += \ + rk3036-sdk.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3128) += \ + rk3128-evb.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3188) += \ + rk3188-radxarock.dtb + +dtb-$(CONFIG_ROCKCHIP_RK322X) += \ + rk3229-evb.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-evb.dtb \ rk3288-fennec.dtb \ rk3288-firefly.dtb \ rk3288-miqi.dtb \ - rk3399-orangepi.dtb \ rk3288-phycore-rdk.dtb \ rk3288-popmetal.dtb \ rk3288-rock2-square.dtb \ @@ -83,22 +90,32 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-mickey.dtb \ rk3288-veyron-minnie.dtb \ rk3288-veyron-speedy.dtb \ - rk3288-vyasa.dtb \ - rk3328-evb.dtb \ - rk3399-ficus.dtb \ + rk3288-vyasa.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3328) += \ + rk3328-evb.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-lion.dtb \ rk3368-sheep.dtb \ rk3368-geekbox.dtb \ rk3368-px5-evb.dtb \ + +dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-evb.dtb \ + rk3399-ficus.dtb \ rk3399-firefly.dtb \ rk3399-gru-bob.dtb \ + rk3399-orangepi.dtb \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \ rk3399-puma-ddr1866.dtb \ rk3399-rock960.dtb \ + +dtb-$(CONFIG_ROCKCHIP_RV1108) += \ rv1108-elgin-r1.dtb \ rv1108-evb.dtb + dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-nanopi-k2.dtb \ meson-gxbb-odroidc2.dtb \ -- cgit v1.2.3 From ddf49cbf35c97d043c46e9bc9c3029053720a812 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 7 May 2019 23:51:50 +0530 Subject: arm64: rockchip: dts: rk3399: Add board -u-boot.dtsi files Devicetree files in RK3399 platform is synced from Linux, like other platforms does. Apart from these u-boot in rk3399 would also require some u-boot specific node like dmc. dmc node has big chunk of DDR timing parameters which are specific to specific board, and maintained with rk3399-sdram*.dtsi. So, create board specific -u-boot.dtsi files and move these sdram dtsi files accordingly. This would help of maintain u-boot specific changes separately without touching Linux dts(i) files which indeed easy for syncing from Linux between releases. These board specific -u-boot.dtsi can be extendible to add more u-boot specific nodes or properties in future. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-evb-u-boot.dtsi | 6 ++++++ arch/arm/dts/rk3399-evb.dts | 1 - arch/arm/dts/rk3399-ficus-u-boot.dtsi | 6 ++++++ arch/arm/dts/rk3399-ficus.dts | 1 - arch/arm/dts/rk3399-firefly-u-boot.dtsi | 6 ++++++ arch/arm/dts/rk3399-firefly.dts | 1 - arch/arm/dts/rk3399-gru-bob-u-boot.dtsi | 6 ++++++ arch/arm/dts/rk3399-gru-bob.dts | 1 - arch/arm/dts/rk3399-rock960-u-boot.dtsi | 6 ++++++ arch/arm/dts/rk3399-rock960.dts | 1 - 10 files changed, 30 insertions(+), 5 deletions(-) create mode 100644 arch/arm/dts/rk3399-evb-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-ficus-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-firefly-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-gru-bob-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rock960-u-boot.dtsi (limited to 'arch/arm') diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi new file mode 100644 index 0000000000..7e2c57af22 --- /dev/null +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399-sdram-lpddr3-4GB-1600.dtsi" diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index 9162f3dd50..a506e8da37 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -7,7 +7,6 @@ #include #include #include "rk3399.dtsi" -#include "rk3399-sdram-lpddr3-4GB-1600.dtsi" / { model = "Rockchip RK3399 Evaluation Board"; diff --git a/arch/arm/dts/rk3399-ficus-u-boot.dtsi b/arch/arm/dts/rk3399-ficus-u-boot.dtsi new file mode 100644 index 0000000000..eab86bdb30 --- /dev/null +++ b/arch/arm/dts/rk3399-ficus-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399-sdram-ddr3-1600.dtsi" diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts index 4af0e4e383..4b2dd82b67 100644 --- a/arch/arm/dts/rk3399-ficus.dts +++ b/arch/arm/dts/rk3399-ficus.dts @@ -8,7 +8,6 @@ /dts-v1/; #include "rk3399-rock960.dtsi" -#include "rk3399-sdram-ddr3-1600.dtsi" / { model = "96boards RK3399 Ficus"; diff --git a/arch/arm/dts/rk3399-firefly-u-boot.dtsi b/arch/arm/dts/rk3399-firefly-u-boot.dtsi new file mode 100644 index 0000000000..eab86bdb30 --- /dev/null +++ b/arch/arm/dts/rk3399-firefly-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399-sdram-ddr3-1600.dtsi" diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts index 46f2ffaf8d..a4cb64f8bd 100644 --- a/arch/arm/dts/rk3399-firefly.dts +++ b/arch/arm/dts/rk3399-firefly.dts @@ -7,7 +7,6 @@ #include #include #include "rk3399.dtsi" -#include "rk3399-sdram-ddr3-1600.dtsi" / { model = "Firefly-RK3399 Board"; diff --git a/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi b/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi new file mode 100644 index 0000000000..9edb8cf841 --- /dev/null +++ b/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" diff --git a/arch/arm/dts/rk3399-gru-bob.dts b/arch/arm/dts/rk3399-gru-bob.dts index 0e3d91fc28..1ee0dc0d9f 100644 --- a/arch/arm/dts/rk3399-gru-bob.dts +++ b/arch/arm/dts/rk3399-gru-bob.dts @@ -7,7 +7,6 @@ /dts-v1/; #include "rk3399-gru-chromebook.dtsi" -#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" / { model = "Google Bob"; diff --git a/arch/arm/dts/rk3399-rock960-u-boot.dtsi b/arch/arm/dts/rk3399-rock960-u-boot.dtsi new file mode 100644 index 0000000000..5256f6d3f2 --- /dev/null +++ b/arch/arm/dts/rk3399-rock960-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399-sdram-lpddr3-2GB-1600.dtsi" diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts index 25c58b4261..7e06bc97e5 100644 --- a/arch/arm/dts/rk3399-rock960.dts +++ b/arch/arm/dts/rk3399-rock960.dts @@ -5,7 +5,6 @@ /dts-v1/; #include "rk3399-rock960.dtsi" -#include "rk3399-sdram-lpddr3-2GB-1600.dtsi" / { model = "96boards Rock960"; -- cgit v1.2.3 From b5f88913a661a668ae6da1e7c82bc9e654347ce5 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 7 May 2019 23:51:51 +0530 Subject: rockchip: dts: rk3399-u-boot: Add u-boot, dm-pre-reloc for spi1 Add u-boot,dm-pre-reloc property for spi1, so-that the subsequent rk3399 boards which boot from SPI. This help to separate the u-boot specific properties away from base dts files so-that the Linux sync become easy and meaningful. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index f533ed95eb..0786c1193a 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -6,3 +6,7 @@ &sdmmc { u-boot,dm-pre-reloc; }; + +&spi1 { + u-boot,dm-pre-reloc; +}; -- cgit v1.2.3 From 90430fa895a197206da93a601607809998dc5a74 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 7 May 2019 23:51:52 +0530 Subject: arm64: rockchip: dts: rk3399: Use rk3399-u-boot.dtsi Now we have - board specific -u-boot.dtsi files for board specific u-boot dts changes. - soc specific rk3399-u-boot.dtsi for soc specific u-boot dts changes. So, include the rk3399-u-boot-dtsi on respective board -u-boot.dtsi and drop the properties which are globally available in rk3399-u-boot.dtsi Right now rk3399-u-boot.dtsi has sdmmc, spi1 u-boot,dm-pre-reloc property and more properties and nodes can be move further based on the requirements. This would fix, the -u-boot.dtsi inclusion for evb, firefly, puma boards that was accidentally merged on below commit. "rockchip: dts: rk3399: Create initial rk3399-u-boot.dtsi" (sha1: e05b4a4fa84b65a0c8873e8f34721741fe2bc09d) Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-evb-u-boot.dtsi | 1 + arch/arm/dts/rk3399-firefly-u-boot.dtsi | 1 + arch/arm/dts/rk3399-gru-bob-u-boot.dtsi | 1 + arch/arm/dts/rk3399-gru-u-boot.dtsi | 6 ++++++ arch/arm/dts/rk3399-gru.dtsi | 1 - arch/arm/dts/rk3399-puma-ddr1600.dts | 1 + arch/arm/dts/rk3399-puma.dtsi | 2 -- 7 files changed, 10 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/rk3399-gru-u-boot.dtsi (limited to 'arch/arm') diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi index 7e2c57af22..20910e744b 100644 --- a/arch/arm/dts/rk3399-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi @@ -3,4 +3,5 @@ * Copyright (C) 2019 Jagan Teki */ +#include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr3-4GB-1600.dtsi" diff --git a/arch/arm/dts/rk3399-firefly-u-boot.dtsi b/arch/arm/dts/rk3399-firefly-u-boot.dtsi index eab86bdb30..67b63a8352 100644 --- a/arch/arm/dts/rk3399-firefly-u-boot.dtsi +++ b/arch/arm/dts/rk3399-firefly-u-boot.dtsi @@ -3,4 +3,5 @@ * Copyright (C) 2019 Jagan Teki */ +#include "rk3399-u-boot.dtsi" #include "rk3399-sdram-ddr3-1600.dtsi" diff --git a/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi b/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi index 9edb8cf841..726f396f32 100644 --- a/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi @@ -3,4 +3,5 @@ * Copyright (C) 2019 Jagan Teki */ +#include "rk3399-gru-u-boot.dtsi" #include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi new file mode 100644 index 0000000000..7bddc3acdb --- /dev/null +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399-u-boot.dtsi" diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi index 4cdb4320b7..ca0fc391b2 100644 --- a/arch/arm/dts/rk3399-gru.dtsi +++ b/arch/arm/dts/rk3399-gru.dtsi @@ -545,7 +545,6 @@ ap_i2c_audio: &i2c8 { &spi1 { status = "okay"; - u-boot,dm-pre-reloc; pinctrl-names = "default", "sleep"; pinctrl-1 = <&spi1_sleep>; diff --git a/arch/arm/dts/rk3399-puma-ddr1600.dts b/arch/arm/dts/rk3399-puma-ddr1600.dts index 337e0eabb4..42763f82d0 100644 --- a/arch/arm/dts/rk3399-puma-ddr1600.dts +++ b/arch/arm/dts/rk3399-puma-ddr1600.dts @@ -6,5 +6,6 @@ /dts-v1/; #include "rk3399-puma.dtsi" +#include "rk3399-u-boot.dtsi" #include "rk3399-sdram-ddr3-1600.dtsi" diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index 319a610022..897e0bda85 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -647,8 +647,6 @@ &spi1 { - u-boot,dm-pre-reloc; - status = "okay"; #address-cells = <1>; -- cgit v1.2.3 From e0bca2821f63fc5566cc2d74710beaa51e7ccd33 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 8 May 2019 11:11:41 +0530 Subject: rockchip: dts: rk3399: Sync pwm2_pin_pull_down from Linux 5.1-rc2 To make successful build with dts(i) files syncing from Linux 5.1-rc2 the rk3399.dtsi would require pwm2_pin_pull_down. So, sync the pwm2_pin_pull_down node from Linux 5.1-rc2. Since this node is strictly not part of any commit alone, I have mentioned Linux 5.1-rc2 tag for future reference of where would this sync coming from. Signed-off-by: Jagan Teki Reviewed-by: Paul Kocialkowski Reviewed-by: Kever Yang --- arch/arm/dts/rk3399.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index b53e41b4dc..b73442ee34 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -2495,6 +2495,11 @@ rockchip,pins = <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; }; + + pwm2_pin_pull_down: pwm2-pin-pull-down { + rockchip,pins = + <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>; + }; }; pwm3a { -- cgit v1.2.3 From 2666bd42c6ebac995dc65cf31512e26c26b59599 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 8 May 2019 11:11:43 +0530 Subject: arm: rockchip: rk3399: Move common configs in Kconfig Few SPL and U-Boot proper configs are common to all rk3399 target defconfigs, move them and select it from platform kconfig. Moved configs: - SPL_ATF - SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF - SPL_LOAD_FIT - SPL_CLK if SPL - SPL_PINCTRL if SPL - SPL_RAM if SPL - SPL_REGMAP if SPL - SPL_SYSCON if SPL - CLK - FIT - PINCTRL - RAM - REGMAP - SYSCON - DM_PMIC - DM_REGULATOR_FIXED Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 16 ++++++++++++++++ configs/chromebook_bob_defconfig | 16 ---------------- configs/evb-rk3399_defconfig | 16 ---------------- configs/ficus-rk3399_defconfig | 16 ---------------- configs/firefly-rk3399_defconfig | 16 ---------------- configs/orangepi-rk3399_defconfig | 16 ---------------- configs/puma-rk3399_defconfig | 16 ---------------- configs/rock960-rk3399_defconfig | 16 ---------------- 8 files changed, 16 insertions(+), 112 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index f5c3329750..c05e3c3f48 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -156,11 +156,27 @@ config ROCKCHIP_RK3399 select SUPPORT_SPL select SUPPORT_TPL select SPL + select SPL_ATF + select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF + select SPL_LOAD_FIT + select SPL_CLK if SPL + select SPL_PINCTRL if SPL + select SPL_RAM if SPL + select SPL_REGMAP if SPL + select SPL_SYSCON if SPL select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_SEPARATE_BSS select SPL_SERIAL_SUPPORT select SPL_DRIVERS_MISC_SUPPORT + select CLK + select FIT + select PINCTRL + select RAM + select REGMAP + select SYSCON + select DM_PMIC + select DM_REGULATOR_FIXED select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER imply TPL_SERIAL_SUPPORT diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index bd836acad5..e61e27c992 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -17,8 +17,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -26,8 +24,6 @@ CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -46,12 +42,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-bob" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -71,16 +61,10 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 94963e4280..f10502cb0e 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -11,15 +11,11 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y @@ -33,12 +29,6 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -48,16 +38,10 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 926d244fbe..6a1b279cc9 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -11,15 +11,11 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -32,12 +28,6 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -49,17 +39,11 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 5016fb8993..61f05b784f 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -11,15 +11,11 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y @@ -32,12 +28,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -48,16 +38,10 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 22ddd8dce3..3f02c89983 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -11,16 +11,12 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -32,12 +28,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -47,16 +37,10 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 964464ac0f..03f0bfdb59 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -15,8 +15,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/puma_rk3399/fit_spl_atf.its" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_MISC_INIT_R=y @@ -32,8 +30,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -52,12 +48,6 @@ CONFIG_OF_LIVE=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-ddr1600" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y @@ -76,20 +66,14 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_DM_RTC=y CONFIG_RTC_ISL1208=y CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 48d14ef7d8..1958b7e190 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -11,16 +11,12 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_SYS_PROMPT="rock960 => " CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y @@ -33,12 +29,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -46,16 +36,10 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y -- cgit v1.2.3 From d364e6bdd7ca9eb94dd03cf54c5d8472cf1850dd Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 8 May 2019 11:11:44 +0530 Subject: rockchip: dts: rk3399: Sync rk3399-nanopi4.dtsi from Linux Sync rk3399-nanopi4.dtsi from Linux 5.1-rc2 tag. Linux commit details about the rk3399-nanopi4.dtsi sync: "arm64: dts: rockchip: Add nanopi4 bluetooth" (sha1: 3e2f0bb72be36aa6c14ee7f11ac4dd8014801030) Signed-off-by: Jagan Teki Reviewed-by: Paul Kocialkowski Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-nanopi4.dtsi | 703 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 703 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi4.dtsi (limited to 'arch/arm') diff --git a/arch/arm/dts/rk3399-nanopi4.dtsi b/arch/arm/dts/rk3399-nanopi4.dtsi new file mode 100644 index 0000000000..d325e11728 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi4.dtsi @@ -0,0 +1,703 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RK3399-based FriendlyElec boards device tree source + * + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2019 Arm Ltd. + */ + +/dts-v1/; +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_sys"; + vin-supply = <&vdd_5v>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_s3"; + vin-supply = <&vcc_1v8>; + }; + + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_sd"; + vin-supply = <&vcc3v3_sys>; + }; + + vbus_typec: vbus-typec { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vbus_typec"; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&power_key>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_gpio>; + + status { + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clock-parents = <&clkin_gmac>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-supply = <&vcc3v3_s3>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c7>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&cpu_b_sleep>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_cpu_b"; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gpu_sleep>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_gpu"; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + clock-output-names = "xin32k", "rtc_clko_wifi"; + #clock-cells = <1>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_center"; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_cpu_l"; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_cam: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_cam"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_touch: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_touch"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmupll: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmupll"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <3000000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_sdio"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcca3v0_codec"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <200000>; + i2c-scl-rising-time-ns = <150>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; + + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vbus_typec>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&io_domains { + bt656-supply = <&vcc_1v8>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sdio>; + gpio1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pcie_phy { + assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; + assigned-clock-rates = <100000000>; + assigned-clocks = <&cru SCLK_PCIEPHY_REF>; + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; + max-link-speed = <2>; + num-lanes = <4>; + status = "okay"; +}; + +&pinctrl { + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + leds_gpio: leds-gpio { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + cpu_b_sleep: cpu-b-sleep { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + gpu_sleep: gpu-sleep { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rockchip-key { + power_key: power-key { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio { + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reg_on_h: bt-reg-on-h { + /* external pullup to VCC1V8_PMUPLL */ + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_reg_on_h: wifi-reg_on-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc0_det_l: sdmmc0-det-l { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin_pull_down>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_host { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_host { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <4000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; -- cgit v1.2.3 From adc91db0e6f83653da06066bc60633d7a437bcbd Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 8 May 2019 11:11:45 +0530 Subject: rockchip: dts: rk3399: nanopi4: Use CD pin as RK_FUNC_1 Attaching GPIO functionality to SDMMC0_DET pin (which does in Linux base dts) make dwmmc driver "fail to detect the card". Card did not respond to voltage select! It may be because the existing driver can't support gpio card detection. So, change the pinctrl functionality from RK_FUNC_GPIO to RK_FUNC_1 like other rk3399 dts does via sdmmc_cd pin. Cc: Robin Murphy Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi4-u-boot.dtsi (limited to 'arch/arm') diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi new file mode 100644 index 0000000000..bb8bdf08c5 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +&sdmmc { + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; +}; -- cgit v1.2.3 From b2f5da9dd0689a718bf0c9dbfa48fedfce0bb336 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 8 May 2019 11:11:46 +0530 Subject: rockchip: rk3399: Add Nanopi M4 board support Add initial support for Nanopi M4 board. Specification - Rockchip RK3399 - Dual-Channel 4GB LPDDR3-1866 - SD card slot - eMMC socket - RTL8211E 1Gbps - AP6356S WiFI/BT - HDMI In/Out, DP, MIPI DSI/CSI - USB 3.0 x4 - USB Type C power and data - GPIO1, GPIO2 expansion ports - DC5V/3A Commit details of rk3399-nanopi-m4.dts sync from Linux 5.1-rc2: "arm64: dts: rockchip: Refine nanopi4 differences" (sha1: c62ffaf5026d0b7633e62b2cea8450b5543c349a) Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Reviewed-by: Philipp Tomsich --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi | 7 ++++ arch/arm/dts/rk3399-nanopi-m4.dts | 66 +++++++++++++++++++++++++++++++ arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 2 + board/rockchip/evb_rk3399/MAINTAINERS | 6 +++ configs/nanopi-m4-rk3399_defconfig | 59 +++++++++++++++++++++++++++ 6 files changed, 141 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-m4.dts create mode 100644 configs/nanopi-m4-rk3399_defconfig (limited to 'arch/arm') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b76e0ba726..c77e7631d0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-ficus.dtb \ rk3399-firefly.dtb \ rk3399-gru-bob.dtb \ + rk3399-nanopi-m4.dtb \ rk3399-orangepi.dtb \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \ diff --git a/arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi new file mode 100644 index 0000000000..17201bcf41 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" diff --git a/arch/arm/dts/rk3399-nanopi-m4.dts b/arch/arm/dts/rk3399-nanopi-m4.dts new file mode 100644 index 0000000000..60358ab8c7 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-m4.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * FriendlyElec NanoPi M4 board device tree source + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2019 Arm Ltd. + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPi M4"; + compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399"; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_core: vcc5v0-core { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_core"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v>; + }; + + vcc5v0_usb1: vcc5v0-usb1 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb1"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb2: vcc5v0-usb2 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb2"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&vcc3v3_sys { + vin-supply = <&vcc5v0_core>; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_usb1>; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_usb2>; +}; + +&vbus_typec { + regulator-always-on; + vin-supply = <&vdd_5v>; +}; diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi index bb8bdf08c5..a126bbaf08 100644 --- a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2019 Jagan Teki */ +#include "rk3399-u-boot.dtsi" + &sdmmc { pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; }; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 07ee8ce92c..ae43805a6a 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -6,6 +6,12 @@ F: include/configs/evb_rk3399.h F: configs/evb-rk3399_defconfig F: configs/firefly-rk3399_defconfig +NANOPI-M4 +M: Jagan Teki +S: Maintained +F: configs/nanopi-m4-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi + ORANGEPI-RK3399 M: Jagan Teki S: Maintained diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig new file mode 100644 index 0000000000..c2832788f0 --- /dev/null +++ b/configs/nanopi-m4-rk3399_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_TEXT_BASE=0xff8c2000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y -- cgit v1.2.3 From 65cc7dcd77aef48ed20d73d17367e32f5cc4e8dd Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 8 May 2019 11:11:47 +0530 Subject: rockchip: rk3399: Add Nanopc T4 board support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add initial support for Nanopc T4 board. Specification - Rockchip RK3399 - Dual-Channel 4GB LPDDR3-1866 - SD card slot - 16GB eMMC - RTL8211E 1Gbps - AP6356S WiFI/BT - HDMI In/Out, DP, MIPI DSI/CSI, eDP - USB 3.0, 2.0 - USB Type C power and data - GPIO expansion ports - DC 12V/2A Commit details of rk3399-nanopc-t4.dts sync from Linux 5.1-rc2: "arm64: dts: rockchip: Add NanoPC-T4 IR receiver" (sha1: 95658e21b1707ad7844f873db2fdaa295109a5a3) Tested-by: Daniel Gröber Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi | 7 +++ arch/arm/dts/rk3399-nanopc-t4.dts | 91 +++++++++++++++++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 6 ++ configs/nanopc-t4-rk3399_defconfig | 59 ++++++++++++++++++++ 5 files changed, 164 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopc-t4.dts create mode 100644 configs/nanopc-t4-rk3399_defconfig (limited to 'arch/arm') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c77e7631d0..75d4fda73e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-ficus.dtb \ rk3399-firefly.dtb \ rk3399-gru-bob.dtb \ + rk3399-nanopc-t4.dtb \ rk3399-nanopi-m4.dtb \ rk3399-orangepi.dtb \ rk3399-puma-ddr1333.dtb \ diff --git a/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi new file mode 100644 index 0000000000..17201bcf41 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" diff --git a/arch/arm/dts/rk3399-nanopc-t4.dts b/arch/arm/dts/rk3399-nanopc-t4.dts new file mode 100644 index 0000000000..84433cf02b --- /dev/null +++ b/arch/arm/dts/rk3399-nanopc-t4.dts @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * FriendlyElec NanoPC-T4 board device tree source + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPC-T4"; + compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399"; + + vcc12v0_sys: vcc12v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "vcc12v0_sys"; + }; + + vcc5v0_host0: vcc5v0-host0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_host0"; + vin-supply = <&vcc5v0_sys>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <18000>; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_rx>; + }; +}; + +&pinctrl { + ir { + ir_rx: ir-rx { + /* external pullup to VCC3V3_SYS, despite being 1.8V :/ */ + rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; + }; + }; +}; + +&sdhci { + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host0>; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host0>; +}; + +&vcc5v0_sys { + vin-supply = <&vcc12v0_sys>; +}; + +&vcc3v3_sys { + vin-supply = <&vcc12v0_sys>; +}; + +&vbus_typec { + enable-active-high; + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; +}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index ae43805a6a..f55c92f80c 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -6,6 +6,12 @@ F: include/configs/evb_rk3399.h F: configs/evb-rk3399_defconfig F: configs/firefly-rk3399_defconfig +NANOPC-T4 +M: Jagan Teki +S: Maintained +F: configs/nanopc-t4-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi + NANOPI-M4 M: Jagan Teki S: Maintained diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig new file mode 100644 index 0000000000..d9f2137b4c --- /dev/null +++ b/configs/nanopc-t4-rk3399_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_TEXT_BASE=0xff8c2000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopc-t4" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y -- cgit v1.2.3