From 827edf1818db0eb19ae604f8c95996b2112ef242 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 11 Dec 2020 17:06:09 +0100 Subject: mips: octeon: mrvl, cn73xx.dtsi: Add PCIe controller DT node This patch adds the PCIe controller node to the MIPS Octeon 73xx dtsi file. Signed-off-by: Stefan Roese --- arch/mips/dts/mrvl,cn73xx.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/mips/dts') diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi index 27cdfd0a2c..9f3dc615d6 100644 --- a/arch/mips/dts/mrvl,cn73xx.dtsi +++ b/arch/mips/dts/mrvl,cn73xx.dtsi @@ -230,5 +230,21 @@ dr_mode = "host"; }; }; + + /* PCIe 0 */ + pcie0: pcie@1180069000000 { + compatible = "marvell,pcie-host-octeon"; + reg = <0 0xf2600000 0 0x10000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + + bus-range = <0 0xff>; + marvell,pcie-port = <0>; + ranges = <0x81000000 0x00000000 0xd0000000 0x00011a00 0xd0000000 0x00000000 0x01000000 /* IO */ + 0x02000000 0x00000000 0xe0000000 0x00011b00 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ + 0x43000000 0x00011c00 0x00000000 0x00011c00 0x00000000 0x00000010 0x00000000>;/* prefetchable memory */ + }; }; }; -- cgit v1.2.3