From d8b326976a44f185c52255458142086e0e8a7c34 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 21 Nov 2017 11:18:38 -0800 Subject: MIPS: Clear instruction hazards in flush_cache() When writing code, for example during relocation, we ensure that the icache has a coherent view of the new instructions with a call to flush_cache(). This handles the bulk of the work to ensure the new instructions will execute as expected, however it does not ensure that the CPU pipeline doesn't already contain instructions taken from a stale view of the affected memory. This could theoretically be a problem for relocation, but in practice typically isn't because we sync caches for enough code after the entry point of the newly written code that by the time the CPU pipeline might possibly fetch any of it we'll have long ago written it back & invalidated any stale icache entries. This is however a problem for shorter regions of code. In preparation for later patches which write shorter segments of code, ensure any instruction hazards are cleared by flush_cache() by introducing & using a new instruction_hazard_barrier() function which makes use of the jr.hb instruction to clear the hazard. Signed-off-by: Paul Burton Cc: Daniel Schwierzeck Cc: u-boot@lists.denx.de --- arch/mips/include/asm/system.h | 13 +++++++++++++ arch/mips/lib/cache.c | 4 ++++ 2 files changed, 17 insertions(+) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h index c9c5961462..eaf1b2290d 100644 --- a/arch/mips/include/asm/system.h +++ b/arch/mips/include/asm/system.h @@ -14,8 +14,10 @@ #ifndef _ASM_SYSTEM_H #define _ASM_SYSTEM_H +#include #include #include +#include #if 0 #include #endif @@ -270,4 +272,15 @@ static inline void execution_hazard_barrier(void) ".set reorder"); } +static inline void instruction_hazard_barrier(void) +{ + unsigned long tmp; + + asm volatile( + __stringify(PTR_LA) "\t%0, 1f\n" + " jr.hb %0\n" + "1: .insn" + : "=&r"(tmp)); +} + #endif /* _ASM_SYSTEM_H */ diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index eba7fff316..8e5b028c66 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -12,6 +12,7 @@ #endif #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -134,6 +135,9 @@ void flush_cache(ulong start_addr, ulong size) ops_done: /* ensure cache ops complete before any further memory accesses */ sync(); + + /* ensure the pipeline doesn't contain now-invalid instructions */ + instruction_hazard_barrier(); } void flush_dcache_range(ulong start_addr, ulong stop) -- cgit v1.2.3