From 7818499b71d2b5404ddf4b62bf1106710168af9a Mon Sep 17 00:00:00 2001 From: William Qiu Date: Fri, 28 Jul 2023 18:25:21 +0800 Subject: riscv: dts: starfive: limit cclk_in frequency The frequency of cclk_in is limited to 50M, so that it does not do internal part frequency and goes by-pass mode. And delete syscon node. Signed-off-by: William Qiu --- arch/riscv/dts/starfive_evb.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/riscv/dts/starfive_evb.dts') diff --git a/arch/riscv/dts/starfive_evb.dts b/arch/riscv/dts/starfive_evb.dts index 6f865f7094..19b8e5f1e0 100644 --- a/arch/riscv/dts/starfive_evb.dts +++ b/arch/riscv/dts/starfive_evb.dts @@ -246,6 +246,8 @@ }; &sdio0 { + assigned-clocks = <&clkgen JH7110_SDIO0_CLK_SDCARD>; + assigned-clock-rates = <50000000>; fifo-depth = <32>; bus-width = <4>; status = "okay"; -- cgit v1.2.3