From 00018eb98a12f2ebbbd25fcca0d1262939ebc769 Mon Sep 17 00:00:00 2001 From: "yanhong.wang" Date: Sun, 15 May 2022 15:27:22 +0800 Subject: riscv:starfive-jh7110: clear L2 LIM memory Clear L2 LIM memory on StarFive JH7110, avoid some unexpect exception. --- arch/riscv/cpu/jh7110/spl.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/riscv') diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c index cb6ef2fda5..414938bce4 100644 --- a/arch/riscv/cpu/jh7110/spl.c +++ b/arch/riscv/cpu/jh7110/spl.c @@ -42,4 +42,18 @@ void harts_early_init(void) */ if (CONFIG_IS_ENABLED(RISCV_MMODE)) csr_write(CSR_U74_FEATURE_DISABLE, 0); + +#ifdef CONFIG_SPL_BUILD + + /*clear L2 LIM memory + * set __bss_end to 0x81e0000 region to zero + */ + __asm__ __volatile__ ( + "la t1, __bss_end\n" + "li t2, 0x81e0000\n" + "spl_clear_l2im:\n" + "addi t1, t1, 8\n" + "sd zero, 0(t1)\n" + "blt t1, t2, spl_clear_l2im\n"); +#endif } -- cgit v1.2.3