From 76c3fe38884eabb095547ea5fd633855f221a2c5 Mon Sep 17 00:00:00 2001 From: "yanhong.wang" Date: Sat, 14 May 2022 15:32:55 +0800 Subject: clk:starfive-jh7110: Update pll0/pll1/pll2 clk Add JH7110_GMAC0_GTXC clk register and remove pll0/pll1/pll2 clk define from clk-jh7110.c to jh7110_clk.dts Signed-off-by: yanhong.wang --- arch/riscv/dts/jh7110.dtsi | 6 ++++-- arch/riscv/dts/jh7110_clk.dtsi | 19 ++++++++++++++++++- 2 files changed, 22 insertions(+), 3 deletions(-) (limited to 'arch/riscv') diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index a7952031ce..1b570148ef 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -785,12 +785,14 @@ "tx", "ptp_ref", "stmmaceth", - "pclk"; + "pclk", + "gtxc"; clocks = <&clkgen JH7110_GMAC0_GTXCLK>, <&clkgen JH7110_U0_GMAC5_CLK_TX>, <&clkgen JH7110_GMAC0_PTP>, <&clkgen JH7110_U0_GMAC5_CLK_AHB>, - <&clkgen JH7110_U0_GMAC5_CLK_AXI>; + <&clkgen JH7110_U0_GMAC5_CLK_AXI>, + <&clkgen JH7110_GMAC0_GTXC>; resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>, <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>; reset-names = "ahb", "stmmaceth"; diff --git a/arch/riscv/dts/jh7110_clk.dtsi b/arch/riscv/dts/jh7110_clk.dtsi index d67134fa8a..fce9df8419 100644 --- a/arch/riscv/dts/jh7110_clk.dtsi +++ b/arch/riscv/dts/jh7110_clk.dtsi @@ -112,6 +112,23 @@ #clock-cells = <0>; clock-frequency = <297000000>; }; - /* external clocks end */ + + pll0_out: pll0_out { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + }; + + pll1_out: pll1_out { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1066000000>; + }; + + pll2_out: pll2_out { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1228800000>; + }; }; -- cgit v1.2.3