From bd798eed5515ff435642b9b96f759aa0d7f2eb4c Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 29 Jul 2021 20:18:23 +0800 Subject: x86: dts: Add "m25p,fast-read" to SPI flash node Except ICH7 SPI, all SPI flashes connected to ICH9 / Fast SPI should have "m25p,fast-read" property present in their DT nodes. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/dts/bayleybay.dts | 1 + arch/x86/dts/baytrail_som-db5800-som-6867.dts | 1 + arch/x86/dts/cherryhill.dts | 1 + arch/x86/dts/chromebook_coral.dts | 1 + arch/x86/dts/chromebook_link.dts | 1 + arch/x86/dts/chromebook_samus.dts | 1 + arch/x86/dts/chromebox_panther.dts | 1 + arch/x86/dts/conga-qeval20-qa3-e3845.dts | 1 + arch/x86/dts/cougarcanyon2.dts | 1 + arch/x86/dts/dfi-bt700.dtsi | 1 + arch/x86/dts/minnowmax.dts | 1 + 11 files changed, 11 insertions(+) (limited to 'arch/x86') diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 70e5798403..b487bc6655 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -176,6 +176,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0>; + m25p,fast-read; compatible = "winbond,w25q64dw", "jedec,spi-nor"; memory-map = <0xff800000 0x00800000>; diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts index a7dc03b645..9c9b5735d7 100644 --- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts +++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts @@ -200,6 +200,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0>; + m25p,fast-read; compatible = "macronix,mx25l6405d", "jedec,spi-nor"; memory-map = <0xff800000 0x00800000>; diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts index 2ce7f1aa91..54a9e566d1 100644 --- a/arch/x86/dts/cherryhill.dts +++ b/arch/x86/dts/cherryhill.dts @@ -149,6 +149,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0>; + m25p,fast-read; compatible = "macronix,mx25u6435f", "jedec,spi-nor"; memory-map = <0xff800000 0x00800000>; rw-mrc-cache { diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 66c31efb6c..8e98e2d5e0 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -362,6 +362,7 @@ u-boot,dm-pre-proper; u-boot,dm-spl; reg = <0>; + m25p,fast-read; compatible = "winbond,w25q128fw", "jedec,spi-nor"; rw-mrc-cache { diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index e529c4b63e..4f8c65974b 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -430,6 +430,7 @@ #address-cells = <1>; u-boot,dm-pre-reloc; reg = <0>; + m25p,fast-read; compatible = "winbond,w25q64", "jedec,spi-nor"; memory-map = <0xff800000 0x00800000>; diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts index ad35ab2e3f..e624264424 100644 --- a/arch/x86/dts/chromebook_samus.dts +++ b/arch/x86/dts/chromebook_samus.dts @@ -594,6 +594,7 @@ #size-cells = <1>; #address-cells = <1>; reg = <0>; + m25p,fast-read; compatible = "winbond,w25q64", "jedec,spi-nor"; memory-map = <0xff800000 0x00800000>; diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index 77b6ac9ab9..71519ca2cd 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -48,6 +48,7 @@ #size-cells = <1>; #address-cells = <1>; reg = <0>; + m25p,fast-read; compatible = "winbond,w25q64", "jedec,spi-nor"; memory-map = <0xff800000 0x00800000>; diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index bbea99da2c..43fea11eb1 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -187,6 +187,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0>; + m25p,fast-read; compatible = "stmicro,n25q064a", "jedec,spi-nor"; memory-map = <0xff800000 0x00800000>; diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts index 602523333e..94ec111db2 100644 --- a/arch/x86/dts/cougarcanyon2.dts +++ b/arch/x86/dts/cougarcanyon2.dts @@ -156,6 +156,7 @@ spi-flash@0 { reg = <0>; + m25p,fast-read; compatible = "winbond,w25q64bv", "jedec,spi-nor"; memory-map = <0xff800000 0x00800000>; }; diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi index 7d7b8357d9..dff2345d60 100644 --- a/arch/x86/dts/dfi-bt700.dtsi +++ b/arch/x86/dts/dfi-bt700.dtsi @@ -198,6 +198,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0>; + m25p,fast-read; compatible = "stmicro,n25q064a", "jedec,spi-nor"; memory-map = <0xff800000 0x00800000>; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 133d55bc20..aa7718f31c 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -200,6 +200,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0>; + m25p,fast-read; compatible = "stmicro,n25q064a", "jedec,spi-nor"; memory-map = <0xff800000 0x00800000>; -- cgit v1.2.3 From 46db4bbac3287a114ddf941ad3861381b795197b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 30 Jul 2021 23:15:44 +0300 Subject: x86: tangier: Fix DMA controller IRQ polarity in CSRT IRQ polarity in CSRT has the same definition as by ACPI specification chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e. ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller IRQ polarity is ActiveHigh. Note, in DSDT (see southcluster.asl) it's described correctly. Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller") Signed-off-by: Andy Shevchenko Reviewed-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/cpu/tangier/acpi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c index 41bd177e09..82f4ce5a34 100644 --- a/arch/x86/cpu/tangier/acpi.c +++ b/arch/x86/cpu/tangier/acpi.c @@ -89,8 +89,8 @@ static u32 acpi_fill_csrt_dma(struct acpi_csrt_group *grp) si->mmio_base_low = 0xff192000; si->mmio_base_high = 0; si->gsi_interrupt = 32; - si->interrupt_polarity = 1; - si->interrupt_mode = 0; + si->interrupt_polarity = 0; /* Active High */ + si->interrupt_mode = 0; /* Level triggered */ si->num_channels = 8; si->dma_address_width = 32; si->base_request_line = 0; -- cgit v1.2.3 From ffaa7abfc5e930448a3aadb17e5eb00cabb37b9d Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Tue, 27 Jul 2021 23:15:39 +0800 Subject: x86: kconfig: Drop ROM_NEEDS_BLOBS and BUILD_ROM These 2 options are no longer needed as now binman is used to build u-boot.rom. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- Kconfig | 21 --------------------- arch/x86/Kconfig | 2 -- arch/x86/cpu/quark/Kconfig | 1 - doc/arch/x86.rst | 13 ++----------- 4 files changed, 2 insertions(+), 35 deletions(-) (limited to 'arch/x86') diff --git a/Kconfig b/Kconfig index 76c0cdacb0..a6c42b902f 100644 --- a/Kconfig +++ b/Kconfig @@ -343,27 +343,6 @@ config HAS_ROM Enables building of a u-boot.rom target. This collects U-Boot and any necessary binary blobs. -config ROM_NEEDS_BLOBS - bool - depends on HAS_ROM - help - Enable this if building the u-boot.rom target needs binary blobs, and - so cannot be done normally. In this case, U-Boot will only build the - ROM if the required blobs exist. If not, you will see an warning like: - - Image 'main-section' is missing external blobs and is non-functional: - intel-descriptor intel-me intel-refcode intel-vga intel-mrc - -config BUILD_ROM - bool "Build U-Boot as BIOS replacement" - depends on HAS_ROM - default y if !ROM_NEEDS_BLOBS - help - This option allows to build a ROM version of U-Boot. - The build process generally requires several binary blobs - which are not shipped in the U-Boot source tree. - Please, see doc/arch/x86.rst for details. - config SPL_IMAGE string "SPL image used in the combined SPL+U-Boot image" default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 970bdff37f..300b48505e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -364,7 +364,6 @@ config HAVE_FSP depends on !EFI select USE_HOB select HAS_ROM - select ROM_NEEDS_BLOBS help Select this option to add an Firmware Support Package binary to the resulting U-Boot image. It is a binary blob which U-Boot uses @@ -525,7 +524,6 @@ config ENABLE_MRC_CACHE config HAVE_MRC bool "Add a System Agent binary" select HAS_ROM - select ROM_NEEDS_BLOBS depends on !HAVE_FSP help Select this option to add a System Agent binary to diff --git a/arch/x86/cpu/quark/Kconfig b/arch/x86/cpu/quark/Kconfig index 2fee38aed7..430cce184d 100644 --- a/arch/x86/cpu/quark/Kconfig +++ b/arch/x86/cpu/quark/Kconfig @@ -24,7 +24,6 @@ if INTEL_QUARK config HAVE_RMU bool "Add a Remote Management Unit (RMU) binary" - select ROM_NEEDS_BLOBS help Select this option to add a Remote Management Unit (RMU) binary to the resulting U-Boot image. It is a data block (up to 64K) of diff --git a/doc/arch/x86.rst b/doc/arch/x86.rst index 2ebfed871b..0fdd43be80 100644 --- a/doc/arch/x86.rst +++ b/doc/arch/x86.rst @@ -42,17 +42,8 @@ Build Instructions for U-Boot as BIOS replacement (bare mode) ------------------------------------------------------------- Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a little bit tricky, as generally it requires several binary blobs which are not -shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is -not turned on by default in the U-Boot source tree. Firstly, you need turn it -on by enabling the ROM build either via an environment variable:: - - $ export BUILD_ROM=y - -or via configuration:: - - CONFIG_BUILD_ROM=y - -Both tell the Makefile to build u-boot.rom as a target. +shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build may +print some warnings if required binary blobs (e.g.: FSP) are not present. CPU Microcode ------------- -- cgit v1.2.3 From 5824bc6d6fe5f63aa1fb9acbe5ad5aa28d77380f Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 28 Jul 2021 12:00:22 +0800 Subject: x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ Currently there are two places to specify the x86 TSC timer frequency with one in Kconfig used for early timer and the other one in device tree used when the frequency cannot be determined from hardware. This may potentially create an inconsistent config where the 2 values do not match. Let's use the one specified in Kconfig in the device tree as well. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/cpu/quark/Kconfig | 4 ++-- arch/x86/dts/galileo.dts | 2 +- drivers/timer/Kconfig | 8 ++++---- drivers/timer/tsc_timer.c | 5 +++-- 4 files changed, 10 insertions(+), 9 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/quark/Kconfig b/arch/x86/cpu/quark/Kconfig index 430cce184d..61bb5792c8 100644 --- a/arch/x86/cpu/quark/Kconfig +++ b/arch/x86/cpu/quark/Kconfig @@ -130,8 +130,8 @@ config SYS_CAR_SIZE Space in bytes in eSRAM used as Cache-As-ARM (CAR). Note this size must not exceed eSRAM's total size. -config X86_TSC_TIMER_EARLY_FREQ +config X86_TSC_TIMER_FREQ int - default 400 + default 400000000 endif diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index 501047124e..b5ba1181dd 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -42,7 +42,7 @@ }; tsc-timer { - clock-frequency = <400000000>; + clock-frequency = ; }; mrc { diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index ee81dfa776..8913142654 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -124,12 +124,12 @@ config RENESAS_OSTM_TIMER Enables support for the Renesas OSTM Timer driver. This timer is present on Renesas RZ/A1 R7S72100 SoCs. -config X86_TSC_TIMER_EARLY_FREQ - int "x86 TSC timer frequency in MHz when used as the early timer" +config X86_TSC_TIMER_FREQ + int "x86 TSC timer frequency in Hz" depends on X86_TSC_TIMER - default 1000 + default 1000000000 help - Sets the estimated CPU frequency in MHz when TSC is used as the + Sets the estimated CPU frequency in Hz when TSC is used as the early timer and the frequency can neither be calibrated via some hardware ways, nor got from device tree at the time when device tree is not available yet. diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index 7d19a99622..adef50c374 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -425,12 +425,13 @@ static void tsc_timer_ensure_setup(bool early) goto done; if (early) - fast_calibrate = CONFIG_X86_TSC_TIMER_EARLY_FREQ; + gd->arch.clock_rate = CONFIG_X86_TSC_TIMER_FREQ; else return; done: - gd->arch.clock_rate = fast_calibrate * 1000000; + if (!gd->arch.clock_rate) + gd->arch.clock_rate = fast_calibrate * 1000000; } gd->arch.tsc_inited = true; } -- cgit v1.2.3 From c79cbb5952068d9f05e4bcc7bdbbc8957fe35c68 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 28 Jul 2021 12:00:23 +0800 Subject: x86: dts: Define a default TSC timer frequency If for some reason, TSC timer frequency cannot be determined from hardware, nor is it specified in the device tree, U-Boot will panic resulting in endless reset during boot. Let's define a default TSC timer frequency using the Kconfig value CONFIG_X86_TSC_TIMER_FREQ (note: #include must be used instead of /include/ otherwise the macro is not pre-processed). Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/dts/bayleybay.dts | 2 +- arch/x86/dts/baytrail_som-db5800-som-6867.dts | 2 +- arch/x86/dts/cherryhill.dts | 2 +- arch/x86/dts/chromebook_coral.dts | 3 ++- arch/x86/dts/chromebook_link.dts | 2 +- arch/x86/dts/chromebook_samus.dts | 2 +- arch/x86/dts/chromebox_panther.dts | 2 +- arch/x86/dts/conga-qeval20-qa3-e3845.dts | 2 +- arch/x86/dts/coreboot.dts | 7 ++----- arch/x86/dts/cougarcanyon2.dts | 2 +- arch/x86/dts/crownbay.dts | 2 +- arch/x86/dts/edison.dts | 2 +- arch/x86/dts/efi-x86_app.dts | 7 ++----- arch/x86/dts/efi-x86_payload.dts | 7 ++----- arch/x86/dts/galileo.dts | 7 ++----- arch/x86/dts/minnowmax.dts | 2 +- arch/x86/dts/qemu-x86_i440fx.dts | 6 +----- arch/x86/dts/qemu-x86_q35.dts | 6 +----- arch/x86/dts/slimbootloader.dts | 2 +- arch/x86/dts/tsc_timer.dtsi | 1 + 20 files changed, 25 insertions(+), 43 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index b487bc6655..b92729dd0b 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -14,8 +14,8 @@ /include/ "serial.dtsi" /include/ "reset.dtsi" /include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" +#include "tsc_timer.dtsi" #include "smbios.dtsi" / { diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts index 9c9b5735d7..e9b56de792 100644 --- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts +++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts @@ -14,8 +14,8 @@ /include/ "serial.dtsi" /include/ "reset.dtsi" /include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" +#include "tsc_timer.dtsi" #include "smbios.dtsi" / { diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts index 54a9e566d1..7a273670bd 100644 --- a/arch/x86/dts/cherryhill.dts +++ b/arch/x86/dts/cherryhill.dts @@ -12,8 +12,8 @@ /include/ "serial.dtsi" /include/ "reset.dtsi" /include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" +#include "tsc_timer.dtsi" #include "smbios.dtsi" / { diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 8e98e2d5e0..f0caaacfee 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -8,7 +8,8 @@ /include/ "keyboard.dtsi" /include/ "reset.dtsi" /include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" + +#include "tsc_timer.dtsi" #if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE) #include "chromeos-x86.dtsi" diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 4f8c65974b..11ff520ac2 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -9,8 +9,8 @@ /include/ "serial.dtsi" /include/ "reset.dtsi" /include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" +#include "tsc_timer.dtsi" #include "smbios.dtsi" / { diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts index e624264424..930ec1ace0 100644 --- a/arch/x86/dts/chromebook_samus.dts +++ b/arch/x86/dts/chromebook_samus.dts @@ -7,8 +7,8 @@ /include/ "serial.dtsi" /include/ "reset.dtsi" /include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" +#include "tsc_timer.dtsi" #include "smbios.dtsi" #if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE) diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index 71519ca2cd..b25f759c79 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -4,8 +4,8 @@ /include/ "serial.dtsi" /include/ "reset.dtsi" /include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" +#include "tsc_timer.dtsi" #include "smbios.dtsi" / { diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index 43fea11eb1..705157ceaa 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -14,8 +14,8 @@ /include/ "serial.dtsi" /include/ "reset.dtsi" /include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" +#include "tsc_timer.dtsi" #include "smbios.dtsi" / { diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts index 38ddaafa19..d21978d6e0 100644 --- a/arch/x86/dts/coreboot.dts +++ b/arch/x86/dts/coreboot.dts @@ -12,7 +12,8 @@ /include/ "pcspkr.dtsi" /include/ "reset.dtsi" /include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" + +#include "tsc_timer.dtsi" / { model = "coreboot x86 payload"; @@ -30,10 +31,6 @@ stdout-path = "/serial"; }; - tsc-timer { - clock-frequency = <1000000000>; - }; - pci { compatible = "pci-x86"; u-boot,dm-pre-reloc; diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts index 94ec111db2..58395b5eb6 100644 --- a/arch/x86/dts/cougarcanyon2.dts +++ b/arch/x86/dts/cougarcanyon2.dts @@ -12,8 +12,8 @@ /include/ "keyboard.dtsi" /include/ "reset.dtsi" /include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" +#include "tsc_timer.dtsi" #include "smbios.dtsi" / { diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index a7166a9749..5768352531 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -13,8 +13,8 @@ /include/ "pcspkr.dtsi" /include/ "reset.dtsi" /include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" +#include "tsc_timer.dtsi" #include "smbios.dtsi" / { diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts index 8d245bffc2..64b6228363 100644 --- a/arch/x86/dts/edison.dts +++ b/arch/x86/dts/edison.dts @@ -10,8 +10,8 @@ /include/ "skeleton.dtsi" /include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" +#include "tsc_timer.dtsi" #include "smbios.dtsi" / { diff --git a/arch/x86/dts/efi-x86_app.dts b/arch/x86/dts/efi-x86_app.dts index 20150f6ede..04e044a07a 100644 --- a/arch/x86/dts/efi-x86_app.dts +++ b/arch/x86/dts/efi-x86_app.dts @@ -6,7 +6,8 @@ /dts-v1/; /include/ "skeleton.dtsi" -/include/ "tsc_timer.dtsi" + +#include "tsc_timer.dtsi" / { model = "EFI x86 Application"; @@ -16,10 +17,6 @@ stdout-path = &serial; }; - tsc-timer { - clock-frequency = <1000000000>; - }; - serial: serial { compatible = "efi,uart"; }; diff --git a/arch/x86/dts/efi-x86_payload.dts b/arch/x86/dts/efi-x86_payload.dts index 5ccb986774..087865f225 100644 --- a/arch/x86/dts/efi-x86_payload.dts +++ b/arch/x86/dts/efi-x86_payload.dts @@ -12,7 +12,8 @@ /include/ "keyboard.dtsi" /include/ "reset.dtsi" /include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" + +#include "tsc_timer.dtsi" / { model = "EFI x86 Payload"; @@ -30,10 +31,6 @@ stdout-path = "/serial"; }; - tsc-timer { - clock-frequency = <1000000000>; - }; - pci { compatible = "pci-x86"; u-boot,dm-pre-reloc; diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index b5ba1181dd..4120e8f5c4 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -11,7 +11,8 @@ /include/ "skeleton.dtsi" /include/ "reset.dtsi" /include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" + +#include "tsc_timer.dtsi" / { model = "Intel Galileo"; @@ -41,10 +42,6 @@ }; }; - tsc-timer { - clock-frequency = ; - }; - mrc { compatible = "intel,quark-mrc"; flags = ; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index aa7718f31c..68e0510c68 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -13,8 +13,8 @@ /include/ "serial.dtsi" /include/ "reset.dtsi" /include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" +#include "tsc_timer.dtsi" #include "smbios.dtsi" / { diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts index c33a11d593..6556e9ebcd 100644 --- a/arch/x86/dts/qemu-x86_i440fx.dts +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -12,8 +12,8 @@ /include/ "keyboard.dtsi" /include/ "reset.dtsi" /include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" +#include "tsc_timer.dtsi" #include "smbios.dtsi" / { @@ -42,10 +42,6 @@ }; }; - tsc-timer { - clock-frequency = <1000000000>; - }; - pci { compatible = "pci-x86"; #address-cells = <3>; diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index 9faae7fb56..d0830892e8 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -22,8 +22,8 @@ /include/ "keyboard.dtsi" /include/ "reset.dtsi" /include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" +#include "tsc_timer.dtsi" #include "smbios.dtsi" / { @@ -53,10 +53,6 @@ }; }; - tsc-timer { - clock-frequency = <1000000000>; - }; - pci { compatible = "pci-x86"; #address-cells = <3>; diff --git a/arch/x86/dts/slimbootloader.dts b/arch/x86/dts/slimbootloader.dts index d04095c4f8..9b581c8489 100644 --- a/arch/x86/dts/slimbootloader.dts +++ b/arch/x86/dts/slimbootloader.dts @@ -7,7 +7,7 @@ /include/ "skeleton.dtsi" /include/ "reset.dtsi" -/include/ "tsc_timer.dtsi" +#include "tsc_timer.dtsi" / { model = "slimbootloader x86 payload"; diff --git a/arch/x86/dts/tsc_timer.dtsi b/arch/x86/dts/tsc_timer.dtsi index 4f5021d96f..4df8e9d7fc 100644 --- a/arch/x86/dts/tsc_timer.dtsi +++ b/arch/x86/dts/tsc_timer.dtsi @@ -1,6 +1,7 @@ / { tsc-timer { compatible = "x86,tsc-timer"; + clock-frequency = ; u-boot,dm-pre-reloc; }; }; -- cgit v1.2.3 From 596bd0589ad8ee1df78133af740f1d29b235fb66 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sat, 31 Jul 2021 16:45:24 +0800 Subject: x86: mtrr: Do not clear the unused ones in mtrr_commit() Current mtrr_commit() logic assumes that MTRR MSRs are programmed consecutively from index 0 to its maximum number, and whenever it detects an unused one, it clears all other MTRRs starting from that one. However this may not always be the case. In fact, the clear is not much helpful because these MTRRs come out of reset as disabled already. Drop the clear codes. Signed-off-by: Bin Meng Reviewed-by: Simon Glass Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass --- arch/x86/cpu/mtrr.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index 166aff380c..73cf7bb2be 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -157,10 +157,6 @@ int mtrr_commit(bool do_caches) for (i = 0; i < gd->arch.mtrr_req_count; i++, req++) set_var_mtrr(i, req->type, req->start, req->size); - /* Clear the ones that are unused */ - debug("clear\n"); - for (; i < mtrr_get_var_count(); i++) - wrmsrl(MTRR_PHYS_MASK_MSR(i), 0); debug("close\n"); mtrr_close(&state, do_caches); debug("mtrr done\n"); -- cgit v1.2.3 From 3bcd6cf89efee5c8088dce2f770bdd5592186efb Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sat, 31 Jul 2021 16:45:25 +0800 Subject: x86: mtrr: Skip MSRs that were already programmed in mtrr_commit() At present mtrr_commit() programs the MTRR MSRs starting from index 0, which may overwrite MSRs that were already programmed by previous boot stage or FSP. Switch to call mtrr_set_next_var() instead. Signed-off-by: Bin Meng Reviewed-by: Simon Glass Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass --- arch/x86/cpu/mtrr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index 73cf7bb2be..14c644eb56 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -155,7 +155,7 @@ int mtrr_commit(bool do_caches) debug("open done\n"); qsort(req, gd->arch.mtrr_req_count, sizeof(*req), h_comp_mtrr); for (i = 0; i < gd->arch.mtrr_req_count; i++, req++) - set_var_mtrr(i, req->type, req->start, req->size); + mtrr_set_next_var(req->type, req->start, req->size); debug("close\n"); mtrr_close(&state, do_caches); -- cgit v1.2.3 From 9a7c6fde07d04e392dadfd406b7837c04aed0d72 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sat, 31 Jul 2021 16:45:26 +0800 Subject: x86: mtrr: Abort if requested size is not power of 2 The size parameter of mtrr_add_request() and mtrr_set_next_var() shall be power of 2, otherwise the logic creates a mask that does not meet the requirement of IA32_MTRR_PHYSMASK register. Programming such a mask value to IA32_MTRR_PHYSMASK generates #GP. Signed-off-by: Bin Meng Reviewed-by: Simon Glass Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass --- arch/x86/cpu/mtrr.c | 7 +++++++ arch/x86/include/asm/mtrr.h | 7 ++++--- 2 files changed, 11 insertions(+), 3 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index 14c644eb56..260a008093 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -26,6 +26,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -179,6 +180,9 @@ int mtrr_add_request(int type, uint64_t start, uint64_t size) if (!gd->arch.has_mtrr) return -ENOSYS; + if (!is_power_of_2(size)) + return -EINVAL; + if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS) return -ENOSPC; req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++]; @@ -223,6 +227,9 @@ int mtrr_set_next_var(uint type, uint64_t start, uint64_t size) { int mtrr; + if (!is_power_of_2(size)) + return -EINVAL; + mtrr = get_free_var_mtrr(); if (mtrr < 0) return mtrr; diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 384672e93f..d1aa86bf1d 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -119,7 +119,7 @@ void mtrr_close(struct mtrr_state *state, bool do_caches); * * @type: Requested type (MTRR_TYPE_) * @start: Start address - * @size: Size + * @size: Size, must be power of 2 * * @return: 0 on success, non-zero on failure */ @@ -144,8 +144,9 @@ int mtrr_commit(bool do_caches); * * @type: Requested type (MTRR_TYPE_) * @start: Start address - * @size: Size - * @return 0 on success, -ENOSPC if there are no more MTRRs + * @size: Size, must be power of 2 + * @return 0 on success, -EINVAL if size is not power of 2, + * -ENOSPC if there are no more MTRRs */ int mtrr_set_next_var(uint type, uint64_t base, uint64_t size); -- cgit v1.2.3 From 02541601cbc4adbb9a65b68faa9b8ce14dac7f1d Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 2 Aug 2021 17:45:21 +0800 Subject: x86: fsp: Don't program MTRR for DRAM for FSP1 There are several outstanding issues as to why this does not apply to FSP1: * For FSP1, the system memory and reserved memory used by FSP are already programmed in the MTRR by FSP. * The 'mtrr_top' mistakenly includes TSEG memory range that has the same RES_MEM_RESERVED resource type. Its address is programmed and reported by FSP to be near the top of 4 GiB space, which is not what we want for SDRAM. * The call to mtrr_add_request() is not guaranteed to have its size to be exactly the power of 2. This causes reserved bits of the IA32_MTRR_PHYSMASK register to be written which generates #GP. For FSP2, it seems this is necessary as without this, U-Boot boot process on Chromebook Coral goes very slowly. Signed-off-by: Bin Meng Reviewed-by: Simon Glass Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass --- arch/x86/lib/fsp/fsp_dram.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 8ad9aeedac..2bd408d0c5 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -48,12 +48,28 @@ int dram_init_banksize(void) phys_addr_t mtrr_top; phys_addr_t low_end; uint bank; + bool update_mtrr; + + /* + * For FSP1, the system memory and reserved memory used by FSP are + * already programmed in the MTRR by FSP. Also it is observed that + * FSP on Intel Queensbay platform reports the TSEG memory range + * that has the same RES_MEM_RESERVED resource type whose address + * is programmed by FSP to be near the top of 4 GiB space, which is + * not what we want for DRAM. + * + * However it seems FSP2's behavior is different. We need to add the + * DRAM range in MTRR otherwise the boot process goes very slowly, + * which was observed on Chrromebook Coral with FSP2. + */ + update_mtrr = CONFIG_IS_ENABLED(FSP_VERSION2); if (!ll_boot_init()) { gd->bd->bi_dram[0].start = 0; gd->bd->bi_dram[0].size = gd->ram_size; - mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size); + if (update_mtrr) + mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size); return 0; } @@ -76,8 +92,10 @@ int dram_init_banksize(void) } else { gd->bd->bi_dram[bank].start = res_desc->phys_start; gd->bd->bi_dram[bank].size = res_desc->len; - mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start, - res_desc->len); + if (update_mtrr) + mtrr_add_request(MTRR_TYPE_WRBACK, + res_desc->phys_start, + res_desc->len); log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start, gd->bd->bi_dram[bank].size); @@ -92,7 +110,8 @@ int dram_init_banksize(void) * Set up an MTRR to the top of low, reserved memory. This is necessary * for graphics to run at full speed in U-Boot. */ - mtrr_add_request(MTRR_TYPE_WRBACK, 0, mtrr_top); + if (update_mtrr) + mtrr_add_request(MTRR_TYPE_WRBACK, 0, mtrr_top); return 0; } -- cgit v1.2.3 From 33e4ab31a9647b0bacd44b579199eaae239d69e3 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 2 Aug 2021 17:45:22 +0800 Subject: x86: fsp: Only FSP2 has INIT_PHASE_END_FIRMWARE For FSP1, there is no such INIT_PHASE_END_FIRMWARE. Move board_final_cleanup() to fsp2 directory. Fixes: 7c73cea44290 ("x86: Notify the FSP of the 'end firmware' event") Signed-off-by: Bin Meng Reviewed-by: Simon Glass Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass --- arch/x86/lib/fsp/fsp_common.c | 16 ---------------- arch/x86/lib/fsp2/fsp_common.c | 17 +++++++++++++++++ 2 files changed, 17 insertions(+), 16 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 6365b0a50a..82f7d3ab5f 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -61,22 +61,6 @@ void board_final_init(void) debug("OK\n"); } -void board_final_cleanup(void) -{ - u32 status; - - /* TODO(sjg@chromium.org): This causes Linux to crash */ - return; - - /* call into FspNotify */ - debug("Calling into FSP (notify phase INIT_PHASE_END_FIRMWARE): "); - status = fsp_notify(NULL, INIT_PHASE_END_FIRMWARE); - if (status) - debug("fail, error code %x\n", status); - else - debug("OK\n"); -} - int fsp_save_s3_stack(void) { struct udevice *dev; diff --git a/arch/x86/lib/fsp2/fsp_common.c b/arch/x86/lib/fsp2/fsp_common.c index f69456e43a..20c3f6406a 100644 --- a/arch/x86/lib/fsp2/fsp_common.c +++ b/arch/x86/lib/fsp2/fsp_common.c @@ -6,8 +6,25 @@ #include #include +#include int arch_fsp_init(void) { return 0; } + +void board_final_cleanup(void) +{ + u32 status; + + /* TODO(sjg@chromium.org): This causes Linux to crash */ + return; + + /* call into FspNotify */ + debug("Calling into FSP (notify phase INIT_PHASE_END_FIRMWARE): "); + status = fsp_notify(NULL, INIT_PHASE_END_FIRMWARE); + if (status) + debug("fail, error code %x\n", status); + else + debug("OK\n"); +} -- cgit v1.2.3 From c71d5fb717294ed9e46fc9a5855e8a1878b56f85 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 2 Aug 2021 15:05:15 +0800 Subject: x86: queensbay: Return directly if IGD / SDVO were already disabled Initialize 'igd' and 'sdvo' to NULL so that we just need to test them against NULL later, to be compatible with that case that IGD and SDVO devices were already in disabled state. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/cpu/queensbay/tnc.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 782ed863fe..4a008622d1 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -18,19 +18,17 @@ static int __maybe_unused disable_igd(void) { - struct udevice *igd, *sdvo; + struct udevice *igd = NULL; + struct udevice *sdvo = NULL; int ret; - ret = dm_pci_bus_find_bdf(TNC_IGD, &igd); - if (ret) - return ret; - if (!igd) - return 0; - - ret = dm_pci_bus_find_bdf(TNC_SDVO, &sdvo); - if (ret) - return ret; - if (!sdvo) + /* + * In case the IGD and SDVO devices were already in disabled state, + * we should return and not proceed any further. + */ + dm_pci_bus_find_bdf(TNC_IGD, &igd); + dm_pci_bus_find_bdf(TNC_SDVO, &sdvo); + if (!igd || !sdvo) return 0; /* -- cgit v1.2.3