From 46db4bbac3287a114ddf941ad3861381b795197b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 30 Jul 2021 23:15:44 +0300 Subject: x86: tangier: Fix DMA controller IRQ polarity in CSRT IRQ polarity in CSRT has the same definition as by ACPI specification chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e. ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller IRQ polarity is ActiveHigh. Note, in DSDT (see southcluster.asl) it's described correctly. Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller") Signed-off-by: Andy Shevchenko Reviewed-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/cpu/tangier/acpi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c index 41bd177e09..82f4ce5a34 100644 --- a/arch/x86/cpu/tangier/acpi.c +++ b/arch/x86/cpu/tangier/acpi.c @@ -89,8 +89,8 @@ static u32 acpi_fill_csrt_dma(struct acpi_csrt_group *grp) si->mmio_base_low = 0xff192000; si->mmio_base_high = 0; si->gsi_interrupt = 32; - si->interrupt_polarity = 1; - si->interrupt_mode = 0; + si->interrupt_polarity = 0; /* Active High */ + si->interrupt_mode = 0; /* Level triggered */ si->num_channels = 8; si->dma_address_width = 32; si->base_request_line = 0; -- cgit v1.2.3