From 29795302b942e6ee41c9d95f7e6e29f57d108d42 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Sat, 31 Jul 2021 14:22:52 +0200 Subject: arm: mvebu: a38x: Detect CONFIG_SYS_TCLK from SAR register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bit 15 in SAR register specifies if TCLK is running at 200 MHz or 250 MHz. Use this information instead of manual configuration in every board file. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/include/mach/soc.h | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 3f3b15aa8a..cb323aa59a 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -33,11 +33,6 @@ #define MV_88F68XX_A0_ID 0x4 #define MV_88F68XX_B0_ID 0xa -/* TCLK Core Clock definition */ -#ifndef CONFIG_SYS_TCLK -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ -#endif - /* SOC specific definations */ #define INTREG_BASE 0xd0000000 #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) @@ -170,6 +165,9 @@ #define BOOT_FROM_SPI 0x32 #define BOOT_FROM_MMC 0x30 #define BOOT_FROM_MMC_ALT 0x31 + +#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \ + 200000000 : 250000000) #elif defined(CONFIG_ARMADA_MSYS) /* SAR values for MSYS */ #define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200) @@ -207,4 +205,9 @@ #define BOOT_FROM_SPI 0x3 #endif +/* TCLK Core Clock definition */ +#ifndef CONFIG_SYS_TCLK +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ +#endif + #endif /* _MVEBU_SOC_H */ -- cgit v1.2.3