From c8be85f3ffdc3a3cb51d1b54a9b5737c830b7fbe Mon Sep 17 00:00:00 2001 From: Sinan Akman Date: Tue, 11 May 2021 14:18:02 -0400 Subject: mpc8379erdb: enable DM_USB DM_PCI DM_ETH Signed-off-by: Sinan Akman --- arch/powerpc/cpu/mpc83xx/pci.c | 2 ++ arch/powerpc/dts/mpc8379erdb.dts | 52 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c index 5c289d0022..507ab3417b 100644 --- a/arch/powerpc/cpu/mpc83xx/pci.c +++ b/arch/powerpc/cpu/mpc83xx/pci.c @@ -27,6 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct pci_controller pci_hose[MAX_BUSES]; static int pci_num_buses; +#if !defined(CONFIG_DM_PCI) static void pci_init_bus(int bus, struct pci_region *reg) { volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; @@ -184,6 +185,7 @@ void mpc83xx_pcislave_unlock(int bus) hose->last_busno = pci_hose_scan(hose); } #endif +#endif /* CONFIG_DM_PCI */ #if defined(CONFIG_OF_LIBFDT) void ft_pci_setup(void *blob, struct bd_info *bd) diff --git a/arch/powerpc/dts/mpc8379erdb.dts b/arch/powerpc/dts/mpc8379erdb.dts index b1881b161c..2e7c8f103c 100644 --- a/arch/powerpc/dts/mpc8379erdb.dts +++ b/arch/powerpc/dts/mpc8379erdb.dts @@ -69,6 +69,58 @@ device_type = "ipic"; }; + usb@23000 { + compatible = "fsl-usb2-dr"; + reg = <0x23000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&ipic>; + interrupts = <38 0x8>; + phy_type = "ulpi"; + }; + + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <32 0x8 33 0x8 34 0x8>; + phy-connection-type = "mii"; + interrupt-parent = <&ipic>; + fixed-link = <1 0 1000 0 0>; + phy-handle = <&phy>; + fsl,magic-packet; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-mdio"; + reg = <0x520 0x20>; + + phy: ethernet-phy@2 { + interrupt-parent = <&ipic>; + interrupts = <17 0x8>; + reg = <0x2>; + device_type = "ethernet-phy"; + }; + }; + }; + + pci0: pci@e0008300 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + reg = <0x0 0xe0008300 0x0 0x00000fff>; + compatible = "fsl,mpc837x-pci"; + clock-frequency = <0>; + }; + }; }; -- cgit v1.2.3 From 9fe79ca0ac3469a00a7d7fba94155758e2ac2cdf Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 4 Jun 2021 14:25:36 +1200 Subject: arm: iproc: Add higher speed configurations Add support for 1.3GHz, 1.35GHz and 1.4GHz parts. This is based on equivalent code in Broadcom's LDK 5.0.6. Signed-off-by: Chris Packham --- arch/arm/cpu/armv7/iproc-common/armpll.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/iproc-common/armpll.c b/arch/arm/cpu/armv7/iproc-common/armpll.c index efa3d9e5a9..8c3a323f06 100644 --- a/arch/arm/cpu/armv7/iproc-common/armpll.c +++ b/arch/arm/cpu/armv7/iproc-common/armpll.c @@ -19,19 +19,22 @@ struct armpll_parameters { }; struct armpll_parameters armpll_clk_tab[] = { - { 25, 64, 1, 1, 0}, - { 100, 64, 1, 1, 2}, - { 400, 64, 1, 1, 6}, - { 448, 71, 713050, 1, 6}, - { 500, 80, 1, 1, 6}, - { 560, 89, 629145, 1, 6}, - { 600, 96, 1, 1, 6}, - { 800, 64, 1, 1, 7}, - { 896, 71, 713050, 1, 7}, - { 1000, 80, 1, 1, 7}, - { 1100, 88, 1, 1, 7}, - { 1120, 89, 629145, 1, 7}, - { 1200, 96, 1, 1, 7}, + { 25, 64, 1, 1, 0}, + { 100, 64, 1, 1, 2}, + { 400, 64, 1, 1, 6}, + { 448, 71, 713050, 1, 6}, + { 500, 80, 1, 1, 6}, + { 560, 89, 629145, 1, 6}, + { 600, 96, 1, 1, 6}, + { 800, 64, 1, 1, 7}, + { 896, 71, 713050, 1, 7}, + { 1000, 80, 1, 1, 7}, + { 1100, 88, 1, 1, 7}, + { 1120, 89, 629145, 1, 7}, + { 1200, 96, 1, 1, 7}, + { 1300, 104, 1, 1, 7}, + { 1350, 108, 1, 1, 7}, + { 1400, 112, 1, 1, 7}, }; uint32_t armpll_config(uint32_t clkmhz) -- cgit v1.2.3 From 7a672057dcd36792f01529922fc85892a03be22d Mon Sep 17 00:00:00 2001 From: Masami Hiramatsu Date: Fri, 4 Jun 2021 18:43:55 +0900 Subject: gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs Since some SoCs and boards do not hae extra asm/arch/gpio.h, introduce CONFIG_GPIO_EXTRA_HEADER instead of adding !define(CONFIG_ARCH_XXXX) in asm/gpio.h. Signed-off-by: Masami Hiramatsu --- arch/arm/Kconfig | 94 +++++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/gpio.h | 8 +--- 2 files changed, 95 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0448787b8b..993772b643 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -90,6 +90,9 @@ config HAS_VBAR config HAS_THUMB2 bool +config GPIO_EXTRA_HEADER + bool + # Used for compatibility with asm files copied from the kernel config ARM_ASM_UNIFIED bool @@ -518,25 +521,30 @@ choice config ARCH_AT91 bool "Atmel AT91" + select GPIO_EXTRA_HEADER select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB select SPL_SEPARATE_BSS if SPL config TARGET_EDB93XX bool "Support edb93xx" select CPU_ARM920T + select GPIO_EXTRA_HEADER select PL010_SERIAL config TARGET_ASPENITE bool "Support aspenite" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config TARGET_GPLUGD bool "Support gplugd" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config ARCH_DAVINCI bool "TI DaVinci" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select SPL_DM_SPI if SPL imply CMD_SAVES help @@ -547,6 +555,7 @@ config ARCH_KIRKWOOD select ARCH_MISC_INIT select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config ARCH_MVEBU bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)" @@ -555,6 +564,7 @@ config ARCH_MVEBU select DM_SERIAL select DM_SPI select DM_SPI_FLASH + select GPIO_EXTRA_HEADER select SPL_DM_SPI if SPL select SPL_DM_SPI_FLASH if SPL select OF_CONTROL @@ -565,11 +575,13 @@ config ARCH_MVEBU config ARCH_ORION5X bool "Marvell Orion" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config TARGET_SPEAR300 bool "Support spear300" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -577,6 +589,7 @@ config TARGET_SPEAR310 bool "Support spear310" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -584,6 +597,7 @@ config TARGET_SPEAR320 bool "Support spear320" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -591,6 +605,7 @@ config TARGET_SPEAR600 bool "Support spear600" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -601,6 +616,7 @@ config TARGET_STV0991 select DM_SERIAL select DM_SPI select DM_SPI_FLASH + select GPIO_EXTRA_HEADER select PL01X_SERIAL select SPI select SPI_FLASH @@ -610,18 +626,21 @@ config TARGET_X600 bool "Support x600" select BOARD_LATE_INIT select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL select SUPPORT_SPL config TARGET_FLEA3 bool "Support flea3" select CPU_ARM1136 + select GPIO_EXTRA_HEADER config ARCH_BCM283X bool "Broadcom BCM283X family" select DM select DM_GPIO select DM_SERIAL + select GPIO_EXTRA_HEADER select OF_CONTROL select PL01X_SERIAL select SERIAL_SEARCH_ALL @@ -650,6 +669,7 @@ config ARCH_BCMSTB bool "Broadcom BCM7XXX family" select CPU_V7A select DM + select GPIO_EXTRA_HEADER select OF_CONTROL select OF_PRIOR_STAGE imply CMD_DM @@ -660,6 +680,7 @@ config ARCH_BCMSTB config TARGET_BCMCYGNUS bool "Support bcmcygnus" select CPU_V7A + select GPIO_EXTRA_HEADER imply BCM_SF2_ETH imply BCM_SF2_ETH_GMAC imply CMD_HASH @@ -671,6 +692,7 @@ config TARGET_BCMCYGNUS config TARGET_BCMNS2 bool "Support Broadcom Northstar2" select ARM64 + select GPIO_EXTRA_HEADER help Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit ARMv8 Cortex-A57 processors targeting a broad range of networking @@ -695,6 +717,7 @@ config ARCH_EXYNOS select DM_SPI select DM_SPI_FLASH select SPI + select GPIO_EXTRA_HEADER imply SYS_THUMB_BUILD imply CMD_DM imply FAT_WRITE @@ -706,6 +729,7 @@ config ARCH_S5PC1XX select DM_GPIO select DM_I2C select DM_SERIAL + select GPIO_EXTRA_HEADER imply CMD_DM config ARCH_HIGHBANK @@ -726,6 +750,7 @@ config ARCH_INTEGRATOR bool "ARM Ltd. Integrator family" select DM select DM_SERIAL + select GPIO_EXTRA_HEADER select PL01X_SERIAL imply CMD_DM @@ -736,6 +761,7 @@ config ARCH_IPQ40XX select DM_GPIO select DM_SERIAL select DM_RESET + select GPIO_EXTRA_HEADER select MSM_SMEM select PINCTRL select CLK @@ -747,6 +773,7 @@ config ARCH_KEYSTONE bool "TI Keystone" select CMD_POWEROFF select CPU_V7A + select GPIO_EXTRA_HEADER select SUPPORT_SPL select SYS_ARCH_TIMER select SYS_THUMB_BUILD @@ -763,6 +790,7 @@ config ARCH_K3 config ARCH_OMAP2PLUS bool "TI OMAP2+" select CPU_V7A + select GPIO_EXTRA_HEADER select SPL_BOARD_INIT if SPL select SPL_STACK_R if SPL select SUPPORT_SPL @@ -771,6 +799,7 @@ config ARCH_OMAP2PLUS config ARCH_MESON bool "Amlogic Meson" + select GPIO_EXTRA_HEADER imply DISTRO_DEFAULTS imply DM_RNG help @@ -781,6 +810,7 @@ config ARCH_MESON config ARCH_MEDIATEK bool "MediaTek SoCs" select DM + select GPIO_EXTRA_HEADER select OF_CONTROL select SPL_DM if SPL select SPL_LIBCOMMON_SUPPORT if SPL @@ -797,6 +827,7 @@ config ARCH_LPC32XX select DM select DM_GPIO select DM_SERIAL + select GPIO_EXTRA_HEADER select SPL_DM if SPL select SUPPORT_SPL imply CMD_DM @@ -805,12 +836,14 @@ config ARCH_IMX8 bool "NXP i.MX8 platform" select ARM64 select DM + select GPIO_EXTRA_HEADER select OF_CONTROL select ENABLE_ARM_SOC_BOOT0_HOOK config ARCH_IMX8M bool "NXP i.MX8M platform" select ARM64 + select GPIO_EXTRA_HEADER select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -823,33 +856,39 @@ config ARCH_IMXRT select CPU_V7M select DM select DM_SERIAL + select GPIO_EXTRA_HEADER select SUPPORT_SPL imply CMD_DM config ARCH_MX23 bool "NXP i.MX23 family" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL select SUPPORT_SPL config ARCH_MX25 bool "NXP MX25" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER imply MXC_GPIO config ARCH_MX28 bool "NXP i.MX28 family" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL select SUPPORT_SPL config ARCH_MX31 bool "NXP i.MX31 family" select CPU_ARM1136 + select GPIO_EXTRA_HEADER config ARCH_MX7ULP bool "NXP MX7ULP" select CPU_V7A + select GPIO_EXTRA_HEADER select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -861,6 +900,7 @@ config ARCH_MX7 bool "Freescale MX7" select ARCH_MISC_INIT select CPU_V7A + select GPIO_EXTRA_HEADER select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -871,6 +911,7 @@ config ARCH_MX7 config ARCH_MX6 bool "Freescale MX6" select CPU_V7A + select GPIO_EXTRA_HEADER select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -886,18 +927,21 @@ config ARCH_MX5 bool "Freescale MX5" select BOARD_EARLY_INIT_F select CPU_V7A + select GPIO_EXTRA_HEADER imply MXC_GPIO config ARCH_NEXELL bool "Nexell S5P4418/S5P6818 SoC" select ENABLE_ARM_SOC_BOOT0_HOOK select DM + select GPIO_EXTRA_HEADER config ARCH_OWL bool "Actions Semi OWL SoCs" select DM select DM_ETH select DM_SERIAL + select GPIO_EXTRA_HEADER select OWL_SERIAL select CLK select CLK_OWL @@ -920,6 +964,7 @@ config ARCH_RMOBILE bool "Renesas ARM SoCs" select DM select DM_SERIAL + select GPIO_EXTRA_HEADER imply BOARD_EARLY_INIT_F imply CMD_DM imply FAT_WRITE @@ -932,6 +977,7 @@ config ARCH_SNAPDRAGON select DM select DM_GPIO select DM_SERIAL + select GPIO_EXTRA_HEADER select MSM_SMEM select OF_CONTROL select OF_SEPARATE @@ -947,6 +993,7 @@ config ARCH_SOCFPGA select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select DM select DM_SERIAL + select GPIO_EXTRA_HEADER select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select OF_CONTROL select SPL_DM_RESET if DM_RESET @@ -998,6 +1045,7 @@ config ARCH_SUNXI select DM_SCSI if SCSI select DM_SERIAL select DM_USB if DISTRO_DEFAULTS + select GPIO_EXTRA_HEADER select OF_BOARD_SETUP select OF_CONTROL select OF_SEPARATE @@ -1057,6 +1105,7 @@ config ARCH_VERSAL select DM_ETH if NET select DM_MMC if MMC select DM_SERIAL + select GPIO_EXTRA_HEADER select OF_CONTROL imply BOARD_LATE_INIT imply ENV_VARS_UBOOT_RUNTIME_CONFIG @@ -1064,6 +1113,7 @@ config ARCH_VERSAL config ARCH_VF610 bool "Freescale Vybrid" select CPU_V7A + select GPIO_EXTRA_HEADER select SYS_FSL_ERRATUM_ESDHC111 imply CMD_MTDPARTS imply MTD_RAW_NAND @@ -1080,6 +1130,7 @@ config ARCH_ZYNQ select DM_SPI select DM_SPI_FLASH select DM_USB if USB + select GPIO_EXTRA_HEADER select OF_CONTROL select SPI select SPL_BOARD_INIT if SPL @@ -1106,6 +1157,7 @@ config ARCH_ZYNQMP_R5 select DM_ETH if NET select DM_MMC if MMC select DM_SERIAL + select GPIO_EXTRA_HEADER select OF_CONTROL imply CMD_DM imply DM_USB_GADGET @@ -1123,6 +1175,7 @@ config ARCH_ZYNQMP select DM_SPI_FLASH if DM_SPI select DM_USB if USB select FIRMWARE + select GPIO_EXTRA_HEADER select OF_CONTROL select SPL_BOARD_INIT if SPL select SPL_CLK if SPL @@ -1143,23 +1196,27 @@ config ARCH_ZYNQMP config ARCH_TEGRA bool "NVIDIA Tegra" + select GPIO_EXTRA_HEADER imply DISTRO_DEFAULTS imply FAT_WRITE config TARGET_VEXPRESS64_AEMV8A bool "Support vexpress_aemv8a" select ARM64 + select GPIO_EXTRA_HEADER select PL01X_SERIAL config TARGET_VEXPRESS64_BASE_FVP bool "Support Versatile Express ARMv8a FVP BASE model" select ARM64 + select GPIO_EXTRA_HEADER select PL01X_SERIAL select SEMIHOSTING config TARGET_VEXPRESS64_JUNO bool "Support Versatile Express Juno Development Platform" select ARM64 + select GPIO_EXTRA_HEADER select PL01X_SERIAL select DM select OF_CONTROL @@ -1188,6 +1245,7 @@ config TARGET_LS2080A_EMU select ARM64 select ARMV8_MULTIENTRY select FSL_DDR_SYNC_REFRESH + select GPIO_EXTRA_HEADER help Support for Freescale LS2080A_EMU platform. The LS2080A Development System (EMULATOR) is a pre-silicon @@ -1201,6 +1259,7 @@ config TARGET_LS1088AQDS select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER select SUPPORT_SPL select FSL_DDR_INTERACTIVE if !SD_BOOT help @@ -1216,6 +1275,7 @@ config TARGET_LS2080AQDS select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER select SUPPORT_SPL imply SCSI imply SCSI_AHCI @@ -1237,6 +1297,7 @@ config TARGET_LS2080ARDB select SUPPORT_SPL select FSL_DDR_BIST select FSL_DDR_INTERACTIVE if !SPL + select GPIO_EXTRA_HEADER imply SCSI imply SCSI_AHCI help @@ -1251,6 +1312,7 @@ config TARGET_LS2081ARDB select ARM64 select ARMV8_MULTIENTRY select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER select SUPPORT_SPL help Support for Freescale LS2081ARDB platform. @@ -1265,6 +1327,7 @@ config TARGET_LX2160ARDB select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER help Support for NXP LX2160ARDB platform. The lx2160ardb (LX2160A Reference design board (RDB) @@ -1278,6 +1341,7 @@ config TARGET_LX2160AQDS select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER help Support for NXP LX2160AQDS platform. The lx2160aqds (LX2160A QorIQ Development System (QDS) @@ -1292,6 +1356,7 @@ config TARGET_LX2162AQDS select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER help Support for NXP LX2162AQDS platform. The lx2162aqds support is based on LX2160A Layerscape Architecture processor. @@ -1302,6 +1367,7 @@ config TARGET_HIKEY select DM select DM_GPIO select DM_SERIAL + select GPIO_EXTRA_HEADER select OF_CONTROL select PL01X_SERIAL select SPECIFY_CONSOLE_INDEX @@ -1315,6 +1381,7 @@ config TARGET_HIKEY960 select ARM64 select DM select DM_SERIAL + select GPIO_EXTRA_HEADER select OF_CONTROL select PL01X_SERIAL imply CMD_DM @@ -1328,6 +1395,7 @@ config TARGET_POPLAR select DM select DM_SERIAL select DM_USB + select GPIO_EXTRA_HEADER select OF_CONTROL select PL01X_SERIAL imply CMD_DM @@ -1343,6 +1411,7 @@ config TARGET_LS1012AQDS select ARM64 select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER help Support for Freescale LS1012AQDS platform. The LS1012A Development System (QDS) is a high-performance @@ -1355,6 +1424,7 @@ config TARGET_LS1012ARDB select ARM64 select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER imply SCSI imply SCSI_AHCI help @@ -1369,6 +1439,7 @@ config TARGET_LS1012A2G5RDB select ARM64 select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER imply SCSI help Support for Freescale LS1012A2G5RDB platform. @@ -1382,6 +1453,7 @@ config TARGET_LS1012AFRWY select ARM64 select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER imply SCSI imply SCSI_AHCI help @@ -1395,6 +1467,7 @@ config TARGET_LS1012AFRDM select ARCH_LS1012A select ARM64 select ARCH_SUPPORT_TFABOOT + select GPIO_EXTRA_HEADER help Support for Freescale LS1012AFRDM platform. The LS1012A Freedom board (FRDM) is a high-performance @@ -1408,6 +1481,7 @@ config TARGET_LS1028AQDS select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER help Support for Freescale LS1028AQDS platform The LS1028A Development System (QDS) is a high-performance @@ -1421,6 +1495,7 @@ config TARGET_LS1028ARDB select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER help Support for Freescale LS1028ARDB platform The LS1028A Development System (RDB) is a high-performance @@ -1436,6 +1511,7 @@ config TARGET_LS1088ARDB select BOARD_LATE_INIT select SUPPORT_SPL select FSL_DDR_INTERACTIVE if !SD_BOOT + select GPIO_EXTRA_HEADER help Support for NXP LS1088ARDB platform. The LS1088A Reference design board (RDB) is a high-performance @@ -1456,6 +1532,7 @@ config TARGET_LS1021AQDS select SYS_FSL_DDR select FSL_DDR_INTERACTIVE select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI + select GPIO_EXTRA_HEADER select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI imply SCSI @@ -1471,6 +1548,7 @@ config TARGET_LS1021ATWR select LS1_DEEP_SLEEP select SUPPORT_SPL select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI + select GPIO_EXTRA_HEADER imply SCSI config TARGET_PG_WCOM_SELI8 @@ -1484,6 +1562,7 @@ config TARGET_PG_WCOM_SELI8 select CPU_V7_HAS_VIRT select SYS_FSL_DDR select FSL_DDR_INTERACTIVE + select GPIO_EXTRA_HEADER select VENDOR_KM imply SCSI help @@ -1520,6 +1599,7 @@ config TARGET_LS1021ATSN select CPU_V7_HAS_VIRT select LS1_DEEP_SLEEP select SUPPORT_SPL + select GPIO_EXTRA_HEADER imply SCSI config TARGET_LS1021AIOT @@ -1532,6 +1612,7 @@ config TARGET_LS1021AIOT select CPU_V7_HAS_VIRT select SUPPORT_SPL select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI + select GPIO_EXTRA_HEADER imply SCSI help Support for Freescale LS1021AIOT platform. @@ -1551,6 +1632,7 @@ config TARGET_LS1043AQDS select FSL_DDR_INTERACTIVE if !SPL select FSL_DSPI if !SPL_NO_DSPI select DM_SPI_FLASH if FSL_DSPI + select GPIO_EXTRA_HEADER imply SCSI imply SCSI_AHCI help @@ -1567,6 +1649,7 @@ config TARGET_LS1043ARDB select SUPPORT_SPL select FSL_DSPI if !SPL_NO_DSPI select DM_SPI_FLASH if FSL_DSPI + select GPIO_EXTRA_HEADER help Support for Freescale LS1043ARDB platform. @@ -1583,6 +1666,7 @@ config TARGET_LS1046AQDS select FSL_DDR_BIST if !SPL select FSL_DDR_INTERACTIVE if !SPL select FSL_DDR_INTERACTIVE if !SPL + select GPIO_EXTRA_HEADER imply SCSI help Support for Freescale LS1046AQDS platform. @@ -1603,6 +1687,7 @@ config TARGET_LS1046ARDB select SUPPORT_SPL select FSL_DDR_BIST select FSL_DDR_INTERACTIVE if !SPL + select GPIO_EXTRA_HEADER imply SCSI help Support for Freescale LS1046ARDB platform. @@ -1619,6 +1704,7 @@ config TARGET_LS1046AFRWY select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select DM_SPI_FLASH if DM_SPI + select GPIO_EXTRA_HEADER imply SCSI help Support for Freescale LS1046AFRWY platform. @@ -1647,6 +1733,7 @@ config TARGET_SL28 select DM_SERIAL select DM_SPI select DM_USB + select GPIO_EXTRA_HEADER select SPL_DM if SPL select SPL_DM_SPI if SPL select SPL_DM_SPI_FLASH if SPL @@ -1659,6 +1746,7 @@ config TARGET_SL28 config TARGET_COLIBRI_PXA270 bool "Support colibri_pxa270" select CPU_PXA + select GPIO_EXTRA_HEADER config ARCH_UNIPHIER bool "Socionext UniPhier SoCs" @@ -1695,6 +1783,7 @@ config ARCH_STM32 select CPU_V7M select DM select DM_SERIAL + select GPIO_EXTRA_HEADER imply CMD_DM config ARCH_STI @@ -1720,6 +1809,7 @@ config ARCH_STM32MP select DM_GPIO select DM_RESET select DM_SERIAL + select GPIO_EXTRA_HEADER select MISC select OF_CONTROL select OF_LIBFDT @@ -1782,6 +1872,7 @@ config ARCH_OCTEONTX bool "Support OcteonTX SoCs" select CLK select DM + select GPIO_EXTRA_HEADER select ARM64 select OF_CONTROL select OF_LIVE @@ -1792,6 +1883,7 @@ config ARCH_OCTEONTX2 bool "Support OcteonTX2 SoCs" select CLK select DM + select GPIO_EXTRA_HEADER select ARM64 select OF_CONTROL select OF_LIVE @@ -1801,6 +1893,7 @@ config ARCH_OCTEONTX2 config TARGET_THUNDERX_88XX bool "Support ThunderX 88xx" select ARM64 + select GPIO_EXTRA_HEADER select OF_CONTROL select PL01X_SERIAL select SYS_CACHE_SHIFT_7 @@ -1814,6 +1907,7 @@ config ARCH_ASPEED config TARGET_DURIAN bool "Support Phytium Durian Platform" select ARM64 + select GPIO_EXTRA_HEADER help Support for durian platform. It has 2GB Sdram, uart and pcie. diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 7609367884..650783ae73 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,10 +1,4 @@ -#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \ - !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM68360) && \ - !defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \ - !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \ - !defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM) && \ - !defined(CONFIG_TARGET_BCMNS3) && !defined(CONFIG_TARGET_TOTAL_COMPUTE) && \ - !defined(CONFIG_ARCH_QEMU) +#ifdef CONFIG_GPIO_EXTRA_HEADER #include #endif #include -- cgit v1.2.3 From 2f1f797efa331ff4ab0c5dcac6cbb0081c431282 Mon Sep 17 00:00:00 2001 From: Masami Hiramatsu Date: Fri, 4 Jun 2021 18:44:59 +0900 Subject: ARM: dts: synquacer: Add device trees for DeveloperBox Add device trees for 96boards EE DeveloperBox and basement SynQuacer SoC dtsi. These files are imported from EDK2 commit 83d38b0b4c0f240d4488c600bbe87cea391f3922 as-is (except for the changes #include path and some macros). And add U-Boot specific changes in synquacer-sc2a11-developerbox-u-boot.dtsi Signed-off-by: Masami Hiramatsu --- arch/arm/dts/Makefile | 1 + arch/arm/dts/synquacer-sc2a11-caches.dtsi | 73 +++ .../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 75 +++ arch/arm/dts/synquacer-sc2a11-developerbox.dts | 56 ++ arch/arm/dts/synquacer-sc2a11.dtsi | 595 +++++++++++++++++++++ 5 files changed, 800 insertions(+) create mode 100644 arch/arm/dts/synquacer-sc2a11-caches.dtsi create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox.dts create mode 100644 arch/arm/dts/synquacer-sc2a11.dtsi (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index eef94c4706..da4d0ed7c6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -249,6 +249,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ cn9130-crb-A.dtb \ cn9130-crb-B.dtb +dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \ uniphier-ld11-global.dtb \ uniphier-ld11-ref.dtb diff --git a/arch/arm/dts/synquacer-sc2a11-caches.dtsi b/arch/arm/dts/synquacer-sc2a11-caches.dtsi new file mode 100644 index 0000000000..177ddf8c2b --- /dev/null +++ b/arch/arm/dts/synquacer-sc2a11-caches.dtsi @@ -0,0 +1,73 @@ +/** @file + * Copyright (c) 2018, Linaro Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + */ + +#define __L1(cpuref, l2ref) \ +cpuref { \ + i-cache-size = <0x8000>; \ + i-cache-line-size = <64>; \ + i-cache-sets = <256>; \ + d-cache-size = <0x8000>; \ + d-cache-line-size = <64>; \ + d-cache-sets = <128>; \ + l2-cache = ; \ +}; + +#define __L2(idx) \ +L2_##idx: l2-cache##idx { \ + cache-size = <0x40000>; \ + cache-line-size = <64>; \ + cache-sets = <256>; \ + cache-unified; \ + next-level-cache = <&L3>; \ +}; + +/ { + __L2(0) + __L2(1) + __L2(2) + __L2(3) + __L2(4) + __L2(5) + __L2(6) + __L2(7) + __L2(8) + __L2(9) + __L2(10) + __L2(11) + + L3: l3-cache { + cache-level = <3>; + cache-size = <0x400000>; + cache-line-size = <64>; + cache-sets = <4096>; + cache-unified; + }; +}; + +__L1(&CPU0, &L2_0) +__L1(&CPU1, &L2_0) +__L1(&CPU2, &L2_1) +__L1(&CPU3, &L2_1) +__L1(&CPU4, &L2_2) +__L1(&CPU5, &L2_2) +__L1(&CPU6, &L2_3) +__L1(&CPU7, &L2_3) +__L1(&CPU8, &L2_4) +__L1(&CPU9, &L2_4) +__L1(&CPU10, &L2_5) +__L1(&CPU11, &L2_5) +__L1(&CPU12, &L2_6) +__L1(&CPU13, &L2_6) +__L1(&CPU14, &L2_7) +__L1(&CPU15, &L2_7) +__L1(&CPU16, &L2_8) +__L1(&CPU17, &L2_8) +__L1(&CPU18, &L2_9) +__L1(&CPU19, &L2_9) +__L1(&CPU20, &L2_10) +__L1(&CPU21, &L2_10) +__L1(&CPU22, &L2_11) +__L1(&CPU23, &L2_11) diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi new file mode 100644 index 0000000000..2f13a42235 --- /dev/null +++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// Copyright (c) 2021, Linaro Limited. All rights reserved. +// + +/ { + aliases { + spi_nor = &spi_nor; + i2c0 = &i2c0; + }; + + spi_nor: spi@54800000 { + compatible = "socionext,synquacer-spi"; + reg = <0x00 0x54800000 0x00 0x1000>; + interrupts = <0x00 0x9c 0x04 0x00 0x9d 0x04 0x00 0x9e 0x04>; + clocks = <&clk_alw_1_8>; + clock-names = "iHCLK"; + socionext,use-rtm; + socionext,set-aces; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + active_clk_edges; + chipselect_num = <1>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <31250000>; + spi-rx-bus-width = <0x1>; + spi-tx-bus-width = <0x1>; + }; + }; + + i2c0: i2c@51200000 { + compatible = "socionext,synquacer-i2c"; + reg = <0x0 0x51200000 0x0 0x1000>; + interrupts = ; + clocks = <&clk_i2c>; + clock-names = "pclk"; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + firmware { + optee { + status = "okay"; + }; + }; +}; + +&smmu { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&sdhci { + status = "okay"; +}; diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox.dts b/arch/arm/dts/synquacer-sc2a11-developerbox.dts new file mode 100644 index 0000000000..42b6cbbb82 --- /dev/null +++ b/arch/arm/dts/synquacer-sc2a11-developerbox.dts @@ -0,0 +1,56 @@ +/** @file + * Copyright (c) 2017, Linaro Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + */ + +/dts-v1/; + +#include "synquacer-sc2a11.dtsi" + +#define KEY_POWER 116 + +/ { + model = "Socionext Developer Box"; + compatible = "socionext,developer-box", "socionext,synquacer"; + + gpio-keys { + compatible = "gpio-keys"; + interrupt-parent = <&exiu>; + + power { + label = "Power Button"; + linux,code = ; + interrupts = ; + wakeup-source; + }; + }; +}; + +#ifdef TPM2_ENABLE +&tpm { + status = "okay"; +}; +#endif + +&gpio { + gpio-line-names = "DSW3-PIN1", "DSW3-PIN2", "DSW3-PIN3", "DSW3-PIN4", + "DSW3-PIN5", "DSW3-PIN6", "DSW3-PIN7", "DSW3-PIN8", + "PSIN#", "PWROFF#", "GPIO-A", "GPIO-B", + "GPIO-C", "GPIO-D", "PCIE1EXTINT", "PCIE0EXTINT", + "PHY2-INT#", "PHY1-INT#", "GPIO-E", "GPIO-F", + "GPIO-G", "GPIO-H", "GPIO-I", "GPIO-J", + "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27", + "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31"; +}; + +&netsec { + phy-mode = "rgmii-id"; +}; + +&mdio_netsec { + phy_netsec: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; diff --git a/arch/arm/dts/synquacer-sc2a11.dtsi b/arch/arm/dts/synquacer-sc2a11.dtsi new file mode 100644 index 0000000000..1fe7d214b9 --- /dev/null +++ b/arch/arm/dts/synquacer-sc2a11.dtsi @@ -0,0 +1,595 @@ +/** @file + * Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + */ + +/* These are added for U-Boot to avoid compilation error */ +#define PcdNetsecEepromBase 0x08080000 +#define FixedPcdGet32(n) n + +#define GIC_SPI 0 +#define GIC_PPI 1 + +#define IRQ_TYPE_NONE 0 +#define IRQ_TYPE_EDGE_RISING 1 +#define IRQ_TYPE_EDGE_FALLING 2 +#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) +#define IRQ_TYPE_LEVEL_HIGH 4 +#define IRQ_TYPE_LEVEL_LOW 8 + +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + aliases { + serial0 = &soc_uart0; + serial1 = &fuart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU4: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x200>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU5: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x201>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU6: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x300>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU7: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x301>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU8: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x400>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU9: cpu@401 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x401>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU10: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x500>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU11: cpu@501 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x501>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU12: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x600>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU13: cpu@601 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x601>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU14: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x700>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU15: cpu@701 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x701>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU16: cpu@800 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x800>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU17: cpu@801 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x801>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU18: cpu@900 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x900>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU19: cpu@901 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x901>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU20: cpu@a00 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0xa00>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU21: cpu@a01 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0xa01>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU22: cpu@b00 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0xb00>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU23: cpu@b01 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0xb01>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + }; + cluster1 { + core0 { + cpu = <&CPU2>; + }; + core1 { + cpu = <&CPU3>; + }; + }; + cluster2 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + }; + cluster3 { + core0 { + cpu = <&CPU6>; + }; + core1 { + cpu = <&CPU7>; + }; + }; + cluster4 { + core0 { + cpu = <&CPU8>; + }; + core1 { + cpu = <&CPU9>; + }; + }; + cluster5 { + core0 { + cpu = <&CPU10>; + }; + core1 { + cpu = <&CPU11>; + }; + }; + cluster6 { + core0 { + cpu = <&CPU12>; + }; + core1 { + cpu = <&CPU13>; + }; + }; + cluster7 { + core0 { + cpu = <&CPU14>; + }; + core1 { + cpu = <&CPU15>; + }; + }; + cluster8 { + core0 { + cpu = <&CPU16>; + }; + core1 { + cpu = <&CPU17>; + }; + }; + cluster9 { + core0 { + cpu = <&CPU18>; + }; + core1 { + cpu = <&CPU19>; + }; + }; + cluster10 { + core0 { + cpu = <&CPU20>; + }; + core1 { + cpu = <&CPU21>; + }; + }; + cluster11 { + core0 { + cpu = <&CPU22>; + }; + core1 { + cpu = <&CPU23>; + }; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <300>; + exit-latency-us = <1200>; + min-residency-us = <2000>; + local-timer-stop; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <400>; + exit-latency-us = <1200>; + min-residency-us = <2500>; + local-timer-stop; + }; + }; + + gic: interrupt-controller@30000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x30000000 0x0 0x10000>, // GICD + <0x0 0x30400000 0x0 0x300000>, // GICR + <0x0 0x2c000000 0x0 0x2000>, // GICC + <0x0 0x2c010000 0x0 0x1000>, // GICH + <0x0 0x2c020000 0x0 0x10000>; // GICV + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + interrupts = ; + + its: gic-its@30020000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x30020000 0x0 0x20000>; + #msi-cells = <1>; + msi-controller; + socionext,synquacer-pre-its = <0x58000000 0x200000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , // secure + , // non-secure + , // virtual + ; // HYP + }; + + mmio-timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <0>; + interrupts = ; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + clk_uart: refclk62500khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <62500000>; + clock-output-names = "uartclk"; + }; + + clk_apb: refclk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "apb_pclk"; + }; + + soc_uart0: uart@2a400000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2a400000 0x0 0x1000>; + interrupts = ; + clocks = <&clk_uart>, <&clk_apb>; + clock-names = "uartclk", "apb_pclk"; + }; + + fuart: uart@51040000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x51040000 0x0 0x1000>; + interrupts = ; + clocks = <&clk_uart>, <&clk_apb>; + clock-names = "baudclk", "apb_pclk"; + reg-io-width = <4>; + reg-shift = <2>; + }; + + clk_netsec: refclk250mhz { + compatible = "fixed-clock"; + clock-frequency = <250000000>; + #clock-cells = <0>; + }; + + netsec: ethernet@522d0000 { + compatible = "socionext,synquacer-netsec"; + reg = <0 0x522d0000 0x0 0x10000>, + <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>; + interrupts = ; + clocks = <&clk_netsec>; + clock-names = "phy_ref_clk"; + max-speed = <1000>; + max-frame-size = <9000>; + phy-handle = <&phy_netsec>; + dma-coherent; + + mdio_netsec: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + smmu: iommu@582c0000 { + compatible = "arm,mmu-500", "arm,smmu-v2"; + reg = <0x0 0x582c0000 0x0 0x10000>; + #global-interrupts = <1>; + interrupts = , + , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + pcie0: pcie@60000000 { + compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam"; + device_type = "pci"; + reg = <0x0 0x60000000 0x0 0x7f00000>; + bus-range = <0x0 0x7e>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x1000000 0x00 0x00000000 0x00 0x67f00000 0x0 0x00010000>, + <0x2000000 0x00 0x68000000 0x00 0x68000000 0x0 0x08000000>, + <0x3000000 0x3e 0x00000000 0x3e 0x00000000 0x1 0x00000000>; + + #interrupt-cells = <0x1>; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + + msi-map = <0x000 &its 0x0 0x7f00>; + dma-coherent; + status = "disabled"; + }; + + pcie1: pcie@70000000 { + compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam"; + device_type = "pci"; + reg = <0x0 0x70000000 0x0 0x7f00000>; + bus-range = <0x0 0x7e>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x1000000 0x00 0x00000000 0x00 0x77f00000 0x0 0x00010000>, + <0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>, + <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>; + + #interrupt-cells = <0x1>; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + + msi-map = <0x0 &its 0x10000 0x7f00>; + dma-coherent; + status = "disabled"; + }; + + gpio: gpio@51000000 { + compatible = "socionext,synquacer-gpio", "fujitsu,mb86s70-gpio"; + reg = <0x0 0x51000000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clk_apb>; + base = <0>; + }; + + exiu: interrupt-controller@510c0000 { + compatible = "socionext,synquacer-exiu"; + reg = <0x0 0x510c0000 0x0 0x20>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <3>; + socionext,spi-base = <112>; + }; + + clk_alw_b_0: bclk200 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "sd_bclk"; + }; + + clk_alw_c_0: sd4clk800 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "sd_sd4clk"; + }; + + sdhci: sdhci@52300000 { + compatible = "socionext,synquacer-sdhci", "fujitsu,mb86s70-sdhci-3.0"; + reg = <0 0x52300000 0x0 0x1000>; + interrupts = , + ; + bus-width = <8>; + cap-mmc-highspeed; + fujitsu,cmd-dat-delay-select; + clocks = <&clk_alw_c_0 &clk_alw_b_0>; + clock-names = "core", "iface"; + dma-coherent; + status = "disabled"; + }; + + clk_alw_1_8: spi_ihclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "iHCLK"; + }; + + spi: spi@54810000 { + compatible = "socionext,synquacer-spi"; + reg = <0x0 0x54810000 0x0 0x1000>; + interrupts = , + , + ; + clocks = <&clk_alw_1_8>; + clock-names = "iHCLK"; + socionext,use-rtm; + socionext,set-aces; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + clk_i2c: i2c_pclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <62500000>; + clock-output-names = "pclk"; + }; + + i2c: i2c@51210000 { + compatible = "socionext,synquacer-i2c"; + reg = <0x0 0x51210000 0x0 0x1000>; + interrupts = ; + clocks = <&clk_i2c>; + clock-names = "pclk"; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + tpm: tpm_tis@10000000 { + compatible = "socionext,synquacer-tpm-mmio"; + reg = <0x0 0x10000000 0x0 0x5000>; + status = "disabled"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + }; +}; + +#include "synquacer-sc2a11-caches.dtsi" -- cgit v1.2.3 From 5cd4a355e0f0addb718642b877939819b772936c Mon Sep 17 00:00:00 2001 From: Masami Hiramatsu Date: Fri, 4 Jun 2021 18:45:10 +0900 Subject: board: synquacer: Add DeveloperBox 96boards EE support Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu --- arch/arm/Kconfig | 14 +++ board/socionext/developerbox/Kconfig | 36 +++++++ board/socionext/developerbox/MAINTAINERS | 14 +++ board/socionext/developerbox/Makefile | 9 ++ board/socionext/developerbox/developerbox.c | 146 ++++++++++++++++++++++++++++ configs/synquacer_developerbox_defconfig | 112 +++++++++++++++++++++ doc/board/index.rst | 1 + doc/board/socionext/developerbox.rst | 87 +++++++++++++++++ doc/board/socionext/index.rst | 9 ++ include/configs/synquacer.h | 109 +++++++++++++++++++++ 10 files changed, 537 insertions(+) create mode 100644 board/socionext/developerbox/Kconfig create mode 100644 board/socionext/developerbox/MAINTAINERS create mode 100644 board/socionext/developerbox/Makefile create mode 100644 board/socionext/developerbox/developerbox.c create mode 100644 configs/synquacer_developerbox_defconfig create mode 100644 doc/board/socionext/developerbox.rst create mode 100644 doc/board/socionext/index.rst create mode 100644 include/configs/synquacer.h (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 993772b643..03529d7b46 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1778,6 +1778,19 @@ config ARCH_UNIPHIER Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation) +config ARCH_SYNQUACER + bool "Socionext SynQuacer SoCs" + select ARM64 + select DM + select GIC_V3 + select PSCI_RESET + select SYSRESET + select SYSRESET_PSCI + select OF_CONTROL + help + Support for SynQuacer SoC family developed by Socionext Inc. + This SoC is used on 96boards EE DeveloperBox. + config ARCH_STM32 bool "Support STMicroelectronics STM32 MCU with cortex M" select CPU_V7M @@ -2121,6 +2134,7 @@ source "board/isee/igep003x/Kconfig" source "board/kontron/sl28/Kconfig" source "board/myir/mys_6ulx/Kconfig" source "board/seeed/npi_imx6ull/Kconfig" +source "board/socionext/developerbox/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" source "board/spear/spear320/Kconfig" diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig new file mode 100644 index 0000000000..706b8dc0f1 --- /dev/null +++ b/board/socionext/developerbox/Kconfig @@ -0,0 +1,36 @@ +if ARCH_SYNQUACER + +choice + prompt "SC2A11 Cortex-A53 MPCore 24cores" + optional + +config TARGET_DEVELOPERBOX + bool "Socionext DeveloperBox" + select PCI + select DM_PCI + select PCIE_ECAM_SYNQUACER + select SYS_DISABLE_DCACHE_OPS + select OF_BOARD_SETUP + help + Choose this option if you build the U-Boot for the DeveloperBox + 96boards Enterprise Edition. + This board will booted from SCP firmware and it enables SMMU, thus + the dcache is updated automatically when DMA operation is executed. +endchoice + +config SYS_SOC + default "sc2a11" + +if TARGET_DEVELOPERBOX + +config SYS_BOARD + default "developerbox" + +config SYS_VENDOR + default "socionext" + +config SYS_CONFIG_NAME + default "synquacer" + +endif +endif diff --git a/board/socionext/developerbox/MAINTAINERS b/board/socionext/developerbox/MAINTAINERS new file mode 100644 index 0000000000..aa672b6e05 --- /dev/null +++ b/board/socionext/developerbox/MAINTAINERS @@ -0,0 +1,14 @@ +DEVELOPER BOX +M: Masami Hiramatsu +M: Jassi Brar +S: Maintained +F: arch/arm/dts/synquacer-* +F: board/socionext/developerbox/* +F: configs/synquacer_developerbox_defconfig +F: drivers/i2c/synquacer_i2c.c +F: drivers/mmc/f_sdh30.c +F: drivers/net/sni_netsec.c +F: drivers/pci/pcie_ecam_synquacer.c +F: drivers/spi/spi-synquacer.c +F: include/configs/synquacer.h +F: doc/board/socionext/developerbox.rst diff --git a/board/socionext/developerbox/Makefile b/board/socionext/developerbox/Makefile new file mode 100644 index 0000000000..4a46de995a --- /dev/null +++ b/board/socionext/developerbox/Makefile @@ -0,0 +1,9 @@ +# +# Author: Masami Hiramatsu +# +# Copyright (C) 2021 Linaro Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := developerbox.o diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c new file mode 100644 index 0000000000..34335baec3 --- /dev/null +++ b/board/socionext/developerbox/developerbox.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * u-boot/board/socionext/developerbox/developerbox.c + * + * Copyright (C) 2016-2017 Socionext Inc. + * Copyright (C) 2021 Linaro Ltd. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +static struct mm_region sc2a11_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_OUTER_SHARE + }, { + /* 1st DDR block */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = PHYS_SDRAM_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* 2nd DDR place holder */ + 0, + }, { + /* 3rd DDR place holder */ + 0, + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = sc2a11_mem_map; + +#define DDR_REGION_INDEX(i) (1 + (i)) +#define MAX_DDR_REGIONS 3 + +struct draminfo_entry { + u64 base; + u64 size; +}; + +struct draminfo { + u32 nr_regions; + u32 reserved; + struct draminfo_entry entry[3]; +}; + +struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE; + +DECLARE_GLOBAL_DATA_PTR; + +#define LOAD_OFFSET 0x100 + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET; + + gd->env_addr = (ulong)&default_environment[0]; + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* Remove SPI NOR and I2C0 for making DT compatible with EDK2 */ + fdt_del_node_and_alias(blob, "spi_nor"); + fdt_del_node_and_alias(blob, "i2c0"); + + return 0; +} + +/* + * DRAM configuration + */ + +int dram_init(void) +{ + struct draminfo_entry *ent = synquacer_draminfo->entry; + struct mm_region *mr; + int i, ri; + + if (synquacer_draminfo->nr_regions < 1) { + log_err("Failed to get correct DRAM information\n"); + return -1; + } + + /* + * U-Boot RAM size must be under the first DRAM region so that it doesn't + * access secure memory which is at the end of the first DRAM region. + */ + gd->ram_size = ent[0].size; + + /* Update memory region maps */ + for (i = 0; i < synquacer_draminfo->nr_regions; i++) { + if (i >= MAX_DDR_REGIONS) + break; + + ri = DDR_REGION_INDEX(i); + mem_map[ri].phys = ent[i].base; + mem_map[ri].size = ent[i].size; + if (i == 0) + continue; + + mr = &mem_map[DDR_REGION_INDEX(0)]; + mem_map[ri].virt = mr->virt + mr->size; + mem_map[ri].attrs = mr->attrs; + } + + return 0; +} + +int dram_init_banksize(void) +{ + struct draminfo_entry *ent = synquacer_draminfo->entry; + int i; + + for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) { + if (i < synquacer_draminfo->nr_regions) { + debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base); + gd->bd->bi_dram[i].start = ent[i].base; + gd->bd->bi_dram[i].size = ent[i].size; + } + } + + return 0; +} + +int print_cpuinfo(void) +{ + printf("CPU: SC2A11:Cortex-A53 MPCore 24cores\n"); + return 0; +} diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig new file mode 100644 index 0000000000..cbc09d3225 --- /dev/null +++ b/configs/synquacer_developerbox_defconfig @@ -0,0 +1,112 @@ +CONFIG_ARM=y +CONFIG_ARCH_SYNQUACER=y +CONFIG_SYS_TEXT_BASE=0x08200000 +CONFIG_ENV_SIZE=0x30000 +CONFIG_ENV_OFFSET=0x300000 +CONFIG_DEBUG_UART_BASE=0x2a400000 +CONFIG_DEBUG_UART_CLOCK=62500000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_DEVELOPERBOX=y +CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox" +CONFIG_AHCI=y +CONFIG_BOOTSTAGE_STASH_SIZE=4096 +CONFIG_BOOTM_EFI=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTEFI=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_GPT=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_NVEDIT_INFO=y +CONFIG_CMD_DM=y +CONFIG_CMD_MII=y +CONFIG_CMD_NET=y +CONFIG_CMD_BOOTP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_DATE=y +CONFIG_CMD_RTC=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_SATA=y +CONFIG_CMD_NVME=y +CONFIG_CMD_USB=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDPARTS_DEFAULT="nor1:448k(BootStrap-BL1),576k(Flash-Writer),512k(SCP-BL2),480k(FIP-TFA),32k(Stg2-Tables),1m@2m(U-Boot),1m@3m(UBoot-Env),2m@5m(Ex-OPTEE)" +CONFIG_MTDIDS_DEFAULT="nor1=nor1" +CONFIG_CMD_LOG=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_EFI_PARTITION=y +CONFIG_EFI_LOADER=y +CONFIG_EFI_DEVICE_PATH_TO_TEXT=y +CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2=y +CONFIG_EFI_UNICODE_CAPITALIZATION=y +CONFIG_EFI_HAVE_RUNTIME_RESET=y +CONFIG_EFI_GET_TIME=y +CONFIG_EFI_SET_TIME=y +CONFIG_CMD_EFI_VARIABLE_FILE_STORE=Y +CONFIG_OF_SEPARATE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_ENV_SPI_BUS=y +CONFIG_ENV_SPI_BUS=0 +CONFIG_USE_ENV_SPI_CS=y +CONFIG_ENV_SPI_CS=0 +CONFIG_PROT_UDP=y +CONFIG_BAUDRATE=115200 +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_CONS_INDEX=0 +CONFIG_DM_SERIAL=y +CONFIG_PL01X_SERIAL=y +CONFIG_SATA=y +CONFIG_NVME=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_SYNQUACER=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_F_SDH30=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=31250000 +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHYLIB_10G=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SNI_NETSEC=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_PHY_GIGE=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF8563=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SYNQUACER_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_STORAGE=y diff --git a/doc/board/index.rst b/doc/board/index.rst index 747511f7dd..7349e468b2 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -22,6 +22,7 @@ Board-specific doc rockchip/index sifive/index sipeed/index + socionext/index st/index tbs/index toradex/index diff --git a/doc/board/socionext/developerbox.rst b/doc/board/socionext/developerbox.rst new file mode 100644 index 0000000000..2d943c23be --- /dev/null +++ b/doc/board/socionext/developerbox.rst @@ -0,0 +1,87 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Introduction +============ + +DeveloperBox is a certified 96boards Enterprise Edition board. The board/SoC has: - + +* Socionext SC2A11 24-cores ARM Cortex-A53 on tbe Mini-ATX form factor motherboard +* 4 DIMM slots (4GB DDR4-2400 UDIMM shipped by default) +* 1 4xPCIe Gen2 slot and 2 1xPCIe Gen2 slots + (1x slots are connected via PCIe bridge chip) +* 4 USB-3.0 ports +* 2 SATA ports +* 1 GbE network port +* 1 USB-UART serial port (micro USB) +* 64MB SPI NOR Flash +* 8GB eMMC Flash Storage +* 96boards LS connector + +The DeveloperBox schematic can be found here: - +https://www.96boards.org/documentation/enterprise/developerbox/hardware-docs/mzsc2am_v03_20180115_a.pdf + +And the other documents can be found here: - +https://www.96boards.org/documentation/enterprise/developerbox/ + + +Currently, the U-Boot port supports: - + +* USB +* eMMC +* SPI-NOR +* SATA +* GbE + +The DeveloperBox boots the TF-A and EDK2 as a main bootloader by default. +The DeveloperBox U-Boot port will replace the EDK2 and boot from TF-A as +BL33, but no need to combine with it. + +Compile from source +=================== + +You can build U-Boot without any additinal source code.:: + + cd u-boot + export ARCH=arm64 + export CROSS_COMPILE=aarch64-linux-gnu- + make SynQuacer_defconfig + make -j `noproc` + +Then, expand the binary to 1MB for preparing flash.:: + + cp u-boot.bin SPI_NOR_UBOOT.fd + truncate -s 1M SPI_NOR_UBOOT.fd + +Installation +============ + +You can install the SNI_NOR_UBOOT.fd via NOR flash writer. + +Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine or other mezzanine which can connect to LS-UART0 port. +Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the board on again. The flash writer program will be started automatically; don’t forget to turn the DSW2-7 off again after flashing. + +*!!CAUTION!! If you failed to write the U-Boot image on wrong address, the board can be bricked. See below page if you need to recover the bricked board. See the following page for more detail* + +https://www.96boards.org/documentation/enterprise/developerbox/installation/board-recovery.md.html + +When the serial flasher is running correctly is will show the following boot messages shown via LS-UART0:: + + + /*------------------------------------------*/ + /* SC2A11 "SynQuacer" series Flash writer */ + /* */ + /* Version: cd254ac */ + /* Build: 12/15/17 11:25:45 */ + /*------------------------------------------*/ + + Command Input > + +Once the flasher tool is running we are ready flash the UEFI image:: + + flash rawwrite 200000 100000 + >> Send SPI_NOR_UBOOT.fd via XMODEM (Control-A S in minicom) << + +*!!NOTE!! The flasher command parameter is different from the command for board recovery. U-Boot uses the offset 200000 (2-five-0, 2M in hex) and the size 100000 (1-five-0, 1M in hex).* + +After transferring the SPI_NOR_UBOOT.fd, turn off the DSW2-7 and reset the board. + diff --git a/doc/board/socionext/index.rst b/doc/board/socionext/index.rst new file mode 100644 index 0000000000..4673dcc45b --- /dev/null +++ b/doc/board/socionext/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Socionext +========= + +.. toctree:: + :maxdepth: 2 + + developerbox diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h new file mode 100644 index 0000000000..0dab4de1f1 --- /dev/null +++ b/include/configs/synquacer.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016-2017 Socionext Inc. + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Timers for fasp(TIMCLK) */ +#define CONFIG_SYS_HZ 1000 /* 1 msec */ +#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */ + +/* + * SDRAM (for initialize) + */ +#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */ +#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */ + +#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */ +#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE + +#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */ + +/* + * Boot info + */ +#define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */ +#define CONFIG_SYS_MALLOC_LEN (0x01000000) /* 16Mbyte size of malloc() */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default kernel load address */ + +/* + * Hardware drivers support + */ + +/* RTC */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 + +/* Serial (pl011) */ +#define UART_CLK (62500000) +#define CONFIG_SERIAL_MULTI +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK UART_CLK +#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)} + +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ + +/* Support MTD */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BASE (0x08000000) +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} + +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512 * 1024)) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 128 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ +/* #define CONFIG_SYS_PCI_64BIT 1 */ + +/* Distro boot settings */ +#ifndef CONFIG_SPL_BUILD +#ifdef CONFIG_CMD_USB +#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICE_USB(func) +#endif + +#ifdef CONFIG_CMD_MMC +#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICE_MMC(func) +#endif + +#ifdef CONFIG_CMD_NVME +#define BOOT_TARGET_DEVICE_NVME(func) func(NVME, nvme, 0) +#else +#define BOOT_TARGET_DEVICE_NVME(func) +#endif + +#ifdef CONFIG_CMD_SCSI +#define BOOT_TARGET_DEVICE_SCSI(func) func(SCSI, scsi, 0) func(SCSI, scsi, 1) +#else +#define BOOT_TARGET_DEVICE_SCSI(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICE_USB(func) \ + BOOT_TARGET_DEVICE_MMC(func) \ + BOOT_TARGET_DEVICE_SCSI(func) \ + BOOT_TARGET_DEVICE_NVME(func) \ + +#include +#else /* CONFIG_SPL_BUILD */ +#define BOOTENV +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_addr_r=0x9fe00000\0" \ + "kernel_addr_r=0x90000000\0" \ + "ramdisk_addr_r=0xa0000000\0" \ + "scriptaddr=0x88000000\0" \ + "pxefile_addr_r=0x88100000\0" \ + BOOTENV + +#endif /* __CONFIG_H */ -- cgit v1.2.3 From bd4dbf9e435345cf859922fca74dc0603d7dac2b Mon Sep 17 00:00:00 2001 From: Trevor Woerner Date: Thu, 10 Jun 2021 22:37:02 -0400 Subject: lpc32xx: Kconfig: switch to CONFIG_CONS_INDEX There's nothing special or unique to the lpc32xx that requires its own config parameter for specifying the console uart index. Therefore instead of using the lpc32xx-specific CONFIG_SYS_LPC32XX_UART include parameter, use the already-available CONFIG_CONS_INDEX from Kconfig. Signed-off-by: Trevor Woerner Reviewed-by: Simon Glass --- arch/arm/include/asm/arch-lpc32xx/config.h | 4 ++-- arch/arm/mach-lpc32xx/devices.c | 3 +-- board/timll/devkit3250/devkit3250.c | 2 +- board/timll/devkit3250/devkit3250_spl.c | 2 +- board/work-microwave/work_92105/work_92105.c | 2 +- board/work-microwave/work_92105/work_92105_spl.c | 2 +- configs/devkit3250_defconfig | 2 ++ configs/work_92105_defconfig | 2 ++ include/configs/devkit3250.h | 5 ----- include/configs/work_92105.h | 5 ----- scripts/config_whitelist.txt | 1 - 11 files changed, 11 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 0836091af2..45e46f9946 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -12,8 +12,8 @@ /* Basic CPU architecture */ /* UART configuration */ -#if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \ - (CONFIG_SYS_LPC32XX_UART == 7) +#if (CONFIG_CONS_INDEX == 1) || (CONFIG_CONS_INDEX == 2) || \ + (CONFIG_CONS_INDEX == 7) #if !defined(CONFIG_LPC32XX_HSUART) #define CONFIG_LPC32XX_HSUART #endif diff --git a/arch/arm/mach-lpc32xx/devices.c b/arch/arm/mach-lpc32xx/devices.c index e1e2e0d094..0a4fef295a 100644 --- a/arch/arm/mach-lpc32xx/devices.c +++ b/arch/arm/mach-lpc32xx/devices.c @@ -23,8 +23,7 @@ void lpc32xx_uart_init(unsigned int uart_id) return; /* Disable loopback mode, if it is set by S1L bootloader */ - clrbits_le32(&ctrl->loop, - UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART)); + clrbits_le32(&ctrl->loop, UART_LOOPBACK(uart_id)); if (uart_id < 3 || uart_id > 6) return; diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c index 3c744b943f..9d4ffb0f97 100644 --- a/board/timll/devkit3250/devkit3250.c +++ b/board/timll/devkit3250/devkit3250.c @@ -38,7 +38,7 @@ void reset_periph(void) int board_early_init_f(void) { - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + lpc32xx_uart_init(CONFIG_CONS_INDEX); lpc32xx_i2c_init(1); lpc32xx_i2c_init(2); lpc32xx_ssp_init(); diff --git a/board/timll/devkit3250/devkit3250_spl.c b/board/timll/devkit3250/devkit3250_spl.c index 47af78ae0b..12e8ae9c39 100644 --- a/board/timll/devkit3250/devkit3250_spl.c +++ b/board/timll/devkit3250/devkit3250_spl.c @@ -49,7 +49,7 @@ void spl_board_init(void) /* First of all silence buzzer controlled by GPO_20 */ writel((1 << 20), &gpio->p3_outp_clr); - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + lpc32xx_uart_init(CONFIG_CONS_INDEX); preloader_console_init(); ddr_init(&dram_64mb); diff --git a/board/work-microwave/work_92105/work_92105.c b/board/work-microwave/work_92105/work_92105.c index bdcecff730..5d12f84cfe 100644 --- a/board/work-microwave/work_92105/work_92105.c +++ b/board/work-microwave/work_92105/work_92105.c @@ -37,7 +37,7 @@ void reset_periph(void) int board_early_init_f(void) { /* initialize serial port for console */ - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + lpc32xx_uart_init(CONFIG_CONS_INDEX); /* enable I2C, SSP, MAC, NAND */ lpc32xx_i2c_init(1); /* only I2C1 has devices, I2C2 has none */ lpc32xx_ssp_init(); diff --git a/board/work-microwave/work_92105/work_92105_spl.c b/board/work-microwave/work_92105/work_92105_spl.c index a31553a2d2..d9401145f2 100644 --- a/board/work-microwave/work_92105/work_92105_spl.c +++ b/board/work-microwave/work_92105/work_92105_spl.c @@ -58,7 +58,7 @@ const struct emc_dram_settings dram_128mb = { void spl_board_init(void) { /* initialize serial port for console */ - lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + lpc32xx_uart_init(CONFIG_CONS_INDEX); /* initialize console */ preloader_console_init(); /* init DDR and NAND to chainload U-Boot */ diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index 93c048cee8..9ae70f7d46 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -51,6 +51,8 @@ CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ADDR=31 CONFIG_PHY_SMSC=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_CONS_INDEX=5 CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_USB=y diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index c3f666dcfe..e9605adedd 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -48,5 +48,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_SMSC=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_CONS_INDEX=5 CONFIG_SYS_NS16550=y CONFIG_SPI=y diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 5d2b77b4a3..921a38c01e 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -30,11 +30,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ - GENERATED_GBL_DATA_SIZE) -/* - * Serial Driver - */ -#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */ - /* * DMA */ diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 7874b77f3f..076a1b065e 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -35,11 +35,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ - GENERATED_GBL_DATA_SIZE) -/* - * Serial Driver - */ -#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */ - /* * Ethernet Driver */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index e549a5557f..624d851f0d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2734,7 +2734,6 @@ CONFIG_SYS_LOW CONFIG_SYS_LOWMEM_BASE CONFIG_SYS_LOW_RES_TIMER CONFIG_SYS_LPAE_SDRAM_BASE -CONFIG_SYS_LPC32XX_UART CONFIG_SYS_LS1_DDR_BLOCK1_SIZE CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS -- cgit v1.2.3 From eb5807e68f4334bcc610acd827c889e0abe9231b Mon Sep 17 00:00:00 2001 From: Trevor Woerner Date: Thu, 10 Jun 2021 22:37:03 -0400 Subject: lpc32xx: import device tree from Linux Import the dtsi, dts, and clock binding files for the lpc32xx ea3250 board directly and unmodified from the latest Linux kernel. Signed-off-by: Trevor Woerner --- arch/arm/dts/lpc3250-ea3250.dts | 273 ++++++++++++++++ arch/arm/dts/lpc32xx.dtsi | 508 ++++++++++++++++++++++++++++++ include/dt-bindings/clock/lpc32xx-clock.h | 58 ++++ 3 files changed, 839 insertions(+) create mode 100644 arch/arm/dts/lpc3250-ea3250.dts create mode 100644 arch/arm/dts/lpc32xx.dtsi create mode 100644 include/dt-bindings/clock/lpc32xx-clock.h (limited to 'arch') diff --git a/arch/arm/dts/lpc3250-ea3250.dts b/arch/arm/dts/lpc3250-ea3250.dts new file mode 100644 index 0000000000..63c6f17bb7 --- /dev/null +++ b/arch/arm/dts/lpc3250-ea3250.dts @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Embedded Artists LPC3250 board + * + * Copyright 2012 Roland Stigge + */ + +/dts-v1/; +#include "lpc32xx.dtsi" + +/ { + model = "Embedded Artists LPC3250 board based on NXP LPC3250"; + compatible = "ea,ea3250", "nxp,lpc3250"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x4000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + button { + label = "Interrupt Key"; + linux,code = <103>; + gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ + }; + + key1 { + label = "KEY1"; + linux,code = <1>; + gpios = <&pca9532 0 0>; + }; + + key2 { + label = "KEY2"; + linux,code = <2>; + gpios = <&pca9532 1 0>; + }; + + key3 { + label = "KEY3"; + linux,code = <3>; + gpios = <&pca9532 2 0>; + }; + + key4 { + label = "KEY4"; + linux,code = <4>; + gpios = <&pca9532 3 0>; + }; + + joy0 { + label = "Joystick Key 0"; + linux,code = <10>; + gpios = <&gpio 2 0 0>; /* P2.0 */ + }; + + joy1 { + label = "Joystick Key 1"; + linux,code = <11>; + gpios = <&gpio 2 1 0>; /* P2.1 */ + }; + + joy2 { + label = "Joystick Key 2"; + linux,code = <12>; + gpios = <&gpio 2 2 0>; /* P2.2 */ + }; + + joy3 { + label = "Joystick Key 3"; + linux,code = <13>; + gpios = <&gpio 2 3 0>; /* P2.3 */ + }; + + joy4 { + label = "Joystick Key 4"; + linux,code = <14>; + gpios = <&gpio 2 4 0>; /* P2.4 */ + }; + }; + + leds { + compatible = "gpio-leds"; + + /* LEDs on OEM Board */ + + led1 { + gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */ + linux,default-trigger = "timer"; + default-state = "off"; + }; + + led2 { + gpios = <&gpio 2 10 1>; /* P2.10, active low */ + default-state = "off"; + }; + + led3 { + gpios = <&gpio 2 11 1>; /* P2.11, active low */ + default-state = "off"; + }; + + led4 { + gpios = <&gpio 2 12 1>; /* P2.12, active low */ + default-state = "off"; + }; + + /* LEDs on Base Board */ + + lede1 { + gpios = <&pca9532 8 0>; + default-state = "off"; + }; + lede2 { + gpios = <&pca9532 9 0>; + default-state = "off"; + }; + lede3 { + gpios = <&pca9532 10 0>; + default-state = "off"; + }; + lede4 { + gpios = <&pca9532 11 0>; + default-state = "off"; + }; + lede5 { + gpios = <&pca9532 12 0>; + default-state = "off"; + }; + lede6 { + gpios = <&pca9532 13 0>; + default-state = "off"; + }; + lede7 { + gpios = <&pca9532 14 0>; + default-state = "off"; + }; + lede8 { + gpios = <&pca9532 15 0>; + default-state = "off"; + }; + }; +}; + +/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */ +&adc { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + + uda1380: uda1380@18 { + compatible = "nxp,uda1380"; + reg = <0x18>; + power-gpio = <&gpio 3 10 0>; + reset-gpio = <&gpio 3 2 0>; + dac-clk = "wspll"; + }; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; + + eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + }; + + pca9532: pca9532@60 { + compatible = "nxp,pca9532"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x60>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2cusb { + clock-frequency = <100000>; + + isp1301: usb-transceiver@2d { + compatible = "nxp,isp1301"; + reg = <0x2d>; + }; +}; + +&mac { + phy-mode = "rmii"; + use-iram; + status = "okay"; +}; + +/* Here, choose exactly one from: ohci, usbd */ +&ohci /* &usbd */ { + transceiver = <&isp1301>; + status = "okay"; +}; + +&sd { + wp-gpios = <&pca9532 5 0>; + cd-gpios = <&pca9532 4 0>; + cd-inverted; + bus-width = <4>; + status = "okay"; +}; + +/* 128MB Flash via SLC NAND controller */ +&slc { + status = "okay"; + + nxp,wdr-clks = <14>; + nxp,wwidth = <260000000>; + nxp,whold = <104000000>; + nxp,wsetup = <200000000>; + nxp,rdr-clks = <14>; + nxp,rwidth = <34666666>; + nxp,rhold = <104000000>; + nxp,rsetup = <200000000>; + nand-on-flash-bbt; + gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + mtd0@0 { + label = "ea3250-boot"; + reg = <0x00000000 0x00080000>; + read-only; + }; + + mtd1@80000 { + label = "ea3250-uboot"; + reg = <0x00080000 0x000c0000>; + read-only; + }; + + mtd2@140000 { + label = "ea3250-kernel"; + reg = <0x00140000 0x00400000>; + }; + + mtd3@540000 { + label = "ea3250-rootfs"; + reg = <0x00540000 0x07ac0000>; + }; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&uart6 { + status = "okay"; +}; diff --git a/arch/arm/dts/lpc32xx.dtsi b/arch/arm/dts/lpc32xx.dtsi new file mode 100644 index 0000000000..c87066d6c9 --- /dev/null +++ b/arch/arm/dts/lpc32xx.dtsi @@ -0,0 +1,508 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NXP LPC32xx SoC + * + * Copyright (C) 2015-2019 Vladimir Zapolskiy + * Copyright 2012 Roland Stigge + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "nxp,lpc3220"; + interrupt-parent = <&mic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0x0>; + }; + }; + + clocks { + xtal_32k: xtal_32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32k"; + }; + + xtal: xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <13000000>; + clock-output-names = "xtal"; + }; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x00000000 0x00000000 0x10000000>, + <0x20000000 0x20000000 0x30000000>, + <0xe0000000 0xe0000000 0x04000000>; + + iram: sram@8000000 { + compatible = "mmio-sram"; + reg = <0x08000000 0x20000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x08000000 0x20000>; + }; + + /* + * Enable either SLC or MLC + */ + slc: flash@20020000 { + compatible = "nxp,lpc3220-slc"; + reg = <0x20020000 0x1000>; + clocks = <&clk LPC32XX_CLK_SLC>; + status = "disabled"; + }; + + mlc: flash@200a8000 { + compatible = "nxp,lpc3220-mlc"; + reg = <0x200a8000 0x11000>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_MLC>; + status = "disabled"; + }; + + dma: dma@31000000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0x31000000 0x1000>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_DMA>; + clock-names = "apb_pclk"; + }; + + usb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x0 0x31020000 0x00001000>; + + /* + * Enable either ohci or usbd (gadget)! + */ + ohci: ohci@0 { + compatible = "nxp,ohci-nxp", "usb-ohci"; + reg = <0x0 0x300>; + interrupt-parent = <&sic1>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usbclk LPC32XX_USB_CLK_HOST>; + status = "disabled"; + }; + + usbd: usbd@0 { + compatible = "nxp,lpc3220-udc"; + reg = <0x0 0x300>; + interrupt-parent = <&sic1>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, + <30 IRQ_TYPE_LEVEL_HIGH>, + <28 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_LOW>; + clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; + status = "disabled"; + }; + + i2cusb: i2c@300 { + compatible = "nxp,pnx-i2c"; + reg = <0x300 0x100>; + interrupt-parent = <&sic1>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usbclk LPC32XX_USB_CLK_I2C>; + #address-cells = <1>; + #size-cells = <0>; + }; + + usbclk: clock-controller@f00 { + compatible = "nxp,lpc3220-usb-clk"; + reg = <0xf00 0x100>; + #clock-cells = <1>; + }; + }; + + clcd: clcd@31040000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x31040000 0x1000>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>; + clock-names = "clcdclk", "apb_pclk"; + status = "disabled"; + }; + + mac: ethernet@31060000 { + compatible = "nxp,lpc-eth"; + reg = <0x31060000 0x1000>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_MAC>; + status = "disabled"; + }; + + emc: memory-controller@31080000 { + compatible = "arm,pl175", "arm,primecell"; + reg = <0x31080000 0x1000>; + clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>; + clock-names = "mpmcclk", "apb_pclk"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xe0000000 0x01000000>, + <1 0xe1000000 0x01000000>, + <2 0xe2000000 0x01000000>, + <3 0xe3000000 0x01000000>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x20000000 0x20000000 0x30000000>; + + /* + * ssp0 and spi1 are shared pins; + * enable one in your board dts, as needed. + */ + ssp0: spi@20084000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x20084000 0x1000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_SSP0>; + clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@20088000 { + compatible = "nxp,lpc3220-spi"; + reg = <0x20088000 0x1000>; + clocks = <&clk LPC32XX_CLK_SPI1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* + * ssp1 and spi2 are shared pins; + * enable one in your board dts, as needed. + */ + ssp1: spi@2008c000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x2008c000 0x1000>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_SSP1>; + clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@20090000 { + compatible = "nxp,lpc3220-spi"; + reg = <0x20090000 0x1000>; + clocks = <&clk LPC32XX_CLK_SPI2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2s0: i2s@20094000 { + compatible = "nxp,lpc3220-i2s"; + reg = <0x20094000 0x1000>; + status = "disabled"; + }; + + sd: sd@20098000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x20098000 0x1000>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_SD>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + i2s1: i2s@2009c000 { + compatible = "nxp,lpc3220-i2s"; + reg = <0x2009c000 0x1000>; + status = "disabled"; + }; + + /* UART5 first since it is the default console, ttyS0 */ + uart5: serial@40090000 { + /* actually, ns16550a w/ 64 byte fifos! */ + compatible = "nxp,lpc3220-uart"; + reg = <0x40090000 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + clocks = <&clk LPC32XX_CLK_UART5>; + status = "disabled"; + }; + + uart3: serial@40080000 { + compatible = "nxp,lpc3220-uart"; + reg = <0x40080000 0x1000>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + clocks = <&clk LPC32XX_CLK_UART3>; + status = "disabled"; + }; + + uart4: serial@40088000 { + compatible = "nxp,lpc3220-uart"; + reg = <0x40088000 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + clocks = <&clk LPC32XX_CLK_UART4>; + status = "disabled"; + }; + + uart6: serial@40098000 { + compatible = "nxp,lpc3220-uart"; + reg = <0x40098000 0x1000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + clocks = <&clk LPC32XX_CLK_UART6>; + status = "disabled"; + }; + + i2c1: i2c@400a0000 { + compatible = "nxp,pnx-i2c"; + reg = <0x400a0000 0x100>; + interrupt-parent = <&sic1>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk LPC32XX_CLK_I2C1>; + }; + + i2c2: i2c@400a8000 { + compatible = "nxp,pnx-i2c"; + reg = <0x400a8000 0x100>; + interrupt-parent = <&sic1>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk LPC32XX_CLK_I2C2>; + }; + + mpwm: mpwm@400e8000 { + compatible = "nxp,lpc3220-motor-pwm"; + reg = <0x400e8000 0x78>; + status = "disabled"; + #pwm-cells = <2>; + }; + }; + + fab { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x20000000 0x20000000 0x30000000>; + + /* System Control Block */ + scb { + compatible = "simple-bus"; + ranges = <0x0 0x040004000 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + + clk: clock-controller@0 { + compatible = "nxp,lpc3220-clk"; + reg = <0x00 0x114>; + #clock-cells = <1>; + + clocks = <&xtal_32k>, <&xtal>; + clock-names = "xtal_32k", "xtal"; + }; + }; + + mic: interrupt-controller@40008000 { + compatible = "nxp,lpc3220-mic"; + reg = <0x40008000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sic1: interrupt-controller@4000c000 { + compatible = "nxp,lpc3220-sic"; + reg = <0x4000c000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&mic>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>, + <30 IRQ_TYPE_LEVEL_LOW>; + }; + + sic2: interrupt-controller@40010000 { + compatible = "nxp,lpc3220-sic"; + reg = <0x40010000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&mic>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>, + <31 IRQ_TYPE_LEVEL_LOW>; + }; + + uart1: serial@40014000 { + compatible = "nxp,lpc3220-hsuart"; + reg = <0x40014000 0x1000>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart2: serial@40018000 { + compatible = "nxp,lpc3220-hsuart"; + reg = <0x40018000 0x1000>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart7: serial@4001c000 { + compatible = "nxp,lpc3220-hsuart"; + reg = <0x4001c000 0x1000>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + rtc: rtc@40024000 { + compatible = "nxp,lpc3220-rtc"; + reg = <0x40024000 0x1000>; + interrupt-parent = <&sic1>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_RTC>; + }; + + gpio: gpio@40028000 { + compatible = "nxp,lpc3220-gpio"; + reg = <0x40028000 0x1000>; + gpio-controller; + #gpio-cells = <3>; /* bank, pin, flags */ + }; + + timer4: timer@4002c000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x4002c000 0x1000>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk LPC32XX_CLK_TIMER4>; + clock-names = "timerclk"; + status = "disabled"; + }; + + timer5: timer@40030000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40030000 0x1000>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk LPC32XX_CLK_TIMER5>; + clock-names = "timerclk"; + status = "disabled"; + }; + + watchdog: watchdog@4003c000 { + compatible = "nxp,pnx4008-wdt"; + reg = <0x4003c000 0x1000>; + clocks = <&clk LPC32XX_CLK_WDOG>; + }; + + timer0: timer@40044000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40044000 0x1000>; + clocks = <&clk LPC32XX_CLK_TIMER0>; + clock-names = "timerclk"; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + }; + + /* + * TSC vs. ADC: Since those two share the same + * hardware, you need to choose from one of the + * following two and do 'status = "okay";' for one of + * them + */ + + adc: adc@40048000 { + compatible = "nxp,lpc3220-adc"; + reg = <0x40048000 0x1000>; + interrupt-parent = <&sic1>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_ADC>; + status = "disabled"; + }; + + tsc: tsc@40048000 { + compatible = "nxp,lpc3220-tsc"; + reg = <0x40048000 0x1000>; + interrupt-parent = <&sic1>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_ADC>; + status = "disabled"; + }; + + timer1: timer@4004c000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x4004c000 0x1000>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk LPC32XX_CLK_TIMER1>; + clock-names = "timerclk"; + }; + + key: key@40050000 { + compatible = "nxp,lpc3220-key"; + reg = <0x40050000 0x1000>; + clocks = <&clk LPC32XX_CLK_KEY>; + interrupt-parent = <&sic1>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer2: timer@40058000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40058000 0x1000>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk LPC32XX_CLK_TIMER2>; + clock-names = "timerclk"; + status = "disabled"; + }; + + pwm1: pwm@4005c000 { + compatible = "nxp,lpc3220-pwm"; + reg = <0x4005c000 0x4>; + clocks = <&clk LPC32XX_CLK_PWM1>; + assigned-clocks = <&clk LPC32XX_CLK_PWM1>; + assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; + status = "disabled"; + }; + + pwm2: pwm@4005c004 { + compatible = "nxp,lpc3220-pwm"; + reg = <0x4005c004 0x4>; + clocks = <&clk LPC32XX_CLK_PWM2>; + assigned-clocks = <&clk LPC32XX_CLK_PWM2>; + assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; + status = "disabled"; + }; + + timer3: timer@40060000 { + compatible = "nxp,lpc3220-timer"; + reg = <0x40060000 0x1000>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk LPC32XX_CLK_TIMER3>; + clock-names = "timerclk"; + status = "disabled"; + }; + }; + }; +}; diff --git a/include/dt-bindings/clock/lpc32xx-clock.h b/include/dt-bindings/clock/lpc32xx-clock.h new file mode 100644 index 0000000000..e624d3a527 --- /dev/null +++ b/include/dt-bindings/clock/lpc32xx-clock.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2015 Vladimir Zapolskiy + * + * This code is released using a dual license strategy: BSD/GPL + * You can choose the licence that better fits your requirements. + * + * Released under the terms of 3-clause BSD License + * Released under the terms of GNU General Public License Version 2.0 + * + */ + +#ifndef __DT_BINDINGS_LPC32XX_CLOCK_H +#define __DT_BINDINGS_LPC32XX_CLOCK_H + +/* LPC32XX System Control Block clocks */ +#define LPC32XX_CLK_RTC 1 +#define LPC32XX_CLK_DMA 2 +#define LPC32XX_CLK_MLC 3 +#define LPC32XX_CLK_SLC 4 +#define LPC32XX_CLK_LCD 5 +#define LPC32XX_CLK_MAC 6 +#define LPC32XX_CLK_SD 7 +#define LPC32XX_CLK_DDRAM 8 +#define LPC32XX_CLK_SSP0 9 +#define LPC32XX_CLK_SSP1 10 +#define LPC32XX_CLK_UART3 11 +#define LPC32XX_CLK_UART4 12 +#define LPC32XX_CLK_UART5 13 +#define LPC32XX_CLK_UART6 14 +#define LPC32XX_CLK_IRDA 15 +#define LPC32XX_CLK_I2C1 16 +#define LPC32XX_CLK_I2C2 17 +#define LPC32XX_CLK_TIMER0 18 +#define LPC32XX_CLK_TIMER1 19 +#define LPC32XX_CLK_TIMER2 20 +#define LPC32XX_CLK_TIMER3 21 +#define LPC32XX_CLK_TIMER4 22 +#define LPC32XX_CLK_TIMER5 23 +#define LPC32XX_CLK_WDOG 24 +#define LPC32XX_CLK_I2S0 25 +#define LPC32XX_CLK_I2S1 26 +#define LPC32XX_CLK_SPI1 27 +#define LPC32XX_CLK_SPI2 28 +#define LPC32XX_CLK_MCPWM 29 +#define LPC32XX_CLK_HSTIMER 30 +#define LPC32XX_CLK_KEY 31 +#define LPC32XX_CLK_PWM1 32 +#define LPC32XX_CLK_PWM2 33 +#define LPC32XX_CLK_ADC 34 +#define LPC32XX_CLK_HCLK_PLL 35 +#define LPC32XX_CLK_PERIPH 36 + +/* LPC32XX USB clocks */ +#define LPC32XX_USB_CLK_I2C 1 +#define LPC32XX_USB_CLK_DEVICE 2 +#define LPC32XX_USB_CLK_HOST 3 + +#endif /* __DT_BINDINGS_LPC32XX_CLOCK_H */ -- cgit v1.2.3 From faf78fd464f46269887be90e5b9d2db405aa5f4e Mon Sep 17 00:00:00 2001 From: Trevor Woerner Date: Thu, 10 Jun 2021 22:37:04 -0400 Subject: arm: lpc32xx: add EA LPC3250 DevKitv2 board support Add basic support for running U-Boot on the Embedded Artists LPC3250 Developer's Kit v2 board by launching U-Boot from the board's s1l loader (which comes pre-installed on the board). Signed-off-by: Trevor Woerner --- arch/arm/dts/Makefile | 2 + arch/arm/dts/lpc3250-ea3250-u-boot.dtsi | 15 +++ arch/arm/mach-lpc32xx/Kconfig | 4 + board/ea/ea-lpc3250devkitv2/Kconfig | 15 +++ board/ea/ea-lpc3250devkitv2/MAINTAINERS | 9 ++ board/ea/ea-lpc3250devkitv2/Makefile | 4 + board/ea/ea-lpc3250devkitv2/README.rst | 132 +++++++++++++++++++++++ board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c | 37 +++++++ configs/ea-lpc3250devkitv2_defconfig | 23 ++++ include/configs/ea-lpc3250devkitv2.h | 37 +++++++ 10 files changed, 278 insertions(+) create mode 100644 arch/arm/dts/lpc3250-ea3250-u-boot.dtsi create mode 100644 board/ea/ea-lpc3250devkitv2/Kconfig create mode 100644 board/ea/ea-lpc3250devkitv2/MAINTAINERS create mode 100644 board/ea/ea-lpc3250devkitv2/Makefile create mode 100644 board/ea/ea-lpc3250devkitv2/README.rst create mode 100644 board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c create mode 100644 configs/ea-lpc3250devkitv2_defconfig create mode 100644 include/configs/ea-lpc3250devkitv2.h (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index da4d0ed7c6..59d8078558 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1117,6 +1117,8 @@ dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb +dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here diff --git a/arch/arm/dts/lpc3250-ea3250-u-boot.dtsi b/arch/arm/dts/lpc3250-ea3250-u-boot.dtsi new file mode 100644 index 0000000000..0c82e512c6 --- /dev/null +++ b/arch/arm/dts/lpc3250-ea3250-u-boot.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Trevor Woerner + */ + +/{ + model = "Embedded Artists LPC3250 DevKit v2 board based on the NXP LPC3250 SoC"; + chosen { + stdout-path = &uart5; + }; +}; + +&uart5 { + compatible = "nxp,lpc3220-uart", "ns16550a"; +}; diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig index 986ad738ac..185bda41c2 100644 --- a/arch/arm/mach-lpc32xx/Kconfig +++ b/arch/arm/mach-lpc32xx/Kconfig @@ -12,9 +12,13 @@ config TARGET_DEVKIT3250 config TARGET_WORK_92105 bool "Work Microwave Work_92105" +config TARGET_EA_LPC3250DEVKITV2 + bool "Embedded Artists LPC3250 Developer's Kit v2" + endchoice source "board/timll/devkit3250/Kconfig" source "board/work-microwave/work_92105/Kconfig" +source "board/ea/ea-lpc3250devkitv2/Kconfig" endif diff --git a/board/ea/ea-lpc3250devkitv2/Kconfig b/board/ea/ea-lpc3250devkitv2/Kconfig new file mode 100644 index 0000000000..368ce027e6 --- /dev/null +++ b/board/ea/ea-lpc3250devkitv2/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EA_LPC3250DEVKITV2 + +config SYS_BOARD + default "ea-lpc3250devkitv2" + +config SYS_VENDOR + default "ea" + +config SYS_SOC + default "lpc32xx" + +config SYS_CONFIG_NAME + default "ea-lpc3250devkitv2" + +endif diff --git a/board/ea/ea-lpc3250devkitv2/MAINTAINERS b/board/ea/ea-lpc3250devkitv2/MAINTAINERS new file mode 100644 index 0000000000..b4b9362f5b --- /dev/null +++ b/board/ea/ea-lpc3250devkitv2/MAINTAINERS @@ -0,0 +1,9 @@ +EMBEDDED ARTISTS LPC3250 DEVKIT v2 +M: Trevor Woerner +S: Maintained +F: board/ea/ea-lpc3250devkitv2 +F: include/configs/ea-lpc3250devkitv2.h +F: configs/ea-lpc3250devkitv2_defconfig +F: arch/arm/dts/lpc32xx.dtsi +F: arch/arm/dts/lpc3250-ea3250.dts +F: arch/arm/dts/lpc3250-ea3250-u-boot.dtsi diff --git a/board/ea/ea-lpc3250devkitv2/Makefile b/board/ea/ea-lpc3250devkitv2/Makefile new file mode 100644 index 0000000000..a4a40b6d4f --- /dev/null +++ b/board/ea/ea-lpc3250devkitv2/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2021 Trevor Woerner + +obj-y += ea-lpc3250devkitv2.o diff --git a/board/ea/ea-lpc3250devkitv2/README.rst b/board/ea/ea-lpc3250devkitv2/README.rst new file mode 100644 index 0000000000..56b5d0dbb1 --- /dev/null +++ b/board/ea/ea-lpc3250devkitv2/README.rst @@ -0,0 +1,132 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +ToC: +- Introduction +- Booting +- Debugging + + +Introduction +============ +The Embedded Artists LPC3250 Developer's Kit v2 features the LPC3250 SoC +which is based on the ARM926EJ-S CPU. The kit features a base board and +a removable OEM board which features the SoC. Details, schematics, and +documentation are available from the Embedded Artists product website: + + https://www.embeddedartists.com/products/lpc3250-developers-kit-v2/ + +The base board includes:: +- 200 pos, 0.6mm pitch SODIMM connector for OEM Board +- LCD expansion connector with control signals for touch screen interface +- Expansion connector with all OEM Board signals +- Ethernet connector (RJ45) +- CAN interface & connector (provision for second CAN interface, but not mounted) +- MMC/SD interface & connector +- USB1: OTG or Host interface & connector +- USB2: Device or Host interface & connector +- Provision for NXP JN5148 RF module (former Jennic) interface (RF module not included) +- Full modem RS232 (cannot be fully used on 32-bit databus OEM boards) +- RS422/485 interface & connector +- Provision for IrDA transceiver interface (transceiver not mounted) +- I2S audio codec (mic in, line in, line out, headphone out) +- SWD/JTAG connector +- Trace connector and pads for ETM connector +- Serial Expansion Connector, 14-pos connector with UART/I2C/SPI/GPIO pins +- Power supply, either via USB or external 5V DC +- Optional coin cell battery for RTC and LED on ALARM output (coin cell not included) +- OEM Board current measuring +- Parallel NOR flash on external memory bus +- 16-bit register and LEDs on external memory bus +- 5-key joystick +- LM75 temperature sensor (I2C connected) +- 5 push-button keys (four via I2C and one on ISP-ENABLE) +- 9 LEDs (8 via I2C and one on ISP-ENABLE) +- Trimming potentiometer to analog input +- USB-to-serial bridge on UART #0 (FT232R) and ISP functionality +- Reset push-button and LED +- Speaker output on analog output from OEM Board, or from I2S audio codec +- 160x150 mm in size + +The OEM board:: +- ARMv5 ARM926EJ-S @ 266 MHz with hard-float VFPv2 +- 256 KByte IRAM, 64 MByte SDRAM +- 128 MByte NAND flash +- 4 MByte NOR Flash +- Graphics Output: Parallel RGB +- Hardware 2D/3D Graphic: No +- Hardware Video: SW only +- Graphics input: No +- Audio: I2S +- Ethernet: 10/100 Mbps +- USB: 1x FS USB 2.0 OTG +- Wi-Fi: No +- FlexIO: No +- Serial: 2x I2C, 2x SPI, 7x UART +- ADC/PWM: 3 ch (10-bit) / 2 ch +- SD: MCI +- PCIe: No +- Serial ATA: No +- Size: 68 x 48 mm +- Connector: 200 pos SODIMM + + +Booting +======= +The processor will start its code execution from an internal ROM, +containing the boot code. This boot loader can load code from one of four +external sources to internal RAM (IRAM) at address 0x0:: +- UART5 +- SSP0 (in SPI mode) +- EMC Static CS0 memory +- NAND FLASH + +The ROM boot loader loads code as a single contiguous block at a maximum +size of 56 kByte. Programs larger than this size must be loaded in more +steps, for example, by a secondary boot loader. + +Kickstart Loader +---------------- +By default the Embedded Artists LPC3250 OEM Board is programmed with the +kickstart loader in block 0 of the NAND flash. The responsibility of this +loader is to load an application stored in block 1 and onwards of the NAND +flash. The kickstart loader will load the application into internal RAM +(IRAM) at address 0x0. + +Stage 1 Loader (s1l) +-------------------- +By default the Embedded Artists LPC3250 OEM Board is programmed with the +stage 1 loader (s1l) in block 1 of the NAND flash. This application will be +loaded by the kickstart loader when the LPC3250 OEM Board powers up. The +S1L loader will initialize the board, such as clocks and external memory +and then start a console where you can give input commands to the loader. +S1L offers the following booting options:: +- MMC/SD card +- UART5 +- NAND Flash + +U-Boot with kickstart+s1l +------------------------- +Out of the box, the easiest way to get U-Boot running on the EA LPC3250 +DevKit v2 board is to build the ea-lpc3250devkitv2_defconfig, copy the +resulting u-boot.bin to a vfat-formatted MMC/SD card, insert the MMC/SD card +into the MMC/SD card slot on the board, reset the board (SW1), and:: + + Embedded Artist 3250 Board (S1L 2.0) + Build date: Oct 31 2016 13:00:37 + + EA3250>load blk u-boot.bin raw 0x83000000 + File loaded successfully + + EA3250>exec 0x83000000 + + +Debugging +========= +JTAG debugging of the Embedded Artists LPC3250 Developer's Kit v2 board is +easy thanks to the included/populated 20-pin JTAG port on the main board (J8). +openocd 0.11 has been used with this board along with the ARM-USB-OCD-H JTAG +dongle from Olimex successfully as follows: + + # openocd \ + -f interface/ftdi/olimex-arm-usb-ocd-h.cfg \ + -f board/phytec_lpc3250.cfg diff --git a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c new file mode 100644 index 0000000000..7a19400041 --- /dev/null +++ b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board init file for Embedded Artists LPC3250 DevKit v2 + * Copyright (C) 2021 Trevor Woerner + */ + +#include +#include +#include +#include + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int +board_early_init_f(void) +{ + lpc32xx_uart_init(CONFIG_CONS_INDEX); + return 0; +} + +int +board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x2000; + return 0; +} + +int +dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_64M); + return 0; +} diff --git a/configs/ea-lpc3250devkitv2_defconfig b/configs/ea-lpc3250devkitv2_defconfig new file mode 100644 index 0000000000..dc90e16475 --- /dev/null +++ b/configs/ea-lpc3250devkitv2_defconfig @@ -0,0 +1,23 @@ +CONFIG_ARM=y +CONFIG_SYS_ICACHE_OFF=y +CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_LPC32XX=y +CONFIG_SYS_TEXT_BASE=0x83000000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_TARGET_EA_LPC3250DEVKITV2=y +CONFIG_DEFAULT_DEVICE_TREE="lpc3250-ea3250" +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +# CONFIG_AUTOBOOT is not set +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="EA-LPC3250v2=> " +CONFIG_CMD_GPIO=y +CONFIG_OF_CONTROL=y +# CONFIG_NET is not set +CONFIG_LPC32XX_GPIO=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_CONS_INDEX=5 +CONFIG_SYS_NS16550=y +CONFIG_PANIC_HANG=y diff --git a/include/configs/ea-lpc3250devkitv2.h b/include/configs/ea-lpc3250devkitv2.h new file mode 100644 index 0000000000..c1a37c8a79 --- /dev/null +++ b/include/configs/ea-lpc3250devkitv2.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Embedded Artists LPC3250 DevKit v2 + * Copyright (C) 2021 Trevor Woerner + */ + +#ifndef __CONFIG_EA_LPC3250DEVKITV2_H__ +#define __CONFIG_EA_LPC3250DEVKITV2_H__ + +#include +#include + +/* + * SoC and board defines + */ +#define CONFIG_MACH_TYPE MACH_TYPE_LPC3XXX +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_SIZE_LIMIT 0x000fffff /* maximum allowable size for full U-Boot binary */ + +/* + * RAM + */ +#define CONFIG_SYS_MALLOC_LEN SZ_4M +#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE + +/* + * cmd + */ +#define CONFIG_SYS_LOAD_ADDR 0x80100000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE) + +/* + * SoC-specific config + */ +#include + +#endif -- cgit v1.2.3 From 9b6b25c63512604bb17a40a6005dff451699ef5e Mon Sep 17 00:00:00 2001 From: Sheep Sun Date: Sun, 20 Jun 2021 10:34:34 +0800 Subject: arm: snapdragon: Use correct GICC register on APQ8016 The GICC register used by u-boot is 0x0a20c000, which is actually a GICC for WCNSS, the WLAN processor. U-boot runs on the Application Processor, therefore it should use APCS GICC instead. Hence, correct it with APCS GICC register address. Signed-off-by: Sheep Sun --- arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h index 520e2e6bd7..d9a3b1af98 100644 --- a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h +++ b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h @@ -8,7 +8,7 @@ #define _MACH_SYSMAP_APQ8016_H #define GICD_BASE (0x0b000000) -#define GICC_BASE (0x0a20c000) +#define GICC_BASE (0x0b002000) /* Clocks: (from CLK_CTL_BASE) */ #define GPLL0_STATUS (0x2101C) -- cgit v1.2.3 From 6d430e11a86463745eeaec9292401ffbdfbc07d3 Mon Sep 17 00:00:00 2001 From: Sheep Sun Date: Sun, 20 Jun 2021 10:34:35 +0800 Subject: arm: snapdragon: Fix typo in clk_bcr_update() Fix typo in clock-snapdragon.c Signed-off-by: Sheep Sun --- arch/arm/mach-snapdragon/clock-snapdragon.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index fbe0b5212f..2b76371718 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -56,15 +56,15 @@ void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk) } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL)); } -#define APPS_CMD_RGCR_UPDATE BIT(0) +#define APPS_CMD_RCGR_UPDATE BIT(0) -/* Update clock command via CMD_RGCR */ -void clk_bcr_update(phys_addr_t apps_cmd_rgcr) +/* Update clock command via CMD_RCGR */ +void clk_bcr_update(phys_addr_t apps_cmd_rcgr) { - setbits_le32(apps_cmd_rgcr, APPS_CMD_RGCR_UPDATE); + setbits_le32(apps_cmd_rcgr, APPS_CMD_RCGR_UPDATE); /* Wait for frequency to be updated. */ - while (readl(apps_cmd_rgcr) & APPS_CMD_RGCR_UPDATE) + while (readl(apps_cmd_rcgr) & APPS_CMD_RCGR_UPDATE) ; } -- cgit v1.2.3 From 698c1df4d1bed2778d3344b98dabf4e4ba0efd0d Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Sun, 27 Jun 2021 13:06:15 +0200 Subject: arm: dts: db410c: Add missing cd-gpios for SD card detection It looks like SD card detection is broken at the moment for DB410c. The eMMC is detected correctly, but the SD card is not. This is probably similar to the issue fixed in commit 850514740358 ("mmc: msm_sdhci: Use mmc_of_parse for setting host_caps") for eMMC, except that the SD card does not have a property like "non-removable" that skips the card detection. The SDHCI on DB410c cannot detect itself if a SD card is inserted, so add the necessary cd-gpios to make SD card detection work again. While at it, fix the #gpio-cells for the soc_gpios to avoid DTC warnings - the soc_gpios are actually already used with two cells for the gpio-leds so this was just wrong all the time. Cc: Ramon Fried Signed-off-by: Stephan Gerhold Reviewed-by: Ramon Fried --- arch/arm/dts/dragonboard410c.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts index fa348bc621..7e56140df2 100644 --- a/arch/arm/dts/dragonboard410c.dts +++ b/arch/arm/dts/dragonboard410c.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "skeleton64.dtsi" +#include #include / { @@ -91,7 +92,7 @@ gpio-controller; gpio-count = <122>; gpio-bank-name="soc"; - #gpio-cells = <1>; + #gpio-cells = <2>; }; ehci@78d9000 { @@ -123,6 +124,7 @@ bus-width = <0x4>; clock = <&clkc 1>; clock-frequency = <200000000>; + cd-gpios = <&soc_gpios 38 GPIO_ACTIVE_LOW>; }; wcnss { -- cgit v1.2.3