From 221146c55868e0f1c1cd3d9add440081b677f559 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 24 Aug 2021 11:05:27 -0500 Subject: ARM: rmobile: beacon-renesom: Enable QSPI NOR Flash There is a QSPI NOR flash part on the board. Because this chip isn't yet supported in Linux, but it is supported in U-Boot, and the face that the RPC_SPI compatible names are different in U-Boot and Linux, the device tree updates are confined to -u-boot.dtsi files. In order to use the QSPI, TF-A must leave RPC unlocked by compiling TF-A with RZG_RPC_HYPERFLASH_LOCKED=0. Signed-off-by: Adam Ford Reviewed-by: Biju Bas --- arch/arm/dts/beacon-renesom-som.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/beacon-renesom-som.dtsi b/arch/arm/dts/beacon-renesom-som.dtsi index 9565495b49..d30bab3c8b 100644 --- a/arch/arm/dts/beacon-renesom-som.dtsi +++ b/arch/arm/dts/beacon-renesom-som.dtsi @@ -7,6 +7,10 @@ #include / { + aliases { + spi0 = &rpc; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ @@ -275,6 +279,25 @@ }; }; +&rpc { + compatible = "renesas,rcar-gen3-rpc"; + num-cs = <1>; + spi-max-frequency = <40000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "spi-flash", "jedec,spi-nor"; + spi-max-frequency = <40000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + &scif_clk { clock-frequency = <14745600>; }; -- cgit v1.2.3 From 3404aa464696fbb5a976bdde0746e6ca82b8af82 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Wed, 11 Aug 2021 20:53:29 +0200 Subject: arm: mvebu: axp: Properly check for Armada XP in mach/soc.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit File mach/soc.h is included also in 64-bit mvebu processors, so define Armada XP related macros only when compiling for Armada XP. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/include/mach/soc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 8e8a405855..aab61f7c15 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -189,7 +189,7 @@ #define BOOT_FROM_SPI 0x3 #define CONFIG_SYS_TCLK 200000000 /* 200MHz */ -#else +#elif defined(CONFIG_ARMADA_XP) /* SAR values for Armada XP */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) #define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) -- cgit v1.2.3 From dc595e3e45913ae932bb269739a8a48a27fdd585 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Mon, 16 Aug 2021 15:19:37 +0200 Subject: arm: mvebu: Move get_boot_device() to cpu.c and make visible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the function get_boot_device() from spl.c to cpu.c. Make it visible, so that it may be used from other files. Signed-off-by: Marek Behún Reviewed-by: Pali Rohár Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/cpu.c | 60 ++++++++++++++++++++++++++ arch/arm/mach-mvebu/include/mach/cpu.h | 2 + arch/arm/mach-mvebu/spl.c | 77 ++++------------------------------ 3 files changed, 71 insertions(+), 68 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 0b935c46fb..daf8bd66a0 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) @@ -80,6 +81,65 @@ int mvebu_soc_family(void) return MVEBU_SOC_UNKNOWN; } +u32 get_boot_device(void) +{ + u32 val; + u32 boot_device; + + /* + * First check, if UART boot-mode is active. This can only + * be done, via the bootrom error register. Here the + * MSB marks if the UART mode is active. + */ + val = readl(CONFIG_BOOTROM_ERR_REG); + boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS; + debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device); + if (boot_device == BOOTROM_ERR_MODE_UART) + return BOOT_DEVICE_UART; + +#ifdef CONFIG_ARMADA_38X + /* + * If the bootrom error code contains any other than zeros it's an + * error condition and the bootROM has fallen back to UART boot + */ + boot_device = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS; + if (boot_device) + return BOOT_DEVICE_UART; +#endif + + /* + * Now check the SAR register for the strapped boot-device + */ + val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ + boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS; + debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device); + switch (boot_device) { +#ifdef BOOT_FROM_NAND + case BOOT_FROM_NAND: + return BOOT_DEVICE_NAND; +#endif +#ifdef BOOT_FROM_MMC + case BOOT_FROM_MMC: + case BOOT_FROM_MMC_ALT: + return BOOT_DEVICE_MMC1; +#endif + case BOOT_FROM_UART: +#ifdef BOOT_FROM_UART_ALT + case BOOT_FROM_UART_ALT: +#endif + return BOOT_DEVICE_UART; +#ifdef BOOT_FROM_SATA + case BOOT_FROM_SATA: + case BOOT_FROM_SATA_ALT: + return BOOT_DEVICE_SATA; +#endif + case BOOT_FROM_SPI: + return BOOT_DEVICE_SPI; + default: + return BOOT_DEVICE_BOOTROM; + }; +} + #if defined(CONFIG_DISPLAY_CPUINFO) #if defined(CONFIG_ARMADA_375) diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 79858858c2..a7a62c7e7d 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -148,6 +148,8 @@ void __noreturn return_to_bootrom(void); int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks); #endif +u32 get_boot_device(void); + void get_sar_freq(struct sar_freq_modes *sar_freq); /* diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index f0cf60bb14..8d6d4902f6 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -171,74 +171,6 @@ int spl_parse_board_header(struct spl_image_info *spl_image, return 0; } -static u32 get_boot_device(void) -{ - u32 val; - u32 boot_device; - - /* - * First check, if UART boot-mode is active. This can only - * be done, via the bootrom error register. Here the - * MSB marks if the UART mode is active. - */ - val = readl(CONFIG_BOOTROM_ERR_REG); - boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS; - debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device); - if (boot_device == BOOTROM_ERR_MODE_UART) - return BOOT_DEVICE_UART; - -#ifdef CONFIG_ARMADA_38X - /* - * If the bootrom error code contains any other than zeros it's an - * error condition and the bootROM has fallen back to UART boot - */ - boot_device = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS; - if (boot_device) - return BOOT_DEVICE_UART; -#endif - - /* - * Now check the SAR register for the strapped boot-device - */ - val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ - boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS; - debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device); - switch (boot_device) { -#ifdef BOOT_FROM_NAND - case BOOT_FROM_NAND: - return BOOT_DEVICE_NAND; -#endif -#ifdef BOOT_FROM_MMC - case BOOT_FROM_MMC: - case BOOT_FROM_MMC_ALT: - return BOOT_DEVICE_MMC1; -#endif - case BOOT_FROM_UART: -#ifdef BOOT_FROM_UART_ALT - case BOOT_FROM_UART_ALT: -#endif - return BOOT_DEVICE_UART; -#ifdef BOOT_FROM_SATA - case BOOT_FROM_SATA: - case BOOT_FROM_SATA_ALT: - return BOOT_DEVICE_SATA; -#endif - case BOOT_FROM_SPI: - return BOOT_DEVICE_SPI; - default: - return BOOT_DEVICE_BOOTROM; - }; -} - -#else - -static u32 get_boot_device(void) -{ - return BOOT_DEVICE_BOOTROM; -} - -#endif - u32 spl_boot_device(void) { u32 boot_device = get_boot_device(); @@ -285,6 +217,15 @@ u32 spl_boot_device(void) } } +#else + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOOTROM; +} + +#endif + int board_return_to_bootrom(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { -- cgit v1.2.3 From c8510e397fad4056619d2dab6f2b61c48766a239 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 1 Sep 2021 09:56:02 +0200 Subject: stm32mp: Fix board_get_usable_ram_top() When booting in EFI, lib/efi_loader/efi_memory.c calls board_get_usable_ram_top(0) which returns by default gd->ram_base + gd->ram_size which is the top of DDR. In case of OPTEE boot, the top of DDR is currently reserved by OPTEE, board_get_usable_ram_top(0) must return an address outside OPTEE reserved memory. gd->ram_top matches this constraint as it has already been initialized by substracting all DT reserved-memory (included OPTEE memory area). Fixes: 92b611e8b003 ("stm32mp: correctly handle board_get_usable_ram_top(0)") Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/mach-stm32mp/dram_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 94f25f34e0..920b99bb68 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -47,7 +47,7 @@ ulong board_get_usable_ram_top(ulong total_size) struct lmb lmb; if (!total_size) - return gd->ram_base + gd->ram_size; + return gd->ram_top; /* found enough not-reserved memory to relocated U-Boot */ lmb_init(&lmb); -- cgit v1.2.3 From f6431e8fb358e2fdd01692604cd5796a1b7c10a0 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 4 Sep 2021 10:36:49 +0200 Subject: riscv: show code leading to exception To make analyzing exceptions easier output the code that leads to it. We already do the same on the ARM platform. Here is an example: => exception ebreak Unhandled exception: Breakpoint EPC: 000000008ff5d50e RA: 000000008ff5d62c TVAL: 0000000000000000 EPC: 000000008020b50e RA: 000000008020b62c reloc adjusted Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002) To disassemble the code we can use the decodecode script: $ echo 'Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)' | \ CROSS_COMPILE=riscv64-linux-gnu- scripts/decodecode Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002) All code ======== 0: 2785 addiw a5,a5,1 2: 07a00693 li a3,122 6: fef6dce3 bge a3,a5,0xfffffffffffffffe a: 47a5 li a5,9 c: 00e7d563 bge a5,a4,0x16 10:* 9002 ebreak <-- trapping instruction ... Code starting with the faulting instruction =========================================== 0: 9002 ebreak ... As it is not always clear if the first 16 bits are at the start or in the middle of a 32bit instruction it may become necessary to strip the first u16 from the output before calling decodecode to get the correct disassembled code. Signed-off-by: Heinrich Schuchardt Reviewed-by: Bin Meng Reviewed-by: Sean Anderson --- arch/riscv/lib/interrupts.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch') diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 7525c152b8..100be2e966 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -51,6 +51,38 @@ static void show_regs(struct pt_regs *regs) #endif } +/** + * instr_len() - get instruction length + * + * @i: low 16 bits of the instruction + * Return: number of u16 in instruction + */ +static int instr_len(u16 i) +{ + if ((i & 0x03) != 0x03) + return 1; + /* Instructions with more than 32 bits are not yet specified */ + return 2; +} + +/** + * show_code() - display code leading to exception + * + * @epc: program counter + */ +static void show_code(ulong epc) +{ + u16 *pos = (u16 *)(epc & ~1UL); + int i, len = instr_len(*pos); + + printf("\nCode: "); + for (i = -8; i; ++i) + printf("%04x ", pos[i]); + printf("("); + for (i = 0; i < len; ++i) + printf("%04x%s", pos[i], i + 1 == len ? ")\n" : " "); +} + static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) { static const char * const exception_code[] = { @@ -85,6 +117,7 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) epc - gd->reloc_off, regs->ra - gd->reloc_off); show_regs(regs); + show_code(epc); show_efi_loaded_images(epc); panic("\n"); } -- cgit v1.2.3 From 4d4222d07432faffe3a0fe35c483e116a28eb217 Mon Sep 17 00:00:00 2001 From: Zong Li Date: Wed, 1 Sep 2021 15:01:40 +0800 Subject: common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li Reviewed-by: Rick Chen --- arch/riscv/lib/cache.c | 4 ++++ common/board_r.c | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index b1d42bcc2b..686e699efb 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -70,3 +70,7 @@ __weak int dcache_status(void) { return 0; } + +__weak void enable_caches(void) +{ +} diff --git a/common/board_r.c b/common/board_r.c index e3e6248a1f..630c2451a2 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -114,7 +114,7 @@ static int initr_reloc(void) return 0; } -#ifdef CONFIG_ARM +#if defined(CONFIG_ARM) || defined(CONFIG_RISCV) /* * Some of these functions are needed purely because the functions they * call return void. If we change them to return 0, these stubs can go away. @@ -607,7 +607,7 @@ static init_fnc_t init_sequence_r[] = { initr_trace, initr_reloc, /* TODO: could x86/PPC have this also perhaps? */ -#ifdef CONFIG_ARM +#if defined(CONFIG_ARM) || defined(CONFIG_RISCV) initr_caches, /* Note: For Freescale LS2 SoCs, new MMU table is created in DDR. * A temporary mapping of IFC high region is since removed, -- cgit v1.2.3 From 213ed175b0a97313982c8341c34e48f0ea59b60e Mon Sep 17 00:00:00 2001 From: Zong Li Date: Wed, 1 Sep 2021 15:01:41 +0800 Subject: riscv: lib: implement enable_caches for sifive cache The enable_caches is a generic hook for architecture-implemented, we define this function to enable composable cache of sifive platforms. In sifive_cache, it invokes the generic cache_enable interface of cache uclass to execute the relative implementation in SiFive ccache driver. Signed-off-by: Zong Li Reviewed-by: Rick Chen --- arch/riscv/Kconfig | 5 +++++ arch/riscv/lib/Makefile | 1 + arch/riscv/lib/sifive_cache.c | 27 +++++++++++++++++++++++++++ 3 files changed, 33 insertions(+) create mode 100644 arch/riscv/lib/sifive_cache.c (limited to 'arch') diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 4b0c3dffa6..ec651fe0a4 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. +config SIFIVE_CACHE + bool + help + This enables the operations to configure SiFive cache + config ANDES_PLIC bool depends on RISCV_MMODE || SPL_RISCV_MMODE diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index c4cc41434b..06020fcc2a 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o +obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o obj-$(CONFIG_ANDES_PLIC) += andes_plic.o diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c new file mode 100644 index 0000000000..28154878fc --- /dev/null +++ b/arch/riscv/lib/sifive_cache.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 SiFive, Inc + */ + +#include +#include +#include +#include + +void enable_caches(void) +{ + struct udevice *dev; + int ret; + + /* Enable ways of ccache */ + ret = uclass_get_device_by_driver(UCLASS_CACHE, + DM_DRIVER_GET(sifive_ccache), + &dev); + if (ret) { + log_debug("Cannot enable cache ways"); + } else { + ret = cache_enable(dev); + if (ret) + log_debug("ccache enable failed"); + } +} -- cgit v1.2.3 From 835210a125bef56dacb687cb9f4deae61e68e79d Mon Sep 17 00:00:00 2001 From: Zong Li Date: Wed, 1 Sep 2021 15:01:42 +0800 Subject: board: sifive: use ccache driver instead of helper function Invokes the common cache_init function to initialize ccache. Signed-off-by: Zong Li Reviewed-by: Sean Anderson Reviewed-by: Rick Chen --- arch/riscv/cpu/fu540/Kconfig | 2 ++ arch/riscv/cpu/fu540/Makefile | 1 - arch/riscv/cpu/fu540/cache.c | 55 ------------------------------- arch/riscv/cpu/fu740/Kconfig | 2 ++ arch/riscv/cpu/fu740/Makefile | 1 - arch/riscv/cpu/fu740/cache.c | 55 ------------------------------- arch/riscv/include/asm/arch-fu540/cache.h | 14 -------- arch/riscv/include/asm/arch-fu740/cache.h | 14 -------- board/sifive/unleashed/unleashed.c | 10 ++---- board/sifive/unmatched/unmatched.c | 11 ++----- 10 files changed, 9 insertions(+), 156 deletions(-) delete mode 100644 arch/riscv/cpu/fu540/cache.c delete mode 100644 arch/riscv/cpu/fu740/cache.c delete mode 100644 arch/riscv/include/asm/arch-fu540/cache.h delete mode 100644 arch/riscv/include/asm/arch-fu740/cache.h (limited to 'arch') diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig index 05463b2625..1604b412b4 100644 --- a/arch/riscv/cpu/fu540/Kconfig +++ b/arch/riscv/cpu/fu540/Kconfig @@ -19,6 +19,8 @@ config SIFIVE_FU540 imply SMP imply CLK_SIFIVE imply CLK_SIFIVE_PRCI + imply SIFIVE_CACHE + imply SIFIVE_CCACHE imply SIFIVE_SERIAL imply MACB imply MII diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile index 088205ef57..043fb961a5 100644 --- a/arch/riscv/cpu/fu540/Makefile +++ b/arch/riscv/cpu/fu540/Makefile @@ -8,5 +8,4 @@ obj-y += spl.o else obj-y += dram.o obj-y += cpu.o -obj-y += cache.o endif diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c deleted file mode 100644 index 0fc4ef6c00..0000000000 --- a/arch/riscv/cpu/fu540/cache.c +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020 SiFive, Inc - * - * Authors: - * Pragnesh Patel - */ - -#include -#include -#include -#include - -/* Register offsets */ -#define L2_CACHE_CONFIG 0x000 -#define L2_CACHE_ENABLE 0x008 - -#define MASK_NUM_WAYS GENMASK(15, 8) -#define NUM_WAYS_SHIFT 8 - -DECLARE_GLOBAL_DATA_PTR; - -int cache_enable_ways(void) -{ - const void *blob = gd->fdt_blob; - int node; - fdt_addr_t base; - u32 config; - u32 ways; - - volatile u32 *enable; - - node = fdt_node_offset_by_compatible(blob, -1, - "sifive,fu540-c000-ccache"); - - if (node < 0) - return node; - - base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0, - NULL, false); - if (base == FDT_ADDR_T_NONE) - return FDT_ADDR_T_NONE; - - config = readl((volatile u32 *)base + L2_CACHE_CONFIG); - ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT; - - enable = (volatile u32 *)(base + L2_CACHE_ENABLE); - - /* memory barrier */ - mb(); - (*enable) = ways - 1; - /* memory barrier */ - mb(); - return 0; -} diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig index 408195f149..049a0a0584 100644 --- a/arch/riscv/cpu/fu740/Kconfig +++ b/arch/riscv/cpu/fu740/Kconfig @@ -19,6 +19,8 @@ config SIFIVE_FU740 imply SMP imply CLK_SIFIVE imply CLK_SIFIVE_PRCI + imply SIFIVE_CACHE + imply SIFIVE_CCACHE imply SIFIVE_SERIAL imply MACB imply MII diff --git a/arch/riscv/cpu/fu740/Makefile b/arch/riscv/cpu/fu740/Makefile index 5ef8ac18a7..1d1ad98ba7 100644 --- a/arch/riscv/cpu/fu740/Makefile +++ b/arch/riscv/cpu/fu740/Makefile @@ -8,5 +8,4 @@ obj-y += spl.o else obj-y += dram.o obj-y += cpu.o -obj-y += cache.o endif diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c deleted file mode 100644 index 680955c9e3..0000000000 --- a/arch/riscv/cpu/fu740/cache.c +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020-2021 SiFive, Inc - * - * Authors: - * Pragnesh Patel - */ - -#include -#include -#include -#include - -/* Register offsets */ -#define L2_CACHE_CONFIG 0x000 -#define L2_CACHE_ENABLE 0x008 - -#define MASK_NUM_WAYS GENMASK(15, 8) -#define NUM_WAYS_SHIFT 8 - -DECLARE_GLOBAL_DATA_PTR; - -int cache_enable_ways(void) -{ - const void *blob = gd->fdt_blob; - int node; - fdt_addr_t base; - u32 config; - u32 ways; - - volatile u32 *enable; - - node = fdt_node_offset_by_compatible(blob, -1, - "sifive,fu740-c000-ccache"); - - if (node < 0) - return node; - - base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0, - NULL, false); - if (base == FDT_ADDR_T_NONE) - return FDT_ADDR_T_NONE; - - config = readl((volatile u32 *)base + L2_CACHE_CONFIG); - ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT; - - enable = (volatile u32 *)(base + L2_CACHE_ENABLE); - - /* memory barrier */ - mb(); - (*enable) = ways - 1; - /* memory barrier */ - mb(); - return 0; -} diff --git a/arch/riscv/include/asm/arch-fu540/cache.h b/arch/riscv/include/asm/arch-fu540/cache.h deleted file mode 100644 index 135a17c679..0000000000 --- a/arch/riscv/include/asm/arch-fu540/cache.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2020 SiFive, Inc. - * - * Authors: - * Pragnesh Patel - */ - -#ifndef _CACHE_SIFIVE_H -#define _CACHE_SIFIVE_H - -int cache_enable_ways(void); - -#endif /* _CACHE_SIFIVE_H */ diff --git a/arch/riscv/include/asm/arch-fu740/cache.h b/arch/riscv/include/asm/arch-fu740/cache.h deleted file mode 100644 index 7d4fe9942b..0000000000 --- a/arch/riscv/include/asm/arch-fu740/cache.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2020-2021 SiFive, Inc. - * - * Authors: - * Pragnesh Patel - */ - -#ifndef _CACHE_SIFIVE_H -#define _CACHE_SIFIVE_H - -int cache_enable_ways(void); - -#endif /* _CACHE_SIFIVE_H */ diff --git a/board/sifive/unleashed/unleashed.c b/board/sifive/unleashed/unleashed.c index fa65fcade0..8cd514df30 100644 --- a/board/sifive/unleashed/unleashed.c +++ b/board/sifive/unleashed/unleashed.c @@ -6,6 +6,7 @@ * Anup Patel */ +#include #include #include #include @@ -15,7 +16,6 @@ #include #include #include -#include #include /* @@ -126,14 +126,8 @@ void *board_fdt_blob_setup(void) int board_init(void) { - int ret; - /* enable all cache ways */ - ret = cache_enable_ways(); - if (ret) { - debug("%s: could not enable cache ways\n", __func__); - return ret; - } + enable_caches(); return 0; } diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c index da23a6ce24..d90b252bae 100644 --- a/board/sifive/unmatched/unmatched.c +++ b/board/sifive/unmatched/unmatched.c @@ -7,8 +7,8 @@ */ #include +#include #include -#include #include void *board_fdt_blob_setup(void) @@ -23,13 +23,8 @@ void *board_fdt_blob_setup(void) int board_init(void) { - int ret; - /* enable all cache ways */ - ret = cache_enable_ways(); - if (ret) { - debug("%s: could not enable cache ways\n", __func__); - return ret; - } + enable_caches(); + return 0; } -- cgit v1.2.3 From 30fa33dc808b8f28185bca9c812225cbc1ec6e8f Mon Sep 17 00:00:00 2001 From: Zong Li Date: Wed, 1 Sep 2021 15:01:43 +0800 Subject: riscv: lib: modify the indent We usually use a space in function declaration, rather than a tab. Signed-off-by: Zong Li Reviewed-by: Sean Anderson Reviewed-by: Rick Chen --- arch/riscv/include/asm/cache.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index ec8fe201d3..874963d731 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -8,7 +8,7 @@ #define _ASM_RISCV_CACHE_H /* cache */ -void cache_flush(void); +void cache_flush(void); /* * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. -- cgit v1.2.3 From e60e449931201eaf9a1883dfddef1c5cb6bf161d Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Thu, 2 Sep 2021 19:54:18 -0500 Subject: lib: Drop SHA512_ALGO in lieu of SHA512 SHA512_ALGO was used as a "either SHA512 or SHA384", although the implementations of these two algorithms share a majority of code. From a Kconfig interface perspective, it makes sense to present two distinct options. This requires #ifdefing out the SHA512 implementation from sha512.c. The latter doesn't make any sense. It's reasonable to say in Kconfig that SHA384 depends on SHA512, and seems to be the more polite way to handle the selection. Thus, automatically select SHA512 when SHA384 is enabled. Signed-off-by: Alexandru Gagniuc --- arch/arm/mach-socfpga/Kconfig | 2 +- lib/Kconfig | 12 ++++-------- lib/Makefile | 2 +- lib/crypt/Kconfig | 2 +- lib/efi_loader/Kconfig | 2 +- lib/sha512.c | 2 -- 6 files changed, 8 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index f4791c1ebe..bddfd44427 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -11,7 +11,7 @@ config SOCFPGA_SECURE_VAB_AUTH depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X select FIT_IMAGE_POST_PROCESS select SHA384 - select SHA512_ALGO + select SHA512 select SPL_FIT_IMAGE_POST_PROCESS help All images loaded from FIT will be authenticated by Secure Device diff --git a/lib/Kconfig b/lib/Kconfig index c535147aea..48565a4169 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -375,14 +375,9 @@ config SHA256 The SHA256 algorithm produces a 256-bit (32-byte) hash value (digest). -config SHA512_ALGO - bool "Enable SHA512 algorithm" - help - This option enables support of internal SHA512 algorithm. config SHA512 bool "Enable SHA512 support" - depends on SHA512_ALGO help This option enables support of hashing using SHA512 algorithm. The hash is calculated in software. @@ -391,10 +386,11 @@ config SHA512 config SHA384 bool "Enable SHA384 support" - depends on SHA512_ALGO + select SHA512 help This option enables support of hashing using SHA384 algorithm. - The hash is calculated in software. + The hash is calculated in software. This is also selects SHA512, + because these implementations share the bulk of the code.. The SHA384 algorithm produces a 384-bit (48-byte) hash value (digest). @@ -409,7 +405,7 @@ if SHA_HW_ACCEL config SHA512_HW_ACCEL bool "Enable hardware acceleration for SHA512" - depends on SHA512_ALGO + depends on SHA512 help This option enables hardware acceleration for the SHA384 and SHA512 hashing algorithms. This affects the 'hash' command and also the diff --git a/lib/Makefile b/lib/Makefile index 8ba745faa0..6aa48ca3d5 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -65,7 +65,7 @@ obj-$(CONFIG_$(SPL_)RSA) += rsa/ obj-$(CONFIG_HASH) += hash-checksum.o obj-$(CONFIG_SHA1) += sha1.o obj-$(CONFIG_SHA256) += sha256.o -obj-$(CONFIG_SHA512_ALGO) += sha512.o +obj-$(CONFIG_SHA512) += sha512.o obj-$(CONFIG_CRYPT_PW) += crypt/ obj-$(CONFIG_$(SPL_)ZLIB) += zlib/ diff --git a/lib/crypt/Kconfig b/lib/crypt/Kconfig index 5495ae8d4c..6a50029642 100644 --- a/lib/crypt/Kconfig +++ b/lib/crypt/Kconfig @@ -20,7 +20,7 @@ config CRYPT_PW_SHA256 config CRYPT_PW_SHA512 bool "Provide sha512crypt" select SHA512 - select SHA512_ALGO + select SHA512 help Enables support for the sha512crypt password-hashing algorithm. The prefix is "$6$". diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index dacc3b5881..08463251cd 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -323,7 +323,7 @@ config EFI_TCG2_PROTOCOL depends on TPM_V2 select SHA1 select SHA256 - select SHA512_ALGO + select SHA512 select SHA384 select SHA512 select HASH diff --git a/lib/sha512.c b/lib/sha512.c index 35f31e3dc5..a421f249ba 100644 --- a/lib/sha512.c +++ b/lib/sha512.c @@ -320,7 +320,6 @@ void sha384_csum_wd(const unsigned char *input, unsigned int ilen, #endif -#if defined(CONFIG_SHA512) void sha512_starts(sha512_context * ctx) { ctx->state[0] = SHA512_H0; @@ -381,4 +380,3 @@ void sha512_csum_wd(const unsigned char *input, unsigned int ilen, sha512_finish(&ctx, output); } -#endif -- cgit v1.2.3 From 88426bd6b08e42ce3ca2b1b9c3e11e5c390c3020 Mon Sep 17 00:00:00 2001 From: Sven Auhagen Date: Tue, 24 Aug 2021 10:14:25 +0200 Subject: arm: mvebu: dts: Armada8k enable mdio Since mvpp2 is using the new mdio driver and the cp110 has been synced with the linux upstream, the mdio has to enabled in the device tree file. This is missing for some device tree files and therefore the network cards do not come online. Signed-off-by: Sven Auhagen Reviewed-by: Stefan Roese --- arch/arm/dts/armada-7040-db.dts | 1 + arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 1 + arch/arm/dts/armada-8040-db.dts | 1 + arch/arm/dts/armada-8040-mcbin.dts | 1 + 4 files changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts index b158f92349..9104042359 100644 --- a/arch/arm/dts/armada-7040-db.dts +++ b/arch/arm/dts/armada-7040-db.dts @@ -175,6 +175,7 @@ }; &cp0_mdio { + status = "okay"; phy0: ethernet-phy@0 { reg = <0>; }; diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts index 6a586dbbba..79ee871c5a 100644 --- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts @@ -295,6 +295,7 @@ }; &cp1_mdio { + status = "okay"; phy0: ethernet-phy@0 { reg = <0>; }; diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts index 51c2f23f4d..2686e00242 100644 --- a/arch/arm/dts/armada-8040-db.dts +++ b/arch/arm/dts/armada-8040-db.dts @@ -270,6 +270,7 @@ }; &cp0_mdio { + status = "okay"; phy1: ethernet-phy@1 { reg = <1>; }; diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index 2184648318..b0bed77ae6 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -155,6 +155,7 @@ }; &cp0_mdio { + status = "okay"; ge_phy: ethernet-phy@0 { reg = <0>; }; -- cgit v1.2.3 From 4c9289f52f004927a5fc87ff41137829312f10d6 Mon Sep 17 00:00:00 2001 From: "Matwey V. Kornilov" Date: Sat, 7 Aug 2021 14:17:38 +0300 Subject: am33xx: Fix USB for am335x boards USB nodes were mistakenly disabled in commit 942853dd96df ("arm: dts: Resync BeagleBone device trees") This commit is to fix the following issue: starting USB... No working controllers found USB is stopped. Please issue 'usb start' first. starting USB... No working controllers found Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0782e8572ce43f521ed6ff15e4a7ab9aa5acdc85 Fixes: 942853dd96df ("arm: dts: Resync BeagleBone device trees") Signed-off-by: Matwey V. Kornilov Reviewed-by: Paul Barker --- arch/arm/dts/am33xx.dtsi | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi index ce07cec846..b5093020ee 100644 --- a/arch/arm/dts/am33xx.dtsi +++ b/arch/arm/dts/am33xx.dtsi @@ -380,28 +380,24 @@ #address-cells = <1>; #size-cells = <1>; ti,hwmods = "usb_otg_hs"; - status = "disabled"; usb_ctrl_mod: control@44e10620 { compatible = "ti,am335x-usb-ctrl-module"; reg = <0x44e10620 0x10 0x44e10648 0x4>; reg-names = "phy_ctrl", "wakeup"; - status = "disabled"; }; usb0_phy: usb-phy@47401300 { compatible = "ti,am335x-usb-phy"; reg = <0x47401300 0x100>; reg-names = "phy"; - status = "disabled"; ti,ctrl_mod = <&usb_ctrl_mod>; #phy-cells = <0>; }; usb0: usb@47401000 { compatible = "ti,musb-am33xx"; - status = "disabled"; reg = <0x47401400 0x400 0x47401000 0x200>; reg-names = "mc", "control"; @@ -443,14 +439,12 @@ compatible = "ti,am335x-usb-phy"; reg = <0x47401b00 0x100>; reg-names = "phy"; - status = "disabled"; ti,ctrl_mod = <&usb_ctrl_mod>; #phy-cells = <0>; }; usb1: usb@47401800 { compatible = "ti,musb-am33xx"; - status = "disabled"; reg = <0x47401c00 0x400 0x47401800 0x200>; reg-names = "mc", "control"; -- cgit v1.2.3 From 7ca1af635ac7a323f2715e6478173f3c8eb8c413 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Mon, 9 Aug 2021 22:32:23 +0530 Subject: arm: dts: k3-am642-evm-u-boot: Add u-boot, dm-spl tag in the pinmux node of mmc1 Add u-boot,dm-spl tag in the pinmux device tree node, required for MMCSD1 subsystem. Fixes: b6059ddc45b9 ("arm: dts: k3-am642: Add r5 specific dt support") Signed-off-by: Aswath Govindraju --- arch/arm/dts/k3-am642-evm-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi index ed38b7269e..03688a51a3 100644 --- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi @@ -59,6 +59,10 @@ u-boot,dm-spl; }; +&main_mmc1_pins_default { + u-boot,dm-spl; +}; + &main_usb0_pins_default { u-boot,dm-spl; }; -- cgit v1.2.3 From 72f78c69185f9fe13f36454f3eeb08057872510c Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 24 Aug 2021 14:07:27 +0300 Subject: ARM: dts: Fix node status to "okay" on TI boards As per Device Tree Specification [1], the status parameter of nodes can be "okay", "disabled", etc. "ok" is not a valid parameter. U-boot Driver Model does not recognize status="ok" either and treats the node as disabled. [1] https://github.com/devicetree-org/devicetree-specification/releases/tag/v0.3 Signed-off-by: Roger Quadros Reviewed-by: Nishanth Menon --- arch/arm/dts/am3517-evm-ui.dtsi | 4 ++-- arch/arm/dts/am3517-evm.dts | 2 +- arch/arm/dts/am437x-gp-evm.dts | 2 +- arch/arm/dts/am43x-epos-evm.dts | 2 +- arch/arm/dts/am57xx-beagle-x15-common.dtsi | 6 +++--- arch/arm/dts/da850-evm.dts | 2 +- arch/arm/dts/dra7-evm.dts | 2 +- arch/arm/dts/dra72-evm-common.dtsi | 6 +++--- arch/arm/dts/keystone-k2e-evm.dts | 2 +- arch/arm/dts/keystone-k2hk-evm.dts | 2 +- arch/arm/dts/keystone-k2l-evm.dts | 2 +- arch/arm/dts/omap3-beagle-xm.dts | 4 ++-- arch/arm/dts/omap3-beagle.dts | 6 +++--- arch/arm/dts/omap3-igep0020-common.dtsi | 2 +- arch/arm/dts/omap3-panel-sharp-ls037v7dw01.dtsi | 2 +- arch/arm/dts/omap34xx.dtsi | 2 +- arch/arm/dts/omap36xx.dtsi | 2 +- arch/arm/dts/omap4-panda-common.dtsi | 6 +++--- arch/arm/dts/omap4-sdp.dts | 8 ++++---- arch/arm/dts/omap5-board-common.dtsi | 4 ++-- 20 files changed, 34 insertions(+), 34 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/am3517-evm-ui.dtsi b/arch/arm/dts/am3517-evm-ui.dtsi index e841918c1c..54aa2522aa 100644 --- a/arch/arm/dts/am3517-evm-ui.dtsi +++ b/arch/arm/dts/am3517-evm-ui.dtsi @@ -186,14 +186,14 @@ }; &mcbsp1 { - status = "ok"; + status = "okay"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp1_pins>; }; &mcbsp2 { - status = "ok"; + status = "okay"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp2_pins>; diff --git a/arch/arm/dts/am3517-evm.dts b/arch/arm/dts/am3517-evm.dts index 3527c0f2df..935c471c97 100644 --- a/arch/arm/dts/am3517-evm.dts +++ b/arch/arm/dts/am3517-evm.dts @@ -193,7 +193,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; diff --git a/arch/arm/dts/am437x-gp-evm.dts b/arch/arm/dts/am437x-gp-evm.dts index 3c500d52db..21f7691f49 100644 --- a/arch/arm/dts/am437x-gp-evm.dts +++ b/arch/arm/dts/am437x-gp-evm.dts @@ -742,7 +742,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_pins>; diff --git a/arch/arm/dts/am43x-epos-evm.dts b/arch/arm/dts/am43x-epos-evm.dts index 65f157ed59..b940bc6ccf 100644 --- a/arch/arm/dts/am43x-epos-evm.dts +++ b/arch/arm/dts/am43x-epos-evm.dts @@ -752,7 +752,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_pins>; diff --git a/arch/arm/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/dts/am57xx-beagle-x15-common.dtsi index d6b94d528f..1912ea9a15 100644 --- a/arch/arm/dts/am57xx-beagle-x15-common.dtsi +++ b/arch/arm/dts/am57xx-beagle-x15-common.dtsi @@ -528,13 +528,13 @@ }; &dss { - status = "ok"; + status = "okay"; vdda_video-supply = <&ldoln_reg>; }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&ldo4_reg>; port { @@ -545,7 +545,7 @@ }; &pcie1_rc { - status = "ok"; + status = "okay"; gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/da850-evm.dts b/arch/arm/dts/da850-evm.dts index f04bc3e153..b331cefd18 100644 --- a/arch/arm/dts/da850-evm.dts +++ b/arch/arm/dts/da850-evm.dts @@ -405,7 +405,7 @@ &aemif { pinctrl-names = "default"; pinctrl-0 = <&nand_pins>; - status = "ok"; + status = "okay"; cs3 { #address-cells = <2>; #size-cells = <1>; diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts index 43de9638e3..8e9a1a80a8 100644 --- a/arch/arm/dts/dra7-evm.dts +++ b/arch/arm/dts/dra7-evm.dts @@ -501,7 +501,7 @@ }; &dcan1 { - status = "ok"; + status = "okay"; pinctrl-names = "default", "sleep", "active"; pinctrl-0 = <&dcan1_pins_sleep>; pinctrl-1 = <&dcan1_pins_sleep>; diff --git a/arch/arm/dts/dra72-evm-common.dtsi b/arch/arm/dts/dra72-evm-common.dtsi index 2e485a13df..964e5e9b90 100644 --- a/arch/arm/dts/dra72-evm-common.dtsi +++ b/arch/arm/dts/dra72-evm-common.dtsi @@ -430,7 +430,7 @@ }; &dcan1 { - status = "ok"; + status = "okay"; pinctrl-names = "default", "sleep", "active"; pinctrl-0 = <&dcan1_pins_sleep>; pinctrl-1 = <&dcan1_pins_sleep>; @@ -499,11 +499,11 @@ }; &dss { - status = "ok"; + status = "okay"; }; &hdmi { - status = "ok"; + status = "okay"; port { hdmi_out: endpoint { diff --git a/arch/arm/dts/keystone-k2e-evm.dts b/arch/arm/dts/keystone-k2e-evm.dts index 9288df21ce..bb197e133e 100644 --- a/arch/arm/dts/keystone-k2e-evm.dts +++ b/arch/arm/dts/keystone-k2e-evm.dts @@ -142,7 +142,7 @@ }; &mdio { - status = "ok"; + status = "okay"; ethphy0: ethernet-phy@0 { compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; reg = <0>; diff --git a/arch/arm/dts/keystone-k2hk-evm.dts b/arch/arm/dts/keystone-k2hk-evm.dts index 84c58d75ad..acfcaff0a8 100644 --- a/arch/arm/dts/keystone-k2hk-evm.dts +++ b/arch/arm/dts/keystone-k2hk-evm.dts @@ -170,7 +170,7 @@ }; &mdio { - status = "ok"; + status = "okay"; ethphy0: ethernet-phy@0 { compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; reg = <0>; diff --git a/arch/arm/dts/keystone-k2l-evm.dts b/arch/arm/dts/keystone-k2l-evm.dts index 91cefdf2aa..ca049ba81b 100644 --- a/arch/arm/dts/keystone-k2l-evm.dts +++ b/arch/arm/dts/keystone-k2l-evm.dts @@ -119,7 +119,7 @@ }; &mdio { - status = "ok"; + status = "okay"; ethphy0: ethernet-phy@0 { compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; reg = <0>; diff --git a/arch/arm/dts/omap3-beagle-xm.dts b/arch/arm/dts/omap3-beagle-xm.dts index 0349fcc9dc..8461159baf 100644 --- a/arch/arm/dts/omap3-beagle-xm.dts +++ b/arch/arm/dts/omap3-beagle-xm.dts @@ -379,7 +379,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = < @@ -396,7 +396,7 @@ }; &venc { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; diff --git a/arch/arm/dts/omap3-beagle.dts b/arch/arm/dts/omap3-beagle.dts index 3ca8991a6c..4ceee2ba19 100644 --- a/arch/arm/dts/omap3-beagle.dts +++ b/arch/arm/dts/omap3-beagle.dts @@ -353,7 +353,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; @@ -367,7 +367,7 @@ }; &venc { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; @@ -380,7 +380,7 @@ }; &gpmc { - status = "ok"; + status = "okay"; ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */ /* Chip select 0 */ diff --git a/arch/arm/dts/omap3-igep0020-common.dtsi b/arch/arm/dts/omap3-igep0020-common.dtsi index ecbec23af4..d62481dacd 100644 --- a/arch/arm/dts/omap3-igep0020-common.dtsi +++ b/arch/arm/dts/omap3-igep0020-common.dtsi @@ -248,7 +248,7 @@ }; &dss { - status = "ok"; + status = "okay"; port { dpi_out: endpoint { diff --git a/arch/arm/dts/omap3-panel-sharp-ls037v7dw01.dtsi b/arch/arm/dts/omap3-panel-sharp-ls037v7dw01.dtsi index b8b9fcc41e..2dbb687d4d 100644 --- a/arch/arm/dts/omap3-panel-sharp-ls037v7dw01.dtsi +++ b/arch/arm/dts/omap3-panel-sharp-ls037v7dw01.dtsi @@ -46,7 +46,7 @@ }; &dss { - status = "ok"; + status = "okay"; port { dpi_out: endpoint { remote-endpoint = <&lcd_in>; diff --git a/arch/arm/dts/omap34xx.dtsi b/arch/arm/dts/omap34xx.dtsi index ac4f8795b7..a703d09736 100644 --- a/arch/arm/dts/omap34xx.dtsi +++ b/arch/arm/dts/omap34xx.dtsi @@ -69,7 +69,7 @@ }; &ssi { - status = "ok"; + status = "okay"; clocks = <&ssi_ssr_fck>, <&ssi_sst_fck>, diff --git a/arch/arm/dts/omap36xx.dtsi b/arch/arm/dts/omap36xx.dtsi index 6fb23ada1f..52e1b8ce0f 100644 --- a/arch/arm/dts/omap36xx.dtsi +++ b/arch/arm/dts/omap36xx.dtsi @@ -153,7 +153,7 @@ }; &ssi { - status = "ok"; + status = "okay"; clocks = <&ssi_ssr_fck>, <&ssi_sst_fck>, diff --git a/arch/arm/dts/omap4-panda-common.dtsi b/arch/arm/dts/omap4-panda-common.dtsi index 55ea8b6189..c124b20d46 100644 --- a/arch/arm/dts/omap4-panda-common.dtsi +++ b/arch/arm/dts/omap4-panda-common.dtsi @@ -546,7 +546,7 @@ }; &dss { - status = "ok"; + status = "okay"; port { dpi_out: endpoint { @@ -557,12 +557,12 @@ }; &dsi2 { - status = "ok"; + status = "okay"; vdd-supply = <&vcxio>; }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; port { diff --git a/arch/arm/dts/omap4-sdp.dts b/arch/arm/dts/omap4-sdp.dts index 91480ac1f3..28b989cfdb 100644 --- a/arch/arm/dts/omap4-sdp.dts +++ b/arch/arm/dts/omap4-sdp.dts @@ -648,11 +648,11 @@ }; &dss { - status = "ok"; + status = "okay"; }; &dsi1 { - status = "ok"; + status = "okay"; vdd-supply = <&vcxio>; port { @@ -677,7 +677,7 @@ }; &dsi2 { - status = "ok"; + status = "okay"; vdd-supply = <&vcxio>; port { @@ -702,7 +702,7 @@ }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; port { diff --git a/arch/arm/dts/omap5-board-common.dtsi b/arch/arm/dts/omap5-board-common.dtsi index 68ac04641b..1eedd8d706 100644 --- a/arch/arm/dts/omap5-board-common.dtsi +++ b/arch/arm/dts/omap5-board-common.dtsi @@ -743,11 +743,11 @@ }; &dss { - status = "ok"; + status = "okay"; }; &hdmi { - status = "ok"; + status = "okay"; /* vdda-supply populated in board specific dts file */ -- cgit v1.2.3 From fa7a14576dcdf8db6c0791ad346472bd8b0d8ee1 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Thu, 26 Aug 2021 21:28:57 +0530 Subject: arm: dts: k3-j721e-r5-*.dts: Fix clock-names property in the usb0 instance In the cdns3 usb driver, the clock name looked for is ref. Therefore, fix the clock-names property in usb0 instance for proper initialization of cdns3 usb gadget driver. Signed-off-by: Aswath Govindraju --- arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index a12607dc2f..4b2362a5dd 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -280,7 +280,7 @@ /delete-property/ assigned-clocks; /delete-property/ assigned-clock-parents; clocks = <&clk_19_2mhz>; - clock-names = "usb2_refclk"; + clock-names = "ref"; pinctrl-names = "default"; pinctrl-0 = <&main_usbss0_pins_default>; ti,vbus-divider; -- cgit v1.2.3 From 46596c653b7aa08eceef3b4ccea3c438144fd6f8 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 1 Aug 2021 18:54:15 -0600 Subject: ppc: Remove UCP1020 board This board has not been converted to CONFIG_DM_PCI by the deadline. Remove it. Note that we have to add CONFIG_SPIFLASH to scripts/config_whitelist.txt because it's not really migrated at this point. Acked-by: Michael Durrant Acked-by: Oleksandr Zhadan Acked-by: Oleksandr Zhadan and Michael Durrant Signed-off-by: Simon Glass [trini: Handle CONFIG_SPIFLASH differently and delete Kconfig file] Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc85xx/Kconfig | 7 - board/Arcturus/ucp1020/Kconfig | 36 -- board/Arcturus/ucp1020/MAINTAINERS | 7 - board/Arcturus/ucp1020/Makefile | 31 -- board/Arcturus/ucp1020/README | 54 --- board/Arcturus/ucp1020/cmd_arc.c | 408 ----------------- board/Arcturus/ucp1020/ddr.c | 161 ------- board/Arcturus/ucp1020/law.c | 24 - board/Arcturus/ucp1020/spl.c | 127 ------ board/Arcturus/ucp1020/spl_minimal.c | 67 --- board/Arcturus/ucp1020/tlb.c | 100 ----- board/Arcturus/ucp1020/ucp1020.c | 372 ---------------- board/Arcturus/ucp1020/ucp1020.h | 45 -- configs/UCP1020_defconfig | 58 --- include/configs/UCP1020.h | 832 ----------------------------------- scripts/config_whitelist.txt | 1 + 16 files changed, 1 insertion(+), 2329 deletions(-) delete mode 100644 board/Arcturus/ucp1020/Kconfig delete mode 100644 board/Arcturus/ucp1020/MAINTAINERS delete mode 100644 board/Arcturus/ucp1020/Makefile delete mode 100644 board/Arcturus/ucp1020/README delete mode 100644 board/Arcturus/ucp1020/cmd_arc.c delete mode 100644 board/Arcturus/ucp1020/ddr.c delete mode 100644 board/Arcturus/ucp1020/law.c delete mode 100644 board/Arcturus/ucp1020/spl.c delete mode 100644 board/Arcturus/ucp1020/spl_minimal.c delete mode 100644 board/Arcturus/ucp1020/tlb.c delete mode 100644 board/Arcturus/ucp1020/ucp1020.c delete mode 100644 board/Arcturus/ucp1020/ucp1020.h delete mode 100644 configs/UCP1020_defconfig delete mode 100644 include/configs/UCP1020.h (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 395423582a..66ebaf529f 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -178,12 +178,6 @@ config TARGET_KMCENT2 bool "Support kmcent2" select VENDOR_KM -config TARGET_UCP1020 - bool "Support uCP1020" - select ARCH_P1020 - imply CMD_SATA - imply PANIC_HANG - endchoice config ARCH_B4420 @@ -1147,6 +1141,5 @@ source "board/freescale/t208xrdb/Kconfig" source "board/freescale/t4rdb/Kconfig" source "board/keymile/Kconfig" source "board/socrates/Kconfig" -source "board/Arcturus/ucp1020/Kconfig" endmenu diff --git a/board/Arcturus/ucp1020/Kconfig b/board/Arcturus/ucp1020/Kconfig deleted file mode 100644 index fe2c3be1b7..0000000000 --- a/board/Arcturus/ucp1020/Kconfig +++ /dev/null @@ -1,36 +0,0 @@ -if TARGET_UCP1020 - -config SYS_BOARD - string - default "ucp1020" - -config SYS_VENDOR - string - default "Arcturus" - -config SYS_CONFIG_NAME - string - default "UCP1020" - -choice - prompt "Target image select" - -config TARGET_UCP1020_NOR - bool "NOR flash u-boot image" - -config TARGET_UCP1020_SPIFLASH - bool "SPI flash u-boot image" - -endchoice - -if TARGET_UCP1020_SPIFLASH -config UCBOOT - bool - default y - -config SPIFLASH - bool - default y -endif - -endif diff --git a/board/Arcturus/ucp1020/MAINTAINERS b/board/Arcturus/ucp1020/MAINTAINERS deleted file mode 100644 index e4a4718188..0000000000 --- a/board/Arcturus/ucp1020/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -UCP1020 BOARD -M: Oleksandr Zhadan and Michael Durrant -S: Maintained -F: board/Arcturus/ucp1020/ -F: include/configs/UCP1020.h -F: configs/UCP1020_defconfig -F: configs/UCP1020_SPIFLASH_defconfig diff --git a/board/Arcturus/ucp1020/Makefile b/board/Arcturus/ucp1020/Makefile deleted file mode 100644 index 46d04fb78c..0000000000 --- a/board/Arcturus/ucp1020/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2013-2015 Arcturus Networks, Inc. -# based on board/freescale/p1_p2_rdb_pc/Makefile -# original copyright follows: -# Copyright 2010-2011 Freescale Semiconductor, Inc. - -MINIMAL= - -ifdef CONFIG_SPL_BUILD -ifdef CONFIG_SPL_INIT_MINIMAL -MINIMAL=y -endif -endif - -ifdef MINIMAL - -obj-y += spl_minimal.o tlb.o law.o - -else -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -endif - -obj-y += ucp1020.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o -obj-y += cmd_arc.o - -endif diff --git a/board/Arcturus/ucp1020/README b/board/Arcturus/ucp1020/README deleted file mode 100644 index 555c4ef79f..0000000000 --- a/board/Arcturus/ucp1020/README +++ /dev/null @@ -1,54 +0,0 @@ -The uCP1020 product family (ucp1020) is an Arcturus Networks Inc. System on Modules -product featuring a Freescale P1020 CPU, optionally populated with 1, 2 or 3 Gig-Ethernet PHYs, -DDR3, NOR Flash, eMMC NAND Flash and/or SPI Flash. - -Information on the generic product family can be found here: - http://www.arcturusnetworks.com/products/ucp1020 - -The UCP1020 several configurable options -======================================== - -- the selection of populated phy(s): - KSZ9031 (current default for eTSEC 1 and 3) - -- the selection of boot location: - SPI Flash or NOR flash - -The UCP1020 includes 2 default configurations -============================================= -NOR boot image: - configs/UCP1020_defconfig -SPI boot image: - configs/UCP1020_SPIFLASH_defconfig - -The UCP1020 adds an additional command in cmd_arc.c to access and program -SPI resident factory defaults for serial number, and 1, 2 or 3 Ethernet -HW Addresses. - - -Build example -============= - -make distclean -make UCP1020_defconfig -make - -Default Scripts -=============== -A default upgrade scripts is included in the default environment variable example: - -B$ run tftpflash - -Dual Environment -================ - -This build enables dual / failover environment environment. - -NOR Flash Partition declarations and scripts -============================================ -Several scripts are available to allow TFTP of images and programming directly -into defined NOR flash partitions. Examples: - -B$ run program0 -B$ run program1 -B$ run program2 diff --git a/board/Arcturus/ucp1020/cmd_arc.c b/board/Arcturus/ucp1020/cmd_arc.c deleted file mode 100644 index 4b30b66e20..0000000000 --- a/board/Arcturus/ucp1020/cmd_arc.c +++ /dev/null @@ -1,408 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Command for accessing Arcturus factory environment. - * - * Copyright 2013-2019 Arcturus Networks Inc. - * https://www.arcturusnetworks.com/products/ - * by Oleksandr G Zhadan et al. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static ulong fwenv_addr[MAX_FWENV_ADDR]; -const char mystrerr[] = "ERROR: Failed to save factory info"; - -static int ishwaddr(char *hwaddr) -{ - if (strlen(hwaddr) == MAX_HWADDR_SIZE) - if (hwaddr[2] == ':' && - hwaddr[5] == ':' && - hwaddr[8] == ':' && - hwaddr[11] == ':' && - hwaddr[14] == ':') - return 0; - return -1; -} - -#if (FWENV_TYPE == FWENV_MMC) - -static char smac[29][18] __attribute__ ((aligned(0x200))); /* 1 MMC block is 512 bytes */ - -int set_mmc_arc_product(int argc, char *const argv[]) -{ - struct mmc *mmc; - u32 blk, cnt, n; - int i, err = 1; - void *addr; - const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV; - - mmc = find_mmc_device(mmc_dev_num); - if (!mmc) { - printf("No SD/MMC/eMMC card found\n"); - return 0; - } - if (mmc_init(mmc)) { - printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC", - mmc_dev_num); - return 0; - } - if (mmc_getwp(mmc) == 1) { - printf("Error: card is write protected!\n"); - return CMD_RET_FAILURE; - } - - /* Save factory defaults */ - addr = (void *)smac; - cnt = 1; /* One 512 bytes block */ - - for (i = 0; i < MAX_FWENV_ADDR; i++) - if (fwenv_addr[i] != -1) { - blk = fwenv_addr[i] / 512; - n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr); - if (n != cnt) - printf("%s: %s [%d]\n", __func__, mystrerr, i); - else - err = 0; - } - if (err) - return -2; - - return err; -} - -static int read_mmc_arc_info(void) -{ - struct mmc *mmc; - u32 blk, cnt, n; - int i; - void *addr; - const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV; - - mmc = find_mmc_device(mmc_dev_num); - if (!mmc) { - printf("No SD/MMC/eMMC card found\n"); - return 0; - } - if (mmc_init(mmc)) { - printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC", - mmc_dev_num); - return 0; - } - - addr = (void *)smac; - cnt = 1; /* One 512 bytes block */ - - for (i = 0; i < MAX_FWENV_ADDR; i++) - if (fwenv_addr[i] != -1) { - blk = fwenv_addr[i] / 512; - n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr); - flush_cache((ulong) addr, 512); - if (n == cnt) - return (i + 1); - } - return 0; -} -#endif - -#if (FWENV_TYPE == FWENV_SPI_FLASH) - -static struct spi_flash *flash; -static char smac[4][18]; - -int set_spi_arc_product(int argc, char *const argv[]) -{ - int i, err = 1; - - flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, - CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); - if (!flash) { - printf("Failed to initialize SPI flash at %u:%u\n", - CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS); - return -1; - } - - /* Save factory defaults */ - for (i = 0; i < MAX_FWENV_ADDR; i++) - if (fwenv_addr[i] != -1) - if (spi_flash_write - (flash, fwenv_addr[i], sizeof(smac), smac)) - printf("%s: %s [%d]\n", __func__, mystrerr, i); - else - err = 0; - if (err) - return -2; - - return err; -} - -static int read_spi_arc_info(void) -{ - int i; - - flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, - CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); - if (!flash) { - printf("Failed to initialize SPI flash at %u:%u\n", - CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS); - return 0; - } - for (i = 0; i < MAX_FWENV_ADDR; i++) - if (fwenv_addr[i] != -1) - if (!spi_flash_read - (flash, fwenv_addr[i], sizeof(smac), smac)) - return (i + 1); - return 0; -} -#endif - -#if (FWENV_TYPE == FWENV_NOR_FLASH) - -static char smac[4][18]; - -int set_nor_arc_product(int argc, char *const argv[]) -{ - int i, err = 1; - - /* Save factory defaults */ - for (i = 0; i < MAX_FWENV_ADDR; i++) - if (fwenv_addr[i] != -1) { - ulong fwenv_end = fwenv_addr[i] + 4; - - flash_sect_roundb(&fwenv_end); - flash_sect_protect(0, fwenv_addr[i], fwenv_end); - if (flash_write - ((char *)smac, fwenv_addr[i], sizeof(smac))) - printf("%s: %s [%d]\n", __func__, mystrerr, i); - else - err = 0; - flash_sect_protect(1, fwenv_addr[i], fwenv_end); - } - if (err) - return -2; - - return err; -} - -static int read_nor_arc_info(void) -{ - int i; - - for (i = 0; i < MAX_FWENV_ADDR; i++) - if (fwenv_addr[i] != -1) { - memcpy(smac, (void *)fwenv_addr[i], sizeof(smac)); - return (i + 1); - } - - return 0; -} -#endif - -int set_arc_product(int argc, char *const argv[]) -{ - if (argc != 5) - return -1; - - /* Check serial number */ - if (strlen(argv[1]) != MAX_SERIAL_SIZE) - return -1; - - /* Check HWaddrs */ - if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4])) - return -1; - - strcpy(smac[0], argv[1]); - strcpy(smac[1], argv[2]); - strcpy(smac[2], argv[3]); - strcpy(smac[3], argv[4]); - -#if (FWENV_TYPE == FWENV_NOR_FLASH) - return set_nor_arc_product(argc, argv); -#endif -#if (FWENV_TYPE == FWENV_SPI_FLASH) - return set_spi_arc_product(argc, argv); -#endif -#if (FWENV_TYPE == FWENV_MMC) - return set_mmc_arc_product(argc, argv); -#endif - return -2; -} - -static int read_arc_info(void) -{ -#if (FWENV_TYPE == FWENV_NOR_FLASH) - return read_nor_arc_info(); -#endif -#if (FWENV_TYPE == FWENV_SPI_FLASH) - return read_spi_arc_info(); -#endif -#if (FWENV_TYPE == FWENV_MMC) - return read_mmc_arc_info(); -#endif - return 0; -} - -static int do_get_arc_info(void) -{ - int l = read_arc_info(); - char *oldserial = env_get("SERIAL"); - char *oldversion = env_get("VERSION"); - - if (oldversion != NULL) - if (strcmp(oldversion, U_BOOT_VERSION) != 0) - oldversion = NULL; - - if (l == 0) { - printf("%s: failed to read factory info\n", __func__); - return -2; - } - - printf("\rSERIAL: "); - if (smac[0][0] == EMPY_CHAR) { - printf("\n"); - } else { - printf("%s\n", smac[0]); - env_set("SERIAL", smac[0]); - } - - if (strcmp(smac[1], "00:00:00:00:00:00") == 0) { - env_set("ethaddr", NULL); - env_set("eth1addr", NULL); - env_set("eth2addr", NULL); - goto done; - } - - printf("HWADDR0: "); - if (smac[1][0] == EMPY_CHAR) { - printf("\n"); - } else { - char *ret = env_get("ethaddr"); - - if (ret == NULL) { - env_set("ethaddr", smac[1]); - printf("%s\n", smac[1]); - } else if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) { - env_set("ethaddr", smac[1]); - printf("%s (factory)\n", smac[1]); - } else { - printf("%s\n", ret); - } - } - - if (strcmp(smac[2], "00:00:00:00:00:00") == 0) { - env_set("eth1addr", NULL); - env_set("eth2addr", NULL); - goto done; - } - - printf("HWADDR1: "); - if (smac[2][0] == EMPY_CHAR) { - printf("\n"); - } else { - char *ret = env_get("eth1addr"); - - if (ret == NULL) { - env_set("ethaddr", smac[2]); - printf("%s\n", smac[2]); - } else if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) { - env_set("eth1addr", smac[2]); - printf("%s (factory)\n", smac[2]); - } else { - printf("%s\n", ret); - } - } - - if (strcmp(smac[3], "00:00:00:00:00:00") == 0) { - env_set("eth2addr", NULL); - goto done; - } - - printf("HWADDR2: "); - if (smac[3][0] == EMPY_CHAR) { - printf("\n"); - } else { - char *ret = env_get("eth2addr"); - - if (ret == NULL) { - env_set("ethaddr", smac[3]); - printf("%s\n", smac[3]); - } else if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) { - env_set("eth2addr", smac[3]); - printf("%s (factory)\n", smac[3]); - } else { - printf("%s\n", ret); - } - } -done: - if (oldserial == NULL || oldversion == NULL) { - if (oldversion == NULL) - env_set("VERSION", U_BOOT_VERSION); - env_save(); - } - - return 0; -} - -static int init_fwenv(void) -{ - int i, ret = -1; - - fwenv_addr[0] = FWENV_ADDR1; - fwenv_addr[1] = FWENV_ADDR2; - fwenv_addr[2] = FWENV_ADDR3; - fwenv_addr[3] = FWENV_ADDR4; - - for (i = 0; i < MAX_FWENV_ADDR; i++) - if (fwenv_addr[i] != -1) - ret = 0; - if (ret) - printf("%s: No firmfare info storage address is defined\n", - __func__); - return ret; -} - -void get_arc_info(void) -{ - if (!init_fwenv()) - do_get_arc_info(); -} - -static int do_arc_cmd(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - const char *cmd; - int ret = -1; - - cmd = argv[1]; - --argc; - ++argv; - - if (init_fwenv()) - return ret; - - if (strcmp(cmd, "product") == 0) - ret = set_arc_product(argc, argv); - else if (strcmp(cmd, "info") == 0) - ret = do_get_arc_info(); - - if (ret == -1) - return CMD_RET_USAGE; - - return ret; -} - -U_BOOT_CMD(arc, 6, 1, do_arc_cmd, - "Arcturus product command sub-system", - "product serial hwaddr0 hwaddr1 hwaddr2 - save Arcturus factory env\n" - "info - show Arcturus factory env\n\n"); diff --git a/board/Arcturus/ucp1020/ddr.c b/board/Arcturus/ucp1020/ddr.c deleted file mode 100644 index a3285ebe5c..0000000000 --- a/board/Arcturus/ucp1020/ddr.c +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013-2015 Arcturus Networks, Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ - * based on board/freescale/p1_p2_rdb_pc/spl.c - * original copyright follows: - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_SYS_DDR_RAW_TIMING -#if defined(CONFIG_UCP1020) || defined(CONFIG_UCP1020T1) -/* - * Micron MT41J128M16HA-15E - * */ -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 536870912u, - .capacity = 536870912u, - .primary_sdram_width = 32, - .ec_sdram_width = 8, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 14, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 2, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 1650, - .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */ - .taa_ps = 14050, - .twr_ps = 15000, - .trcd_ps = 13500, - .trrd_ps = 75000, - .trp_ps = 13500, - .tras_ps = 40000, - .trc_ps = 49500, - .trfc_ps = 160000, - .twtr_ps = 75000, - .trtp_ps = 75000, - .refresh_rate_ps = 7800000, - .tfaw_ps = 30000, -}; - -#else -#error Missing raw timing data for this board -#endif - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - const char dimm_model[] = "Fixed DDR on board"; - - if ((controller_number == 0) && (dimm_number == 0)) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} -#endif /* CONFIG_SYS_DDR_RAW_TIMING */ - -#ifdef CONFIG_SYS_DDR_CS0_BNDS -/* Fixed sdram init -- doesn't use serial presence detect. */ -phys_size_t fixed_sdram(void) -{ - sys_info_t sysinfo; - char buf[32]; - size_t ddr_size; - fsl_ddr_cfg_regs_t ddr_cfg_regs = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, -#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, -#endif - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL, - .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 - }; - - get_sys_info(&sysinfo); - printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, sysinfo.freq_ddrbus)); - - ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); - - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - ddr_size, LAW_TRGT_IF_DDR_1) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - }; - - return ddr_size; -} -#endif - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - int i; - - popts->clk_adjust = 6; - popts->cpo_override = 0x1f; - popts->write_data_delay = 2; - popts->half_strength_driver_enable = 1; - /* Write leveling override */ - popts->wrlvl_en = 1; - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - popts->wrlvl_start = 0x8; - popts->trwt_override = 1; - popts->trwt = 0; - - if (pdimm->primary_sdram_width == 64) - popts->data_bus_width = 0; - else if (pdimm->primary_sdram_width == 32) - popts->data_bus_width = 1; - else - printf("Error in DDR bus width configuration!\n"); - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; - popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; - } -} diff --git a/board/Arcturus/ucp1020/law.c b/board/Arcturus/ucp1020/law.c deleted file mode 100644 index cb53692a32..0000000000 --- a/board/Arcturus/ucp1020/law.c +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013-2015 Arcturus Networks, Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ - * based on board/freescale/p1_p2_rdb_pc/spl.c - * original copyright follows: - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct law_entry law_table[] = { -#ifdef CONFIG_VSC7385_ENET - SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -#endif - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/Arcturus/ucp1020/spl.c b/board/Arcturus/ucp1020/spl.c deleted file mode 100644 index f7c4960da7..0000000000 --- a/board/Arcturus/ucp1020/spl.c +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013-2015 Arcturus Networks, Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ - * based on board/freescale/p1_p2_rdb_pc/spl.c - * original copyright follows: - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static const u32 sysclk_tbl[] = { - 66666000, 7499900, 83332500, 8999900, - 99999000, 11111000, 12499800, 13333200 -}; - -phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_L2_SIZE; -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio, bus_clk; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - - console_init_f(); - - /* Set pmuxcr to allow both i2c1 and i2c2 */ - setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); - setbits_be32(&gur->pmuxcr, - in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); - - /* Read back the register to synchronize the write. */ - in_be32(&gur->pmuxcr); - -#ifdef CONFIG_SPL_SPI_BOOT - clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); -#endif - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; - gd->bus_clk = bus_clk; - - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, - bus_clk / 16 / CONFIG_BAUDRATE); -#ifdef CONFIG_SPL_MMC_BOOT - puts("\nSD boot...\n"); -#elif defined(CONFIG_SPL_SPI_BOOT) - puts("\nSPI Flash boot...\n"); -#endif - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *)CONFIG_SPL_GD_ADDR; - struct bd_info *bd; - - memset(gd, 0, sizeof(gd_t)); - bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); - memset(bd, 0, sizeof(struct bd_info)); - gd->bd = bd; - - arch_cpu_init(); - get_clocks(); - mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, - CONFIG_SPL_RELOC_MALLOC_SIZE); - -#ifndef CONFIG_SPL_NAND_BOOT - env_init(); -#endif -#ifdef CONFIG_SPL_MMC_BOOT - mmc_initialize(bd); -#endif - /* relocate environment function pointers etc. */ -#ifdef CONFIG_SPL_NAND_BOOT - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_ENV_ADDR); - gd->env_addr = (ulong)(CONFIG_ENV_ADDR); - gd->env_valid = ENV_VALID; -#else - env_relocate(); -#endif - -#ifdef CONFIG_SYS_I2C_LEGACY - i2c_init_all(); -#else - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - - dram_init(); -#ifdef CONFIG_SPL_NAND_BOOT - puts("Tertiary program loader running in sram..."); -#else - puts("Second program loader running in sram...\n"); -#endif - -#ifdef CONFIG_SPL_MMC_BOOT - mmc_boot(); -#elif defined(CONFIG_SPL_NAND_BOOT) - nand_boot(); -#endif -} diff --git a/board/Arcturus/ucp1020/spl_minimal.c b/board/Arcturus/ucp1020/spl_minimal.c deleted file mode 100644 index 90abec9cce..0000000000 --- a/board/Arcturus/ucp1020/spl_minimal.c +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013-2015 Arcturus Networks, Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ - * based on board/freescale/p1_p2_rdb_pc/spl_minimal.c - * original copyright follows: - * Copyright 2011 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - -#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) - set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); -#endif - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; - - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, - gd->bus_clk / 16 / CONFIG_BAUDRATE); - - puts("\nNAND boot... "); - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - puts("\nSecond program loader running in sram..."); - nand_boot(); -} - -void putc(char c) -{ - if (c == '\n') - ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r'); - - ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c); -} - -void puts(const char *str) -{ - while (*str) - putc(*str++); -} diff --git a/board/Arcturus/ucp1020/tlb.c b/board/Arcturus/ucp1020/tlb.c deleted file mode 100644 index 2c07df63e5..0000000000 --- a/board/Arcturus/ucp1020/tlb.c +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013-2015 Arcturus Networks, Inc - * http://www.arcturusnetworks.com/products/ucp1020/ - * based on board/freescale/p1_p2_rdb_pc/tlb.c - * original copyright follows: - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - -#ifndef CONFIG_SPL_BUILD - /* W**G* - Flash/promjet, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX | MAS3_SR, MAS2_W | MAS2_G, - 0, 2, BOOKE_PAGESZ_64M, 1), - -#ifdef CONFIG_PCI - /* *I*G* - PCI memory 1.5G */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI I/O effective: 192K */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 4, BOOKE_PAGESZ_256K, 1), -#endif - -#ifdef CONFIG_VSC7385_ENET - /* *I*G - VSC7385 Switch */ - SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 5, BOOKE_PAGESZ_1M, 1), -#endif -#endif /* not SPL */ - -#ifdef CONFIG_SYS_NAND_BASE - /* *I*G - NAND */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 7, BOOKE_PAGESZ_1M, 1), -#endif - -#if defined(CONFIG_SYS_RAMBOOT) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) - /* *I*G - eSDHC/eSPI/NAND boot */ - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, - 0, 8, BOOKE_PAGESZ_1G, 1), - -#endif /* RAMBOOT/SPL */ - -#ifdef CONFIG_SYS_INIT_L2_ADDR - /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G, - 0, 11, BOOKE_PAGESZ_256K, 1), -#if CONFIG_SYS_L2_SIZE >= (256 << 10) - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 12, BOOKE_PAGESZ_256K, 1) -#endif -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/Arcturus/ucp1020/ucp1020.c b/board/Arcturus/ucp1020/ucp1020.c deleted file mode 100644 index ee8a9e0a5e..0000000000 --- a/board/Arcturus/ucp1020/ucp1020.c +++ /dev/null @@ -1,372 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013-2019 Arcturus Networks, Inc. - * https://www.arcturusnetworks.com/products/ucp1020/ - * by Oleksandr G Zhadan et al. - * based on board/freescale/p1_p2_rdb_pc/spl.c - * original copyright follows: - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ucp1020.h" - -void spi_set_speed(struct spi_slave *slave, uint hz) -{ - /* TO DO: It's actially have to be in spi/ */ -} - -/* - * To be compatible with cmd_gpio - */ -int name_to_gpio(const char *name) -{ - int gpio = 31 - dectoul(name, NULL); - - if (gpio < 16) - gpio = -1; - - return gpio; -} - -void board_gpio_init(void) -{ - int i; - char envname[8], *val; - - for (i = 0; i < GPIO_MAX_NUM; i++) { - sprintf(envname, "GPIO%d", i); - val = env_get(envname); - if (val) { - char direction = toupper(val[0]); - char level = toupper(val[1]); - - if (direction == 'I') { - gpio_direction_input(i); - } else { - if (direction == 'O') { - if (level == '1') - gpio_direction_output(i, 1); - else - gpio_direction_output(i, 0); - } - } - } - } - - val = env_get("PCIE_OFF"); - if (val) { - gpio_direction_input(GPIO_PCIE1_EN); - gpio_direction_input(GPIO_PCIE2_EN); - } else { - gpio_direction_output(GPIO_PCIE1_EN, 1); - gpio_direction_output(GPIO_PCIE2_EN, 1); - } - - val = env_get("SDHC_CDWP_OFF"); - if (!val) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - setbits_be32(&gur->pmuxcr, - (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); - } -} - -int board_early_init_f(void) -{ - return 0; /* Just in case. Could be disable in config file */ -} - -int checkboard(void) -{ - printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL); - board_gpio_init(); -#ifdef CONFIG_MMC - printf("SD/MMC: 4-bit Mode\n"); -#endif - - return 0; -} - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} -#endif - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */ - 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */ - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ -#if defined(CONFIG_PHY_MICREL_KSZ9021) - int regval; - static int cnt; - - if (cnt++ == 0) - printf("PHYs address ["); - - if (phydev->addr == TSEC1_PHY_ADDR || phydev->addr == TSEC3_PHY_ADDR) { - regval = - ksz9021_phy_extended_read(phydev, - MII_KSZ9021_EXT_STRAP_STATUS); - /* - * min rx data delay - */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, - 0x6666); - /* - * max rx/tx clock delay, min rx/tx control - */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, - 0xf6f6); - printf("0x%x", (regval & 0x1f)); - } else { - printf("0x%x", (TSEC2_PHY_ADDR & 0x1f)); - } - if (cnt == 3) - printf("] "); - else - printf(","); -#endif - -#if defined(CONFIG_PHY_MICREL_KSZ9031_DEBUG) - regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000); - if (regval >= 0) - printf(" (ADDR 0x%x) ", regval & 0x1f); -#endif - - return 0; -} - -int last_stage_init(void) -{ - static char newkernelargs[256]; - static u8 id1[16]; - static u8 id2; -#ifdef CONFIG_MMC - struct mmc *mmc; -#endif - char *sval, *kval; - - if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) { - printf("Error reading i2c IDT6V49205B information!\n"); - } else { - printf("IDT6V49205B(0x%02x): ready\n", id1[1]); - i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2); - if (!(id1[1] & 0x02)) { - id1[1] |= 0x02; - i2c_write(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2); - asm("nop; nop"); - } - } - - if (i2c_read(CONFIG_SYS_I2C_NCT72_ADDR, 0xFE, 1, &id2, 1) < 0) - printf("Error reading i2c NCT72 information!\n"); - else - printf("NCT72(0x%x): ready\n", id2); - - kval = env_get("kernelargs"); - -#ifdef CONFIG_MMC - mmc = find_mmc_device(0); - if (mmc) - if (!mmc_init(mmc)) { - printf("MMC/SD card detected\n"); - if (kval) { - int n = strlen(defkargs); - char *tmp = strstr(kval, defkargs); - - *tmp = 0; - strcpy(newkernelargs, kval); - strcat(newkernelargs, " "); - strcat(newkernelargs, mmckargs); - strcat(newkernelargs, " "); - strcat(newkernelargs, &tmp[n]); - env_set("kernelargs", newkernelargs); - } else { - env_set("kernelargs", mmckargs); - } - } -#endif - get_arc_info(); - - if (kval) { - sval = env_get("SERIAL"); - if (sval) { - strcpy(newkernelargs, "SN="); - strcat(newkernelargs, sval); - strcat(newkernelargs, " "); - strcat(newkernelargs, kval); - env_set("kernelargs", newkernelargs); - } - } else { - printf("Error reading kernelargs env variable!\n"); - } - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; -#ifdef CONFIG_TSEC2 - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#endif - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - if (is_serdes_configured(SGMII_TSEC2)) { - if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII2_DIS)) { - puts("eTSEC2 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII; - } - } - num++; -#endif -#ifdef CONFIG_TSEC3 - SET_STD_TSEC_INFO(tsec_info[num], 3); - num++; -#endif - - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); - - return pci_eth_init(bis); -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - phys_addr_t base; - phys_size_t size; - const char *soc_usb_compat = "fsl-usb2-dr"; - int err, usb1_off, usb2_off; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - - FT_FSL_PCI_SETUP; - -#if defined(CONFIG_HAS_FSL_DR_USB) - fsl_fdt_fixup_dr_usb(blob, bd); -#endif - -#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) - /* Delete eLBC node as it is muxed with USB2 controller */ - if (hwconfig("usb2")) { - const char *soc_elbc_compat = "fsl,p1020-elbc"; - int off = fdt_node_offset_by_compatible(blob, -1, - soc_elbc_compat); - if (off < 0) { - printf - ("WARNING: could not find compatible node %s: %s\n", - soc_elbc_compat, fdt_strerror(off)); - return off; - } - err = fdt_del_node(blob, off); - if (err < 0) { - printf("WARNING: could not remove %s: %s\n", - soc_elbc_compat, fdt_strerror(err)); - } - return err; - } -#endif - -/* Delete USB2 node as it is muxed with eLBC */ - usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat); - if (usb1_off < 0) { - printf("WARNING: could not find compatible node %s: %s.\n", - soc_usb_compat, fdt_strerror(usb1_off)); - return usb1_off; - } - usb2_off = - fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat); - if (usb2_off < 0) { - printf("WARNING: could not find compatible node %s: %s.\n", - soc_usb_compat, fdt_strerror(usb2_off)); - return usb2_off; - } - err = fdt_del_node(blob, usb2_off); - if (err < 0) { - printf("WARNING: could not remove %s: %s.\n", - soc_usb_compat, fdt_strerror(err)); - } - return 0; -} -#endif diff --git a/board/Arcturus/ucp1020/ucp1020.h b/board/Arcturus/ucp1020/ucp1020.h deleted file mode 100644 index 1b527cdb1c..0000000000 --- a/board/Arcturus/ucp1020/ucp1020.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013-2019 Arcturus Networks, Inc. - * https://www.arcturusnetworks.com/products/ucp1020/ - * by Oleksandr G Zhadan et al. - */ - -#ifndef __UCP1020_H__ -#define __UCP1020_H__ - -#define GPIO0 31 -#define GPIO1 30 -#define GPIO2 29 -#define GPIO3 28 -#define GPIO4 27 -#define GPIO5 26 -#define GPIO6 25 -#define GPIO7 24 -#define GPIO8 23 -#define GPIO9 22 -#define GPIO10 21 -#define GPIO11 20 -#define GPIO12 19 -#define GPIO13 18 -#define GPIO14 17 -#define GPIO15 16 -#define GPIO_MAX_NUM 16 - -#define GPIO_SDHC_CD GPIO8 -#define GPIO_SDHC_WP GPIO9 -#define GPIO_USB_PCTL0 GPIO10 -#define GPIO_PCIE1_EN GPIO11 -#define GPIO_PCIE2_EN GPIO10 -#define GPIO_USB_PCTL1 GPIO11 - -#define GPIO_WD GPIO15 - -#ifdef CONFIG_MMC -static char *defkargs = "root=/dev/mtdblock1 rootfstype=cramfs ro"; -static char *mmckargs = "root=/dev/mmcblk0p1 rootwait rw"; -#endif - -int get_arc_info(void); - -#endif diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig deleted file mode 100644 index 1fdb1952c8..0000000000 --- a/configs/UCP1020_defconfig +++ /dev/null @@ -1,58 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF80000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_UCP1020=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"\" to stop\n" -CONFIG_AUTOBOOT_STOP_STR="\x1b" -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_LAST_STAGE_INIT=y -# CONFIG_MISC_INIT_R is not set -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="B$ " -CONFIG_CMD_IMLS=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_PCI is not set -# CONFIG_CMD_SATA is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_CRAMFS=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEC0C0000 -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_FS_CRAMFS=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h deleted file mode 100644 index d9a777ea1a..0000000000 --- a/include/configs/UCP1020.h +++ /dev/null @@ -1,832 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013-2019 Arcturus Networks, Inc. - * https://www.arcturusnetworks.com/products/ucp1020/ - * based on include/configs/p1_p2_rdb_pc.h - * original copyright follows: - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -/* - * QorIQ uCP1020-xx boards configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/*** Arcturus FirmWare Environment */ - -#define MAX_SERIAL_SIZE 15 -#define MAX_HWADDR_SIZE 17 - -#define MAX_FWENV_ADDR 4 - -#define FWENV_MMC 1 -#define FWENV_SPI_FLASH 2 -#define FWENV_NOR_FLASH 3 -/* - #define FWENV_TYPE FWENV_MMC - #define FWENV_TYPE FWENV_SPI_FLASH -*/ -#define FWENV_TYPE FWENV_NOR_FLASH - -#if (FWENV_TYPE == FWENV_MMC) -#define FWENV_ADDR1 -1 -#define FWENV_ADDR2 -1 -#define FWENV_ADDR3 -1 -#define FWENV_ADDR4 -1 -#define EMPY_CHAR 0 -#endif - -#if (FWENV_TYPE == FWENV_SPI_FLASH) -#ifndef CONFIG_SF_DEFAULT_SPEED -#define CONFIG_SF_DEFAULT_SPEED 1000000 -#endif -#ifndef CONFIG_SF_DEFAULT_MODE -#define CONFIG_SF_DEFAULT_MODE SPI_MODE0 -#endif -#ifndef CONFIG_SF_DEFAULT_CS -#define CONFIG_SF_DEFAULT_CS 0 -#endif -#ifndef CONFIG_SF_DEFAULT_BUS -#define CONFIG_SF_DEFAULT_BUS 0 -#endif -#define FWENV_ADDR1 (0x200 - sizeof(smac)) -#define FWENV_ADDR2 (0x400 - sizeof(smac)) -#define FWENV_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac)) -#define FWENV_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac)) -#define EMPY_CHAR 0xff -#endif - -#if (FWENV_TYPE == FWENV_NOR_FLASH) -#define FWENV_ADDR1 0xEC080000 -#define FWENV_ADDR2 -1 -#define FWENV_ADDR3 -1 -#define FWENV_ADDR4 -1 -#define EMPY_CHAR 0xff -#endif -/***********************************/ - -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#if defined(CONFIG_TARTGET_UCP1020T1) - -#define CONFIG_UCP1020_REV_1_3 - -#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" - -#define CONFIG_TSEC1 -#define CONFIG_TSEC3 -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF -#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE -#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD -#define CONFIG_IPADDR 10.80.41.229 -#define CONFIG_SERVERIP 10.80.41.227 -#define CONFIG_NETMASK 255.255.252.0 -#define CONFIG_ETHPRIME "eTSEC3" - -#define CONFIG_SYS_L2_SIZE (256 << 10) - -#endif - -#if defined(CONFIG_TARGET_UCP1020) - -#define CONFIG_UCP1020 -#define CONFIG_UCP1020_REV_1_3 - -#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" - -#define CONFIG_TSEC1 -#define CONFIG_TSEC3 -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF -#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE -#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD -#define CONFIG_IPADDR 192.168.1.81 -#define CONFIG_IPADDR1 192.168.1.82 -#define CONFIG_IPADDR2 192.168.1.83 -#define CONFIG_SERVERIP 192.168.1.80 -#define CONFIG_GATEWAYIP 102.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_ETHPRIME "eTSEC1" - -#define CONFIG_SYS_L2_SIZE (256 << 10) - -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc -#endif - -#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000 - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_LBA48 - -#define CONFIG_SYS_CLK_FREQ 66666666 -#define CONFIG_DDR_CLK_FREQ 66666666 - -#define CONFIG_HWCONFIG - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE -#define CONFIG_BTB - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k - SPL code*/ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* DDR Setup */ -#define CONFIG_DDR_ECC_ENABLE -#ifndef CONFIG_DDR_ECC_ENABLE -#define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_DDR_SPD -#endif -#define CONFIG_SYS_SPD_BUS_NUM 1 - -#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 -#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 - -/* Default settings for DDR3 */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 - -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 - -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#ifdef CONFIG_DDR_ECC_ENABLE -#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */ -#else -#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ -#endif -#define CONFIG_SYS_DDR_CONTROL_2 0x04401050 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03402400 - -#define CONFIG_SYS_DDR_TIMING_3 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0 0x00330004 -#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 -#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF -#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 -#define CONFIG_SYS_DDR_MODE_1 0x40461520 -#define CONFIG_SYS_DDR_MODE_2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x0C300000 - -/* - * Memory map - * - * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable - * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2) - * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 - * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable - * (early boot only) - * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ -#define CONFIG_SYS_FLASH_BASE 0xec000000 - -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE - -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ - | BR_PS_16 | BR_V) - -#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -/* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -/* Size of used area in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ - -#define CONFIG_SYS_PMC_BASE 0xff980000 -#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE -#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ - BR_PS_8 | BR_V) -#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ - OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ - OR_GPCM_EAD) - -#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ -#ifdef CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ -#endif - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } -#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ - -#define CONFIG_RTC_DS1337 -#define CONFIG_RTC_DS1337_NOOSC -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 -#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C -#define CONFIG_SYS_I2C_IDT6V49205B 0x69 - -#if defined(CONFIG_PCI) -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -/* controller 2, direct to uli, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9" -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ - -/* controller 1, Slot 2, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* - * Environment - */ -#if !defined(CONFIG_ENV_FIT_UCBOOT) && defined(CONFIG_RAMBOOT_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#endif - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * USB - */ -#define CONFIG_HAS_FSL_DR_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 - -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#endif -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#endif - -/* Misc Extra Settings */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) - -#if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3) -#else -#error "UCP1020 module revision is not defined !!!" -#endif - -#define CONFIG_BOOTP_SERVERIP - -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 4 -#define TSEC2_PHY_ADDR 0 -#define TSEC2_PHY_ADDR_SGMII 0x00 -#define TSEC3_PHY_ADDR 6 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -#endif - -#define CONFIG_HOSTNAME "UCP1020" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#if defined(CONFIG_DONGLE) - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"bootcmd=run prog_spi_mbrbootcramfs\0" \ -"bootfile=uImage\0" \ -"consoledev=ttyS0\0" \ -"cramfsfile=image.cramfs\0" \ -"dtbaddr=0x00c00000\0" \ -"dtbfile=image.dtb\0" \ -"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ -"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ -"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ -"fileaddr=0x01000000\0" \ -"filesize=0x00080000\0" \ -"flashmbr=sf probe 0; " \ - "tftp $loadaddr $mbr; " \ - "sf erase $mbr_offset +$filesize; " \ - "sf write $loadaddr $mbr_offset $filesize\0" \ -"flashrecovery=tftp $recoveryaddr $cramfsfile; " \ - "protect off $nor_recoveryaddr +$filesize; " \ - "erase $nor_recoveryaddr +$filesize; " \ - "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ - "protect on $nor_recoveryaddr +$filesize\0 " \ -"flashuboot=tftp $ubootaddr $ubootfile; " \ - "protect off $nor_ubootaddr +$filesize; " \ - "erase $nor_ubootaddr +$filesize; " \ - "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ - "protect on $nor_ubootaddr +$filesize\0 " \ -"flashworking=tftp $workingaddr $cramfsfile; " \ - "protect off $nor_workingaddr +$filesize; " \ - "erase $nor_workingaddr +$filesize; " \ - "cp.b $workingaddr $nor_workingaddr $filesize; " \ - "protect on $nor_workingaddr +$filesize\0 " \ -"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ -"kerneladdr=0x01100000\0" \ -"kernelfile=uImage\0" \ -"loadaddr=0x01000000\0" \ -"mbr=uCP1020d.mbr\0" \ -"mbr_offset=0x00000000\0" \ -"mmbr=uCP1020Quiet.mbr\0" \ -"mmcpart=0:2\0" \ -"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ - "mmc erase 1 1; " \ - "mmc write $loadaddr 1 1\0" \ -"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \ - "mmc erase 0x40 0x400; " \ - "mmc write $loadaddr 0x40 0x400\0" \ -"netdev=eth0\0" \ -"nor_recoveryaddr=0xEC0A0000\0" \ -"nor_ubootaddr=0xEFF80000\0" \ -"nor_workingaddr=0xECFA0000\0" \ -"norbootrecovery=setenv bootargs $recoverybootargs" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "run norloadrecovery; " \ - "bootm $kerneladdr - $dtbaddr\0" \ -"norbootworking=setenv bootargs $workingbootargs" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "run norloadworking; " \ - "bootm $kerneladdr - $dtbaddr\0" \ -"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ - "setenv cramfsaddr $nor_recoveryaddr; " \ - "cramfsload $dtbaddr $dtbfile; " \ - "cramfsload $kerneladdr $kernelfile\0" \ -"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ - "setenv cramfsaddr $nor_workingaddr; " \ - "cramfsload $dtbaddr $dtbfile; " \ - "cramfsload $kerneladdr $kernelfile\0" \ -"prog_spi_mbr=run spi__mbr\0" \ -"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \ -"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \ - "run spi__cramfs\0" \ -"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "tftp $rootfsaddr $rootfsfile; " \ - "tftp $loadaddr $kernelfile; " \ - "tftp $dtbaddr $dtbfile; " \ - "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ -"ramdisk_size=120000\0" \ -"ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"recoveryaddr=0x02F00000\0" \ -"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ -"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ - "mw.l 0xffe0f008 0x00400000\0" \ -"rootfsaddr=0x02F00000\0" \ -"rootfsfile=rootfs.ext2.gz.uboot\0" \ -"rootpath=/opt/nfsroot\0" \ -"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ - "protect off 0xeC000000 +$filesize; " \ - "erase 0xEC000000 +$filesize; " \ - "cp.b $loadaddr 0xEC000000 $filesize; " \ - "cmp.b $loadaddr 0xEC000000 $filesize; " \ - "protect on 0xeC000000 +$filesize\0" \ -"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ - "protect off 0xeFF80000 +$filesize; " \ - "erase 0xEFF80000 +$filesize; " \ - "cp.b $loadaddr 0xEFF80000 $filesize; " \ - "cmp.b $loadaddr 0xEFF80000 $filesize; " \ - "protect on 0xeFF80000 +$filesize\0" \ -"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \ - "sf probe 0; sf erase 0x8000 +$filesize; " \ - "sf write $loadaddr 0x8000 $filesize\0" \ -"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \ - "protect off 0xec0a0000 +$filesize; " \ - "erase 0xeC0A0000 +$filesize; " \ - "cp.b $loadaddr 0xeC0A0000 $filesize; " \ - "protect on 0xec0a0000 +$filesize\0" \ -"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ - "sf probe 1; sf erase 0 +$filesize; " \ - "sf write $loadaddr 0 $filesize\0" \ -"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ - "sf probe 0; sf erase 0 +$filesize; " \ - "sf write $loadaddr 0 $filesize\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ -"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ -"ubootaddr=0x01000000\0" \ -"ubootfile=u-boot.bin\0" \ -"ubootd=u-boot4dongle.bin\0" \ -"upgrade=run flashworking\0" \ -"usb_phy_type=ulpi\0 " \ -"workingaddr=0x02F00000\0" \ -"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" - -#else - -#if defined(CONFIG_UCP1020T1) - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \ -"bootfile=uImage\0" \ -"consoledev=ttyS0\0" \ -"cramfsfile=image.cramfs\0" \ -"dtbaddr=0x00c00000\0" \ -"dtbfile=image.dtb\0" \ -"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ -"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ -"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ -"fileaddr=0x01000000\0" \ -"filesize=0x00080000\0" \ -"flashmbr=sf probe 0; " \ - "tftp $loadaddr $mbr; " \ - "sf erase $mbr_offset +$filesize; " \ - "sf write $loadaddr $mbr_offset $filesize\0" \ -"flashrecovery=tftp $recoveryaddr $cramfsfile; " \ - "protect off $nor_recoveryaddr +$filesize; " \ - "erase $nor_recoveryaddr +$filesize; " \ - "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ - "protect on $nor_recoveryaddr +$filesize\0 " \ -"flashuboot=tftp $ubootaddr $ubootfile; " \ - "protect off $nor_ubootaddr +$filesize; " \ - "erase $nor_ubootaddr +$filesize; " \ - "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ - "protect on $nor_ubootaddr +$filesize\0 " \ -"flashworking=tftp $workingaddr $cramfsfile; " \ - "protect off $nor_workingaddr +$filesize; " \ - "erase $nor_workingaddr +$filesize; " \ - "cp.b $workingaddr $nor_workingaddr $filesize; " \ - "protect on $nor_workingaddr +$filesize\0 " \ -"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ -"kerneladdr=0x01100000\0" \ -"kernelfile=uImage\0" \ -"loadaddr=0x01000000\0" \ -"mbr=uCP1020.mbr\0" \ -"mbr_offset=0x00000000\0" \ -"netdev=eth0\0" \ -"nor_recoveryaddr=0xEC0A0000\0" \ -"nor_ubootaddr=0xEFF80000\0" \ -"nor_workingaddr=0xECFA0000\0" \ -"norbootrecovery=setenv bootargs $recoverybootargs" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "run norloadrecovery; " \ - "bootm $kerneladdr - $dtbaddr\0" \ -"norbootworking=setenv bootargs $workingbootargs" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "run norloadworking; " \ - "bootm $kerneladdr - $dtbaddr\0" \ -"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ - "setenv cramfsaddr $nor_recoveryaddr; " \ - "cramfsload $dtbaddr $dtbfile; " \ - "cramfsload $kerneladdr $kernelfile\0" \ -"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ - "setenv cramfsaddr $nor_workingaddr; " \ - "cramfsload $dtbaddr $dtbfile; " \ - "cramfsload $kerneladdr $kernelfile\0" \ -"othbootargs=quiet\0" \ -"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "tftp $rootfsaddr $rootfsfile; " \ - "tftp $loadaddr $kernelfile; " \ - "tftp $dtbaddr $dtbfile; " \ - "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ -"ramdisk_size=120000\0" \ -"ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"recoveryaddr=0x02F00000\0" \ -"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ -"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ - "mw.l 0xffe0f008 0x00400000\0" \ -"rootfsaddr=0x02F00000\0" \ -"rootfsfile=rootfs.ext2.gz.uboot\0" \ -"rootpath=/opt/nfsroot\0" \ -"silent=1\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ -"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ -"ubootaddr=0x01000000\0" \ -"ubootfile=u-boot.bin\0" \ -"upgrade=run flashworking\0" \ -"workingaddr=0x02F00000\0" \ -"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" - -#else /* For Arcturus Modules */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"bootcmd=run norkernel\0" \ -"bootfile=uImage\0" \ -"consoledev=ttyS0\0" \ -"dtbaddr=0x00c00000\0" \ -"dtbfile=image.dtb\0" \ -"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ -"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ -"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ -"fileaddr=0x01000000\0" \ -"filesize=0x00080000\0" \ -"flashmbr=sf probe 0; " \ - "tftp $loadaddr $mbr; " \ - "sf erase $mbr_offset +$filesize; " \ - "sf write $loadaddr $mbr_offset $filesize\0" \ -"flashuboot=tftp $loadaddr $ubootfile; " \ - "protect off $nor_ubootaddr0 +$filesize; " \ - "erase $nor_ubootaddr0 +$filesize; " \ - "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \ - "protect on $nor_ubootaddr0 +$filesize; " \ - "protect off $nor_ubootaddr1 +$filesize; " \ - "erase $nor_ubootaddr1 +$filesize; " \ - "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \ - "protect on $nor_ubootaddr1 +$filesize\0 " \ -"format0=protect off $part0base +$part0size; " \ - "erase $part0base +$part0size\0" \ -"format1=protect off $part1base +$part1size; " \ - "erase $part1base +$part1size\0" \ -"format2=protect off $part2base +$part2size; " \ - "erase $part2base +$part2size\0" \ -"format3=protect off $part3base +$part3size; " \ - "erase $part3base +$part3size\0" \ -"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ -"kerneladdr=0x01100000\0" \ -"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \ -"kernelfile=uImage\0" \ -"loadaddr=0x01000000\0" \ -"mbr=uCP1020.mbr\0" \ -"mbr_offset=0x00000000\0" \ -"netdev=eth0\0" \ -"nor_ubootaddr0=0xEC000000\0" \ -"nor_ubootaddr1=0xEFF80000\0" \ -"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \ - "run norkernelload; " \ - "bootm $kerneladdr - $dtbaddr\0" \ -"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \ - "setenv cramfsaddr $part0base; " \ - "cramfsload $dtbaddr $dtbfile; " \ - "cramfsload $kerneladdr $kernelfile\0" \ -"part0base=0xEC100000\0" \ -"part0size=0x00700000\0" \ -"part1base=0xEC800000\0" \ -"part1size=0x02000000\0" \ -"part2base=0xEE800000\0" \ -"part2size=0x00800000\0" \ -"part3base=0xEF000000\0" \ -"part3size=0x00F80000\0" \ -"partENVbase=0xEC080000\0" \ -"partENVsize=0x00080000\0" \ -"program0=tftp part0-000000.bin; " \ - "protect off $part0base +$filesize; " \ - "erase $part0base +$filesize; " \ - "cp.b $loadaddr $part0base $filesize; " \ - "echo Verifying...; " \ - "cmp.b $loadaddr $part0base $filesize\0" \ -"program1=tftp part1-000000.bin; " \ - "protect off $part1base +$filesize; " \ - "erase $part1base +$filesize; " \ - "cp.b $loadaddr $part1base $filesize; " \ - "echo Verifying...; " \ - "cmp.b $loadaddr $part1base $filesize\0" \ -"program2=tftp part2-000000.bin; " \ - "protect off $part2base +$filesize; " \ - "erase $part2base +$filesize; " \ - "cp.b $loadaddr $part2base $filesize; " \ - "echo Verifying...; " \ - "cmp.b $loadaddr $part2base $filesize\0" \ -"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "tftp $rootfsaddr $rootfsfile; " \ - "tftp $loadaddr $kernelfile; " \ - "tftp $dtbaddr $dtbfile; " \ - "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ -"ramdisk_size=120000\0" \ -"ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ - "mw.l 0xffe0f008 0x00400000\0" \ -"rootfsaddr=0x02F00000\0" \ -"rootfsfile=rootfs.ext2.gz.uboot\0" \ -"rootpath=/opt/nfsroot\0" \ -"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ - "sf probe 0; sf erase 0 +$filesize; " \ - "sf write $loadaddr 0 $filesize\0" \ -"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ - "protect off 0xeC000000 +$filesize; " \ - "erase 0xEC000000 +$filesize; " \ - "cp.b $loadaddr 0xEC000000 $filesize; " \ - "cmp.b $loadaddr 0xEC000000 $filesize; " \ - "protect on 0xeC000000 +$filesize\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ -"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ -"ubootfile=u-boot.bin\0" \ -"upgrade=run flashuboot\0" \ -"usb_phy_type=ulpi\0 " \ -"boot_nfs= " \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr\0" \ -"boot_hd = " \ - "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "usb start;" \ - "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ - "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ - "bootm $loadaddr - $fdtaddr\0" \ -"boot_usb_fat = " \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs " \ - "ramdisk_size=$ramdisk_size;" \ - "usb start;" \ - "fatload usb 0:2 $loadaddr $bootfile;" \ - "fatload usb 0:2 $fdtaddr $fdtfile;" \ - "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ -"boot_usb_ext2 = " \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs " \ - "ramdisk_size=$ramdisk_size;" \ - "usb start;" \ - "ext2load usb 0:4 $loadaddr $bootfile;" \ - "ext2load usb 0:4 $fdtaddr $fdtfile;" \ - "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ -"boot_nor = " \ - "setenv bootargs root=/dev/$jffs2nor rw " \ - "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ - "bootm $norbootaddr - $norfdtaddr\0 " \ -"boot_ram = " \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs " \ - "ramdisk_size=$ramdisk_size;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" - -#endif -#endif - -#endif /* __CONFIG_H */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index d86f35856f..fd891e0bf2 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1354,6 +1354,7 @@ CONFIG_SOFT_I2C_GPIO_SCL CONFIG_SOFT_I2C_GPIO_SDA CONFIG_SOFT_I2C_READ_REPEATED_START CONFIG_SPD_EEPROM +CONFIG_SPIFLASH CONFIG_SPI_ADDR CONFIG_SPI_BOOTING CONFIG_SPI_DATAFLASH_WRITE_VERIFY -- cgit v1.2.3 From 3232bdf0b30b057ace64f192bc55a0bed4199770 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 1 Aug 2021 18:54:44 -0600 Subject: pci: Drop DM_PCI This option has not effect now. Drop it, using PCI instead where needed. Signed-off-by: Simon Glass --- arch/Kconfig | 1 - arch/arm/Kconfig | 2 +- arch/arm/mach-imx/mx6/Kconfig | 2 +- arch/mips/Kconfig | 2 +- board/emulation/qemu-riscv/Kconfig | 1 - board/socionext/developerbox/Kconfig | 1 - common/Kconfig | 1 - drivers/gpio/Kconfig | 2 +- drivers/i2c/Makefile | 2 +- drivers/net/Kconfig | 6 ++---- drivers/net/mscc_eswitch/Kconfig | 2 +- drivers/pci/Kconfig | 40 +++--------------------------------- drivers/spi/Kconfig | 2 +- drivers/virtio/Kconfig | 2 +- test/dm/Makefile | 2 +- 15 files changed, 14 insertions(+), 54 deletions(-) (limited to 'arch') diff --git a/arch/Kconfig b/arch/Kconfig index b6f9e177b6..8f8daadcf9 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -182,7 +182,6 @@ config X86 select SUPPORT_TPL select CREATE_ARCH_SYMLINK select DM - select DM_PCI select HAVE_ARCH_IOMAP select HAVE_PRIVATE_LIBGCC select OF_CONTROL diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2d59562665..b5bd3284cd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1681,7 +1681,7 @@ config TARGET_SL28 select DM_SPI_FLASH select DM_ETH select DM_MDIO - select DM_PCI + select PCI select DM_RNG select DM_RTC select DM_SCSI diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 789a50d4e9..515c3020fa 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -237,7 +237,7 @@ config TARGET_KOSAGI_NOVENA select DM_ETH select DM_GPIO select DM_MMC - select DM_PCI + select PCI select DM_SCSI select DM_VIDEO select OF_CONTROL diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 6b1f10d9a0..a5cec387a0 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -17,7 +17,7 @@ config TARGET_MALTA select BOARD_EARLY_INIT_R select DM select DM_SERIAL - select DM_PCI + select PCI select DM_ETH select DYNAMIC_IO_PORT_BASE select MIPS_CM diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index a7de82d3bf..1bbf1bc84a 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -51,7 +51,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply E1000 imply NVME imply PCI - imply DM_PCI imply PCIE_ECAM_GENERIC imply SCSI imply DM_SCSI diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig index 706b8dc0f1..c181d26a44 100644 --- a/board/socionext/developerbox/Kconfig +++ b/board/socionext/developerbox/Kconfig @@ -7,7 +7,6 @@ choice config TARGET_DEVELOPERBOX bool "Socionext DeveloperBox" select PCI - select DM_PCI select PCIE_ECAM_SYNQUACER select SYS_DISABLE_DCACHE_OPS select OF_BOARD_SETUP diff --git a/common/Kconfig b/common/Kconfig index 2ab20a6c85..ee14d3ad5b 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -551,7 +551,6 @@ config MISC_INIT_R config PCI_INIT_R bool "Enumerate PCI buses during init" depends on PCI - default y if !DM_PCI help With this option U-Boot will call pci_init() soon after relocation, which will enumerate PCI buses. This is needed, for instance, in the diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 4a89c1a62b..e37ac9f494 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -358,7 +358,7 @@ config PIC32_GPIO config OCTEON_GPIO bool "Octeon II/III/TX/TX2 GPIO driver" - depends on DM_GPIO && DM_PCI && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) + depends on DM_GPIO && PCI && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) default y help Add support for the Marvell Octeon GPIO driver. This is used with diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index c2eb24e0f7..c16ebb2491 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -18,7 +18,7 @@ obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o obj-$(CONFIG_SYS_I2C_CA) += i2c-cortina.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o -ifdef CONFIG_DM_PCI +ifdef CONFIG_PCI obj-$(CONFIG_SYS_I2C_DW) += designware_i2c_pci.o endif obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 32f2708dc3..d4dc72046c 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -222,7 +222,6 @@ config DWC_ETH_QOS_TEGRA186 config E1000 bool "Intel PRO/1000 Gigabit Ethernet support" - depends on (DM_ETH && DM_PCI) || !DM_ETH help This driver supports Intel(R) PRO/1000 gigabit ethernet family of adapters. For more information on how to identify your adapter, go @@ -506,7 +505,7 @@ config OCTEONTX2_CGX_INTF config PCH_GBE bool "Intel Platform Controller Hub EG20T GMAC driver" - depends on DM_ETH && DM_PCI + depends on DM_ETH select PHYLIB help This MAC is present in Intel Platform Controller Hub EG20T. It @@ -606,7 +605,6 @@ source "drivers/net/ti/Kconfig" config TULIP bool "DEC Tulip DC2114x Ethernet support" - depends on (DM_ETH && DM_PCI) || !DM_ETH help This driver supports DEC DC2114x Fast ethernet chips. @@ -791,7 +789,7 @@ config HIGMACV300_ETH config FSL_ENETC bool "NXP ENETC Ethernet controller" - depends on DM_PCI && DM_ETH && DM_MDIO + depends on DM_ETH && DM_MDIO help This driver supports the NXP ENETC Ethernet controller found on some of the NXP SoCs. diff --git a/drivers/net/mscc_eswitch/Kconfig b/drivers/net/mscc_eswitch/Kconfig index ccf7822dbe..930d2ef113 100644 --- a/drivers/net/mscc_eswitch/Kconfig +++ b/drivers/net/mscc_eswitch/Kconfig @@ -39,7 +39,7 @@ config MSCC_SERVAL_SWITCH config MSCC_FELIX_SWITCH bool "Felix switch driver" - depends on DM_DSA && DM_PCI + depends on DM_DSA select FSL_ENETC help This driver supports the Ethernet switch integrated in the diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 2ef4d46797..e4123ba820 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -2,35 +2,26 @@ menuconfig PCI bool "PCI support" depends on DM default y if PPC - select DM_PCI help Enable support for PCI (Peripheral Interconnect Bus), a type of bus used on some devices to allow the CPU to communicate with its peripherals. -config DM_PCI - bool - help - Use driver model for PCI. Driver model is the new method for - orgnising devices in U-Boot. For PCI, driver model keeps track of - available PCI devices, allows scanning of PCI buses and provides - device configuration support. + This subsystem requires driver model. if PCI config DM_PCI_COMPAT bool "Enable compatible functions for PCI" - depends on DM_PCI help Enable compatibility functions for PCI so that old code can be used - with CONFIG_DM_PCI enabled. This should be used as an interim + with CONFIG_PCI enabled. This should be used as an interim measure when porting a board to use driver model for PCI. Once the board is fully supported, this option should be disabled. config PCI_AARDVARK bool "Enable Aardvark PCIe driver" default n - depends on DM_PCI depends on DM_GPIO depends on ARMADA_3700 help @@ -40,14 +31,12 @@ config PCI_AARDVARK config PCI_PNP bool "Enable Plug & Play support for PCI" - depends on PCI || DM_PCI default y help Enable PCI memory and I/O space resource allocation and assignment. config PCI_REGION_MULTI_ENTRY bool "Enable Multiple entries of region type MEMORY in ranges for PCI" - depends on PCI || DM_PCI default n help Enable PCI memory regions to be of multiple entry. Multiple entry @@ -57,7 +46,6 @@ config PCI_REGION_MULTI_ENTRY config PCI_MAP_SYSTEM_MEMORY bool "Map local system memory from a virtual base address" - depends on PCI || DM_PCI depends on MIPS default n help @@ -70,7 +58,6 @@ config PCI_MAP_SYSTEM_MEMORY config PCI_SRIOV bool "Enable Single Root I/O Virtualization support for PCI" - depends on PCI || DM_PCI default n help Say Y here if you want to enable PCI Single Root I/O Virtualization @@ -80,7 +67,6 @@ config PCI_SRIOV config PCI_ARID bool "Enable Alternate Routing-ID support for PCI" - depends on PCI || DM_PCI default n help Say Y here if you want to enable Alternate Routing-ID capability @@ -90,7 +76,6 @@ config PCI_ARID config PCIE_ECAM_GENERIC bool "Generic ECAM-based PCI host controller support" default n - depends on DM_PCI help Say Y here if you want to enable support for generic ECAM-based PCIe host controllers, such as the one emulated by QEMU. @@ -98,7 +83,6 @@ config PCIE_ECAM_GENERIC config PCIE_ECAM_SYNQUACER bool "SynQuacer ECAM-based PCI host controller support" default n - depends on DM_PCI select PCI_INIT_R select PCI_REGION_MULTI_ENTRY help @@ -109,14 +93,12 @@ config PCIE_ECAM_SYNQUACER config PCI_PHYTIUM bool "Phytium PCIe support" - depends on DM_PCI help Say Y here if you want to enable PCIe controller support on Phytium SoCs. config PCIE_DW_MVEBU bool "Enable Armada-8K PCIe driver (DesignWare core)" - depends on DM_PCI depends on ARMADA_8K help Say Y here if you want to enable PCIe controller support on @@ -135,7 +117,6 @@ config PCIE_DW_SIFIVE config PCIE_FSL bool "FSL PowerPC PCIe support" - depends on DM_PCI help Say Y here if you want to enable PCIe controller support on FSL PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs. @@ -143,14 +124,12 @@ config PCIE_FSL config PCI_MPC85XX bool "MPC85XX PowerPC PCI support" - depends on DM_PCI help Say Y here if you want to enable PCI controller support on FSL PowerPC MPC85xx SoC. config PCI_RCAR_GEN2 bool "Renesas RCar Gen2 PCIe driver" - depends on DM_PCI depends on RCAR_32 help Say Y here if you want to enable PCIe controller support on @@ -159,7 +138,6 @@ config PCI_RCAR_GEN2 config PCI_RCAR_GEN3 bool "Renesas RCar Gen3 PCIe driver" - depends on DM_PCI depends on RCAR_GEN3 help Say Y here if you want to enable PCIe controller support on @@ -167,7 +145,7 @@ config PCI_RCAR_GEN3 config PCI_SANDBOX bool "Sandbox PCI support" - depends on SANDBOX && DM_PCI + depends on SANDBOX help Support PCI on sandbox, as an emulated bus. This permits testing of PCI feature such as bus scanning, device configuration and device @@ -202,7 +180,6 @@ config PCIE_OCTEON config PCI_XILINX bool "Xilinx AXI Bridge for PCI Express" - depends on DM_PCI help Enable support for the Xilinx AXI bridge for PCI express, an IP block which can be used on some generations of Xilinx FPGAs. @@ -213,7 +190,6 @@ config PCIE_LAYERSCAPE config PCIE_LAYERSCAPE_RC bool "Layerscape PCIe Root Complex mode support" - depends on DM_PCI select PCIE_LAYERSCAPE help Enable Layerscape PCIe Root Complex mode driver support. The Layerscape @@ -235,7 +211,6 @@ config PCI_IOMMU_EXTRA_MAPPINGS config PCIE_LAYERSCAPE_EP bool "Layerscape PCIe Endpoint mode support" - depends on DM_PCI select PCIE_LAYERSCAPE select PCI_ENDPOINT help @@ -246,7 +221,6 @@ config PCIE_LAYERSCAPE_EP config PCIE_LAYERSCAPE_GEN4 bool "Layerscape Gen4 PCIe support" - depends on DM_PCI help Support PCIe Gen4 on NXP Layerscape SoCs, which may have one or several PCIe controllers. The PCIe controller can work in RC or @@ -279,14 +253,12 @@ config FSL_PCIE_EP_COMPAT config PCIE_INTEL_FPGA bool "Intel FPGA PCIe support" - depends on DM_PCI help Say Y here if you want to enable PCIe controller support on Intel FPGA, example Stratix 10. config PCIE_IPROC bool "Iproc PCIe support" - depends on DM_PCI help Broadcom iProc PCIe controller driver. Say Y here if you want to enable Broadcom iProc PCIe controller, @@ -294,7 +266,6 @@ config PCIE_IPROC config PCI_MVEBU bool "Enable Armada XP/38x PCIe driver" depends on ARCH_MVEBU - select DM_PCI select MISC help Say Y here if you want to enable PCIe controller support on @@ -302,7 +273,6 @@ config PCI_MVEBU config PCIE_DW_COMMON bool - select DM_PCI config PCI_KEYSTONE bool "TI Keystone PCIe controller" @@ -312,7 +282,6 @@ config PCI_KEYSTONE config PCIE_MEDIATEK bool "MediaTek PCIe Gen2 controller" - depends on DM_PCI depends on ARCH_MEDIATEK help Say Y here if you want to enable Gen2 PCIe controller, @@ -329,7 +298,6 @@ config PCIE_DW_MESON config PCIE_ROCKCHIP bool "Enable Rockchip PCIe driver" depends on ARCH_ROCKCHIP - select DM_PCI select PHY_ROCKCHIP_PCIE default y if ROCKCHIP_RK3399 help @@ -347,7 +315,6 @@ config PCIE_DW_ROCKCHIP config PCI_BRCMSTB bool "Broadcom STB PCIe controller" - depends on DM_PCI depends on ARCH_BCM283X help Say Y here if you want to enable support for PCIe controller @@ -357,7 +324,6 @@ config PCI_BRCMSTB config PCIE_UNIPHIER bool "Socionext UniPhier PCIe driver" - depends on DM_PCI depends on ARCH_UNIPHIER select PHY_UNIPHIER_PCIE help diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index e12699bec7..d07e9a28af 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -271,7 +271,7 @@ config NXP_FSPI config OCTEON_SPI bool "Octeon SPI driver" - depends on DM_PCI && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) + depends on ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2 help Enable the Octeon SPI driver. This driver can be used to access the SPI NOR flash on Octeon II/III and OcteonTX/TX2 diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig index 1835607083..863c3fbe02 100644 --- a/drivers/virtio/Kconfig +++ b/drivers/virtio/Kconfig @@ -31,7 +31,7 @@ config VIRTIO_MMIO config VIRTIO_PCI bool "PCI driver for virtio devices" - depends on DM_PCI + depends on PCI select VIRTIO help This driver provides support for virtio based paravirtual device diff --git a/test/dm/Makefile b/test/dm/Makefile index 516f69d61c..55162e9499 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -65,7 +65,7 @@ obj-y += of_extra.o obj-$(CONFIG_OSD) += osd.o obj-$(CONFIG_DM_VIDEO) += panel.o obj-$(CONFIG_EFI_PARTITION) += part.o -obj-$(CONFIG_DM_PCI) += pci.o +obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_P2SB) += p2sb.o obj-$(CONFIG_PCI_ENDPOINT) += pci_ep.o obj-$(CONFIG_PCH) += pch.o -- cgit v1.2.3