From 00ed0e3ee38773bc8430fd51b1085c0cec1f9a50 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 6 Dec 2017 13:16:45 +0900 Subject: ARM: uniphier: compile pll-base-ld20.c for PXs3 Fix the link error for the combination of CONFIG_ARCH_UNIPHIER_LD11=n CONFIG_ARCH_UNIPHIER_LD20=n CONFIG_ARCH_UNIPHIER_PXS3=y Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index 76633bcd49..5cd0897dff 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -27,3 +27,4 @@ endif obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pll-base-ld20.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o +obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += pll-base-ld20.o -- cgit v1.2.3 From c30c44e799e1f7d5184c487809edbd612705ba5c Mon Sep 17 00:00:00 2001 From: Dai Okamura Date: Wed, 6 Dec 2017 14:16:32 +0900 Subject: ARM: uniphier: fix SSCPLL init code for LD11 SoC Commit 682e09ff9f35 ("ARM: uniphier: add PLL init code for LD20 SoC") missed to write the computed value to the SSCPLLCTRL2 register. Fixes: 682e09ff9f35 ("ARM: uniphier: add PLL init code for LD20 SoC") Signed-off-by: Dai Okamura Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/pll-base-ld20.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c index 3aa42f8bfd..45fdf0a322 100644 --- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c @@ -48,6 +48,7 @@ int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, tmp = readl(base + 4); tmp &= ~SC_PLLCTRL2_SSC_JK_MASK; tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK; + writel(tmp, base + 4); udelay(50); } -- cgit v1.2.3 From f2ce50b2d076ccec56d33df71f77e6f3fd7a33f4 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 6 Dec 2017 14:16:33 +0900 Subject: ARM: uniphier: compute SSCPLL values more precisely Use DIV_ROUND_CLOSEST(). To make the JK value even more precise, I used a bigger coefficient, then divide it by 512. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/pll-base-ld20.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c index 45fdf0a322..c9b78b9e88 100644 --- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -41,13 +42,14 @@ int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, if (freq != UNIPHIER_PLL_FREQ_DEFAULT) { tmp = readl(base); /* SSCPLLCTRL */ tmp &= ~SC_PLLCTRL_SSC_DK_MASK; - tmp |= (487 * freq * ssc_rate / divn / 512) & + tmp |= DIV_ROUND_CLOSEST(487UL * freq * ssc_rate, divn * 512) & SC_PLLCTRL_SSC_DK_MASK; writel(tmp, base); tmp = readl(base + 4); tmp &= ~SC_PLLCTRL2_SSC_JK_MASK; - tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK; + tmp |= DIV_ROUND_CLOSEST(21431887UL * freq, divn * 512) & + SC_PLLCTRL2_SSC_JK_MASK; writel(tmp, base + 4); udelay(50); -- cgit v1.2.3 From 7f8e75390b9c9b79748b2f87dd7ab45674323d58 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 6 Dec 2017 14:16:34 +0900 Subject: ARM: uniphier: use FIELD_PREP for PLL settings It is tedious to define both mask and bit-shift. provides a convenient way to get access to register fields with a single shifted mask. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/pll-base-ld20.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c index c9b78b9e88..385f54dfc3 100644 --- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c @@ -5,6 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include #include @@ -19,7 +20,6 @@ #define SC_PLLCTRL_SSC_EN BIT(31) #define SC_PLLCTRL2_NRSTDS BIT(28) #define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0) -#define SC_PLLCTRL3_REGI_SHIFT 16 #define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16) /* PLL type: VPLL27 */ @@ -42,14 +42,16 @@ int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, if (freq != UNIPHIER_PLL_FREQ_DEFAULT) { tmp = readl(base); /* SSCPLLCTRL */ tmp &= ~SC_PLLCTRL_SSC_DK_MASK; - tmp |= DIV_ROUND_CLOSEST(487UL * freq * ssc_rate, divn * 512) & - SC_PLLCTRL_SSC_DK_MASK; + tmp |= FIELD_PREP(SC_PLLCTRL_SSC_DK_MASK, + DIV_ROUND_CLOSEST(487UL * freq * ssc_rate, + divn * 512)); writel(tmp, base); tmp = readl(base + 4); tmp &= ~SC_PLLCTRL2_SSC_JK_MASK; - tmp |= DIV_ROUND_CLOSEST(21431887UL * freq, divn * 512) & - SC_PLLCTRL2_SSC_JK_MASK; + tmp |= FIELD_PREP(SC_PLLCTRL2_SSC_JK_MASK, + DIV_ROUND_CLOSEST(21431887UL * freq, + divn * 512)); writel(tmp, base + 4); udelay(50); @@ -93,7 +95,7 @@ int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) tmp = readl(base + 8); /* SSCPLLCTRL3 */ tmp &= ~SC_PLLCTRL3_REGI_MASK; - tmp |= regi << SC_PLLCTRL3_REGI_SHIFT; + tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); writel(tmp, base + 8); iounmap(base); -- cgit v1.2.3