From 464ca99f8e8ea43e31cffc6dcf026520c8de0609 Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Fri, 10 Jul 2020 23:52:32 +0800 Subject: arm: socfpga: soc64: Remove PHY interface setup from misc arch init 'dwmac_socfpga' driver will setup the PHY interface during probe. PHY interface setup in arch_misc_init() is no longer needed. Signed-off-by: Chee Hong Ang Reviewed-by: Ley Foon Tan --- arch/arm/mach-socfpga/misc_s10.c | 85 +--------------------------------------- 1 file changed, 2 insertions(+), 83 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c index 52868fb344..07dfa5ed0b 100644 --- a/arch/arm/mach-socfpga/misc_s10.c +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -8,20 +8,13 @@ #include #include #include -#include #include #include -#include -#include #include +#include +#include #include #include -#include -#include -#include -#include - -#include DECLARE_GLOBAL_DATA_PTR; @@ -45,79 +38,6 @@ static Altera_desc altera_fpga[] = { }, }; -/* - * DesignWare Ethernet initialization - */ -#ifdef CONFIG_ETH_DESIGNWARE - -static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode) -{ - u32 modereg; - - if (!phymode) - return -EINVAL; - - if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii") || - !strcmp(phymode, "sgmii")) - modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; - else if (!strcmp(phymode, "rgmii")) - modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; - else if (!strcmp(phymode, "rmii")) - modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; - else - return -EINVAL; - - clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0 + - (gmac_index * sizeof(u32)), - SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg); - - return 0; -} - -static int socfpga_set_phymode(void) -{ - const void *fdt = gd->fdt_blob; - struct fdtdec_phandle_args args; - const char *phy_mode; - u32 gmac_index; - int nodes[3]; /* Max. 3 GMACs */ - int ret, count; - int i, node; - - count = fdtdec_find_aliases_for_id(fdt, "ethernet", - COMPAT_ALTERA_SOCFPGA_DWMAC, - nodes, ARRAY_SIZE(nodes)); - for (i = 0; i < count; i++) { - node = nodes[i]; - if (node <= 0) - continue; - - ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", - "#reset-cells", 1, 0, - &args); - if (ret || args.args_count != 1) { - debug("GMAC%i: Failed to parse DT 'resets'!\n", i); - continue; - } - - gmac_index = args.args[0] - EMAC0_RESET; - - phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); - ret = socfpga_phymode_setup(gmac_index, phy_mode); - if (ret) { - debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); - continue; - } - } - - return 0; -} -#else -static int socfpga_set_phymode(void) -{ - return 0; -}; -#endif /* * Print CPU information @@ -139,7 +59,6 @@ int arch_misc_init(void) sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz()); env_set("qspi_clock", qspi_string); - socfpga_set_phymode(); return 0; } #endif -- cgit v1.2.3 From 12cc44884b0e74260c2f7396b993f178f8c8df27 Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Fri, 10 Jul 2020 23:53:13 +0800 Subject: arm: socfpga: soc64: Initialize timer in SPL only Timer only need to be initialized once in SPL. This patch remove the redundancy of initializing the timer again in U-Boot proper Signed-off-by: Chee Hong Ang Reviewed-by: Ley Foon Tan --- arch/arm/mach-socfpga/timer_s10.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c index 3ad98bdb25..7d5598e1a3 100644 --- a/arch/arm/mach-socfpga/timer_s10.c +++ b/arch/arm/mach-socfpga/timer_s10.c @@ -14,6 +14,7 @@ */ int timer_init(void) { +#ifdef CONFIG_SPL_BUILD int enable = 0x3; /* timer enable + output signal masked */ int loadval = ~0; @@ -22,6 +23,6 @@ int timer_init(void) /* enable processor pysical counter */ asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable)); asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval)); - +#endif return 0; } -- cgit v1.2.3 From a6510993a5a5929f38d7672cd3fdde2959bdb21d Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Wed, 5 Aug 2020 20:11:25 +0800 Subject: sysreset: socfpga: soc64: Rename SYSRESET SoCFPGA driver for S10 to SoC64 Rename the driver from S10 to SoC64 because Intel Agilex platform also using the this SYSRESET SoCFPGA driver for S10. Signed-off-by: Chee Hong Ang Reviewed-by: Ley Foon Tan --- arch/arm/Kconfig | 2 +- drivers/sysreset/Kconfig | 6 +++--- drivers/sysreset/Makefile | 2 +- drivers/sysreset/sysreset_socfpga_s10.c | 29 ----------------------------- drivers/sysreset/sysreset_socfpga_soc64.c | 29 +++++++++++++++++++++++++++++ 5 files changed, 34 insertions(+), 34 deletions(-) delete mode 100644 drivers/sysreset/sysreset_socfpga_s10.c create mode 100644 drivers/sysreset/sysreset_socfpga_soc64.c (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index abbc89a889..9e7c2931cd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -994,7 +994,7 @@ config ARCH_SOCFPGA select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 - select SYSRESET_SOCFPGA_S10 if TARGET_SOCFPGA_STRATIX10 + select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_STRATIX10 imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 6ebc90e1d3..b812af9359 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -79,12 +79,12 @@ config SYSRESET_SOCFPGA This enables the system reset driver support for Intel SOCFPGA SoCs (Cyclone 5, Arria 5 and Arria 10). -config SYSRESET_SOCFPGA_S10 - bool "Enable support for Intel SOCFPGA Stratix 10" +config SYSRESET_SOCFPGA_SOC64 + bool "Enable support for Intel SOCFPGA SoC64 family (Stratix10/Agilex)" depends on ARCH_SOCFPGA && TARGET_SOCFPGA_STRATIX10 help This enables the system reset driver support for Intel SOCFPGA - Stratix SoCs. + SoC64 SoCs. config SYSRESET_TI_SCI bool "TI System Control Interface (TI SCI) system reset driver" diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index df2293b848..920c69233f 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -13,7 +13,7 @@ obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o -obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o +obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o diff --git a/drivers/sysreset/sysreset_socfpga_s10.c b/drivers/sysreset/sysreset_socfpga_s10.c deleted file mode 100644 index 9837aadf64..0000000000 --- a/drivers/sysreset/sysreset_socfpga_s10.c +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Pepperl+Fuchs - * Simon Goldschmidt - */ - -#include -#include -#include -#include -#include - -static int socfpga_sysreset_request(struct udevice *dev, - enum sysreset_t type) -{ - puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n"); - mbox_reset_cold(); - return -EINPROGRESS; -} - -static struct sysreset_ops socfpga_sysreset = { - .request = socfpga_sysreset_request, -}; - -U_BOOT_DRIVER(sysreset_socfpga) = { - .id = UCLASS_SYSRESET, - .name = "socfpga_sysreset", - .ops = &socfpga_sysreset, -}; diff --git a/drivers/sysreset/sysreset_socfpga_soc64.c b/drivers/sysreset/sysreset_socfpga_soc64.c new file mode 100644 index 0000000000..9837aadf64 --- /dev/null +++ b/drivers/sysreset/sysreset_socfpga_soc64.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Pepperl+Fuchs + * Simon Goldschmidt + */ + +#include +#include +#include +#include +#include + +static int socfpga_sysreset_request(struct udevice *dev, + enum sysreset_t type) +{ + puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n"); + mbox_reset_cold(); + return -EINPROGRESS; +} + +static struct sysreset_ops socfpga_sysreset = { + .request = socfpga_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_socfpga) = { + .id = UCLASS_SYSRESET, + .name = "socfpga_sysreset", + .ops = &socfpga_sysreset, +}; -- cgit v1.2.3 From 289ebe077a18462d38628a9cc2213c9e010216de Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Wed, 5 Aug 2020 20:11:26 +0800 Subject: sysreset: socfpga: agilex: Enable sysreset support Enable sysreset support for Agilex platform. Signed-off-by: Chee Hong Ang Reviewed-by: Ley Foon Tan --- arch/arm/Kconfig | 2 +- drivers/sysreset/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9e7c2931cd..a17f33042f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -994,7 +994,7 @@ config ARCH_SOCFPGA select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 - select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_STRATIX10 + select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index b812af9359..70692f07e7 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -81,7 +81,7 @@ config SYSRESET_SOCFPGA config SYSRESET_SOCFPGA_SOC64 bool "Enable support for Intel SOCFPGA SoC64 family (Stratix10/Agilex)" - depends on ARCH_SOCFPGA && TARGET_SOCFPGA_STRATIX10 + depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX) help This enables the system reset driver support for Intel SOCFPGA SoC64 SoCs. -- cgit v1.2.3 From d7a1ff40d6006c818c9e74d3e13bec008638349f Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Wed, 5 Aug 2020 21:15:56 +0800 Subject: arm: socfpga: soc64: Add SDM triggered warm reset bit mask Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat register when checking for HPS warm reset status. Refactor the warm reset mask macro for clarity purpose. Signed-off-by: Chee Hong Ang Reviewed-by: Ley Foon Tan --- arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index 3f952bcc6e..fc60f6a105 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -21,8 +21,15 @@ void socfpga_bridges_reset(int enable); #define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 #define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004 -/* Watchdogs and MPU warm reset mask */ -#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00 +/* SDM, Watchdogs and MPU warm reset mask */ +#define RSTMGR_STAT_SDMWARMRST BIT(1) +#define RSTMGR_STAT_MPU0RST_BITPOS 8 +#define RSTMGR_STAT_L4WD0RST_BITPOS 16 +#define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \ + GENMASK(RSTMGR_STAT_MPU0RST_BITPOS + 3, \ + RSTMGR_STAT_MPU0RST_BITPOS) | \ + GENMASK(RSTMGR_STAT_L4WD0RST_BITPOS + 3, \ + RSTMGR_STAT_L4WD0RST_BITPOS)) /* * SocFPGA Stratix10 reset IDs, bank mapping is as follows: -- cgit v1.2.3 From b3e2d9fccbe7390a859f7f46001c6312cc35455c Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Wed, 5 Aug 2020 21:15:57 +0800 Subject: arm: socfpga: soc64: Show reset state in SPL Print reset state (warm/cold) together with the source (watchdog/MPU) which has triggered the warm reset on S10 & Agilex. Signed-off-by: Chee Hong Ang Reviewed-by: Ley Foon Tan --- .../include/mach/reset_manager_soc64.h | 1 + arch/arm/mach-socfpga/reset_manager_s10.c | 22 ++++++++++++++++++++++ arch/arm/mach-socfpga/spl_agilex.c | 1 + arch/arm/mach-socfpga/spl_s10.c | 1 + 4 files changed, 25 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index fc60f6a105..c8bb727aa2 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -8,6 +8,7 @@ void reset_deassert_peripherals_handoff(void); int cpu_has_been_warmreset(void); +void print_reset_info(void); void socfpga_bridges_reset(int enable); #define RSTMGR_SOC64_STATUS 0x00 diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index c7430777b2..9f16bf92d5 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -104,3 +104,25 @@ int cpu_has_been_warmreset(void) return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) & RSTMGR_L4WD_MPU_WARMRESET_MASK; } + +void print_reset_info(void) +{ + bool iswd; + int n; + u32 stat = cpu_has_been_warmreset(); + + printf("Reset state: %s%s", stat ? "Warm " : "Cold", + (stat & RSTMGR_STAT_SDMWARMRST) ? "[from SDM] " : ""); + + stat &= ~RSTMGR_STAT_SDMWARMRST; + if (!stat) { + puts("\n"); + return; + } + + n = generic_ffs(stat) - 1; + iswd = (n >= RSTMGR_STAT_L4WD0RST_BITPOS); + printf("(Triggered by %s %d)\n", iswd ? "Watchdog" : "MPU", + iswd ? (n - RSTMGR_STAT_L4WD0RST_BITPOS) : + (n - RSTMGR_STAT_MPU0RST_BITPOS)); +} diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index bd971ecbd1..0121ff431f 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -76,6 +76,7 @@ void board_init_f(ulong dummy) } preloader_console_init(); + print_reset_info(); cm_print_clock_quick_summary(); firewall_setup(); diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index b3c6f6afc4..1f7118226c 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -81,6 +81,7 @@ void board_init_f(ulong dummy) #endif preloader_console_init(); + print_reset_info(); cm_print_clock_quick_summary(); firewall_setup(); -- cgit v1.2.3 From 2473e13bb8e81cf90e89863125e85900193b01b7 Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Thu, 6 Aug 2020 12:15:33 +0800 Subject: arm: socfpga: Use DM watchdog timer All SoCFPGA platforms (except Cyclone V) are now switching to CONFIG_WDT (driver model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Signed-off-by: Chee Hong Ang Reviewed-by: Ley Foon Tan --- arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4 ++++ arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi | 4 ++++ arch/arm/dts/socfpga_stratix10.dtsi | 1 - arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 1 + arch/arm/mach-socfpga/spl_agilex.c | 2 +- arch/arm/mach-socfpga/spl_s10.c | 2 +- configs/socfpga_agilex_defconfig | 2 ++ 7 files changed, 13 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index debeb8b239..6cac36a1fc 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -40,3 +40,7 @@ &qspi { status = "okay"; }; + +&watchdog0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi index 58cd497821..22e614d04c 100644 --- a/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi @@ -15,3 +15,7 @@ &uart1 { u-boot,dm-pre-reloc; }; + +&watchdog1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index a8e61cf728..cb799bc551 100755 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -386,7 +386,6 @@ reg = <0xffd00200 0x100>; interrupts = <0 117 4>; resets = <&rst WATCHDOG0_RESET>; - u-boot,dm-pre-reloc; status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi index a903040d60..2669abb383 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi @@ -33,5 +33,6 @@ }; &watchdog0 { + status = "okay"; u-boot,dm-pre-reloc; }; diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index 0121ff431f..78b5d7c8d9 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -51,11 +51,11 @@ void board_init_f(ulong dummy) socfpga_get_managers_addr(); -#ifdef CONFIG_HW_WATCHDOG /* Ensure watchdog is paused when debugging is happening */ writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); +#ifdef CONFIG_HW_WATCHDOG /* Enable watchdog before initializing the HW */ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index 1f7118226c..daed05653a 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -53,11 +53,11 @@ void board_init_f(ulong dummy) socfpga_get_managers_addr(); -#ifdef CONFIG_HW_WATCHDOG /* Ensure watchdog is paused when debugging is happening */ writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); +#ifdef CONFIG_HW_WATCHDOG /* Enable watchdog before initializing the HW */ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index ee1a665605..c4db1d0835 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -60,5 +60,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y -- cgit v1.2.3 From d2170168dd9d762152f27c482faa87973a2fd791 Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Fri, 7 Aug 2020 11:50:03 +0800 Subject: fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang Reviewed-by: Ley Foon Tan --- arch/arm/mach-socfpga/Kconfig | 2 +- arch/arm/mach-socfpga/misc_s10.c | 2 +- drivers/fpga/Kconfig | 12 +- drivers/fpga/Makefile | 2 +- drivers/fpga/altera.c | 7 +- drivers/fpga/intel_sdm_mb.c | 285 +++++++++++++++++++++++++++++++++++++++ drivers/fpga/stratix10.c | 285 --------------------------------------- include/altera.h | 9 +- 8 files changed, 303 insertions(+), 301 deletions(-) create mode 100644 drivers/fpga/intel_sdm_mb.c delete mode 100644 drivers/fpga/stratix10.c (limited to 'arch') diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index a3699e82a1..32549913cc 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -79,7 +79,7 @@ config TARGET_SOCFPGA_STRATIX10 select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN select ARMV8_SPIN_TABLE - select FPGA_STRATIX10 + select FPGA_INTEL_SDM_MAILBOX choice prompt "Altera SOCFPGA board select" diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c index 07dfa5ed0b..0d67b0fd83 100644 --- a/arch/arm/mach-socfpga/misc_s10.c +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; static Altera_desc altera_fpga[] = { { /* Family */ - Intel_FPGA_Stratix10, + Intel_FPGA_SDM_Mailbox, /* Interface type */ secure_device_manager_mailbox, /* No limitation as additional data will be ignored */ diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index fe398a1d49..dd0b39a8d1 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -31,16 +31,16 @@ config FPGA_CYCLON2 Enable FPGA driver for loading bitstream in BIT and BIN format on Altera Cyclone II device. -config FPGA_STRATIX10 - bool "Enable Altera FPGA driver for Stratix 10" +config FPGA_INTEL_SDM_MAILBOX + bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver" depends on TARGET_SOCFPGA_STRATIX10 select FPGA_ALTERA help - Say Y here to enable the Altera Stratix 10 FPGA specific driver + Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver - This provides common functionality for Altera Stratix 10 devices. - Enable FPGA driver for writing bitstream into Altera Stratix10 - device. + This provides common functionality for Intel FPGA devices. + Enable FPGA driver for writing full bitstream into Intel FPGA + devices through SDM (Secure Device Manager) Mailbox. config FPGA_XILINX bool "Enable Xilinx FPGA drivers" diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 04e6480f20..83243fb107 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -16,9 +16,9 @@ ifdef CONFIG_FPGA_ALTERA obj-y += altera.o obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o +obj-$(CONFIG_FPGA_INTEL_SDM_MAILBOX) += intel_sdm_mb.o obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o -obj-$(CONFIG_FPGA_STRATIX10) += stratix10.o obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index bb27b3778f..10c0475d25 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -40,12 +40,13 @@ static const struct altera_fpga { #if defined(CONFIG_FPGA_STRATIX_V) { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL }, #endif -#if defined(CONFIG_FPGA_STRATIX10) - { Intel_FPGA_Stratix10, "Stratix10", stratix10_load, NULL, NULL }, -#endif #if defined(CONFIG_FPGA_SOCFPGA) { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL }, #endif +#if defined(CONFIG_FPGA_INTEL_SDM_MAILBOX) + { Intel_FPGA_SDM_Mailbox, "Intel SDM Mailbox", intel_sdm_mb_load, NULL, + NULL }, +#endif }; static int altera_validate(Altera_desc *desc, const char *fn) diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c new file mode 100644 index 0000000000..3508231191 --- /dev/null +++ b/drivers/fpga/intel_sdm_mb.c @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Intel Corporation + */ + +#include +#include +#include +#include +#include + +#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000 +#define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000 + +static const struct mbox_cfgstat_state { + int err_no; + const char *error_name; +} mbox_cfgstat_state[] = { + {MBOX_CFGSTAT_STATE_IDLE, "FPGA in idle mode."}, + {MBOX_CFGSTAT_STATE_CONFIG, "FPGA in config mode."}, + {MBOX_CFGSTAT_STATE_FAILACK, "Acknowledgment failed!"}, + {MBOX_CFGSTAT_STATE_ERROR_INVALID, "Invalid bitstream!"}, + {MBOX_CFGSTAT_STATE_ERROR_CORRUPT, "Corrupted bitstream!"}, + {MBOX_CFGSTAT_STATE_ERROR_AUTH, "Authentication failed!"}, + {MBOX_CFGSTAT_STATE_ERROR_CORE_IO, "I/O error!"}, + {MBOX_CFGSTAT_STATE_ERROR_HARDWARE, "Hardware error!"}, + {MBOX_CFGSTAT_STATE_ERROR_FAKE, "Fake error!"}, + {MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO, "Error in boot info!"}, + {MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR, "Error in QSPI!"}, + {MBOX_RESP_ERROR, "Mailbox general error!"}, + {-ETIMEDOUT, "I/O timeout error"}, + {-1, "Unknown error!"} +}; + +#define MBOX_CFGSTAT_MAX ARRAY_SIZE(mbox_cfgstat_state) + +static const char *mbox_cfgstat_to_str(int err) +{ + int i; + + for (i = 0; i < MBOX_CFGSTAT_MAX - 1; i++) { + if (mbox_cfgstat_state[i].err_no == err) + return mbox_cfgstat_state[i].error_name; + } + + return mbox_cfgstat_state[MBOX_CFGSTAT_MAX - 1].error_name; +} + +/* + * Add the ongoing transaction's command ID into pending list and return + * the command ID for next transfer. + */ +static u8 add_transfer(u32 *xfer_pending_list, size_t list_size, u8 id) +{ + int i; + + for (i = 0; i < list_size; i++) { + if (xfer_pending_list[i]) + continue; + xfer_pending_list[i] = id; + debug("ID(%d) added to transaction pending list\n", id); + /* + * Increment command ID for next transaction. + * Valid command ID (4 bits) is from 1 to 15. + */ + id = (id % 15) + 1; + break; + } + + return id; +} + +/* + * Check whether response ID match the command ID in the transfer + * pending list. If a match is found in the transfer pending list, + * it clears the transfer pending list and return the matched + * command ID. + */ +static int get_and_clr_transfer(u32 *xfer_pending_list, size_t list_size, + u8 id) +{ + int i; + + for (i = 0; i < list_size; i++) { + if (id != xfer_pending_list[i]) + continue; + xfer_pending_list[i] = 0; + return id; + } + + return 0; +} + +/* + * Polling the FPGA configuration status. + * Return 0 for success, non-zero for error. + */ +static int reconfig_status_polling_resp(void) +{ + int ret; + unsigned long start = get_timer(0); + + while (1) { + ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS); + if (!ret) + return 0; /* configuration success */ + + if (ret != MBOX_CFGSTAT_STATE_CONFIG) + return ret; + + if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS) + break; /* time out */ + + puts("."); + udelay(RECONFIG_STATUS_INTERVAL_DELAY_US); + } + + return -ETIMEDOUT; +} + +static u32 get_resp_hdr(u32 *r_index, u32 *w_index, u32 *resp_count, + u32 *resp_buf, u32 buf_size, u32 client_id) +{ + u32 buf[MBOX_RESP_BUFFER_SIZE]; + u32 mbox_hdr; + u32 resp_len; + u32 hdr_len; + u32 i; + + if (*resp_count < buf_size) { + u32 rcv_len_max = buf_size - *resp_count; + + if (rcv_len_max > MBOX_RESP_BUFFER_SIZE) + rcv_len_max = MBOX_RESP_BUFFER_SIZE; + resp_len = mbox_rcv_resp(buf, rcv_len_max); + + for (i = 0; i < resp_len; i++) { + resp_buf[(*w_index)++] = buf[i]; + *w_index %= buf_size; + (*resp_count)++; + } + } + + /* No response in buffer */ + if (*resp_count == 0) + return 0; + + mbox_hdr = resp_buf[*r_index]; + + hdr_len = MBOX_RESP_LEN_GET(mbox_hdr); + + /* Insufficient header length to return a mailbox header */ + if ((*resp_count - 1) < hdr_len) + return 0; + + *r_index += (hdr_len + 1); + *r_index %= buf_size; + *resp_count -= (hdr_len + 1); + + /* Make sure response belongs to us */ + if (MBOX_RESP_CLIENT_GET(mbox_hdr) != client_id) + return 0; + + return mbox_hdr; +} + +/* Send bit stream data to SDM via RECONFIG_DATA mailbox command */ +static int send_reconfig_data(const void *rbf_data, size_t rbf_size, + u32 xfer_max, u32 buf_size_max) +{ + u32 response_buffer[MBOX_RESP_BUFFER_SIZE]; + u32 xfer_pending[MBOX_RESP_BUFFER_SIZE]; + u32 resp_rindex = 0; + u32 resp_windex = 0; + u32 resp_count = 0; + u32 xfer_count = 0; + int resp_err = 0; + u8 cmd_id = 1; + u32 args[3]; + int ret; + + debug("SDM xfer_max = %d\n", xfer_max); + debug("SDM buf_size_max = %x\n\n", buf_size_max); + + memset(xfer_pending, 0, sizeof(xfer_pending)); + + while (rbf_size || xfer_count) { + if (!resp_err && rbf_size && xfer_count < xfer_max) { + args[0] = MBOX_ARG_DESC_COUNT(1); + args[1] = (u64)rbf_data; + if (rbf_size >= buf_size_max) { + args[2] = buf_size_max; + rbf_size -= buf_size_max; + rbf_data += buf_size_max; + } else { + args[2] = (u64)rbf_size; + rbf_size = 0; + } + + resp_err = mbox_send_cmd_only(cmd_id, MBOX_RECONFIG_DATA, + MBOX_CMD_INDIRECT, 3, args); + if (!resp_err) { + xfer_count++; + cmd_id = add_transfer(xfer_pending, + MBOX_RESP_BUFFER_SIZE, + cmd_id); + } + puts("."); + } else { + u32 resp_hdr = get_resp_hdr(&resp_rindex, &resp_windex, + &resp_count, + response_buffer, + MBOX_RESP_BUFFER_SIZE, + MBOX_CLIENT_ID_UBOOT); + + /* + * If no valid response header found or + * non-zero length from RECONFIG_DATA + */ + if (!resp_hdr || MBOX_RESP_LEN_GET(resp_hdr)) + continue; + + /* Check for response's status */ + if (!resp_err) { + resp_err = MBOX_RESP_ERR_GET(resp_hdr); + debug("Response error code: %08x\n", resp_err); + } + + ret = get_and_clr_transfer(xfer_pending, + MBOX_RESP_BUFFER_SIZE, + MBOX_RESP_ID_GET(resp_hdr)); + if (ret) { + /* Claim and reuse the ID */ + cmd_id = (u8)ret; + xfer_count--; + } + + if (resp_err && !xfer_count) + return resp_err; + } + } + + return 0; +} + +/* + * This is the interface used by FPGA driver. + * Return 0 for success, non-zero for error. + */ +int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) +{ + int ret; + u32 resp_len = 2; + u32 resp_buf[2]; + + debug("Sending MBOX_RECONFIG...\n"); + ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, 0, + NULL, 0, &resp_len, resp_buf); + if (ret) { + puts("Failure in RECONFIG mailbox command!\n"); + return ret; + } + + ret = send_reconfig_data(rbf_data, rbf_size, resp_buf[0], resp_buf[1]); + if (ret) { + printf("RECONFIG_DATA error: %08x, %s\n", ret, + mbox_cfgstat_to_str(ret)); + return ret; + } + + /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */ + udelay(RECONFIG_STATUS_INTERVAL_DELAY_US); + + debug("Polling with MBOX_RECONFIG_STATUS...\n"); + ret = reconfig_status_polling_resp(); + if (ret) { + printf("RECONFIG_STATUS Error: %08x, %s\n", ret, + mbox_cfgstat_to_str(ret)); + return ret; + } + + puts("FPGA reconfiguration OK!\n"); + + return ret; +} diff --git a/drivers/fpga/stratix10.c b/drivers/fpga/stratix10.c deleted file mode 100644 index da8fa315e3..0000000000 --- a/drivers/fpga/stratix10.c +++ /dev/null @@ -1,285 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Intel Corporation - */ - -#include -#include -#include -#include -#include - -#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000 -#define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000 - -static const struct mbox_cfgstat_state { - int err_no; - const char *error_name; -} mbox_cfgstat_state[] = { - {MBOX_CFGSTAT_STATE_IDLE, "FPGA in idle mode."}, - {MBOX_CFGSTAT_STATE_CONFIG, "FPGA in config mode."}, - {MBOX_CFGSTAT_STATE_FAILACK, "Acknowledgment failed!"}, - {MBOX_CFGSTAT_STATE_ERROR_INVALID, "Invalid bitstream!"}, - {MBOX_CFGSTAT_STATE_ERROR_CORRUPT, "Corrupted bitstream!"}, - {MBOX_CFGSTAT_STATE_ERROR_AUTH, "Authentication failed!"}, - {MBOX_CFGSTAT_STATE_ERROR_CORE_IO, "I/O error!"}, - {MBOX_CFGSTAT_STATE_ERROR_HARDWARE, "Hardware error!"}, - {MBOX_CFGSTAT_STATE_ERROR_FAKE, "Fake error!"}, - {MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO, "Error in boot info!"}, - {MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR, "Error in QSPI!"}, - {MBOX_RESP_ERROR, "Mailbox general error!"}, - {-ETIMEDOUT, "I/O timeout error"}, - {-1, "Unknown error!"} -}; - -#define MBOX_CFGSTAT_MAX ARRAY_SIZE(mbox_cfgstat_state) - -static const char *mbox_cfgstat_to_str(int err) -{ - int i; - - for (i = 0; i < MBOX_CFGSTAT_MAX - 1; i++) { - if (mbox_cfgstat_state[i].err_no == err) - return mbox_cfgstat_state[i].error_name; - } - - return mbox_cfgstat_state[MBOX_CFGSTAT_MAX - 1].error_name; -} - -/* - * Add the ongoing transaction's command ID into pending list and return - * the command ID for next transfer. - */ -static u8 add_transfer(u32 *xfer_pending_list, size_t list_size, u8 id) -{ - int i; - - for (i = 0; i < list_size; i++) { - if (xfer_pending_list[i]) - continue; - xfer_pending_list[i] = id; - debug("ID(%d) added to transaction pending list\n", id); - /* - * Increment command ID for next transaction. - * Valid command ID (4 bits) is from 1 to 15. - */ - id = (id % 15) + 1; - break; - } - - return id; -} - -/* - * Check whether response ID match the command ID in the transfer - * pending list. If a match is found in the transfer pending list, - * it clears the transfer pending list and return the matched - * command ID. - */ -static int get_and_clr_transfer(u32 *xfer_pending_list, size_t list_size, - u8 id) -{ - int i; - - for (i = 0; i < list_size; i++) { - if (id != xfer_pending_list[i]) - continue; - xfer_pending_list[i] = 0; - return id; - } - - return 0; -} - -/* - * Polling the FPGA configuration status. - * Return 0 for success, non-zero for error. - */ -static int reconfig_status_polling_resp(void) -{ - int ret; - unsigned long start = get_timer(0); - - while (1) { - ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS); - if (!ret) - return 0; /* configuration success */ - - if (ret != MBOX_CFGSTAT_STATE_CONFIG) - return ret; - - if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS) - break; /* time out */ - - puts("."); - udelay(RECONFIG_STATUS_INTERVAL_DELAY_US); - } - - return -ETIMEDOUT; -} - -static u32 get_resp_hdr(u32 *r_index, u32 *w_index, u32 *resp_count, - u32 *resp_buf, u32 buf_size, u32 client_id) -{ - u32 buf[MBOX_RESP_BUFFER_SIZE]; - u32 mbox_hdr; - u32 resp_len; - u32 hdr_len; - u32 i; - - if (*resp_count < buf_size) { - u32 rcv_len_max = buf_size - *resp_count; - - if (rcv_len_max > MBOX_RESP_BUFFER_SIZE) - rcv_len_max = MBOX_RESP_BUFFER_SIZE; - resp_len = mbox_rcv_resp(buf, rcv_len_max); - - for (i = 0; i < resp_len; i++) { - resp_buf[(*w_index)++] = buf[i]; - *w_index %= buf_size; - (*resp_count)++; - } - } - - /* No response in buffer */ - if (*resp_count == 0) - return 0; - - mbox_hdr = resp_buf[*r_index]; - - hdr_len = MBOX_RESP_LEN_GET(mbox_hdr); - - /* Insufficient header length to return a mailbox header */ - if ((*resp_count - 1) < hdr_len) - return 0; - - *r_index += (hdr_len + 1); - *r_index %= buf_size; - *resp_count -= (hdr_len + 1); - - /* Make sure response belongs to us */ - if (MBOX_RESP_CLIENT_GET(mbox_hdr) != client_id) - return 0; - - return mbox_hdr; -} - -/* Send bit stream data to SDM via RECONFIG_DATA mailbox command */ -static int send_reconfig_data(const void *rbf_data, size_t rbf_size, - u32 xfer_max, u32 buf_size_max) -{ - u32 response_buffer[MBOX_RESP_BUFFER_SIZE]; - u32 xfer_pending[MBOX_RESP_BUFFER_SIZE]; - u32 resp_rindex = 0; - u32 resp_windex = 0; - u32 resp_count = 0; - u32 xfer_count = 0; - int resp_err = 0; - u8 cmd_id = 1; - u32 args[3]; - int ret; - - debug("SDM xfer_max = %d\n", xfer_max); - debug("SDM buf_size_max = %x\n\n", buf_size_max); - - memset(xfer_pending, 0, sizeof(xfer_pending)); - - while (rbf_size || xfer_count) { - if (!resp_err && rbf_size && xfer_count < xfer_max) { - args[0] = MBOX_ARG_DESC_COUNT(1); - args[1] = (u64)rbf_data; - if (rbf_size >= buf_size_max) { - args[2] = buf_size_max; - rbf_size -= buf_size_max; - rbf_data += buf_size_max; - } else { - args[2] = (u64)rbf_size; - rbf_size = 0; - } - - resp_err = mbox_send_cmd_only(cmd_id, MBOX_RECONFIG_DATA, - MBOX_CMD_INDIRECT, 3, args); - if (!resp_err) { - xfer_count++; - cmd_id = add_transfer(xfer_pending, - MBOX_RESP_BUFFER_SIZE, - cmd_id); - } - puts("."); - } else { - u32 resp_hdr = get_resp_hdr(&resp_rindex, &resp_windex, - &resp_count, - response_buffer, - MBOX_RESP_BUFFER_SIZE, - MBOX_CLIENT_ID_UBOOT); - - /* - * If no valid response header found or - * non-zero length from RECONFIG_DATA - */ - if (!resp_hdr || MBOX_RESP_LEN_GET(resp_hdr)) - continue; - - /* Check for response's status */ - if (!resp_err) { - resp_err = MBOX_RESP_ERR_GET(resp_hdr); - debug("Response error code: %08x\n", resp_err); - } - - ret = get_and_clr_transfer(xfer_pending, - MBOX_RESP_BUFFER_SIZE, - MBOX_RESP_ID_GET(resp_hdr)); - if (ret) { - /* Claim and reuse the ID */ - cmd_id = (u8)ret; - xfer_count--; - } - - if (resp_err && !xfer_count) - return resp_err; - } - } - - return 0; -} - -/* - * This is the interface used by FPGA driver. - * Return 0 for success, non-zero for error. - */ -int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) -{ - int ret; - u32 resp_len = 2; - u32 resp_buf[2]; - - debug("Sending MBOX_RECONFIG...\n"); - ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, 0, - NULL, 0, &resp_len, resp_buf); - if (ret) { - puts("Failure in RECONFIG mailbox command!\n"); - return ret; - } - - ret = send_reconfig_data(rbf_data, rbf_size, resp_buf[0], resp_buf[1]); - if (ret) { - printf("RECONFIG_DATA error: %08x, %s\n", ret, - mbox_cfgstat_to_str(ret)); - return ret; - } - - /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */ - udelay(RECONFIG_STATUS_INTERVAL_DELAY_US); - - debug("Polling with MBOX_RECONFIG_STATUS...\n"); - ret = reconfig_status_polling_resp(); - if (ret) { - printf("RECONFIG_STATUS Error: %08x, %s\n", ret, - mbox_cfgstat_to_str(ret)); - return ret; - } - - puts("FPGA reconfiguration OK!\n"); - - return ret; -} diff --git a/include/altera.h b/include/altera.h index 22d55cfd73..946413c66e 100644 --- a/include/altera.h +++ b/include/altera.h @@ -56,10 +56,10 @@ enum altera_family { Altera_StratixII, /* StratixV Family */ Altera_StratixV, - /* Stratix10 Family */ - Intel_FPGA_Stratix10, /* SoCFPGA Family */ Altera_SoCFPGA, + /* Intel FPGA Family with SDM (Secure Device Manager) Mailbox */ + Intel_FPGA_SDM_Mailbox, /* Add new models here */ @@ -120,8 +120,9 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); #endif -#ifdef CONFIG_FPGA_STRATIX10 -int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); +#ifdef CONFIG_FPGA_INTEL_SDM_MAILBOX +int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, + size_t rbf_size); #endif #endif /* _ALTERA_H_ */ -- cgit v1.2.3 From bd99fa59d5daaab736ce665adf2f9b2010798dfc Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Fri, 7 Aug 2020 11:50:05 +0800 Subject: arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang Reviewed-by: Ley Foon Tan --- arch/arm/mach-socfpga/Kconfig | 1 + drivers/fpga/Kconfig | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 32549913cc..26f2cf8e47 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -35,6 +35,7 @@ config TARGET_SOCFPGA_AGILEX select ARMV8_SET_SMPEN select ARMV8_SPIN_TABLE select CLK + select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE select SPL_CLK if SPL diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index dd0b39a8d1..425b52a926 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -33,7 +33,7 @@ config FPGA_CYCLON2 config FPGA_INTEL_SDM_MAILBOX bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver" - depends on TARGET_SOCFPGA_STRATIX10 + depends on TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX select FPGA_ALTERA help Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver -- cgit v1.2.3 From 5edf94d92197473defacd171fa2fe46c6626a5fa Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Mon, 10 Aug 2020 22:59:49 +0800 Subject: arm: socfpga: soc64: Add timeout waiting for NOC idle ACK Add timeout waiting for NOC idle ACK during FPGA bridge disable/enable. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/reset_manager_s10.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index 9f16bf92d5..3746e6a60c 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -9,6 +9,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -54,6 +55,8 @@ void socfpga_per_reset_all(void) void socfpga_bridges_reset(int enable) { + u32 reg; + if (enable) { /* clear idle request to all bridges */ setbits_le32(socfpga_get_sysmgr_addr() + @@ -64,9 +67,9 @@ void socfpga_bridges_reset(int enable) ~0); /* Poll until all idleack to 0 */ - while (readl(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEACK)) - ; + read_poll_timeout(readl, socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEACK, reg, !reg, 1000, + 300000); } else { /* set idle request to all bridges */ writel(~0, @@ -77,14 +80,18 @@ void socfpga_bridges_reset(int enable) writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); /* Poll until all idleack to 1 */ - while ((readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_IDLEACK) ^ - (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK))) - ; + read_poll_timeout(readl, socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEACK, reg, + reg == (SYSMGR_NOC_H2F_MSK | + SYSMGR_NOC_LWH2F_MSK), + 1000, 300000); /* Poll until all idlestatus to 1 */ - while ((readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_IDLESTATUS) ^ - (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK))) - ; + read_poll_timeout(readl, socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLESTATUS, reg, + reg == (SYSMGR_NOC_H2F_MSK | + SYSMGR_NOC_LWH2F_MSK), + 1000, 300000); /* Reset all bridges (except NOR DDR scheduler & F2S) */ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, -- cgit v1.2.3 From e2afbee50c5042fdbca78e2a6f86d9442af68783 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Mon, 10 Aug 2020 10:55:56 +0800 Subject: arm: socfpga: soc64: Document down boot_scratch_cold register usage Document down the usage of boot_scratch_cold register to avoid overlapping of usage in the code for S10 & Agilex. The boot_scratch_cold register is generally used for passing critical system info between SPL, U-Boot and Linux. Signed-off-by: Chin Liang See Signed-off-by: Siew Chin Lim Reviewed-by: Ley Foon Tan --- arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 5e3f54a6a8..4949cae97a 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -46,13 +46,21 @@ void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len); #define SYSMGR_SOC64_GPO 0xe4 #define SYSMGR_SOC64_GPI 0xe8 #define SYSMGR_SOC64_MPU 0xf0 +/* store qspi ref clock */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 +/* store osc1 clock freq */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 +/* store fpga clock freq */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD2 0x208 +/* reserved for customer use */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD3 0x20c +/* store PSCI_CPU_ON value */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD4 0x210 +/* store PSCI_CPU_ON value */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD5 0x214 +/* store VBAR_EL3 value */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD6 0x218 +/* store VBAR_EL3 value */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD7 0x21c #define SYSMGR_SOC64_BOOT_SCRATCH_COLD8 0x220 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD9 0x224 -- cgit v1.2.3 From e3fca5072bf78f7fd7eeab027d6e83bb555def9e Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Wed, 12 Aug 2020 09:56:21 +0800 Subject: arm: socfpga: mailbox: Refactor mailbox timeout event handling Add miliseconds delay when waiting for mailbox event to happen before timeout. This will ensure the timeout duration is predictive. Signed-off-by: Chee Hong Ang Reviewed-by: Ley Foon Tan --- arch/arm/mach-socfpga/mailbox_s10.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index f30e7f80a2..729d9b04fa 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -29,13 +29,14 @@ DECLARE_GLOBAL_DATA_PTR; static __always_inline int mbox_polling_resp(u32 rout) { u32 rin; - unsigned long i = ~0; + unsigned long i = 2000; while (i) { rin = MBOX_READL(MBOX_RIN); if (rout != rin) return 0; + udelay(1000); i--; } @@ -176,11 +177,15 @@ static __always_inline int mbox_send_cmd_common(u8 id, u32 cmd, u8 is_indirect, MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM); while (1) { - ret = ~0; + ret = 1000; /* Wait for doorbell from SDM */ - while (!MBOX_READL(MBOX_DOORBELL_FROM_SDM) && ret--) - ; + do { + if (MBOX_READL(MBOX_DOORBELL_FROM_SDM)) + break; + udelay(1000); + } while (--ret); + if (!ret) return -ETIMEDOUT; -- cgit v1.2.3 From 833230ed33684f399aae84633f4992106b6d3949 Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Wed, 12 Aug 2020 09:56:22 +0800 Subject: arm: socfpga: mailbox: Always read mailbox responses before returning status Mailbox driver should always check for the length of the response and read the response data before returning the response status to caller. Signed-off-by: Chee Hong Ang Reviewed-by: Ley Foon Tan --- arch/arm/mach-socfpga/mailbox_s10.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 729d9b04fa..e8a587f007 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -221,9 +221,7 @@ static __always_inline int mbox_send_cmd_common(u8 id, u32 cmd, u8 is_indirect, if ((MBOX_RESP_CLIENT_GET(resp) == MBOX_CLIENT_ID_UBOOT) && (MBOX_RESP_ID_GET(resp) == id)) { - ret = MBOX_RESP_ERR_GET(resp); - if (ret) - return ret; + int resp_err = MBOX_RESP_ERR_GET(resp); if (resp_buf_len) { buf_len = *resp_buf_len; @@ -252,7 +250,7 @@ static __always_inline int mbox_send_cmd_common(u8 id, u32 cmd, u8 is_indirect, buf_len--; } } - return ret; + return resp_err; } } }; -- cgit v1.2.3 From f6dcf407598411186b0d55b148a23d8e514a0557 Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Wed, 12 Aug 2020 09:56:23 +0800 Subject: arm: socfpga: mailbox: Support sending large mailbox command Mailbox command which is too large to fit into the mailbox FIFO command buffer can be sent to SDM in multiple parts. Signed-off-by: Chee Hong Ang Reviewed-by: Ley Foon Tan --- arch/arm/mach-socfpga/mailbox_s10.c | 113 +++++++++++++++++++++++++----------- 1 file changed, 78 insertions(+), 35 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index e8a587f007..a9ec818492 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -43,41 +43,93 @@ static __always_inline int mbox_polling_resp(u32 rout) return -ETIMEDOUT; } +static __always_inline int mbox_is_cmdbuf_full(u32 cin) +{ + return (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == MBOX_READL(MBOX_COUT)); +} + +static __always_inline int mbox_is_cmdbuf_empty(u32 cin) +{ + return (((MBOX_READL(MBOX_COUT) + 1) % MBOX_CMD_BUFFER_SIZE) == cin); +} + +static __always_inline int mbox_wait_for_cmdbuf_empty(u32 cin) +{ + int timeout = 2000; + + while (timeout) { + if (mbox_is_cmdbuf_empty(cin)) + return 0; + udelay(1000); + timeout--; + } + + return -ETIMEDOUT; +} + +static __always_inline int mbox_write_cmd_buffer(u32 *cin, u32 data, + int *is_cmdbuf_overflow) +{ + int timeout = 1000; + + while (timeout) { + if (mbox_is_cmdbuf_full(*cin)) { + if (is_cmdbuf_overflow && + *is_cmdbuf_overflow == 0) { + /* Trigger SDM doorbell */ + MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM); + *is_cmdbuf_overflow = 1; + } + udelay(1000); + } else { + /* write header to circular buffer */ + MBOX_WRITE_CMD_BUF(data, (*cin)++); + *cin %= MBOX_CMD_BUFFER_SIZE; + MBOX_WRITEL(*cin, MBOX_CIN); + break; + } + timeout--; + } + + if (!timeout) + return -ETIMEDOUT; + + /* Wait for the SDM to drain the FIFO command buffer */ + if (is_cmdbuf_overflow && *is_cmdbuf_overflow) + return mbox_wait_for_cmdbuf_empty(*cin); + + return 0; +} + /* Check for available slot and write to circular buffer. * It also update command valid offset (cin) register. */ static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len, u32 *arg) { - u32 cin; - u32 cout; - u32 i; - - cin = MBOX_READL(MBOX_CIN) % MBOX_CMD_BUFFER_SIZE; - cout = MBOX_READL(MBOX_COUT) % MBOX_CMD_BUFFER_SIZE; + int i, ret; + int is_cmdbuf_overflow = 0; + u32 cin = MBOX_READL(MBOX_CIN) % MBOX_CMD_BUFFER_SIZE; - /* if command buffer is full or not enough free space - * to fit the data. Note, len is in u32 unit. - */ - if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout || - ((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) % - MBOX_CMD_BUFFER_SIZE) < (len + 1)) - return -ENOMEM; - - /* write header to circular buffer */ - MBOX_WRITE_CMD_BUF(header, cin++); - /* wrapping around when it reach the buffer size */ - cin %= MBOX_CMD_BUFFER_SIZE; + ret = mbox_write_cmd_buffer(&cin, header, &is_cmdbuf_overflow); + if (ret) + return ret; /* write arguments */ for (i = 0; i < len; i++) { - MBOX_WRITE_CMD_BUF(arg[i], cin++); - /* wrapping around when it reach the buffer size */ - cin %= MBOX_CMD_BUFFER_SIZE; + is_cmdbuf_overflow = 0; + ret = mbox_write_cmd_buffer(&cin, arg[i], &is_cmdbuf_overflow); + if (ret) + return ret; } - /* write command valid offset */ - MBOX_WRITEL(cin, MBOX_CIN); + /* If SDM doorbell is not triggered after the last data is + * written into mailbox FIFO command buffer, trigger the + * SDM doorbell again to ensure SDM able to read the remaining + * data. + */ + if (!is_cmdbuf_overflow) + MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM); return 0; } @@ -90,10 +142,6 @@ static __always_inline int mbox_prepare_cmd_only(u8 id, u32 cmd, u32 header; int ret; - /* Total length is command + argument length */ - if ((len + 1) > MBOX_CMD_BUFFER_SIZE) - return -EINVAL; - if (cmd > MBOX_MAX_CMD_INDEX) return -EINVAL; @@ -110,11 +158,7 @@ static __always_inline int mbox_send_cmd_only_common(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg) { - int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg); - /* write doorbell */ - MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM); - - return ret; + return mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg); } /* Return number of responses received in buffer */ @@ -167,15 +211,14 @@ static __always_inline int mbox_send_cmd_common(u8 id, u32 cmd, u8 is_indirect, status = MBOX_READL(MBOX_STATUS) & MBOX_STATUS_UA_MSK; /* Write urgent command to urgent register */ MBOX_WRITEL(cmd, MBOX_URG); + /* write doorbell */ + MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM); } else { ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg); if (ret) return ret; } - /* write doorbell */ - MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM); - while (1) { ret = 1000; -- cgit v1.2.3 From 6a48f95c6be15f0b2cad49b9ba1b7e04374da641 Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Wed, 12 Aug 2020 09:56:24 +0800 Subject: arm: socfpga: mailbox: Update mailbox response codes Sync latest mailbox response codes from SDM firmware. Signed-off-by: Ley Foon Tan Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 38 ++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h index 55707ab9c5..4d783119ea 100644 --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h @@ -67,8 +67,42 @@ enum ALT_SDM_MBOX_RESP_CODE { MBOX_RESP_UNKNOWN_BR = 2, /* CMD code not recognized by firmware */ MBOX_RESP_UNKNOWN = 3, - /* Indicates that the device is not configured */ - MBOX_RESP_NOT_CONFIGURED = 256, + /* Length setting is not a valid length for this CMD type */ + MBOX_RESP_INVALID_LEN = 4, + /* Indirect setting is not valid for this CMD type */ + MBOX_RESP_INVALID_INDIRECT_SETTING = 5, + /* HW source which is not allowed to send CMD type */ + MBOX_RESP_CMD_INVALID_ON_SRC = 6, + /* Client with ID not associated with any running PR CMD tries to run + * RECONFIG_DATA RECONFIG_STATUS and accessing QSPI / SDMMC using ID + * without exclusive access + */ + MBOX_RESP_CLIENT_ID_NO_MATCH = 8, + /* Address provided to the system is invalid (alignment, range + * permission) + */ + MBOX_RESP_INVALID_ADDR = 0x9, + /* Signature authentication failed */ + MBOX_RESP_AUTH_FAIL = 0xA, + /* CMD timed out */ + MBOX_RESP_TIMEOUT = 0xB, + /* HW (i.e. QSPI) is not ready (initialized or configured) */ + MBOX_RESP_HW_NOT_RDY = 0xC, + /* Invalid license for IID registration */ + MBOX_RESP_PUF_ACCCES_FAILED = 0x80, + MBOX_PUF_ENROLL_DISABLE = 0x81, + MBOX_RESP_PUF_ENROLL_FAIL = 0x82, + MBOX_RESP_PUF_RAM_TEST_FAIL = 0x83, + MBOX_RESP_ATTEST_CERT_GEN_FAIL = 0x84, + /* Operation not allowed under current security settings */ + MBOX_RESP_NOT_ALLOWED_UNDER_SECURITY_SETTINGS = 0x85, + MBOX_RESP_PUF_TRNG_FAIL = 0x86, + MBOX_RESP_FUSE_ALREADY_BLOWN = 0x87, + MBOX_RESP_INVALID_SIGNATURE = 0x88, + MBOX_RESP_INVALID_HASH = 0x8b, + MBOX_RESP_INVALID_CERTIFICATE = 0x91, + /* Indicates that the device (FPGA or HPS) is not configured */ + MBOX_RESP_NOT_CONFIGURED = 0x100, /* Indicates that the device is busy */ MBOX_RESP_DEVICE_BUSY = 0x1FF, /* Indicates that there is no valid response available */ -- cgit v1.2.3 From de84e2d8c9e60452a2a1a6f99474d54a9919c024 Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Wed, 12 Aug 2020 09:56:25 +0800 Subject: arm: socfpga: mailbox: Add mailbox retry support Resend mailbox command for 3 times with 2ms interval in between if it receives MBOX_RESP_TIMEOUT and MBOX_RESP_DEVICE_BUSY response code. Add a wrapper function mbox_send_cmd_common_retry() for retry, change all the callers to use this wrapper function. Signed-off-by: Ley Foon Tan Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/mailbox_s10.c | 40 ++++++++++++++++++++++++++++--------- 1 file changed, 31 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index a9ec818492..18d44924e6 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -296,11 +296,33 @@ static __always_inline int mbox_send_cmd_common(u8 id, u32 cmd, u8 is_indirect, return resp_err; } } - }; + } return -EIO; } +static __always_inline int mbox_send_cmd_common_retry(u8 id, u32 cmd, + u8 is_indirect, + u32 len, u32 *arg, + u8 urgent, + u32 *resp_buf_len, + u32 *resp_buf) +{ + int ret; + int i; + + for (i = 0; i < 3; i++) { + ret = mbox_send_cmd_common(id, cmd, is_indirect, len, arg, + urgent, resp_buf_len, resp_buf); + if (ret == MBOX_RESP_TIMEOUT || ret == MBOX_RESP_DEVICE_BUSY) + udelay(2000); /* wait for 2ms before resend */ + else + break; + } + + return ret; +} + int mbox_init(void) { int ret; @@ -395,10 +417,10 @@ static __always_inline int mbox_get_fpga_config_status_common(u32 cmd) int ret; reconfig_status_resp_len = RECONFIG_STATUS_RESPONSE_LEN; - ret = mbox_send_cmd_common(MBOX_ID_UBOOT, cmd, - MBOX_CMD_DIRECT, 0, NULL, 0, - &reconfig_status_resp_len, - reconfig_status_resp); + ret = mbox_send_cmd_common_retry(MBOX_ID_UBOOT, cmd, + MBOX_CMD_DIRECT, 0, NULL, 0, + &reconfig_status_resp_len, + reconfig_status_resp); if (ret) return ret; @@ -438,16 +460,16 @@ int __secure mbox_get_fpga_config_status_psci(u32 cmd) int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, u32 *resp_buf) { - return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent, - resp_buf_len, resp_buf); + return mbox_send_cmd_common_retry(id, cmd, is_indirect, len, arg, + urgent, resp_buf_len, resp_buf); } int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, u32 *resp_buf) { - return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent, - resp_buf_len, resp_buf); + return mbox_send_cmd_common_retry(id, cmd, is_indirect, len, arg, + urgent, resp_buf_len, resp_buf); } int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg) -- cgit v1.2.3 From 5c0adb0a71f1c52e950edbac642b39d835fff845 Mon Sep 17 00:00:00 2001 From: Dalon Westergreen Date: Fri, 27 Sep 2019 18:43:24 -0700 Subject: arm: socfpga: arria10: Add qts-filter for Arria10 socfpga Add a script to process HPS handoff data and generate a header for inclusion in u-boot specific devicetree addons. The header should be included in the top level of u-boot.dtsi. Signed-off-by: Dalon Westergreen Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/qts-filter-a10.sh | 141 ++++++++++++++++++++++++++++++++ doc/README.socfpga | 37 ++++++++- 2 files changed, 174 insertions(+), 4 deletions(-) create mode 100755 arch/arm/mach-socfpga/qts-filter-a10.sh (limited to 'arch') diff --git a/arch/arm/mach-socfpga/qts-filter-a10.sh b/arch/arm/mach-socfpga/qts-filter-a10.sh new file mode 100755 index 0000000000..57d77e8e12 --- /dev/null +++ b/arch/arm/mach-socfpga/qts-filter-a10.sh @@ -0,0 +1,141 @@ +#!/bin/bash + +# +# helper function to convert from DOS to Unix, if necessary, and handle +# lines ending in '\'. +# +fix_newlines_in_macros() { + sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1 +} + +#filter out only what we need from a10 hps.xml +grep_a10_hps_config() { + egrep "clk_hz|i_clk_mgr|i_io48_pin_mux|AXI_SLAVE|AXI_MASTER" +} + +# +# Process hps.xml +# $1: hps.xml +# $2: Output File +# +process_a10_hps_config() { + hps_xml="$1" + outfile="$2" + + (cat << EOF +// SPDX-License-Identifier: BSD-3-Clause +/* + * Intel Arria 10 SoCFPGA configuration + */ + +#ifndef __SOCFPGA_ARRIA10_CONFIG_H__ +#define __SOCFPGA_ARRIA10_CONFIG_H__ + +EOF + + echo "/* Clocks */" + fix_newlines_in_macros \ + ${hps_xml} | egrep "clk_hz" | + awk -F"'" '{ gsub("\\.","_",$2) ; \ + print "#define" " " toupper($2) " " $4}' | + sed 's/\.[0-9]//' | + sed 's/I_CLK_MGR_//' | + sort + fix_newlines_in_macros \ + ${hps_xml} | egrep "i_clk_mgr_mainpll" | + awk -F"'" '{ gsub("\\.","_",$2) ; \ + print "#define" " " toupper($2) " " $4}' | + sed 's/\.[0-9]//' | + sed 's/I_CLK_MGR_//' | + sort + fix_newlines_in_macros \ + ${hps_xml} | egrep "i_clk_mgr_perpll" | + awk -F"'" '{ gsub("\\.","_",$2) ; \ + print "#define" " " toupper($2) " " $4}' | + sed 's/\.[0-9]//' | + sed 's/I_CLK_MGR_//' | + sort + fix_newlines_in_macros \ + ${hps_xml} | egrep "i_clk_mgr_clkmgr" | + awk -F"'" '{ gsub("\\.","_",$2) ; \ + print "#define" " " toupper($2) " " $4}' | + sed 's/\.[0-9]//' | + sed 's/I_CLK_MGR_//' | + sort + fix_newlines_in_macros \ + ${hps_xml} | egrep "i_clk_mgr_alteragrp" | + awk -F"'" '{ gsub("\\.","_",$2) ; \ + print "#define" " " toupper($2) " " $4}' | + sed 's/\.[0-9]//' | + sed 's/I_CLK_MGR_//' | + sort + echo "#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \\" + echo " (ALTERAGRP_MPUCLK_MAINCNT))" + echo "#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \\" + echo " (ALTERAGRP_NOCCLK_MAINCNT))" + + echo + echo "/* Pin Mux Configuration */" + fix_newlines_in_macros \ + ${hps_xml} | egrep "i_io48_pin_mux" | + awk -F"'" '{ gsub("\\.","_",$2) ; \ + print "#define" " " toupper($2) " " $4}' | + sed 's/I_IO48_PIN_MUX_//' | + sed 's/SHARED_3V_IO_GRP_//' | + sed 's/FPGA_INTERFACE_GRP_//' | + sed 's/DEDICATED_IO_GRP_//' | + sed 's/CONFIGURATION_DEDICATED/CONFIG/' | + sort + + echo + echo "/* Bridge Configuration */" + fix_newlines_in_macros \ + ${hps_xml} | egrep "AXI_SLAVE|AXI_MASTER" | + awk -F"'" '{ gsub("\\.","_",$2) ; \ + print "#define" " " toupper($2) " " $4}' | + sed 's/true/1/' | + sed 's/false/0/' | + sort + + echo + echo "/* Voltage Select for Config IO */" + echo "#define CONFIG_IO_BANK_VSEL \\" + echo " (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \\" + echo " (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))" + + echo + echo "/* Macro for Config IO bit mapping */" + echo -n "#define CONFIG_IO_MACRO(NAME) " + echo "(((NAME ## _RTRIM & 0xff) << 19) | \\" + echo " ((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \\" + echo " ((NAME ## _WK_PU_EN & 0x1) << 16) | \\" + echo " ((NAME ## _PU_SLW_RT & 0x1) << 13) | \\" + echo " ((NAME ## _PU_DRV_STRG & 0xf) << 8) | \\" + echo " ((NAME ## _PD_SLW_RT & 0x1) << 5) | \\" + echo " (NAME ## _PD_DRV_STRG & 0x1f))" + + cat << EOF + +#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */ +EOF + ) > "${outfile}" +} + +usage() { + echo "$0 [hps_xml] [output_file]" + echo "Process QTS-generated hps.xml into devicetree header." + echo "" + echo " hps_xml - hps.xml file from hps_isw_handoff" + echo " output_file - Output header file for dtsi include" + echo "" +} + +hps_xml="$1" +outfile="$2" + +if [ "$#" -ne 2 ] ; then + usage + exit 1 +fi + +process_a10_hps_config "${hps_xml}" "${outfile}" diff --git a/doc/README.socfpga b/doc/README.socfpga index cae0ef1a21..4d73398eb9 100644 --- a/doc/README.socfpga +++ b/doc/README.socfpga @@ -16,9 +16,9 @@ controller support within SOCFPGA #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 -> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM --------------------------------------------------- -Generating the handoff header files for U-Boot SPL --------------------------------------------------- +--------------------------------------------------------------------- +Cyclone 5 / Arria 5 generating the handoff header files for U-Boot SPL +--------------------------------------------------------------------- This text is assuming quartus 16.1, but newer versions will probably work just fine too; verified with DE1_SOC_Linux_FB demo project (https://github.com/VCTLabs/DE1_SOC_Linux_FB). @@ -32,7 +32,7 @@ Rebuilding your Quartus project Choose one of the follwing methods, either command line or GUI. -Using the comaand line +Using the command line ~~~~~~~~~~~~~~~~~~~~~~ First run the embedded command shell, using your path to the Quartus install: @@ -147,3 +147,32 @@ Note: file sizes will differ slightly depending on the selected board. Now your board is ready for full mainline support including U-Boot SPL. The Preloader will not be needed any more. + +---------------------------------------------------------- +Arria 10 generating the handoff header files for U-Boot SPL +---------------------------------------------------------- + +A header file for inclusion in a devicetree for Arria10 can be generated +by the qts-filter-a10.sh script directly from the hps_isw_handoff/hps.xml +file generated during the FPGA project compilation. The header contains +all PLL, clock, pinmux, and bridge configurations required. + +Please look at the socfpga_arria10_socdk_sdmmc-u-boot.dtsi for an example +that includes use of the generated handoff header. + +Devicetree header generation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The qts-filter-a10.sh script can process the compile time genetated hps.xml +to create the appropriate devicetree header. + + + $ ./arch/arm/mach-socfpga/qts-filter-a10.sh \ + \ + + + hps_xml - hps_isw_handoff/hps.xml from Quartus project + output_file - Output filename and location for header file + +The script generates a single header file names that should +be placed in arch/arm/dts. -- cgit v1.2.3 From ed9c0823c53a62ed5dcbfec21e84d040e0ada53c Mon Sep 17 00:00:00 2001 From: Dalon Westergreen Date: Fri, 4 Oct 2019 14:23:48 -0700 Subject: arm: socfpga: arria10: Add handoff header for A10 SoCDK SDMMC Add the qts-filter-a10.sh generated handoff header file for the Arria10 SoCDK SDMMC u-boot device tree. Signed-off-by: Dalon Westergreen Signed-off-by: Ley Foon Tan --- arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h | 305 +++++++++++++++++++++ 1 file changed, 305 insertions(+) create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h (limited to 'arch') diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h new file mode 100644 index 0000000000..4e3fe30578 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Intel Arria 10 SoCFPGA configuration + */ + +#ifndef __SOCFPGA_ARRIA10_CONFIG_H__ +#define __SOCFPGA_ARRIA10_CONFIG_H__ + +/* Clocks */ +#define CB_INTOSC_LS_CLK_HZ 60000000 +#define EMAC0_CLK_HZ 250000000 +#define EMAC1_CLK_HZ 250000000 +#define EMAC2_CLK_HZ 250000000 +#define EOSC1_CLK_HZ 25000000 +#define F2H_FREE_CLK_HZ 200000000 +#define H2F_USER0_CLK_HZ 400000000 +#define H2F_USER1_CLK_HZ 400000000 +#define L3_MAIN_FREE_CLK_HZ 200000000 +#define SDMMC_CLK_HZ 200000000 +#define TPIU_CLK_HZ 100000000 +#define MAINPLLGRP_CNTR15CLK_CNT 900 +#define MAINPLLGRP_CNTR2CLK_CNT 900 +#define MAINPLLGRP_CNTR3CLK_CNT 900 +#define MAINPLLGRP_CNTR4CLK_CNT 900 +#define MAINPLLGRP_CNTR5CLK_CNT 900 +#define MAINPLLGRP_CNTR6CLK_CNT 900 +#define MAINPLLGRP_CNTR7CLK_CNT 900 +#define MAINPLLGRP_CNTR7CLK_SRC 0 +#define MAINPLLGRP_CNTR8CLK_CNT 900 +#define MAINPLLGRP_CNTR9CLK_CNT 900 +#define MAINPLLGRP_CNTR9CLK_SRC 0 +#define MAINPLLGRP_MPUCLK_CNT 0 +#define MAINPLLGRP_MPUCLK_SRC 0 +#define MAINPLLGRP_NOCCLK_CNT 0 +#define MAINPLLGRP_NOCCLK_SRC 0 +#define MAINPLLGRP_NOCDIV_CSATCLK 0 +#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1 +#define MAINPLLGRP_NOCDIV_CSTRACECLK 1 +#define MAINPLLGRP_NOCDIV_L4MAINCLK 0 +#define MAINPLLGRP_NOCDIV_L4MPCLK 0 +#define MAINPLLGRP_NOCDIV_L4SPCLK 2 +#define MAINPLLGRP_VCO0_PSRC 0 +#define MAINPLLGRP_VCO1_DENOM 1 +#define MAINPLLGRP_VCO1_NUMER 191 +#define PERPLLGRP_CNTR2CLK_CNT 7 +#define PERPLLGRP_CNTR2CLK_SRC 1 +#define PERPLLGRP_CNTR3CLK_CNT 900 +#define PERPLLGRP_CNTR3CLK_SRC 1 +#define PERPLLGRP_CNTR4CLK_CNT 19 +#define PERPLLGRP_CNTR4CLK_SRC 1 +#define PERPLLGRP_CNTR5CLK_CNT 499 +#define PERPLLGRP_CNTR5CLK_SRC 1 +#define PERPLLGRP_CNTR6CLK_CNT 9 +#define PERPLLGRP_CNTR6CLK_SRC 1 +#define PERPLLGRP_CNTR7CLK_CNT 900 +#define PERPLLGRP_CNTR8CLK_CNT 900 +#define PERPLLGRP_CNTR8CLK_SRC 0 +#define PERPLLGRP_CNTR9CLK_CNT 900 +#define PERPLLGRP_EMACCTL_EMAC0SEL 0 +#define PERPLLGRP_EMACCTL_EMAC1SEL 0 +#define PERPLLGRP_EMACCTL_EMAC2SEL 0 +#define PERPLLGRP_GPIODIV_GPIODBCLK 32000 +#define PERPLLGRP_VCO0_PSRC 0 +#define PERPLLGRP_VCO1_DENOM 1 +#define PERPLLGRP_VCO1_NUMER 159 +#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16 +#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8 +#define CLKMGR_TESTIOCTRL_PERICLKSEL 8 +#define ALTERAGRP_MPUCLK_MAINCNT 1 +#define ALTERAGRP_MPUCLK_PERICNT 900 +#define ALTERAGRP_NOCCLK_MAINCNT 11 +#define ALTERAGRP_NOCCLK_PERICNT 900 +#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \ + (ALTERAGRP_MPUCLK_MAINCNT)) +#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \ + (ALTERAGRP_NOCCLK_MAINCNT)) + +/* Pin Mux Configuration */ +#define CONFIG_IO_10_INPUT_BUF_EN 0 +#define CONFIG_IO_10_PD_DRV_STRG 0 +#define CONFIG_IO_10_PD_SLW_RT 0 +#define CONFIG_IO_10_PU_DRV_STRG 0 +#define CONFIG_IO_10_PU_SLW_RT 0 +#define CONFIG_IO_10_RTRIM 1 +#define CONFIG_IO_10_WK_PU_EN 1 +#define CONFIG_IO_11_INPUT_BUF_EN 0 +#define CONFIG_IO_11_PD_DRV_STRG 0 +#define CONFIG_IO_11_PD_SLW_RT 0 +#define CONFIG_IO_11_PU_DRV_STRG 0 +#define CONFIG_IO_11_PU_SLW_RT 0 +#define CONFIG_IO_11_RTRIM 1 +#define CONFIG_IO_11_WK_PU_EN 1 +#define CONFIG_IO_12_INPUT_BUF_EN 1 +#define CONFIG_IO_12_PD_DRV_STRG 10 +#define CONFIG_IO_12_PD_SLW_RT 1 +#define CONFIG_IO_12_PU_DRV_STRG 8 +#define CONFIG_IO_12_PU_SLW_RT 1 +#define CONFIG_IO_12_RTRIM 1 +#define CONFIG_IO_12_WK_PU_EN 1 +#define CONFIG_IO_13_INPUT_BUF_EN 1 +#define CONFIG_IO_13_PD_DRV_STRG 10 +#define CONFIG_IO_13_PD_SLW_RT 1 +#define CONFIG_IO_13_PU_DRV_STRG 8 +#define CONFIG_IO_13_PU_SLW_RT 1 +#define CONFIG_IO_13_RTRIM 1 +#define CONFIG_IO_13_WK_PU_EN 1 +#define CONFIG_IO_14_INPUT_BUF_EN 1 +#define CONFIG_IO_14_PD_DRV_STRG 10 +#define CONFIG_IO_14_PD_SLW_RT 1 +#define CONFIG_IO_14_PU_DRV_STRG 8 +#define CONFIG_IO_14_PU_SLW_RT 1 +#define CONFIG_IO_14_RTRIM 1 +#define CONFIG_IO_14_WK_PU_EN 1 +#define CONFIG_IO_15_INPUT_BUF_EN 1 +#define CONFIG_IO_15_PD_DRV_STRG 10 +#define CONFIG_IO_15_PD_SLW_RT 1 +#define CONFIG_IO_15_PU_DRV_STRG 8 +#define CONFIG_IO_15_PU_SLW_RT 1 +#define CONFIG_IO_15_RTRIM 1 +#define CONFIG_IO_15_WK_PU_EN 1 +#define CONFIG_IO_16_INPUT_BUF_EN 0 +#define CONFIG_IO_16_PD_DRV_STRG 10 +#define CONFIG_IO_16_PD_SLW_RT 1 +#define CONFIG_IO_16_PU_DRV_STRG 8 +#define CONFIG_IO_16_PU_SLW_RT 1 +#define CONFIG_IO_16_RTRIM 1 +#define CONFIG_IO_16_WK_PU_EN 0 +#define CONFIG_IO_17_INPUT_BUF_EN 1 +#define CONFIG_IO_17_PD_DRV_STRG 10 +#define CONFIG_IO_17_PD_SLW_RT 1 +#define CONFIG_IO_17_PU_DRV_STRG 8 +#define CONFIG_IO_17_PU_SLW_RT 1 +#define CONFIG_IO_17_RTRIM 1 +#define CONFIG_IO_17_WK_PU_EN 0 +#define CONFIG_IO_1_INPUT_BUF_EN 1 +#define CONFIG_IO_1_PD_DRV_STRG 10 +#define CONFIG_IO_1_PD_SLW_RT 0 +#define CONFIG_IO_1_PU_DRV_STRG 8 +#define CONFIG_IO_1_PU_SLW_RT 0 +#define CONFIG_IO_1_RTRIM 1 +#define CONFIG_IO_1_WK_PU_EN 1 +#define CONFIG_IO_2_INPUT_BUF_EN 1 +#define CONFIG_IO_2_PD_DRV_STRG 10 +#define CONFIG_IO_2_PD_SLW_RT 0 +#define CONFIG_IO_2_PU_DRV_STRG 8 +#define CONFIG_IO_2_PU_SLW_RT 0 +#define CONFIG_IO_2_RTRIM 1 +#define CONFIG_IO_2_WK_PU_EN 1 +#define CONFIG_IO_3_INPUT_BUF_EN 1 +#define CONFIG_IO_3_PD_DRV_STRG 10 +#define CONFIG_IO_3_PD_SLW_RT 0 +#define CONFIG_IO_3_PU_DRV_STRG 8 +#define CONFIG_IO_3_PU_SLW_RT 0 +#define CONFIG_IO_3_RTRIM 1 +#define CONFIG_IO_3_WK_PU_EN 1 +#define CONFIG_IO_4_INPUT_BUF_EN 1 +#define CONFIG_IO_4_PD_DRV_STRG 10 +#define CONFIG_IO_4_PD_SLW_RT 1 +#define CONFIG_IO_4_PU_DRV_STRG 8 +#define CONFIG_IO_4_PU_SLW_RT 1 +#define CONFIG_IO_4_RTRIM 1 +#define CONFIG_IO_4_WK_PU_EN 0 +#define CONFIG_IO_5_INPUT_BUF_EN 1 +#define CONFIG_IO_5_PD_DRV_STRG 10 +#define CONFIG_IO_5_PD_SLW_RT 1 +#define CONFIG_IO_5_PU_DRV_STRG 8 +#define CONFIG_IO_5_PU_SLW_RT 1 +#define CONFIG_IO_5_RTRIM 1 +#define CONFIG_IO_5_WK_PU_EN 0 +#define CONFIG_IO_6_INPUT_BUF_EN 0 +#define CONFIG_IO_6_PD_DRV_STRG 10 +#define CONFIG_IO_6_PD_SLW_RT 1 +#define CONFIG_IO_6_PU_DRV_STRG 8 +#define CONFIG_IO_6_PU_SLW_RT 1 +#define CONFIG_IO_6_RTRIM 1 +#define CONFIG_IO_6_WK_PU_EN 0 +#define CONFIG_IO_7_INPUT_BUF_EN 1 +#define CONFIG_IO_7_PD_DRV_STRG 10 +#define CONFIG_IO_7_PD_SLW_RT 1 +#define CONFIG_IO_7_PU_DRV_STRG 8 +#define CONFIG_IO_7_PU_SLW_RT 1 +#define CONFIG_IO_7_RTRIM 1 +#define CONFIG_IO_7_WK_PU_EN 0 +#define CONFIG_IO_8_INPUT_BUF_EN 1 +#define CONFIG_IO_8_PD_DRV_STRG 10 +#define CONFIG_IO_8_PD_SLW_RT 1 +#define CONFIG_IO_8_PU_DRV_STRG 8 +#define CONFIG_IO_8_PU_SLW_RT 1 +#define CONFIG_IO_8_RTRIM 1 +#define CONFIG_IO_8_WK_PU_EN 0 +#define CONFIG_IO_9_INPUT_BUF_EN 1 +#define CONFIG_IO_9_PD_DRV_STRG 10 +#define CONFIG_IO_9_PD_SLW_RT 1 +#define CONFIG_IO_9_PU_DRV_STRG 8 +#define CONFIG_IO_9_PU_SLW_RT 1 +#define CONFIG_IO_9_RTRIM 1 +#define CONFIG_IO_9_WK_PU_EN 0 +#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1 +#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1 +#define PINMUX_DEDICATED_IO_10_SEL 10 +#define PINMUX_DEDICATED_IO_11_SEL 10 +#define PINMUX_DEDICATED_IO_12_SEL 8 +#define PINMUX_DEDICATED_IO_13_SEL 8 +#define PINMUX_DEDICATED_IO_14_SEL 8 +#define PINMUX_DEDICATED_IO_15_SEL 8 +#define PINMUX_DEDICATED_IO_16_SEL 13 +#define PINMUX_DEDICATED_IO_17_SEL 13 +#define PINMUX_DEDICATED_IO_4_SEL 8 +#define PINMUX_DEDICATED_IO_5_SEL 8 +#define PINMUX_DEDICATED_IO_6_SEL 8 +#define PINMUX_DEDICATED_IO_7_SEL 8 +#define PINMUX_DEDICATED_IO_8_SEL 8 +#define PINMUX_DEDICATED_IO_9_SEL 8 +#define PINMUX_I2C0_USEFPGA_SEL 0 +#define PINMUX_I2C1_USEFPGA_SEL 0 +#define PINMUX_I2CEMAC0_USEFPGA_SEL 0 +#define PINMUX_I2CEMAC1_USEFPGA_SEL 0 +#define PINMUX_I2CEMAC2_USEFPGA_SEL 0 +#define PINMUX_NAND_USEFPGA_SEL 0 +#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0 +#define PINMUX_QSPI_USEFPGA_SEL 0 +#define PINMUX_RGMII0_USEFPGA_SEL 0 +#define PINMUX_RGMII1_USEFPGA_SEL 0 +#define PINMUX_RGMII2_USEFPGA_SEL 0 +#define PINMUX_SDMMC_USEFPGA_SEL 0 +#define PINMUX_SHARED_IO_Q1_10_SEL 8 +#define PINMUX_SHARED_IO_Q1_11_SEL 8 +#define PINMUX_SHARED_IO_Q1_12_SEL 8 +#define PINMUX_SHARED_IO_Q1_1_SEL 8 +#define PINMUX_SHARED_IO_Q1_2_SEL 8 +#define PINMUX_SHARED_IO_Q1_3_SEL 8 +#define PINMUX_SHARED_IO_Q1_4_SEL 8 +#define PINMUX_SHARED_IO_Q1_5_SEL 8 +#define PINMUX_SHARED_IO_Q1_6_SEL 8 +#define PINMUX_SHARED_IO_Q1_7_SEL 8 +#define PINMUX_SHARED_IO_Q1_8_SEL 8 +#define PINMUX_SHARED_IO_Q1_9_SEL 8 +#define PINMUX_SHARED_IO_Q2_10_SEL 4 +#define PINMUX_SHARED_IO_Q2_11_SEL 4 +#define PINMUX_SHARED_IO_Q2_12_SEL 4 +#define PINMUX_SHARED_IO_Q2_1_SEL 4 +#define PINMUX_SHARED_IO_Q2_2_SEL 4 +#define PINMUX_SHARED_IO_Q2_3_SEL 4 +#define PINMUX_SHARED_IO_Q2_4_SEL 4 +#define PINMUX_SHARED_IO_Q2_5_SEL 4 +#define PINMUX_SHARED_IO_Q2_6_SEL 4 +#define PINMUX_SHARED_IO_Q2_7_SEL 4 +#define PINMUX_SHARED_IO_Q2_8_SEL 4 +#define PINMUX_SHARED_IO_Q2_9_SEL 4 +#define PINMUX_SHARED_IO_Q3_10_SEL 10 +#define PINMUX_SHARED_IO_Q3_11_SEL 1 +#define PINMUX_SHARED_IO_Q3_12_SEL 1 +#define PINMUX_SHARED_IO_Q3_1_SEL 3 +#define PINMUX_SHARED_IO_Q3_2_SEL 3 +#define PINMUX_SHARED_IO_Q3_3_SEL 3 +#define PINMUX_SHARED_IO_Q3_4_SEL 3 +#define PINMUX_SHARED_IO_Q3_5_SEL 3 +#define PINMUX_SHARED_IO_Q3_6_SEL 15 +#define PINMUX_SHARED_IO_Q3_7_SEL 10 +#define PINMUX_SHARED_IO_Q3_8_SEL 10 +#define PINMUX_SHARED_IO_Q3_9_SEL 10 +#define PINMUX_SHARED_IO_Q4_10_SEL 12 +#define PINMUX_SHARED_IO_Q4_11_SEL 12 +#define PINMUX_SHARED_IO_Q4_12_SEL 12 +#define PINMUX_SHARED_IO_Q4_1_SEL 0 +#define PINMUX_SHARED_IO_Q4_2_SEL 0 +#define PINMUX_SHARED_IO_Q4_3_SEL 15 +#define PINMUX_SHARED_IO_Q4_4_SEL 12 +#define PINMUX_SHARED_IO_Q4_5_SEL 15 +#define PINMUX_SHARED_IO_Q4_6_SEL 15 +#define PINMUX_SHARED_IO_Q4_7_SEL 10 +#define PINMUX_SHARED_IO_Q4_8_SEL 15 +#define PINMUX_SHARED_IO_Q4_9_SEL 12 +#define PINMUX_SPIM0_USEFPGA_SEL 0 +#define PINMUX_SPIM1_USEFPGA_SEL 0 +#define PINMUX_SPIS0_USEFPGA_SEL 0 +#define PINMUX_SPIS1_USEFPGA_SEL 0 +#define PINMUX_UART0_USEFPGA_SEL 0 +#define PINMUX_UART1_USEFPGA_SEL 0 +#define PINMUX_USB0_USEFPGA_SEL 0 +#define PINMUX_USB1_USEFPGA_SEL 0 + +/* Bridge Configuration */ +#define F2H_AXI_SLAVE 1 +#define F2SDRAM0_AXI_SLAVE 1 +#define F2SDRAM1_AXI_SLAVE 0 +#define F2SDRAM2_AXI_SLAVE 1 +#define H2F_AXI_MASTER 1 +#define LWH2F_AXI_MASTER 1 + +/* Voltage Select for Config IO */ +#define CONFIG_IO_BANK_VSEL \ + (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \ + (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3)) + +/* Macro for Config IO bit mapping */ +#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \ + ((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \ + ((NAME ## _WK_PU_EN & 0x1) << 16) | \ + ((NAME ## _PU_SLW_RT & 0x1) << 13) | \ + ((NAME ## _PU_DRV_STRG & 0xf) << 8) | \ + ((NAME ## _PD_SLW_RT & 0x1) << 5) | \ + (NAME ## _PD_DRV_STRG & 0x1f)) + +#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */ -- cgit v1.2.3 From 98c28a79b44ef7b008091f7a5aa4f1a76e1d602b Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Wed, 8 Jul 2020 16:34:01 +0800 Subject: arm: dts: socfpga: arria10: Move to use generic handoff dtsi Move to use generic handoff dtsi (socfpga_arria10-handoff.dtsi) and include the specify generated _handoff.h header file from qts-filter-a10.sh script. Signed-off-by: Ley Foon Tan --- arch/arm/dts/socfpga_arria10-handoff.dtsi | 290 ++++++++++++++++++ .../dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi | 3 +- .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi | 329 --------------------- 3 files changed, 292 insertions(+), 330 deletions(-) create mode 100644 arch/arm/dts/socfpga_arria10-handoff.dtsi delete mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi (limited to 'arch') diff --git a/arch/arm/dts/socfpga_arria10-handoff.dtsi b/arch/arm/dts/socfpga_arria10-handoff.dtsi new file mode 100644 index 0000000000..c08371625e --- /dev/null +++ b/arch/arm/dts/socfpga_arria10-handoff.dtsi @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 + +/ { + clocks { + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = ; + clock-output-names = "altera_arria10_hps_eosc1-clk"; + u-boot,dm-pre-reloc; + }; + + altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = ; + clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk"; + u-boot,dm-pre-reloc; + }; + + /* Clock source: altera_arria10_hps_f2h_free */ + altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = ; + clock-output-names = "altera_arria10_hps_f2h_free-clk"; + u-boot,dm-pre-reloc; + }; + }; + + clkmgr@0xffd04000 { + compatible = "altr,socfpga-a10-clk-init"; + reg = <0xffd04000 0x00000200>; + reg-names = "soc_clock_manager_OCP_SLV"; + u-boot,dm-pre-reloc; + + mainpll { + vco0-psrc = ; + vco1-denom = ; + vco1-numer = ; + mpuclk-cnt = ; + mpuclk-src = ; + nocclk-cnt = ; + nocclk-src = ; + cntr2clk-cnt = ; + cntr3clk-cnt = ; + cntr4clk-cnt = ; + cntr5clk-cnt = ; + cntr6clk-cnt = ; + cntr7clk-cnt = ; + cntr7clk-src = ; + cntr8clk-cnt = ; + cntr9clk-cnt = ; + cntr9clk-src = ; + cntr15clk-cnt = ; + nocdiv-l4mainclk = ; + nocdiv-l4mpclk = ; + nocdiv-l4spclk = ; + nocdiv-csatclk = ; + nocdiv-cstraceclk = ; + nocdiv-cspdbgclk = ; + u-boot,dm-pre-reloc; + }; + + perpll { + vco0-psrc = ; + vco1-denom = ; + vco1-numer = ; + cntr2clk-cnt = ; + cntr2clk-src = ; + cntr3clk-cnt = ; + cntr3clk-src = ; + cntr4clk-cnt = ; + cntr4clk-src = ; + cntr5clk-cnt = ; + cntr5clk-src = ; + cntr6clk-cnt = ; + cntr6clk-src = ; + cntr7clk-cnt = ; + cntr8clk-cnt = ; + cntr8clk-src = ; + cntr9clk-cnt = ; + emacctl-emac0sel = ; + emacctl-emac1sel = ; + emacctl-emac2sel = ; + gpiodiv-gpiodbclk = ; + u-boot,dm-pre-reloc; + }; + + alteragrp { + nocclk = ; + mpuclk = ; + u-boot,dm-pre-reloc; + }; + }; + + i_io48_pin_mux: pinmux@0xffd07000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "pinctrl-single"; + reg = <0xffd07000 0x00000800>; + reg-names = "soc_3v_io48_pin_mux_OCP_SLV"; + u-boot,dm-pre-reloc; + + shared { + reg = <0xffd07000 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + pinctrl-single,pins = + <0x00000000 PINMUX_SHARED_IO_Q1_1_SEL>, + <0x00000004 PINMUX_SHARED_IO_Q1_2_SEL>, + <0x00000008 PINMUX_SHARED_IO_Q1_3_SEL>, + <0x0000000c PINMUX_SHARED_IO_Q1_4_SEL>, + <0x00000010 PINMUX_SHARED_IO_Q1_5_SEL>, + <0x00000014 PINMUX_SHARED_IO_Q1_6_SEL>, + <0x00000018 PINMUX_SHARED_IO_Q1_7_SEL>, + <0x0000001c PINMUX_SHARED_IO_Q1_8_SEL>, + <0x00000020 PINMUX_SHARED_IO_Q1_9_SEL>, + <0x00000024 PINMUX_SHARED_IO_Q1_10_SEL>, + <0x00000028 PINMUX_SHARED_IO_Q1_11_SEL>, + <0x0000002c PINMUX_SHARED_IO_Q1_12_SEL>, + <0x00000030 PINMUX_SHARED_IO_Q2_1_SEL>, + <0x00000034 PINMUX_SHARED_IO_Q2_2_SEL>, + <0x00000038 PINMUX_SHARED_IO_Q2_3_SEL>, + <0x0000003c PINMUX_SHARED_IO_Q2_4_SEL>, + <0x00000040 PINMUX_SHARED_IO_Q2_5_SEL>, + <0x00000044 PINMUX_SHARED_IO_Q2_6_SEL>, + <0x00000048 PINMUX_SHARED_IO_Q2_7_SEL>, + <0x0000004c PINMUX_SHARED_IO_Q2_8_SEL>, + <0x00000050 PINMUX_SHARED_IO_Q2_9_SEL>, + <0x00000054 PINMUX_SHARED_IO_Q2_10_SEL>, + <0x00000058 PINMUX_SHARED_IO_Q2_11_SEL>, + <0x0000005c PINMUX_SHARED_IO_Q2_12_SEL>, + <0x00000060 PINMUX_SHARED_IO_Q3_1_SEL>, + <0x00000064 PINMUX_SHARED_IO_Q3_2_SEL>, + <0x00000068 PINMUX_SHARED_IO_Q3_3_SEL>, + <0x0000006c PINMUX_SHARED_IO_Q3_4_SEL>, + <0x00000070 PINMUX_SHARED_IO_Q3_5_SEL>, + <0x00000074 PINMUX_SHARED_IO_Q3_6_SEL>, + <0x00000078 PINMUX_SHARED_IO_Q3_7_SEL>, + <0x0000007c PINMUX_SHARED_IO_Q3_8_SEL>, + <0x00000080 PINMUX_SHARED_IO_Q3_9_SEL>, + <0x00000084 PINMUX_SHARED_IO_Q3_10_SEL>, + <0x00000088 PINMUX_SHARED_IO_Q3_11_SEL>, + <0x0000008c PINMUX_SHARED_IO_Q3_12_SEL>, + <0x00000090 PINMUX_SHARED_IO_Q4_1_SEL>, + <0x00000094 PINMUX_SHARED_IO_Q4_2_SEL>, + <0x00000098 PINMUX_SHARED_IO_Q4_3_SEL>, + <0x0000009c PINMUX_SHARED_IO_Q4_4_SEL>, + <0x000000a0 PINMUX_SHARED_IO_Q4_5_SEL>, + <0x000000a4 PINMUX_SHARED_IO_Q4_6_SEL>, + <0x000000a8 PINMUX_SHARED_IO_Q4_7_SEL>, + <0x000000ac PINMUX_SHARED_IO_Q4_8_SEL>, + <0x000000b0 PINMUX_SHARED_IO_Q4_9_SEL>, + <0x000000b4 PINMUX_SHARED_IO_Q4_10_SEL>, + <0x000000b8 PINMUX_SHARED_IO_Q4_11_SEL>, + <0x000000bc PINMUX_SHARED_IO_Q4_12_SEL>; + u-boot,dm-pre-reloc; + }; + + dedicated { + reg = <0xffd07200 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + pinctrl-single,pins = + <0x0000000c PINMUX_DEDICATED_IO_4_SEL>, + <0x00000010 PINMUX_DEDICATED_IO_5_SEL>, + <0x00000014 PINMUX_DEDICATED_IO_6_SEL>, + <0x00000018 PINMUX_DEDICATED_IO_7_SEL>, + <0x0000001c PINMUX_DEDICATED_IO_8_SEL>, + <0x00000020 PINMUX_DEDICATED_IO_9_SEL>, + <0x00000024 PINMUX_DEDICATED_IO_10_SEL>, + <0x00000028 PINMUX_DEDICATED_IO_11_SEL>, + <0x0000002c PINMUX_DEDICATED_IO_12_SEL>, + <0x00000030 PINMUX_DEDICATED_IO_13_SEL>, + <0x00000034 PINMUX_DEDICATED_IO_14_SEL>, + <0x00000038 PINMUX_DEDICATED_IO_15_SEL>, + <0x0000003c PINMUX_DEDICATED_IO_16_SEL>, + <0x00000040 PINMUX_DEDICATED_IO_17_SEL>; + u-boot,dm-pre-reloc; + }; + + dedicated_cfg { + reg = <0xffd07200 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x003f3f3f>; + pinctrl-single,pins = + <0x00000100 CONFIG_IO_BANK_VSEL>, + <0x00000104 CONFIG_IO_MACRO (CONFIG_IO_1)>, + <0x00000108 CONFIG_IO_MACRO (CONFIG_IO_2)>, + <0x0000010c CONFIG_IO_MACRO (CONFIG_IO_3)>, + <0x00000110 CONFIG_IO_MACRO (CONFIG_IO_4)>, + <0x00000114 CONFIG_IO_MACRO (CONFIG_IO_5)>, + <0x00000118 CONFIG_IO_MACRO (CONFIG_IO_6)>, + <0x0000011c CONFIG_IO_MACRO (CONFIG_IO_7)>, + <0x00000120 CONFIG_IO_MACRO (CONFIG_IO_8)>, + <0x00000124 CONFIG_IO_MACRO (CONFIG_IO_9)>, + <0x00000128 CONFIG_IO_MACRO (CONFIG_IO_10)>, + <0x0000012c CONFIG_IO_MACRO (CONFIG_IO_11)>, + <0x00000130 CONFIG_IO_MACRO (CONFIG_IO_12)>, + <0x00000134 CONFIG_IO_MACRO (CONFIG_IO_13)>, + <0x00000138 CONFIG_IO_MACRO (CONFIG_IO_14)>, + <0x0000013c CONFIG_IO_MACRO (CONFIG_IO_15)>, + <0x00000140 CONFIG_IO_MACRO (CONFIG_IO_16)>, + <0x00000144 CONFIG_IO_MACRO (CONFIG_IO_17)>; + u-boot,dm-pre-reloc; + }; + + fpga { + reg = <0xffd07400 0x00000100>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000001>; + pinctrl-single,pins = + <0x00000000 PINMUX_RGMII0_USEFPGA_SEL>, + <0x00000004 PINMUX_RGMII1_USEFPGA_SEL>, + <0x00000008 PINMUX_RGMII2_USEFPGA_SEL>, + <0x0000000c PINMUX_I2C0_USEFPGA_SEL>, + <0x00000010 PINMUX_I2C1_USEFPGA_SEL>, + <0x00000014 PINMUX_I2CEMAC0_USEFPGA_SEL>, + <0x00000018 PINMUX_I2CEMAC1_USEFPGA_SEL>, + <0x0000001c PINMUX_I2CEMAC2_USEFPGA_SEL>, + <0x00000020 PINMUX_NAND_USEFPGA_SEL>, + <0x00000024 PINMUX_QSPI_USEFPGA_SEL>, + <0x00000028 PINMUX_SDMMC_USEFPGA_SEL>, + <0x0000002c PINMUX_SPIM0_USEFPGA_SEL>, + <0x00000030 PINMUX_SPIM1_USEFPGA_SEL>, + <0x00000034 PINMUX_SPIS0_USEFPGA_SEL>, + <0x00000038 PINMUX_SPIS1_USEFPGA_SEL>, + <0x0000003c PINMUX_UART0_USEFPGA_SEL>, + <0x00000040 PINMUX_UART1_USEFPGA_SEL>; + u-boot,dm-pre-reloc; + }; + }; + + i_noc: noc@0xffd10000 { + compatible = "altr,socfpga-a10-noc"; + reg = <0xffd10000 0x00008000>; + reg-names = "mpu_m0"; + u-boot,dm-pre-reloc; + + firewall { + mpu0 = <0x00000000 0x0000ffff>; + l3-0 = <0x00000000 0x0000ffff>; + fpga2sdram0-0 = <0x00000000 0x0000ffff>; + fpga2sdram1-0 = <0x00000000 0x0000ffff>; + fpga2sdram2-0 = <0x00000000 0x0000ffff>; + u-boot,dm-pre-reloc; + }; + }; + + hps_fpgabridge0: fpgabridge@0 { + compatible = "altr,socfpga-hps2fpga-bridge"; + init-val = ; + u-boot,dm-pre-reloc; + }; + + hps_fpgabridge1: fpgabridge@1 { + compatible = "altr,socfpga-lwhps2fpga-bridge"; + init-val = ; + u-boot,dm-pre-reloc; + }; + + hps_fpgabridge2: fpgabridge@2 { + compatible = "altr,socfpga-fpga2hps-bridge"; + init-val = ; + u-boot,dm-pre-reloc; + }; + + hps_fpgabridge3: fpgabridge@3 { + compatible = "altr,socfpga-fpga2sdram0-bridge"; + init-val = ; + u-boot,dm-pre-reloc; + }; + + hps_fpgabridge4: fpgabridge@4 { + compatible = "altr,socfpga-fpga2sdram1-bridge"; + init-val = ; + u-boot,dm-pre-reloc; + }; + + hps_fpgabridge5: fpgabridge@5 { + compatible = "altr,socfpga-fpga2sdram2-bridge"; + init-val = ; + u-boot,dm-pre-reloc; + }; +}; diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi index c229e82de9..298c337ed7 100644 --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi @@ -3,7 +3,8 @@ * Copyright (C) 2014-2015, 2020 Intel. All rights reserved. */ -#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi" +#include "socfpga_arria10_socdk_sdmmc_handoff.h" +#include "socfpga_arria10-handoff.dtsi" #include "socfpga_arria10_handoff_u-boot.dtsi" #include "socfpga_arria10_socdk-u-boot.dtsi" diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi deleted file mode 100644 index 60c419251b..0000000000 --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi +++ /dev/null @@ -1,329 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright (C) 2016-2017 Intel Corporation - * - * - * This code was generated by a tool based on - * handoffs from both Qsys and Quartus. - * - * Changes to this file may be lost if - * the code is regenerated. - * - */ - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */ - - /* Clock sources */ - clocks { - #address-cells = <1>; - #size-cells = <1>; - - /* Clock source: altera_arria10_hps_eosc1 */ - altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "altera_arria10_hps_eosc1-clk"; - }; - - /* Clock source: altera_arria10_hps_cb_intosc_ls */ - altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <60000000>; - clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk"; - }; - - /* Clock source: altera_arria10_hps_f2h_free */ - altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - clock-output-names = "altera_arria10_hps_f2h_free-clk"; - }; - }; - - /* - * Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver - * Version: 1.0 - * Binding: device - */ - i_clk_mgr: clock_manager@0xffd04000 { - compatible = "altr,socfpga-a10-clk-init"; - reg = <0xffd04000 0x00000200>; - reg-names = "soc_clock_manager_OCP_SLV"; - - /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */ - mainpll { - vco0-psrc = <0>; /* Field: vco0.psrc */ - vco1-denom = <1>; /* Field: vco1.denom */ - vco1-numer = <191>; /* Field: vco1.numer */ - mpuclk-cnt = <0>; /* Field: mpuclk.cnt */ - mpuclk-src = <0>; /* Field: mpuclk.src */ - nocclk-cnt = <0>; /* Field: nocclk.cnt */ - nocclk-src = <0>; /* Field: nocclk.src */ - cntr2clk-cnt = <900>; /* Field: cntr2clk.cnt */ - cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */ - cntr4clk-cnt = <900>; /* Field: cntr4clk.cnt */ - cntr5clk-cnt = <900>; /* Field: cntr5clk.cnt */ - cntr6clk-cnt = <900>; /* Field: cntr6clk.cnt */ - cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */ - cntr7clk-src = <0>; /* Field: cntr7clk.src */ - cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */ - cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */ - cntr9clk-src = <0>; /* Field: cntr9clk.src */ - cntr15clk-cnt = <900>; /* Field: cntr15clk.cnt */ - nocdiv-l4mainclk = <0>; /* Field: nocdiv.l4mainclk */ - nocdiv-l4mpclk = <0>; /* Field: nocdiv.l4mpclk */ - nocdiv-l4spclk = <2>; /* Field: nocdiv.l4spclk */ - nocdiv-csatclk = <0>; /* Field: nocdiv.csatclk */ - nocdiv-cstraceclk = <1>; /* Field: nocdiv.cstraceclk */ - nocdiv-cspdbgclk = <1>; /* Field: nocdiv.cspdbgclk */ - }; - - /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */ - perpll { - vco0-psrc = <0>; /* Field: vco0.psrc */ - vco1-denom = <1>; /* Field: vco1.denom */ - vco1-numer = <159>; /* Field: vco1.numer */ - cntr2clk-cnt = <7>; /* Field: cntr2clk.cnt */ - cntr2clk-src = <1>; /* Field: cntr2clk.src */ - cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */ - cntr3clk-src = <1>; /* Field: cntr3clk.src */ - cntr4clk-cnt = <19>; /* Field: cntr4clk.cnt */ - cntr4clk-src = <1>; /* Field: cntr4clk.src */ - cntr5clk-cnt = <499>; /* Field: cntr5clk.cnt */ - cntr5clk-src = <1>; /* Field: cntr5clk.src */ - cntr6clk-cnt = <9>; /* Field: cntr6clk.cnt */ - cntr6clk-src = <1>; /* Field: cntr6clk.src */ - cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */ - cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */ - cntr8clk-src = <0>; /* Field: cntr8clk.src */ - cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */ - emacctl-emac0sel = <0>; /* Field: emacctl.emac0sel */ - emacctl-emac1sel = <0>; /* Field: emacctl.emac1sel */ - emacctl-emac2sel = <0>; /* Field: emacctl.emac2sel */ - gpiodiv-gpiodbclk = <32000>; /* Field: gpiodiv.gpiodbclk */ - }; - - /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */ - alteragrp { - nocclk = <0x0384000b>; /* Register: nocclk */ - mpuclk = <0x03840001>; /* Register: mpuclk */ - }; - }; - - /* - * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver - * Version: 1.0 - * Binding: pinmux - */ - i_io48_pin_mux: pinmux@0xffd07000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "pinctrl-single"; - reg = <0xffd07000 0x00000800>; - reg-names = "soc_3v_io48_pin_mux_OCP_SLV"; - - /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */ - shared { - reg = <0xffd07000 0x00000200>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000f>; - pinctrl-single,pins = - <0x00000000 0x00000008>, /* Register: pinmux_shared_io_q1_1 */ - <0x00000004 0x00000008>, /* Register: pinmux_shared_io_q1_2 */ - <0x00000008 0x00000008>, /* Register: pinmux_shared_io_q1_3 */ - <0x0000000c 0x00000008>, /* Register: pinmux_shared_io_q1_4 */ - <0x00000010 0x00000008>, /* Register: pinmux_shared_io_q1_5 */ - <0x00000014 0x00000008>, /* Register: pinmux_shared_io_q1_6 */ - <0x00000018 0x00000008>, /* Register: pinmux_shared_io_q1_7 */ - <0x0000001c 0x00000008>, /* Register: pinmux_shared_io_q1_8 */ - <0x00000020 0x00000008>, /* Register: pinmux_shared_io_q1_9 */ - <0x00000024 0x00000008>, /* Register: pinmux_shared_io_q1_10 */ - <0x00000028 0x00000008>, /* Register: pinmux_shared_io_q1_11 */ - <0x0000002c 0x00000008>, /* Register: pinmux_shared_io_q1_12 */ - <0x00000030 0x00000004>, /* Register: pinmux_shared_io_q2_1 */ - <0x00000034 0x00000004>, /* Register: pinmux_shared_io_q2_2 */ - <0x00000038 0x00000004>, /* Register: pinmux_shared_io_q2_3 */ - <0x0000003c 0x00000004>, /* Register: pinmux_shared_io_q2_4 */ - <0x00000040 0x00000004>, /* Register: pinmux_shared_io_q2_5 */ - <0x00000044 0x00000004>, /* Register: pinmux_shared_io_q2_6 */ - <0x00000048 0x00000004>, /* Register: pinmux_shared_io_q2_7 */ - <0x0000004c 0x00000004>, /* Register: pinmux_shared_io_q2_8 */ - <0x00000050 0x00000004>, /* Register: pinmux_shared_io_q2_9 */ - <0x00000054 0x00000004>, /* Register: pinmux_shared_io_q2_10 */ - <0x00000058 0x00000004>, /* Register: pinmux_shared_io_q2_11 */ - <0x0000005c 0x00000004>, /* Register: pinmux_shared_io_q2_12 */ - <0x00000060 0x00000003>, /* Register: pinmux_shared_io_q3_1 */ - <0x00000064 0x00000003>, /* Register: pinmux_shared_io_q3_2 */ - <0x00000068 0x00000003>, /* Register: pinmux_shared_io_q3_3 */ - <0x0000006c 0x00000003>, /* Register: pinmux_shared_io_q3_4 */ - <0x00000070 0x00000003>, /* Register: pinmux_shared_io_q3_5 */ - <0x00000074 0x0000000f>, /* Register: pinmux_shared_io_q3_6 */ - <0x00000078 0x0000000a>, /* Register: pinmux_shared_io_q3_7 */ - <0x0000007c 0x0000000a>, /* Register: pinmux_shared_io_q3_8 */ - <0x00000080 0x0000000a>, /* Register: pinmux_shared_io_q3_9 */ - <0x00000084 0x0000000a>, /* Register: pinmux_shared_io_q3_10 */ - <0x00000088 0x00000001>, /* Register: pinmux_shared_io_q3_11 */ - <0x0000008c 0x00000001>, /* Register: pinmux_shared_io_q3_12 */ - <0x00000090 0x00000000>, /* Register: pinmux_shared_io_q4_1 */ - <0x00000094 0x00000000>, /* Register: pinmux_shared_io_q4_2 */ - <0x00000098 0x0000000f>, /* Register: pinmux_shared_io_q4_3 */ - <0x0000009c 0x0000000c>, /* Register: pinmux_shared_io_q4_4 */ - <0x000000a0 0x0000000f>, /* Register: pinmux_shared_io_q4_5 */ - <0x000000a4 0x0000000f>, /* Register: pinmux_shared_io_q4_6 */ - <0x000000a8 0x0000000a>, /* Register: pinmux_shared_io_q4_7 */ - <0x000000ac 0x0000000a>, /* Register: pinmux_shared_io_q4_8 */ - <0x000000b0 0x0000000c>, /* Register: pinmux_shared_io_q4_9 */ - <0x000000b4 0x0000000c>, /* Register: pinmux_shared_io_q4_10 */ - <0x000000b8 0x0000000c>, /* Register: pinmux_shared_io_q4_11 */ - <0x000000bc 0x0000000c>; /* Register: pinmux_shared_io_q4_12 */ - }; - - /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */ - dedicated { - reg = <0xffd07200 0x00000200>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000f>; - pinctrl-single,pins = - <0x0000000c 0x00000008>, /* Register: pinmux_dedicated_io_4 */ - <0x00000010 0x00000008>, /* Register: pinmux_dedicated_io_5 */ - <0x00000014 0x00000008>, /* Register: pinmux_dedicated_io_6 */ - <0x00000018 0x00000008>, /* Register: pinmux_dedicated_io_7 */ - <0x0000001c 0x00000008>, /* Register: pinmux_dedicated_io_8 */ - <0x00000020 0x00000008>, /* Register: pinmux_dedicated_io_9 */ - <0x00000024 0x0000000a>, /* Register: pinmux_dedicated_io_10 */ - <0x00000028 0x0000000a>, /* Register: pinmux_dedicated_io_11 */ - <0x0000002c 0x00000008>, /* Register: pinmux_dedicated_io_12 */ - <0x00000030 0x00000008>, /* Register: pinmux_dedicated_io_13 */ - <0x00000034 0x00000008>, /* Register: pinmux_dedicated_io_14 */ - <0x00000038 0x00000008>, /* Register: pinmux_dedicated_io_15 */ - <0x0000003c 0x0000000d>, /* Register: pinmux_dedicated_io_16 */ - <0x00000040 0x0000000d>; /* Register: pinmux_dedicated_io_17 */ - }; - - /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */ - dedicated_cfg { - reg = <0xffd07200 0x00000200>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x003f3f3f>; - pinctrl-single,pins = - <0x00000100 0x00000101>, /* Register: configuration_dedicated_io_bank */ - <0x00000104 0x000b080a>, /* Register: configuration_dedicated_io_1 */ - <0x00000108 0x000b080a>, /* Register: configuration_dedicated_io_2 */ - <0x0000010c 0x000b080a>, /* Register: configuration_dedicated_io_3 */ - <0x00000110 0x000a282a>, /* Register: configuration_dedicated_io_4 */ - <0x00000114 0x000a282a>, /* Register: configuration_dedicated_io_5 */ - <0x00000118 0x0008282a>, /* Register: configuration_dedicated_io_6 */ - <0x0000011c 0x000a282a>, /* Register: configuration_dedicated_io_7 */ - <0x00000120 0x000a282a>, /* Register: configuration_dedicated_io_8 */ - <0x00000124 0x000a282a>, /* Register: configuration_dedicated_io_9 */ - <0x00000128 0x00090000>, /* Register: configuration_dedicated_io_10 */ - <0x0000012c 0x00090000>, /* Register: configuration_dedicated_io_11 */ - <0x00000130 0x000b282a>, /* Register: configuration_dedicated_io_12 */ - <0x00000134 0x000b282a>, /* Register: configuration_dedicated_io_13 */ - <0x00000138 0x000b282a>, /* Register: configuration_dedicated_io_14 */ - <0x0000013c 0x000b282a>, /* Register: configuration_dedicated_io_15 */ - <0x00000140 0x0008282a>, /* Register: configuration_dedicated_io_16 */ - <0x00000144 0x000a282a>; /* Register: configuration_dedicated_io_17 */ - }; - - /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */ - fpga { - reg = <0xffd07400 0x00000100>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x00000001>; - pinctrl-single,pins = - <0x00000000 0x00000000>, /* Register: pinmux_emac0_usefpga */ - <0x00000004 0x00000000>, /* Register: pinmux_emac1_usefpga */ - <0x00000008 0x00000000>, /* Register: pinmux_emac2_usefpga */ - <0x0000000c 0x00000000>, /* Register: pinmux_i2c0_usefpga */ - <0x00000010 0x00000000>, /* Register: pinmux_i2c1_usefpga */ - <0x00000014 0x00000000>, /* Register: pinmux_i2c_emac0_usefpga */ - <0x00000018 0x00000000>, /* Register: pinmux_i2c_emac1_usefpga */ - <0x0000001c 0x00000000>, /* Register: pinmux_i2c_emac2_usefpga */ - <0x00000020 0x00000000>, /* Register: pinmux_nand_usefpga */ - <0x00000024 0x00000000>, /* Register: pinmux_qspi_usefpga */ - <0x00000028 0x00000000>, /* Register: pinmux_sdmmc_usefpga */ - <0x0000002c 0x00000000>, /* Register: pinmux_spim0_usefpga */ - <0x00000030 0x00000000>, /* Register: pinmux_spim1_usefpga */ - <0x00000034 0x00000000>, /* Register: pinmux_spis0_usefpga */ - <0x00000038 0x00000000>, /* Register: pinmux_spis1_usefpga */ - <0x0000003c 0x00000000>, /* Register: pinmux_uart0_usefpga */ - <0x00000040 0x00000000>; /* Register: pinmux_uart1_usefpga */ - }; - }; - - /* - * Driver: altera_arria10_soc_noc_arria10_uboot_driver - * Version: 1.0 - * Binding: device - */ - i_noc: noc@0xffd10000 { - compatible = "altr,socfpga-a10-noc"; - reg = <0xffd10000 0x00008000>; - reg-names = "mpu_m0"; - - firewall { - /* - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit - */ - mpu0 = <0x00000000 0x0000ffff>; - /* - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit - */ - l3-0 = <0x00000000 0x0000ffff>; - /* - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.base - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.limit - */ - fpga2sdram0-0 = <0x00000000 0x0000ffff>; - /* - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.base - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.limit - */ - fpga2sdram1-0 = <0x00000000 0x0000ffff>; - /* - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.base - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.limit - */ - fpga2sdram2-0 = <0x00000000 0x0000ffff>; - }; - }; - - hps_fpgabridge0: fpgabridge@0 { - compatible = "altr,socfpga-hps2fpga-bridge"; - init-val = <1>; - }; - - hps_fpgabridge1: fpgabridge@1 { - compatible = "altr,socfpga-lwhps2fpga-bridge"; - init-val = <1>; - }; - - hps_fpgabridge2: fpgabridge@2 { - compatible = "altr,socfpga-fpga2hps-bridge"; - init-val = <1>; - }; - - hps_fpgabridge3: fpgabridge@3 { - compatible = "altr,socfpga-fpga2sdram0-bridge"; - init-val = <1>; - }; - - hps_fpgabridge4: fpgabridge@4 { - compatible = "altr,socfpga-fpga2sdram1-bridge"; - init-val = <0>; - }; - - hps_fpgabridge5: fpgabridge@5 { - compatible = "altr,socfpga-fpga2sdram2-bridge"; - init-val = <1>; - }; -}; -- cgit v1.2.3