From 67f9f11f197ff39e4e85e56bca84206ef18ab296 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 4 Sep 2020 12:55:19 +0200 Subject: stm32mp: limit size of cacheable DDR in pre-reloc stage In pre-reloc stage, U-Boot marks cacheable the DDR limited by the new config CONFIG_DDR_CACHEABLE_SIZE. This patch allows to avoid any speculative access to DDR protected by firewall and used by OP-TEE; the "no-map" reserved memory node in DT are assumed after this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. Without security, in basic boot, the value is equal to STM32_DDR_SIZE. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/Kconfig | 13 +++++++++++++ arch/arm/mach-stm32mp/cpu.c | 3 ++- arch/arm/mach-stm32mp/spl.c | 3 ++- 3 files changed, 17 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 478fd2f17d..f538d7cb83 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -93,6 +93,19 @@ config SYS_TEXT_BASE config NR_DRAM_BANKS default 1 +config DDR_CACHEABLE_SIZE + hex "Size of the DDR marked cacheable in pre-reloc stage" + default 0x10000000 if TFABOOT + default 0x40000000 + help + Define the size of the DDR marked as cacheable in U-Boot + pre-reloc stage. + This option can be useful to avoid speculatif access + to secured area of DDR used by TF-A or OP-TEE before U-Boot + initialization. + The areas marked "no-map" in device tree should be located + before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. + config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 hex "Partition on MMC2 to use to load U-Boot from" depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index f19e5c3f33..6785ab6b58 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -230,7 +230,8 @@ static void early_enable_caches(void) round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE), DCACHE_DEFAULT_OPTION); else - mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE, + mmu_set_region_dcache_behaviour(STM32_DDR_BASE, + CONFIG_DDR_CACHEABLE_SIZE, DCACHE_DEFAULT_OPTION); } diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c index e84bdad7bf..b679b0a645 100644 --- a/arch/arm/mach-stm32mp/spl.c +++ b/arch/arm/mach-stm32mp/spl.c @@ -138,7 +138,8 @@ void board_init_f(ulong dummy) * to avoid speculative access and issue in get_ram_size() */ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) - mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE, + mmu_set_region_dcache_behaviour(STM32_DDR_BASE, + CONFIG_DDR_CACHEABLE_SIZE, DCACHE_DEFAULT_OPTION); } -- cgit v1.2.3 From 6af78d03d394cb0b28716aaaf684ab99bdeb758d Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 2 Oct 2020 14:08:54 +0200 Subject: arm: stm32: cleanup arch gpio.h Cosmetic update of gpio.h: - remove enumerate: stm32_gpio_port, stm32_gpio_pin because STM32_GPIO_XXX values are unused - move STM32_GPIOS_PER_BANK in stm32_gpio.c as its value is IP dependent and not arch dependent No functional change as number of banks and number of gpio by banks is managed by device tree since since DM migration and commit 8f651ca60ba1 ("pinctrl: stm32: Add get_pins_count() ops"). Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/include/asm/arch-stm32/gpio.h | 37 ++----------------------------- arch/arm/mach-stm32mp/include/mach/gpio.h | 37 ++----------------------------- drivers/gpio/stm32_gpio.c | 2 ++ 3 files changed, 6 insertions(+), 70 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-stm32/gpio.h b/arch/arm/include/asm/arch-stm32/gpio.h index 570e80a6ba..233ce278a7 100644 --- a/arch/arm/include/asm/arch-stm32/gpio.h +++ b/arch/arm/include/asm/arch-stm32/gpio.h @@ -7,39 +7,6 @@ #ifndef _GPIO_H_ #define _GPIO_H_ -#define STM32_GPIOS_PER_BANK 16 - -enum stm32_gpio_port { - STM32_GPIO_PORT_A = 0, - STM32_GPIO_PORT_B, - STM32_GPIO_PORT_C, - STM32_GPIO_PORT_D, - STM32_GPIO_PORT_E, - STM32_GPIO_PORT_F, - STM32_GPIO_PORT_G, - STM32_GPIO_PORT_H, - STM32_GPIO_PORT_I -}; - -enum stm32_gpio_pin { - STM32_GPIO_PIN_0 = 0, - STM32_GPIO_PIN_1, - STM32_GPIO_PIN_2, - STM32_GPIO_PIN_3, - STM32_GPIO_PIN_4, - STM32_GPIO_PIN_5, - STM32_GPIO_PIN_6, - STM32_GPIO_PIN_7, - STM32_GPIO_PIN_8, - STM32_GPIO_PIN_9, - STM32_GPIO_PIN_10, - STM32_GPIO_PIN_11, - STM32_GPIO_PIN_12, - STM32_GPIO_PIN_13, - STM32_GPIO_PIN_14, - STM32_GPIO_PIN_15 -}; - enum stm32_gpio_mode { STM32_GPIO_MODE_IN = 0, STM32_GPIO_MODE_OUT, @@ -85,8 +52,8 @@ enum stm32_gpio_af { }; struct stm32_gpio_dsc { - enum stm32_gpio_port port; - enum stm32_gpio_pin pin; + u8 port; + u8 pin; }; struct stm32_gpio_ctl { diff --git a/arch/arm/mach-stm32mp/include/mach/gpio.h b/arch/arm/mach-stm32mp/include/mach/gpio.h index 5ca76d21ff..7a0f293519 100644 --- a/arch/arm/mach-stm32mp/include/mach/gpio.h +++ b/arch/arm/mach-stm32mp/include/mach/gpio.h @@ -8,39 +8,6 @@ #define _STM32_GPIO_H_ #include -#define STM32_GPIOS_PER_BANK 16 - -enum stm32_gpio_port { - STM32_GPIO_PORT_A = 0, - STM32_GPIO_PORT_B, - STM32_GPIO_PORT_C, - STM32_GPIO_PORT_D, - STM32_GPIO_PORT_E, - STM32_GPIO_PORT_F, - STM32_GPIO_PORT_G, - STM32_GPIO_PORT_H, - STM32_GPIO_PORT_I -}; - -enum stm32_gpio_pin { - STM32_GPIO_PIN_0 = 0, - STM32_GPIO_PIN_1, - STM32_GPIO_PIN_2, - STM32_GPIO_PIN_3, - STM32_GPIO_PIN_4, - STM32_GPIO_PIN_5, - STM32_GPIO_PIN_6, - STM32_GPIO_PIN_7, - STM32_GPIO_PIN_8, - STM32_GPIO_PIN_9, - STM32_GPIO_PIN_10, - STM32_GPIO_PIN_11, - STM32_GPIO_PIN_12, - STM32_GPIO_PIN_13, - STM32_GPIO_PIN_14, - STM32_GPIO_PIN_15 -}; - enum stm32_gpio_mode { STM32_GPIO_MODE_IN = 0, STM32_GPIO_MODE_OUT, @@ -86,8 +53,8 @@ enum stm32_gpio_af { }; struct stm32_gpio_dsc { - enum stm32_gpio_port port; - enum stm32_gpio_pin pin; + u8 port; + u8 pin; }; struct stm32_gpio_ctl { diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c index 473e364796..b885cfb57e 100644 --- a/drivers/gpio/stm32_gpio.c +++ b/drivers/gpio/stm32_gpio.c @@ -18,6 +18,8 @@ #include #include +#define STM32_GPIOS_PER_BANK 16 + #define MODE_BITS(gpio_pin) ((gpio_pin) * 2) #define MODE_BITS_MASK 3 #define BSRR_BIT(gpio_pin, value) BIT((gpio_pin) + (value ? 0 : 16)) -- cgit v1.2.3 From 53de79fecc53338b544b4d2c2d88daba9d82b007 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 15 Oct 2020 14:28:17 +0200 Subject: stm32mp: stm32prog: accept device without partition When partitions are not available on a device the command stm32prog raises an error but a device can have no partition to check in init_device() and the command need to continue to the next part_id. This patch correct an issue for ram0 target, when block_dev and mtd are NULL. For example with the simple flashlayout file: Opt Part Name Type Device Offset Binary - 0x01 fsbl Binary none 0x0 tf-a-serialboot.stm32 - 0x03 ssbl Binary none 0x0 u-boot.stm32 P 0x10 kernel System ram0 0xC2000000 uImage.bin P 0x11 dtb FileSytem ram0 0xC4000000 stm32mp157f-ev1.dtb Fixes: ffc405e63b94 ("stm32mp: stm32prog: add upport of partial update") Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index ec3355d816..a777827c55 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -768,9 +768,8 @@ static int init_device(struct stm32prog_data *data, part_found = true; } + /* no partition for this device */ if (!part_found) { - stm32prog_err("%s (0x%x): Invalid partition", - part->name, part->id); pr_debug("\n"); continue; } -- cgit v1.2.3