From bdba67ba87787d2d6b1d5208cb8dbe22428a87c9 Mon Sep 17 00:00:00 2001 From: Siew Chin Lim Date: Tue, 10 Aug 2021 11:26:27 +0800 Subject: arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h Rename to common file name to used by all SOC64 devices and change "_S10_" to "_SOC64_" in base_addr_soc64.h. Signed-off-by: Siew Chin Lim --- arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 47 ---------------------- .../mach-socfpga/include/mach/base_addr_soc64.h | 47 ++++++++++++++++++++++ 2 files changed, 47 insertions(+), 47 deletions(-) delete mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_soc64.h (limited to 'arch') diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h deleted file mode 100644 index d3eca65e97..0000000000 --- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016-2017 Intel Corporation - */ - -#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_ -#define _SOCFPGA_S10_BASE_HARDWARE_H_ - -#define SOCFPGA_CCU_ADDRESS 0xf7000000 -#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 -#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 -#define SOCFPGA_SDR_ADDRESS 0xf8011000 -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX -#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 -#else -#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 -#endif -#define SOCFPGA_SMMU_ADDRESS 0xfa000000 -#define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 -#define SOCFPGA_UART0_ADDRESS 0xffc02000 -#define SOCFPGA_UART1_ADDRESS 0xffc02100 -#define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000 -#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100 -#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00000 -#define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100 -#define SOCFPGA_L4WD0_ADDRESS 0xffd00200 -#define SOCFPGA_L4WD1_ADDRESS 0xffd00300 -#define SOCFPGA_L4WD2_ADDRESS 0xffd00400 -#define SOCFPGA_L4WD3_ADDRESS 0xffd00500 -#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000 -#define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000 -#define SOCFPGA_CLKMGR_ADDRESS 0xffd10000 -#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000 -#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000 -#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000 -#define SOCFPGA_FIREWALL_L4_PER 0xffd21000 -#define SOCFPGA_FIREWALL_L4_SYS 0xffd21100 -#define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200 -#define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300 -#define SOCFPGA_FIREWALL_TCU 0xffd21400 -#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 -#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 -#define SOCFPGA_OCRAM_ADDRESS 0xffe00000 -#define GICD_BASE 0xfffc1000 -#define GICC_BASE 0xfffc2000 - -#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h new file mode 100644 index 0000000000..f89066d771 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016-2021 Intel Corporation + */ + +#ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_ +#define _SOCFPGA_SOC64_BASE_HARDWARE_H_ + +#define SOCFPGA_CCU_ADDRESS 0xf7000000 +#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 +#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 +#define SOCFPGA_SDR_ADDRESS 0xf8011000 +#ifdef CONFIG_TARGET_SOCFPGA_AGILEX +#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 +#else +#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 +#endif +#define SOCFPGA_SMMU_ADDRESS 0xfa000000 +#define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc02100 +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000 +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100 +#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100 +#define SOCFPGA_L4WD0_ADDRESS 0xffd00200 +#define SOCFPGA_L4WD1_ADDRESS 0xffd00300 +#define SOCFPGA_L4WD2_ADDRESS 0xffd00400 +#define SOCFPGA_L4WD3_ADDRESS 0xffd00500 +#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000 +#define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd10000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000 +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000 +#define SOCFPGA_FIREWALL_L4_PER 0xffd21000 +#define SOCFPGA_FIREWALL_L4_SYS 0xffd21100 +#define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200 +#define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300 +#define SOCFPGA_FIREWALL_TCU 0xffd21400 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 +#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 +#define SOCFPGA_OCRAM_ADDRESS 0xffe00000 +#define GICD_BASE 0xfffc1000 +#define GICC_BASE 0xfffc2000 + +#endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */ -- cgit v1.2.3