From e81a6b4b7a58f56772b48db74ccadfc77a733fe1 Mon Sep 17 00:00:00 2001 From: "yanhong.wang" Date: Tue, 10 May 2022 09:14:37 +0800 Subject: board:starfive: add starfive evb board support Add board support for StarFive EVB. Signed-off-by: yanhong.wang --- arch/riscv/Kconfig | 4 ++ arch/riscv/dts/Makefile | 1 + arch/riscv/dts/jh7110-u-boot.dtsi | 6 ++ arch/riscv/dts/starfive_evb-u-boot.dtsi | 38 ++++++++++++ arch/riscv/dts/starfive_evb.dts | 104 ++++++++++++++++++++++++++++++++ 5 files changed, 153 insertions(+) create mode 100644 arch/riscv/dts/starfive_evb-u-boot.dtsi create mode 100644 arch/riscv/dts/starfive_evb.dts (limited to 'arch') diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 63b0c328bd..b0aa8d2ab9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -26,6 +26,9 @@ config TARGET_SIFIVE_UNMATCHED config TARGET_STARFIVE_VISIONFIVE bool "Support StarFive VisionFive Board" +config TARGET_STARFIVE_EVB + bool "Support StarFive Evb Board" + config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" @@ -69,6 +72,7 @@ source "board/sifive/unmatched/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" source "board/starfive/visionfive/Kconfig" +source "board/starfive/evb/Kconfig" # platform-specific options below source "arch/riscv/cpu/ax25/Kconfig" diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 264639ad26..d433afa6f4 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE) += starfive_visionfive.dtb +dtb-$(CONFIG_TARGET_STARFIVE_EVB) += starfive_evb.dtb targets += $(dtb-y) diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index 455da59622..e355f6a8af 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -68,11 +68,17 @@ }; &sdio0 { + clock-frequency = <4000000>; + max-frequency = <1000000>; + bus-width = <8>; status = "okay"; u-boot,dm-spl; }; &sdio1 { + clock-frequency = <4000000>; + max-frequency = <1000000>; + bus-width = <4>; status = "okay"; u-boot,dm-spl; }; diff --git a/arch/riscv/dts/starfive_evb-u-boot.dtsi b/arch/riscv/dts/starfive_evb-u-boot.dtsi new file mode 100644 index 0000000000..d283272f41 --- /dev/null +++ b/arch/riscv/dts/starfive_evb-u-boot.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#include "jh7110-u-boot.dtsi" +/ { + chosen { + stdout-path = "/soc/serial@10000000:115200"; + u-boot,dm-spl; + }; + + firmware { + spi0="/soc/qspi@11860000"; + u-boot,dm-spl; + }; + + config { + u-boot,dm-spl; + u-boot,spl-payload-offset = <0x100000>; /* loader2 @1044KB */ + }; + + memory@80000000 { + u-boot,dm-spl; + device_type = "memory"; + reg = <0x0 0x40000000 0x1 0x0>; + }; +}; + +&sdio0 { + clock-frequency = <4000000>; + max-frequency = <1000000>; +}; + +&sdio1 { + clock-frequency = <4000000>; + max-frequency = <1000000>; +}; diff --git a/arch/riscv/dts/starfive_evb.dts b/arch/riscv/dts/starfive_evb.dts new file mode 100644 index 0000000000..0a7c297fad --- /dev/null +++ b/arch/riscv/dts/starfive_evb.dts @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +/dts-v1/; + +#include "jh7110.dtsi" +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "StarFive EVB"; + compatible = "starfive,jh7110"; + + aliases { + spi0="/soc/spi@13010000"; + gpio0="/soc/gpio@13040000"; + ethernet0="/soc/ethernet@16030000"; + mmc0="/soc/sdio0@16010000"; + mmc1="/soc/sdio1@16020000"; + }; + + chosen { + stdout-path = "/soc/serial@10000000:115200"; + }; + + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x1 0x0>; + }; + + soc { + }; +}; + +&cpu0 { + status = "okay"; +}; + +&clkgen { + clocks = <&osc>, <&gmac1_rmii_refin>, + <&stg_apb>, <&gmac0_rmii_refin>; + clock-names = "osc", "gmac1_rmii_refin", + "stg_apb", "gmac0_rmii_refin"; +}; + +&sdio0 { + clock-frequency = <4000000>; + max-frequency = <1000000>; + bus-width = <8>; + status = "okay"; +}; + +&sdio1 { + clock-frequency = <4000000>; + max-frequency = <1000000>; + bus-width = <4>; + status = "okay"; +}; + +&gmac0 { + phy-reset-gpios = <&gpio 13 0>; + status = "okay"; +}; + +&gpio { + compatible = "starfive,jh7110-gpio"; + gpio-controller; +}; + +&uart0 { + reg-offset = <0>; + current-speed = <115200>; + status = "okay"; +}; + +&gpioa { + status = "disabled"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_cdns3 { + dr_mode = "host"; +}; + +&timer { + status = "disabled"; +}; + +&wdog { + status = "disabled"; +}; + +&clkvout { + status = "disabled"; +}; + +&pdm { + status = "disabled"; +}; -- cgit v1.2.3