From 7c964c3b93671dbc27eebc876ec592db7ac88ec6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 20 Feb 2021 20:06:24 -0500 Subject: ppc: Remove gdsys hrcon boards These boards have not been converted to CONFIG_DM_MMC, along with other DM conversions, by the deadline. Remove them. Cc: Dirk Eibach Signed-off-by: Tom Rini --- board/gdsys/common/Makefile | 1 - board/gdsys/common/fanctrl.c | 35 --- board/gdsys/common/fanctrl.h | 12 - board/gdsys/common/mclink.c | 141 ----------- board/gdsys/common/mclink.h | 14 -- board/gdsys/common/phy.c | 278 ---------------------- board/gdsys/common/phy.h | 13 -- board/gdsys/mpc8308/Kconfig | 26 +-- board/gdsys/mpc8308/MAINTAINERS | 4 +- board/gdsys/mpc8308/Makefile | 1 - board/gdsys/mpc8308/hrcon.c | 504 ---------------------------------------- 11 files changed, 3 insertions(+), 1026 deletions(-) delete mode 100644 board/gdsys/common/fanctrl.c delete mode 100644 board/gdsys/common/fanctrl.h delete mode 100644 board/gdsys/common/mclink.c delete mode 100644 board/gdsys/common/mclink.h delete mode 100644 board/gdsys/common/phy.c delete mode 100644 board/gdsys/common/phy.h delete mode 100644 board/gdsys/mpc8308/hrcon.c (limited to 'board/gdsys') diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index fa4c65c634..dd6d5e69de 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -6,7 +6,6 @@ obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o obj-$(CONFIG_CONTROLCENTERD) += dp501.o -obj-$(CONFIG_TARGET_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o obj-$(CONFIG_TARGET_GAZERBEAM) += osd.o ihs_mdio.o ioep-fpga.o ifdef CONFIG_OSD diff --git a/board/gdsys/common/fanctrl.c b/board/gdsys/common/fanctrl.c deleted file mode 100644 index 27c875cbec..0000000000 --- a/board/gdsys/common/fanctrl.c +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifdef CONFIG_GDSYS_LEGACY_DRIVERS - -#include -#include - -enum { - FAN_CONFIG = 0x03, - FAN_TACHLIM_LSB = 0x48, - FAN_TACHLIM_MSB = 0x49, - FAN_PWM_FREQ = 0x4D, -}; - -void init_fan_controller(u8 addr) -{ - int val; - - /* set PWM Frequency to 2.5% resolution */ - i2c_reg_write(addr, FAN_PWM_FREQ, 20); - - /* set Tachometer Limit */ - i2c_reg_write(addr, FAN_TACHLIM_LSB, 0x10); - i2c_reg_write(addr, FAN_TACHLIM_MSB, 0x0a); - - /* enable Tach input */ - val = i2c_reg_read(addr, FAN_CONFIG) | 0x04; - i2c_reg_write(addr, FAN_CONFIG, val); -} - -#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/fanctrl.h b/board/gdsys/common/fanctrl.h deleted file mode 100644 index ab7e58def5..0000000000 --- a/board/gdsys/common/fanctrl.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifndef _FANCTRL_H_ -#define _FANCTRL_H_ - -void init_fan_controller(u8 addr); - -#endif diff --git a/board/gdsys/common/mclink.c b/board/gdsys/common/mclink.c deleted file mode 100644 index 6147fbfc87..0000000000 --- a/board/gdsys/common/mclink.c +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2012 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifdef CONFIG_GDSYS_LEGACY_DRIVERS - -#include -#include -#include - -#include -#include - -enum { - MCINT_SLAVE_LINK_CHANGED_EV = 1 << 7, - MCINT_TX_ERROR_EV = 1 << 9, - MCINT_TX_BUFFER_FREE = 1 << 10, - MCINT_TX_PACKET_TRANSMITTED_EV = 1 << 11, - MCINT_RX_ERROR_EV = 1 << 13, - MCINT_RX_CONTENT_AVAILABLE = 1 << 14, - MCINT_RX_PACKET_RECEIVED_EV = 1 << 15, -}; - -int mclink_probe(void) -{ - unsigned int k; - int slaves = 0; - - for (k = 0; k < CONFIG_SYS_MCLINK_MAX; ++k) { - int timeout = 0; - unsigned int ctr = 0; - u16 mc_status; - - FPGA_GET_REG(k, mc_status, &mc_status); - - if (!(mc_status & (1 << 15))) - break; - - FPGA_SET_REG(k, mc_control, 0x8000); - - FPGA_GET_REG(k, mc_status, &mc_status); - while (!(mc_status & (1 << 14))) { - udelay(100); - if (ctr++ > 500) { - timeout = 1; - break; - } - FPGA_GET_REG(k, mc_status, &mc_status); - } - if (timeout) - break; - - printf("waited %d us for mclink %d to come up\n", ctr * 100, k); - - slaves++; - } - - return slaves; -} - -int mclink_send(u8 slave, u16 addr, u16 data) -{ - unsigned int ctr = 0; - u16 int_status; - u16 rx_cmd_status; - u16 rx_cmd; - - /* reset interrupt status */ - FPGA_GET_REG(0, mc_int, &int_status); - FPGA_SET_REG(0, mc_int, int_status); - - /* send */ - FPGA_SET_REG(0, mc_tx_address, addr); - FPGA_SET_REG(0, mc_tx_data, data); - FPGA_SET_REG(0, mc_tx_cmd, (slave & 0x03) << 14); - FPGA_SET_REG(0, mc_control, 0x8001); - - /* wait for reply */ - FPGA_GET_REG(0, mc_int, &int_status); - while (!(int_status & MCINT_RX_PACKET_RECEIVED_EV)) { - udelay(100); - if (ctr++ > 3) - return -ETIMEDOUT; - FPGA_GET_REG(0, mc_int, &int_status); - } - - FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status); - rx_cmd = (rx_cmd_status >> 12) & 0x03; - if (rx_cmd != 0) - printf("mclink_send: received cmd %d, expected %d\n", rx_cmd, - 0); - - return 0; -} - -int mclink_receive(u8 slave, u16 addr, u16 *data) -{ - u16 rx_cmd_status; - u16 rx_cmd; - u16 int_status; - unsigned int ctr = 0; - - /* send read request */ - FPGA_SET_REG(0, mc_tx_address, addr); - FPGA_SET_REG(0, mc_tx_cmd, - ((slave & 0x03) << 14) | (1 << 12) | (1 << 0)); - FPGA_SET_REG(0, mc_control, 0x8001); - - - /* wait for reply */ - FPGA_GET_REG(0, mc_int, &int_status); - while (!(int_status & MCINT_RX_CONTENT_AVAILABLE)) { - udelay(100); - if (ctr++ > 3) - return -ETIMEDOUT; - FPGA_GET_REG(0, mc_int, &int_status); - } - - /* check reply */ - FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status); - if ((rx_cmd_status >> 14) != slave) { - printf("mclink_receive: reply from slave %d, expected %d\n", - rx_cmd_status >> 14, slave); - return -EINVAL; - } - - rx_cmd = (rx_cmd_status >> 12) & 0x03; - if (rx_cmd != 1) { - printf("mclink_send: received cmd %d, expected %d\n", - rx_cmd, 1); - return -EIO; - } - - FPGA_GET_REG(0, mc_rx_data, data); - - return 0; -} - -#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/mclink.h b/board/gdsys/common/mclink.h deleted file mode 100644 index 4dc4058892..0000000000 --- a/board/gdsys/common/mclink.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifndef _MCLINK_H_ -#define _MCLINK_H_ - -int mclink_probe(void); -int mclink_send(u8 slave, u16 addr, u16 data); -int mclink_receive(u8 slave, u16 addr, u16 *data); - -#endif diff --git a/board/gdsys/common/phy.c b/board/gdsys/common/phy.c deleted file mode 100644 index 516f4e8edc..0000000000 --- a/board/gdsys/common/phy.c +++ /dev/null @@ -1,278 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#include -#include - -#include - -enum { - MIICMD_SET, - MIICMD_MODIFY, - MIICMD_VERIFY_VALUE, - MIICMD_WAIT_FOR_VALUE, -}; - -struct mii_setupcmd { - u8 token; - u8 reg; - u16 data; - u16 mask; - u32 timeout; -}; - -/* - * verify we are talking to a 88e1518 - */ -struct mii_setupcmd verify_88e1518[] = { - { MIICMD_SET, 22, 0x0000 }, - { MIICMD_VERIFY_VALUE, 2, 0x0141, 0xffff }, - { MIICMD_VERIFY_VALUE, 3, 0x0dd0, 0xfff0 }, -}; - -/* - * workaround for erratum mentioned in 88E1518 release notes - */ -struct mii_setupcmd fixup_88e1518[] = { - { MIICMD_SET, 22, 0x00ff }, - { MIICMD_SET, 17, 0x214b }, - { MIICMD_SET, 16, 0x2144 }, - { MIICMD_SET, 17, 0x0c28 }, - { MIICMD_SET, 16, 0x2146 }, - { MIICMD_SET, 17, 0xb233 }, - { MIICMD_SET, 16, 0x214d }, - { MIICMD_SET, 17, 0xcc0c }, - { MIICMD_SET, 16, 0x2159 }, - { MIICMD_SET, 22, 0x0000 }, -}; - -/* - * default initialization: - * - set RGMII receive timing to "receive clock transition when data stable" - * - set RGMII transmit timing to "transmit clock internally delayed" - * - set RGMII output impedance target to 78,8 Ohm - * - run output impedance calibration - * - set autonegotiation advertise to 1000FD only - */ -struct mii_setupcmd default_88e1518[] = { - { MIICMD_SET, 22, 0x0002 }, - { MIICMD_MODIFY, 21, 0x0030, 0x0030 }, - { MIICMD_MODIFY, 25, 0x0000, 0x0003 }, - { MIICMD_MODIFY, 24, 0x8000, 0x8000 }, - { MIICMD_WAIT_FOR_VALUE, 24, 0x4000, 0x4000, 2000 }, - { MIICMD_SET, 22, 0x0000 }, - { MIICMD_MODIFY, 4, 0x0000, 0x01e0 }, - { MIICMD_MODIFY, 9, 0x0200, 0x0300 }, -}; - -/* - * turn off CLK125 for PHY daughterboard - */ -struct mii_setupcmd ch1fix_88e1518[] = { - { MIICMD_SET, 22, 0x0002 }, - { MIICMD_MODIFY, 16, 0x0006, 0x0006 }, - { MIICMD_SET, 22, 0x0000 }, -}; - -/* - * perform copper software reset - */ -struct mii_setupcmd swreset_88e1518[] = { - { MIICMD_SET, 22, 0x0000 }, - { MIICMD_MODIFY, 0, 0x8000, 0x8000 }, - { MIICMD_WAIT_FOR_VALUE, 0, 0x0000, 0x8000, 2000 }, -}; - -/* - * special one for 88E1514: - * Force SGMII to Copper mode - */ -struct mii_setupcmd mii_to_copper_88e1514[] = { - { MIICMD_SET, 22, 0x0012 }, - { MIICMD_MODIFY, 20, 0x0001, 0x0007 }, - { MIICMD_MODIFY, 20, 0x8000, 0x8000 }, - { MIICMD_SET, 22, 0x0000 }, -}; - -/* - * turn off SGMII auto-negotiation - */ -struct mii_setupcmd sgmii_autoneg_off_88e1518[] = { - { MIICMD_SET, 22, 0x0001 }, - { MIICMD_MODIFY, 0, 0x0000, 0x1000 }, - { MIICMD_MODIFY, 0, 0x8000, 0x8000 }, - { MIICMD_SET, 22, 0x0000 }, -}; - -/* - * invert LED2 polarity - */ -struct mii_setupcmd invert_led2_88e1514[] = { - { MIICMD_SET, 22, 0x0003 }, - { MIICMD_MODIFY, 17, 0x0030, 0x0010 }, - { MIICMD_SET, 22, 0x0000 }, -}; - -static int process_setupcmd(const char *bus, unsigned char addr, - struct mii_setupcmd *setupcmd) -{ - int res; - u8 reg = setupcmd->reg; - u16 data = setupcmd->data; - u16 mask = setupcmd->mask; - u32 timeout = setupcmd->timeout; - u16 orig_data; - unsigned long start; - - debug("mii %s:%u reg %2u ", bus, addr, reg); - - switch (setupcmd->token) { - case MIICMD_MODIFY: - res = miiphy_read(bus, addr, reg, &orig_data); - if (res) - break; - debug("is %04x. (value %04x mask %04x) ", orig_data, data, - mask); - data = (orig_data & ~mask) | (data & mask); - /* fallthrough */ - case MIICMD_SET: - debug("=> %04x\n", data); - res = miiphy_write(bus, addr, reg, data); - break; - case MIICMD_VERIFY_VALUE: - res = miiphy_read(bus, addr, reg, &orig_data); - if (res) - break; - if ((orig_data & mask) != (data & mask)) - res = -1; - debug("(value %04x mask %04x) == %04x? %s\n", data, mask, - orig_data, res ? "FAIL" : "PASS"); - break; - case MIICMD_WAIT_FOR_VALUE: - res = -1; - start = get_timer(0); - while ((res != 0) && (get_timer(start) < timeout)) { - res = miiphy_read(bus, addr, reg, &orig_data); - if (res) - continue; - if ((orig_data & mask) != (data & mask)) - res = -1; - } - debug("(value %04x mask %04x) == %04x? %s after %lu ms\n", data, - mask, orig_data, res ? "FAIL" : "PASS", - get_timer(start)); - break; - default: - res = -1; - break; - } - - return res; -} - -static int process_setup(const char *bus, unsigned char addr, - struct mii_setupcmd *setupcmd, unsigned int count) -{ - int res = 0; - unsigned int k; - - for (k = 0; k < count; ++k) { - res = process_setupcmd(bus, addr, &setupcmd[k]); - if (res) { - printf("mii cmd %u on bus %s addr %u failed, aborting setup\n", - setupcmd[k].token, bus, addr); - break; - } - } - - return res; -} - -int setup_88e1518(const char *bus, unsigned char addr) -{ - int res; - - res = process_setup(bus, addr, - verify_88e1518, ARRAY_SIZE(verify_88e1518)); - if (res) - return res; - - res = process_setup(bus, addr, - fixup_88e1518, ARRAY_SIZE(fixup_88e1518)); - if (res) - return res; - - res = process_setup(bus, addr, - default_88e1518, ARRAY_SIZE(default_88e1518)); - if (res) - return res; - - if (addr) { - res = process_setup(bus, addr, - ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518)); - if (res) - return res; - } - - res = process_setup(bus, addr, - swreset_88e1518, ARRAY_SIZE(swreset_88e1518)); - if (res) - return res; - - return 0; -} - -int setup_88e1514(const char *bus, unsigned char addr) -{ - int res; - - res = process_setup(bus, addr, - verify_88e1518, ARRAY_SIZE(verify_88e1518)); - if (res) - return res; - - res = process_setup(bus, addr, - fixup_88e1518, ARRAY_SIZE(fixup_88e1518)); - if (res) - return res; - - res = process_setup(bus, addr, - mii_to_copper_88e1514, - ARRAY_SIZE(mii_to_copper_88e1514)); - if (res) - return res; - - res = process_setup(bus, addr, - sgmii_autoneg_off_88e1518, - ARRAY_SIZE(sgmii_autoneg_off_88e1518)); - if (res) - return res; - - res = process_setup(bus, addr, - invert_led2_88e1514, - ARRAY_SIZE(invert_led2_88e1514)); - if (res) - return res; - - res = process_setup(bus, addr, - default_88e1518, ARRAY_SIZE(default_88e1518)); - if (res) - return res; - - if (addr) { - res = process_setup(bus, addr, - ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518)); - if (res) - return res; - } - - res = process_setup(bus, addr, - swreset_88e1518, ARRAY_SIZE(swreset_88e1518)); - if (res) - return res; - - return 0; -} diff --git a/board/gdsys/common/phy.h b/board/gdsys/common/phy.h deleted file mode 100644 index e0aa661b9c..0000000000 --- a/board/gdsys/common/phy.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifndef _PHY_H_ -#define _PHY_H_ - -int setup_88e1514(const char *bus, unsigned char addr); -int setup_88e1518(const char *bus, unsigned char addr); - -#endif diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig index 1c33f0c982..c3fd0518bc 100644 --- a/board/gdsys/mpc8308/Kconfig +++ b/board/gdsys/mpc8308/Kconfig @@ -1,3 +1,5 @@ +if TARGET_GAZERBEAM + config GDSYS_LEGACY_OSD_CMDS bool help @@ -33,27 +35,6 @@ config SYS_FPGA1_SIZE help The base address of the second FPGA's register map. -if TARGET_HRCON - -config SYS_BOARD - default "mpc8308" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "hrcon" - -config GDSYS_LEGACY_OSD_CMDS - default y - -config GDSYS_LEGACY_DRIVERS - default y - -endif - -if TARGET_GAZERBEAM - config SYS_BOARD default "mpc8308" @@ -71,9 +52,6 @@ config SYS_FPGA1_SIZE config GDSYS_LEGACY_OSD_CMDS default y -endif - -if TARGET_HRCON || TARGET_GAZERBEAM choice prompt "FPGA flavor selection" diff --git a/board/gdsys/mpc8308/MAINTAINERS b/board/gdsys/mpc8308/MAINTAINERS index cc0fbebccd..dc0b389f73 100644 --- a/board/gdsys/mpc8308/MAINTAINERS +++ b/board/gdsys/mpc8308/MAINTAINERS @@ -2,7 +2,5 @@ MPC8308 BOARD M: Dirk Eibach S: Maintained F: board/gdsys/mpc8308/ -F: include/configs/hrcon.h -F: configs/hrcon_defconfig -F: configs/hrcon_dh_defconfig +F: include/configs/gazerbeam.h F: configs/gazerbeam_defconfig diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile index 578b36653d..f86d997bc7 100644 --- a/board/gdsys/mpc8308/Makefile +++ b/board/gdsys/mpc8308/Makefile @@ -4,5 +4,4 @@ # Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc obj-y := mpc8308.o sdram.o -obj-$(CONFIG_TARGET_HRCON) += hrcon.o obj-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.o diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c deleted file mode 100644 index b5c681c2d1..0000000000 --- a/board/gdsys/mpc8308/hrcon.c +++ /dev/null @@ -1,504 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "mpc8308.h" - -#include - -#include "../common/ioep-fpga.h" -#include "../common/osd.h" -#include "../common/mclink.h" -#include "../common/phy.h" -#include "../common/fanctrl.h" - -#include -#include - -#include - -#define MAX_MUX_CHANNELS 2 - -enum { - MCFPGA_DONE = BIT(0), - MCFPGA_INIT_N = BIT(1), - MCFPGA_PROGRAM_N = BIT(2), - MCFPGA_UPDATE_ENABLE_N = BIT(3), - MCFPGA_RESET_N = BIT(4), -}; - -enum { - GPIO_MDC = 1 << 14, - GPIO_MDIO = 1 << 15, -}; - -uint mclink_fpgacount; -struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; - -struct { - u8 bus; - u8 addr; -} hrcon_fans[] = CONFIG_HRCON_FANS; - -int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) -{ - int res; - - switch (fpga) { - case 0: - out_le16(reg, data); - break; - default: - res = mclink_send(fpga - 1, regoff, data); - if (res < 0) { - printf("mclink_send reg %02lx data %04x returned %d\n", - regoff, data, res); - return res; - } - break; - } - - return 0; -} - -int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) -{ - int res; - - switch (fpga) { - case 0: - *data = in_le16(reg); - break; - default: - if (fpga > mclink_fpgacount) - return -EINVAL; - res = mclink_receive(fpga - 1, regoff, data); - if (res < 0) { - printf("mclink_receive reg %02lx returned %d\n", - regoff, res); - return res; - } - } - - return 0; -} - -int checkboard(void) -{ - char *s = env_get("serial#"); - bool hw_type_cat = pca9698_get_value(0x20, 20); - - puts("Board: "); - - printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber"); - - if (s) { - puts(", serial# "); - puts(s); - } - - puts("\n"); - - return 0; -} - -int last_stage_init(void) -{ - int slaves; - uint k; - uchar mclink_controllers[] = { 0x3c, 0x3d, 0x3e }; - u16 fpga_features; - bool hw_type_cat = pca9698_get_value(0x20, 20); - bool ch0_rgmii2_present; - - FPGA_GET_REG(0, fpga_features, &fpga_features); - - /* Turn on Parade DP501 */ - pca9698_direction_output(0x20, 10, 1); - pca9698_direction_output(0x20, 11, 1); - - ch0_rgmii2_present = !pca9698_get_value(0x20, 30); - - /* wait for FPGA done, then reset FPGA */ - for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { - uint ctr = 0; - - if (i2c_probe(mclink_controllers[k])) - continue; - - while (!(pca953x_get_val(mclink_controllers[k]) - & MCFPGA_DONE)) { - mdelay(100); - if (ctr++ > 5) { - printf("no done for mclink_controller %u\n", k); - break; - } - } - - pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0); - pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0); - udelay(10); - pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, - MCFPGA_RESET_N); - } - - if (hw_type_cat) { - uint mux_ch; - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; - for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { - if ((mux_ch == 1) && !ch0_rgmii2_present) - continue; - - setup_88e1514(bb_miiphy_buses[0].name, mux_ch); - } - } - - /* give slave-PLLs and Parade DP501 some time to be up and running */ - mdelay(500); - - mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; - slaves = mclink_probe(); - mclink_fpgacount = 0; - - ioep_fpga_print_info(0); - osd_probe(0); -#ifdef CONFIG_SYS_OSD_DH - osd_probe(4); -#endif - - if (slaves <= 0) - return 0; - - mclink_fpgacount = slaves; - - for (k = 1; k <= slaves; ++k) { - FPGA_GET_REG(k, fpga_features, &fpga_features); - - ioep_fpga_print_info(k); - osd_probe(k); -#ifdef CONFIG_SYS_OSD_DH - osd_probe(k + 4); -#endif - if (hw_type_cat) { - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, bb_miiphy_buses[k].name, - MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; - setup_88e1514(bb_miiphy_buses[k].name, 0); - } - } - - for (k = 0; k < ARRAY_SIZE(hrcon_fans); ++k) { - i2c_set_bus_num(hrcon_fans[k].bus); - init_fan_controller(hrcon_fans[k].addr); - } - - return 0; -} - -/* - * provide access to fpga gpios and controls (for I2C bitbang) - * (these may look all too simple but make iocon.h much more readable) - */ -void fpga_gpio_set(uint bus, int pin) -{ - FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin); -} - -void fpga_gpio_clear(uint bus, int pin) -{ - FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin); -} - -int fpga_gpio_get(uint bus, int pin) -{ - u16 val; - - FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, gpio.read, &val); - - return val & pin; -} - -void fpga_control_set(uint bus, int pin) -{ - u16 val; - - FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val); - FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin); -} - -void fpga_control_clear(uint bus, int pin) -{ - u16 val; - - FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val); - FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin); -} - -void mpc8308_init(void) -{ - pca9698_direction_output(0x20, 4, 1); -} - -void mpc8308_set_fpga_reset(uint state) -{ - pca9698_set_value(0x20, 4, state ? 0 : 1); -} - -void mpc8308_setup_hw(void) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - /* - * set "startup-finished"-gpios - */ - setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12)); - setbits_gpio0_out(BIT(31 - 12)); -} - -int mpc8308_get_fpga_done(uint fpga) -{ - return pca9698_get_value(0x20, 19); -} - -#ifdef CONFIG_FSL_ESDHC -int board_mmc_init(struct bd_info *bd) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - sysconf83xx_t *sysconf = &immr->sysconf; - - /* Enable cache snooping in eSDHC system configuration register */ - out_be32(&sysconf->sdhccr, 0x02000000); - - return fsl_esdhc_mmc_init(bd); -} -#endif - -static struct pci_region pcie_regions_0[] = { - { - .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, - .size = CONFIG_SYS_PCIE1_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE1_IO_BASE, - .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, - .size = CONFIG_SYS_PCIE1_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -void pci_init_board(void) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - sysconf83xx_t *sysconf = &immr->sysconf; - law83xx_t *pcie_law = sysconf->pcielaw; - struct pci_region *pcie_reg[] = { pcie_regions_0 }; - - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - - /* Deassert the resets in the control register */ - out_be32(&sysconf->pecr1, 0xE0008000); - udelay(2000); - - /* Configure PCI Express Local Access Windows */ - out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); - out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); - - mpc83xx_pcie_init(1, pcie_reg); -} - -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - info->portwidth = FLASH_CFI_16BIT; - info->chipwidth = FLASH_CFI_BY16; - info->interface = FLASH_CFI_X16; - return 1; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - fsl_fdt_fixup_dr_usb(blob, bd); - fdt_fixup_esdhc(blob, bd); - - return 0; -} -#endif - -/* - * FPGA MII bitbang implementation - */ - -struct fpga_mii { - uint fpga; - int mdio; -} fpga_mii[] = { - { 0, 1}, - { 1, 1}, - { 2, 1}, - { 3, 1}, -}; - -static int mii_dummy_init(struct bb_miiphy_bus *bus) -{ - return 0; -} - -static int mii_mdio_active(struct bb_miiphy_bus *bus) -{ - struct fpga_mii *fpga_mii = bus->priv; - - if (fpga_mii->mdio) - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); - else - FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); - - return 0; -} - -static int mii_mdio_tristate(struct bb_miiphy_bus *bus) -{ - struct fpga_mii *fpga_mii = bus->priv; - - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); - - return 0; -} - -static int mii_set_mdio(struct bb_miiphy_bus *bus, int v) -{ - struct fpga_mii *fpga_mii = bus->priv; - - if (v) - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); - else - FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); - - fpga_mii->mdio = v; - - return 0; -} - -static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v) -{ - u16 gpio; - struct fpga_mii *fpga_mii = bus->priv; - - FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); - - *v = ((gpio & GPIO_MDIO) != 0); - - return 0; -} - -static int mii_set_mdc(struct bb_miiphy_bus *bus, int v) -{ - struct fpga_mii *fpga_mii = bus->priv; - - if (v) - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); - else - FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC); - - return 0; -} - -static int mii_delay(struct bb_miiphy_bus *bus) -{ - udelay(1); - - return 0; -} - -struct bb_miiphy_bus bb_miiphy_buses[] = { - { - .name = "board0", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[0], - }, - { - .name = "board1", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[1], - }, - { - .name = "board2", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[2], - }, - { - .name = "board3", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[3], - }, -}; - -int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); -- cgit v1.2.3