From a25feb7a6d2ac3351ee00c59a58a0dcfb9a13c9d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 27 Nov 2013 10:33:32 +0100 Subject: ARM: versatile: pass correct machine type for Versatile AB When U-Boot is configured for Versatile AB, it will still pass the machine ID of Versatile PB to the kernel. After this simple fix the system boots correctly. Cc: Stefano Babic Cc: Marek Vasut Signed-off-by: Linus Walleij Acked-by: Marek Vasut Acked-by: Stefano Babic --- board/armltd/versatile/versatile.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'board') diff --git a/board/armltd/versatile/versatile.c b/board/armltd/versatile/versatile.c index 30a3b904db..4e2d3421d8 100644 --- a/board/armltd/versatile/versatile.c +++ b/board/armltd/versatile/versatile.c @@ -52,7 +52,11 @@ int board_early_init_f (void) int board_init (void) { /* arch number of Versatile Board */ +#ifdef CONFIG_ARCH_VERSATILE_AB + gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_AB; +#else gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB; +#endif /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; -- cgit v1.2.3 From 7da765125165c172078489336117f95de2904322 Mon Sep 17 00:00:00 2001 From: Inderpal Singh Date: Wed, 8 Jan 2014 09:19:57 +0530 Subject: usb: exynos5: arndale: Add network support Arndale board has AX88760, which is USB 2.0 Hub & USB 2.0 Ethernet Combo controller, connected to HSIC Phy of USB host controller via USB3503 hub. This patch uses board specific board_usb_init function to perform reset sequence for USB3503 hub and enables the relevant config options for network to work. Signed-off-by: Inderpal Singh Signed-off-by: Chander Kashyap --- board/samsung/arndale/arndale.c | 21 +++++++++++++++++++++ drivers/usb/host/ehci-exynos.c | 2 ++ include/configs/arndale.h | 4 ++++ 3 files changed, 27 insertions(+) (limited to 'board') diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index 052fecdd5b..9efc355dab 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -5,12 +5,33 @@ */ #include +#include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_USB_EHCI_EXYNOS +int board_usb_init(int index, enum usb_init_type init) +{ + struct exynos5_gpio_part1 *gpio = (struct exynos5_gpio_part1 *) + samsung_get_base_gpio_part1(); + + /* Configure gpios for usb 3503 hub: + * disconnect, toggle reset and connect + */ + s5p_gpio_direction_output(&gpio->d1, 7, 0); + s5p_gpio_direction_output(&gpio->x3, 5, 0); + + s5p_gpio_direction_output(&gpio->x3, 5, 1); + s5p_gpio_direction_output(&gpio->d1, 7, 1); + + return 0; +} +#endif + int board_init(void) { gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c index 88e646690a..9356878eb2 100644 --- a/drivers/usb/host/ehci-exynos.c +++ b/drivers/usb/host/ehci-exynos.c @@ -203,6 +203,8 @@ int ehci_hcd_init(int index, enum usb_init_type init, setup_usb_phy(ctx->usb); + board_usb_init(index, init); + *hccr = ctx->hcd; *hcor = (struct ehci_hcor *)((uint32_t) *hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 7e367f39b2..9584d82af7 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -117,6 +117,10 @@ #define CONFIG_USB_EHCI_EXYNOS #define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + /* MMC SPL */ #define CONFIG_EXYNOS_SPL #define CONFIG_SPL -- cgit v1.2.3 From a113fb39df43546c704aa8eba55720da9a9dfedd Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 20 Dec 2013 18:34:53 -0300 Subject: board: nios2: Add CONFIG_CFI_FLASH_MTD guard to flash.h header include Signed-off-by: Ezequiel Garcia --- board/altera/nios2-generic/nios2-generic.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'board') diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c index 5c5b1b9148..aa126d71bc 100644 --- a/board/altera/nios2-generic/nios2-generic.c +++ b/board/altera/nios2-generic/nios2-generic.c @@ -8,7 +8,9 @@ #include #include +#if defined(CONFIG_CFI_FLASH_MTD) #include +#endif #include #include -- cgit v1.2.3 From c47817be257277f6445ea77bbf00954377ca9802 Mon Sep 17 00:00:00 2001 From: Piotr Wilczek Date: Tue, 14 Jan 2014 08:15:07 +0100 Subject: board:universal: fix i2c adapter Universal uses only one adapter I2C_0. Signed-off-by: Piotr Wilczek Signed-off-by: Kyungmin Park Acked-by: Przemyslaw Marczak --- board/samsung/universal_c210/universal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 54d0e1e0e3..3feef3f777 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -49,7 +49,7 @@ int power_init_board(void) * For PMIC the I2C bus is named as I2C5, but it is connected * to logical I2C adapter 0 */ - ret = pmic_init(I2C_5); + ret = pmic_init(I2C_0); if (ret) return ret; -- cgit v1.2.3 From f66f2aa265f00d4fcf49cdfb23bcfd64360b291d Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 13 Jan 2014 19:50:11 -0700 Subject: ARM: rpi_b: power on SDHCI and USB HW modules Send RPC commands to the VideoCore to turn on the SDHCI and USB modules. For SDHCI this isn't needed in practice, since the firmware already turned on the power in order to load U-Boot. However, it's best to be explicit. For USB, this is necessary, since the module isn't powered otherwise. This will allow the kernel USB driver to work. Signed-off-by: Stephen Warren --- arch/arm/include/asm/arch-bcm2835/mbox.h | 48 ++++++++++++++++++++++++++++++++ board/raspberrypi/rpi_b/rpi_b.c | 34 +++++++++++++++++++++- 2 files changed, 81 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h index 6b806ec57f..38cb42a3b3 100644 --- a/arch/arm/include/asm/arch-bcm2835/mbox.h +++ b/arch/arm/include/asm/arch-bcm2835/mbox.h @@ -133,6 +133,54 @@ struct bcm2835_mbox_tag_get_arm_mem { } body; }; +#define BCM2835_MBOX_POWER_DEVID_SDHCI 0 +#define BCM2835_MBOX_POWER_DEVID_UART0 1 +#define BCM2835_MBOX_POWER_DEVID_UART1 2 +#define BCM2835_MBOX_POWER_DEVID_USB_HCD 3 +#define BCM2835_MBOX_POWER_DEVID_I2C0 4 +#define BCM2835_MBOX_POWER_DEVID_I2C1 5 +#define BCM2835_MBOX_POWER_DEVID_I2C2 6 +#define BCM2835_MBOX_POWER_DEVID_SPI 7 +#define BCM2835_MBOX_POWER_DEVID_CCP2TX 8 + +#define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 1) +/* Device doesn't exist */ +#define BCM2835_MBOX_POWER_STATE_RESP_NODEV (1 << 1) + +#define BCM2835_MBOX_TAG_GET_POWER_STATE 0x00020001 + +struct bcm2835_mbox_tag_get_power_state { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + u32 device_id; + } req; + struct { + u32 device_id; + u32 state; + } resp; + } body; +}; + +#define BCM2835_MBOX_TAG_SET_POWER_STATE 0x00028001 + +#define BCM2835_MBOX_SET_POWER_STATE_REQ_ON (1 << 0) +#define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT (1 << 1) + +struct bcm2835_mbox_tag_set_power_state { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + u32 device_id; + u32 state; + } req; + struct { + u32 device_id; + u32 state; + } resp; + } body; +}; + #define BCM2835_MBOX_TAG_GET_CLOCK_RATE 0x00030002 #define BCM2835_MBOX_CLOCK_ID_EMMC 1 diff --git a/board/raspberrypi/rpi_b/rpi_b.c b/board/raspberrypi/rpi_b/rpi_b.c index 16d442aa62..f33fae9170 100644 --- a/board/raspberrypi/rpi_b/rpi_b.c +++ b/board/raspberrypi/rpi_b/rpi_b.c @@ -29,6 +29,12 @@ struct msg_get_arm_mem { u32 end_tag; }; +struct msg_set_power_state { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_set_power_state set_power_state; + u32 end_tag; +}; + struct msg_get_clock_rate { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_get_clock_rate get_clock_rate; @@ -54,11 +60,35 @@ int dram_init(void) return 0; } +static int power_on_module(u32 module) +{ + ALLOC_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1, 16); + int ret; + + BCM2835_MBOX_INIT_HDR(msg_pwr); + BCM2835_MBOX_INIT_TAG(&msg_pwr->set_power_state, + SET_POWER_STATE); + msg_pwr->set_power_state.body.req.device_id = module; + msg_pwr->set_power_state.body.req.state = + BCM2835_MBOX_SET_POWER_STATE_REQ_ON | + BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT; + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, + &msg_pwr->hdr); + if (ret) { + printf("bcm2835: Could not set module %u power state\n", + module); + return -1; + } + + return 0; +} + int board_init(void) { gd->bd->bi_boot_params = 0x100; - return 0; + return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD); } int board_mmc_init(void) @@ -66,6 +96,8 @@ int board_mmc_init(void) ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 16); int ret; + power_on_module(BCM2835_MBOX_POWER_DEVID_SDHCI); + BCM2835_MBOX_INIT_HDR(msg_clk); BCM2835_MBOX_INIT_TAG(&msg_clk->get_clock_rate, GET_CLOCK_RATE); msg_clk->get_clock_rate.body.req.clock_id = BCM2835_MBOX_CLOCK_ID_EMMC; -- cgit v1.2.3 From 2eb3ac7fe8ee29b2edfd7e0309115c2fc6875f95 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Fri, 3 Jan 2014 11:24:55 +0530 Subject: powerpc/t1040qds: Update DDR initialization related settings Update following DDR related settings for T1040QDS -Correct number of chip selects to two as t1040qds supports two Chip selects. -Update board_specific_parameters udimm structure with settings derived via calibration. -Reduced I2C speed to 50KHz as DDR-SPD does not get reliably read at 400KHz. Verified the updated settings to be working fine with dual-ranked Micron, MT18KSF51272AZ-1G6 DIMM at data rate 833MT/s, 1333MT/s and 1600MT/s. Signed-off-by: Poonam Aggrwal Signed-off-by: Priyanka Jain Reviewed-by: York Sun --- board/freescale/t1040qds/ddr.h | 22 ++++++++++++---------- include/configs/T1040QDS.h | 6 +++--- 2 files changed, 15 insertions(+), 13 deletions(-) (limited to 'board') diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h index 8ee206e79d..afa72af26a 100644 --- a/board/freescale/t1040qds/ddr.h +++ b/board/freescale/t1040qds/ddr.h @@ -31,16 +31,18 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, - {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, - {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, + {2, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, + {2, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, + {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, + {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, + {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, + {1, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, + {1, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, + {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, + {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, + {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, + {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, {} }; diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 7d0bc043f9..cfaac43050 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -167,7 +167,7 @@ unsigned long get_board_ddr_clk(void); /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR3 @@ -414,9 +414,9 @@ unsigned long get_board_ddr_clk(void); /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ -#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 -- cgit v1.2.3 From 1576b558b93ed2fb77dcd8bc138e77fe139974e3 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 3 Jan 2014 14:48:44 +0800 Subject: powerpc/t2080qds: some update for t2080qds - add more serdes protocols support. - fix some serdes lanes route. - fix SGMII doesn't work and incorrect mdio display for XFI when serdes 0x6d. - correct boot location info for SD/SPI boot. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- board/freescale/t2080qds/eth_t2080qds.c | 12 ++++-- board/freescale/t2080qds/t2080qds.c | 66 ++++++++++++++++++++++++++++++--- drivers/net/fm/t2080.c | 10 +++-- 3 files changed, 75 insertions(+), 13 deletions(-) (limited to 'board') diff --git a/board/freescale/t2080qds/eth_t2080qds.c b/board/freescale/t2080qds/eth_t2080qds.c index 3613f93981..3e4ab8fa57 100644 --- a/board/freescale/t2080qds/eth_t2080qds.c +++ b/board/freescale/t2080qds/eth_t2080qds.c @@ -371,9 +371,11 @@ int board_eth_init(bd_t *bis) break; case 0x6c: case 0x6d: + fm_info_set_phy_address(FM1_10GEC1, 4); + fm_info_set_phy_address(FM1_10GEC2, 5); /* SGMII in Slot3 */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); break; case 0x71: /* SGMII in Slot3 */ @@ -418,7 +420,6 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); break; default: - puts("Invalid SerDes1 protocol for T2080QDS\n"); break; } @@ -448,7 +449,12 @@ int board_eth_init(bd_t *bis) fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; - }; + case 3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + } break; case PHY_INTERFACE_MODE_RGMII: if (i == FM1_DTSEC3) diff --git a/board/freescale/t2080qds/t2080qds.c b/board/freescale/t2080qds/t2080qds.c index cac32fe73c..4fe8ccb54c 100644 --- a/board/freescale/t2080qds/t2080qds.c +++ b/board/freescale/t2080qds/t2080qds.c @@ -40,6 +40,11 @@ int checkboard(void) printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4); printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); +#ifdef CONFIG_SDCARD + puts("SD/MMC\n"); +#elif CONFIG_SPIFLASH + puts("SPI\n"); +#else sw = QIXIS_READ(brdcfg[0]); sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; @@ -51,6 +56,7 @@ int checkboard(void) puts("NAND\n"); else printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); +#endif printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver), qixis_read_tag(buf), (int)qixis_read_minor()); @@ -97,13 +103,25 @@ int brd_mux_lane_to_slot(void) /* SerDes1 is not enabled */ break; case 0x1c: - case 0x95: case 0xa2: - case 0x94: /* SD1(A:D) => SLOT3 SGMII * SD1(G:H) => SLOT1 SGMII */ - QIXIS_WRITE(brdcfg[12], 0x58); + QIXIS_WRITE(brdcfg[12], 0x1a); + break; + case 0x94: + case 0x95: + /* SD1(A:B) => SLOT3 SGMII@1.25bps + * SD1(C:D) => SFP Module, SGMII@3.125bps + * SD1(E:H) => SLOT1 SGMII@1.25bps + */ + case 0x96: + /* SD1(A:B) => SLOT3 SGMII@1.25bps + * SD1(C) => SFP Module, SGMII@3.125bps + * SD1(D) => SFP Module, SGMII@1.25bps + * SD1(E:H) => SLOT1 PCIe4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0x3a); break; case 0x51: /* SD1(A:D) => SLOT3 XAUI @@ -134,6 +152,34 @@ int brd_mux_lane_to_slot(void) */ QIXIS_WRITE(brdcfg[12], 0xda); break; + case 0x6e: + /* SD1(A:B) => SFP Module, XFI + * SD1(C:D) => SLOT3 SGMII + * SD1(E:F) => SLOT1 PCIe4 x2 + * SD1(G:H) => SLOT2 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0xd9); + break; + case 0xda: + /* SD1(A:H) => SLOT3 PCIe3 x8 + */ + QIXIS_WRITE(brdcfg[12], 0x0); + break; + case 0xc8: + /* SD1(A) => SLOT3 PCIe3 x1 + * SD1(B) => SFP Module, SGMII@1.25bps + * SD1(C:D) => SFP Module, SGMII@3.125bps + * SD1(E:F) => SLOT1 PCIe4 x2 + * SD1(G:H) => SLOT2 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x79); + break; + case 0xab: + /* SD1(A:D) => SLOT3 PCIe3 x4 + * SD1(E:H) => SLOT1 PCIe4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0x1a); + break; default: printf("WARNING: unsupported for SerDes1 Protocol %d\n", srds_prtcl_s1); @@ -147,7 +193,7 @@ int brd_mux_lane_to_slot(void) case 0x01: case 0x02: /* SD2(A:H) => SLOT4 PCIe1 */ - QIXIS_WRITE(brdcfg[13], 0x20); + QIXIS_WRITE(brdcfg[13], 0x10); break; case 0x15: case 0x16: @@ -164,7 +210,7 @@ int brd_mux_lane_to_slot(void) * SD2(E:F) => SLOT5 Aurora * SD2(G:H) => SATA1,SATA2 */ - QIXIS_WRITE(brdcfg[13], 0x70); + QIXIS_WRITE(brdcfg[13], 0x78); break; case 0x1f: /* @@ -180,7 +226,15 @@ int brd_mux_lane_to_slot(void) * SD2(A:D) => SLOT4 SRIO2 * SD2(E:H) => SLOT5 SRIO1 */ - QIXIS_WRITE(brdcfg[13], 0x50); + QIXIS_WRITE(brdcfg[13], 0xa0); + break; + case 0x36: + /* + * SD2(A:D) => SLOT4 SRIO2 + * SD2(E:F) => Aurora + * SD2(G:H) => SATA1,SATA2 + */ + QIXIS_WRITE(brdcfg[13], 0x78); break; default: printf("WARNING: unsupported for SerDes2 Protocol %d\n", diff --git a/drivers/net/fm/t2080.c b/drivers/net/fm/t2080.c index b5c1e9f76e..3b6212f858 100644 --- a/drivers/net/fm/t2080.c +++ b/drivers/net/fm/t2080.c @@ -50,15 +50,17 @@ phy_interface_t fman_port_enet_if(enum fm_port port) if (is_device_disabled(port)) return PHY_INTERFACE_MODE_NONE; - if ((port == FM1_10GEC1 || port == FM1_10GEC2 || - port == FM1_10GEC3 || port == FM1_10GEC4) && + if ((port == FM1_10GEC1 || port == FM1_10GEC2) && ((is_serdes_configured(XAUI_FM1_MAC9)) || - (is_serdes_configured(XFI_FM1_MAC1)) || - (is_serdes_configured(XFI_FM1_MAC2)) || (is_serdes_configured(XFI_FM1_MAC9)) || (is_serdes_configured(XFI_FM1_MAC10)))) return PHY_INTERFACE_MODE_XGMII; + if ((port == FM1_10GEC3 || port == FM1_10GEC4) && + ((is_serdes_configured(XFI_FM1_MAC1)) || + (is_serdes_configured(XFI_FM1_MAC2)))) + return PHY_INTERFACE_MODE_XGMII; + if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII)) return PHY_INTERFACE_MODE_RGMII; -- cgit v1.2.3 From eb6b458cef28c86603d56a27b9ee699b13c60c14 Mon Sep 17 00:00:00 2001 From: Po Liu Date: Fri, 10 Jan 2014 10:10:59 +0800 Subject: powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Using the TPL/SPL method to booting from 8k page NAND flash. - Add 256kB size SRAM tlb for second step booting; - Add spl.c for TPL image boot; - Add spl_minimal.c for minimal SPL image; - Add C29XPCIE_NAND configure; - Modify C29XPCIE.h for nand config and enviroment; Signed-off-by: Po Liu Reviewed-by: York Sun --- board/freescale/c29xpcie/Makefile | 15 ++++ board/freescale/c29xpcie/cpld.c | 2 + board/freescale/c29xpcie/spl.c | 77 +++++++++++++++++++ board/freescale/c29xpcie/spl_minimal.c | 63 ++++++++++++++++ board/freescale/c29xpcie/tlb.c | 13 +++- boards.cfg | 1 + include/configs/C29XPCIE.h | 130 ++++++++++++++++++++++++++++++++- 7 files changed, 295 insertions(+), 6 deletions(-) create mode 100644 board/freescale/c29xpcie/spl.c create mode 100644 board/freescale/c29xpcie/spl_minimal.c (limited to 'board') diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile index 626d48aea7..818484a57d 100644 --- a/board/freescale/c29xpcie/Makefile +++ b/board/freescale/c29xpcie/Makefile @@ -3,8 +3,23 @@ # # SPDX-License-Identifier: GPL-2.0+ +MINIMAL= +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +ifdef MINIMAL +obj-y += spl_minimal.o tlb.o law.o +else +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif + obj-y += c29xpcie.o obj-y += cpld.o obj-y += ddr.o obj-y += law.o obj-y += tlb.o +endif diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c index 5cbccff633..37722daf5b 100644 --- a/board/freescale/c29xpcie/cpld.c +++ b/board/freescale/c29xpcie/cpld.c @@ -89,6 +89,7 @@ static void cpld_dump_regs(void) } #endif +#ifndef CONFIG_SPL_BUILD int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int rc = 0; @@ -129,3 +130,4 @@ U_BOOT_CMD( "cpld_cmd dump - display the CPLD registers\n" #endif ); +#endif diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c new file mode 100644 index 0000000000..3cfdb723b9 --- /dev/null +++ b/board/freescale/c29xpcie/spl.c @@ -0,0 +1,77 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +ulong get_effective_memsize(void) +{ + return CONFIG_SYS_L2_SIZE; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + gd->bus_clk / 16 / CONFIG_BAUDRATE); + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *)CONFIG_SPL_GD_ADDR; + bd_t *bd; + + memset(gd, 0, sizeof(gd_t)); + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; + bd->bi_memsize = CONFIG_SYS_L2_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + + /* relocate environment function pointers etc. */ + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_NAND_BOOT + puts("TPL\n"); +#else + puts("SPL\n"); +#endif + + nand_boot(); +} diff --git a/board/freescale/c29xpcie/spl_minimal.c b/board/freescale/c29xpcie/spl_minimal.c new file mode 100644 index 0000000000..8f96b67e84 --- /dev/null +++ b/board/freescale/c29xpcie/spl_minimal.c @@ -0,0 +1,63 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + +#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); +#endif + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + gd->bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot...\n"); + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + puts("SPL\n"); + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); + + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c index 84844ee0f5..c5abed0504 100644 --- a/board/freescale/c29xpcie/tlb.c +++ b/board/freescale/c29xpcie/tlb.c @@ -30,6 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), +#ifndef CONFIG_SPL_BUILD SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 1, BOOKE_PAGESZ_64M, 1), @@ -42,6 +43,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256K, 1), +#endif #endif SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, @@ -49,7 +51,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 4, BOOKE_PAGESZ_64K, 1), SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64K, 1), SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE, @@ -61,7 +63,8 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 7, BOOKE_PAGESZ_256K, 1), -#ifdef CONFIG_SYS_RAMBOOT +#if defined(CONFIG_SYS_RAMBOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, @@ -71,6 +74,12 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_256M, 1), #endif + +#ifdef CONFIG_SYS_INIT_L2_ADDR + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 12, BOOKE_PAGESZ_256K, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index a8336cc7a9..9276214441 100644 --- a/boards.cfg +++ b/boards.cfg @@ -798,6 +798,7 @@ Active powerpc mpc85xx - freescale bsc9132qds Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu +Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu Active powerpc mpc85xx - freescale corenet_ds P3041DS - - Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 1cfb2c2279..8ec5cee8c1 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -23,6 +23,49 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc #endif +#ifdef CONFIG_NAND +#define CONFIG_SPL +#define CONFIG_TPL +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SPL_NAND_BOOT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NAND_INIT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SPL_MAX_SIZE (128 << 10) +#define CONFIG_SPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) +#elif defined(CONFIG_SPL_BUILD) +#define CONFIG_SPL_INIT_MINIMAL +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TEXT_BASE 0xff800000 +#define CONFIG_SPL_MAX_SIZE 8192 +#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) +#endif +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_TPL_PAD_TO 0x20000 +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#endif + #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xeff80000 #endif @@ -31,8 +74,14 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif /* High Level Configuration Options */ @@ -130,6 +179,10 @@ (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_NO_FLASH +#endif + /* * IFC Definitions */ @@ -183,7 +236,7 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) /* 8Bit NAND Flash - K9F1G08U0B */ #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ @@ -215,6 +268,23 @@ #define CONFIG_SYS_NAND_DDR_LAW 11 /* Set up IFC registers for boot location NOR/NAND */ +#ifdef CONFIG_NAND +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR @@ -230,6 +300,7 @@ #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif /* CPLD on IFC, selected by CS2 */ #define CONFIG_SYS_CPLD_BASE 0xffdf0000 @@ -269,7 +340,44 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) + +/* + * Config the L2 Cache as L2 SRAM + */ +#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) +#elif defined(CONFIG_NAND) +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) +#else +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) +#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) +#endif +#endif +#endif /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -278,6 +386,10 @@ #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif + #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV @@ -364,6 +476,16 @@ #define CONFIG_ENV_SECT_SIZE 0x10000 #define CONFIG_ENV_SIZE 0x2000 #endif +#elif defined(CONFIG_NAND) +#define CONFIG_ENV_IS_IN_NAND +#ifdef CONFIG_TPL_BUILD +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#else +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE +#endif +#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE #else #define CONFIG_ENV_IS_IN_FLASH #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -- cgit v1.2.3 From 3fdc827ca8a770848e8104c42cd6d8321d8c86ff Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Mon, 13 Jan 2014 13:01:06 +0800 Subject: t2080qds/ddr: update ddr parameters - Optimize UDIMM parameters for whole range from 1500MT/s to 2140MT/s. - Remove unused patameters: 'cpo', 'wrdata delay', '2T', which are unrelated to DDR3/3L. Tested with UDIMM 9JSF25672AZ-2G1K1 and verified speed 1200/1866/2133MT/s. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- board/freescale/t2080qds/ddr.c | 12 ++------ board/freescale/t2080qds/ddr.h | 65 +++++++++++++++++------------------------- 2 files changed, 28 insertions(+), 49 deletions(-) (limited to 'board') diff --git a/board/freescale/t2080qds/ddr.c b/board/freescale/t2080qds/ddr.c index 5db5d21622..ed1334d985 100644 --- a/board/freescale/t2080qds/ddr.c +++ b/board/freescale/t2080qds/ddr.c @@ -24,7 +24,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; - if (ctrl_num > 2) { + if (ctrl_num > 1) { printf("Not supported controller number %d\n", ctrl_num); return; } @@ -40,8 +40,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, else pbsp = udimms[0]; - - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; @@ -49,14 +48,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, if (pbsp->n_ranks == pdimm->n_ranks && (pdimm->rank_density >> 30) >= pbsp->rank_gb) { if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -69,13 +64,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, printf("for data rate %lu MT/s\n", ddr_freq); printf("Trying to use the highest speed (%u) parameters\n", pbsp_highest->datarate_mhz_high); - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } diff --git a/board/freescale/t2080qds/ddr.h b/board/freescale/t2080qds/ddr.h index 964eaada18..9fc879a4ef 100644 --- a/board/freescale/t2080qds/ddr.h +++ b/board/freescale/t2080qds/ddr.h @@ -14,9 +14,6 @@ struct board_specific_parameters { u32 wrlvl_start; u32 wrlvl_ctl_2; u32 wrlvl_ctl_3; - u32 cpo; - u32 write_data_delay; - u32 force_2t; }; /* @@ -28,58 +25,48 @@ struct board_specific_parameters { static const struct board_specific_parameters udimm0[] = { /* * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, - {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {1, 1800, 2, 5, 6, 0x06070709, 0x110a0b08, 0xff, 2, 0}, - {1, 1866, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0}, - {1, 1900, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0}, - {1, 2000, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0}, - {1, 2133, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0}, + {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, + {2, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, + {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {2, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b}, + {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, + {1, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, + {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {1, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b}, {} }; static const struct board_specific_parameters rdimm0[] = { /* * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ - {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0}, - {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, - {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, - {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, - {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, - {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + /* TODO: need tuning these parameters if RDIMM is used */ + {4, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906}, + {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, + {2, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, + {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, + {1, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, + {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07}, {} }; -/* - * The three slots have slightly different timing. The center values are good - * for all slots. We use identical speed tables for them. In future use, if - * DIMMs require separated tables, make more entries as needed. - */ static const struct board_specific_parameters *udimms[] = { udimm0, }; -/* - * The three slots have slightly different timing. See comments above. - */ static const struct board_specific_parameters *rdimms[] = { rdimm0, }; - - #endif -- cgit v1.2.3 From e222b1f36fedb0363dbc21e0add7dc3848bae553 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 14 Jan 2014 11:34:26 +0530 Subject: powerpc/mpc85xx:Increase binary size for P, B & T series boards. u-boot binary size for Freescale mpc85xx platforms is 512KB. This has been reached to upper limit for some of the platforms causig linker error. So, Increase the u-boot binary size to 768KB. Signed-off-by: York Sun Signed-off-by: Prabhakar Kushwaha --- board/freescale/c29xpcie/README | 12 +++--- board/freescale/p1010rdb/README.P1010RDB-PA | 12 +++--- board/freescale/p1010rdb/README.P1010RDB-PB | 4 +- board/freescale/p1023rds/README | 4 +- board/freescale/p1_p2_rdb/README | 12 +++--- board/freescale/p2041rdb/README | 12 +++--- board/freescale/t1040qds/README | 12 +++--- board/freescale/t104xrdb/README | 12 +++--- boards.cfg | 66 ++++++++++++++--------------- doc/README.b4860qds | 12 +++--- include/configs/B4860QDS.h | 8 ++-- include/configs/BSC9131RDB.h | 6 +-- include/configs/BSC9132QDS.h | 17 +++----- include/configs/C29XPCIE.h | 10 ++--- include/configs/P1010RDB.h | 16 +++---- include/configs/P1022DS.h | 12 ++---- include/configs/P1023RDB.h | 8 +--- include/configs/P1023RDS.h | 12 ++---- include/configs/P1_P2_RDB.h | 14 +++--- include/configs/P2020DS.h | 10 ++--- include/configs/P2041RDB.h | 16 +++---- include/configs/T1040QDS.h | 16 +++---- include/configs/T1040RDB.h | 16 +++---- include/configs/T1042RDB_PI.h | 16 +++---- include/configs/T2080QDS.h | 16 +++---- include/configs/T4240EMU.h | 4 +- include/configs/T4240QDS.h | 14 +++--- include/configs/corenet_ds.h | 16 +++---- include/configs/p1_p2_rdb_pc.h | 12 ++---- include/configs/p1_twr.h | 8 +--- include/configs/t4qds.h | 2 +- 31 files changed, 184 insertions(+), 223 deletions(-) (limited to 'board') diff --git a/board/freescale/c29xpcie/README b/board/freescale/c29xpcie/README index 430f08244a..3bc396b35a 100644 --- a/board/freescale/c29xpcie/README +++ b/board/freescale/c29xpcie/README @@ -62,9 +62,9 @@ Build and program u-boot to NOR flash 2. Program u-boot.bin into NOR flash => tftp $loadaddr $uboot - => protect off eff80000 +$filesize - => erase eff80000 +$filesize - => cp.b $loadaddr eff80000 $filesize + => protect off eff40000 +$filesize + => erase eff40000 +$filesize + => cp.b $loadaddr eff40000 $filesize 3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on. @@ -73,9 +73,9 @@ Alternate NOR bank There are four banks in C29XPCIE board, example to change bank booting: 1. Program u-boot.bin into alternate NOR bank => tftp $loadaddr $uboot - => protect off e9f80000 +$filesize - => erase e9f80000 +$filesize - => cp.b $loadaddr e9f80000 $filesize + => protect off e9f40000 +$filesize + => erase e9f40000 +$filesize + => cp.b $loadaddr e9f40000 $filesize 2. Switch to alternate NOR bank => cpld_cmd reset altbank [bank] diff --git a/board/freescale/p1010rdb/README.P1010RDB-PA b/board/freescale/p1010rdb/README.P1010RDB-PA index 158a1b3152..cde246dde2 100644 --- a/board/freescale/p1010rdb/README.P1010RDB-PA +++ b/board/freescale/p1010rdb/README.P1010RDB-PA @@ -104,9 +104,9 @@ Build and burn u-boot to NOR flash 2. Burn u-boot.bin into NOR flash => tftp $loadaddr $uboot - => protect off eff80000 +$filesize - => erase eff80000 +$filesize - => cp.b $loadaddr eff80000 $filesize + => protect off eff40000 +$filesize + => erase eff40000 +$filesize + => cp.b $loadaddr eff40000 $filesize 3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. @@ -115,9 +115,9 @@ Alternate NOR bank ================== 1. Burn u-boot.bin into alternate NOR bank => tftp $loadaddr $uboot - => protect off eef80000 +$filesize - => erase eef80000 +$filesize - => cp.b $loadaddr eef80000 $filesize + => protect off eef40000 +$filesize + => erase eef40000 +$filesize + => cp.b $loadaddr eef40000 $filesize 2. Switch to alternate NOR bank => mw.b ffb00009 1 diff --git a/board/freescale/p1010rdb/README.P1010RDB-PB b/board/freescale/p1010rdb/README.P1010RDB-PB index cf459b339e..c5d1419445 100644 --- a/board/freescale/p1010rdb/README.P1010RDB-PB +++ b/board/freescale/p1010rdb/README.P1010RDB-PB @@ -149,11 +149,11 @@ Steps to program images to flash for different boot mode 1. NOR boot => tftp 1000000 u-boot.bin For bank0 - => pro off all;era eff80000 efffffff;cp.b 1000000 eff80000 $filesize + => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board For bank1 - => pro off all;era eef80000 eeffffff;cp.b 1000000 eef80000 $filesize + => pro off all;era eef40000 eeffffff;cp.b 1000000 eef40000 $filesize set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board 2. NAND boot diff --git a/board/freescale/p1023rds/README b/board/freescale/p1023rds/README index 685f5daa99..d382551c4d 100644 --- a/board/freescale/p1023rds/README +++ b/board/freescale/p1023rds/README @@ -62,8 +62,8 @@ To program the image in the boot flash bank: NOR flash boot: => tftp 1000000 u-boot.bin => protect off all - => erase eff80000 efffffff - => cp.b 1000000 eff80000 80000 + => erase eff40000 efffffff + => cp.b 1000000 eff40000 c0000 NAND flash boot: => tftp 1000000 u-boot-nand.bin diff --git a/board/freescale/p1_p2_rdb/README b/board/freescale/p1_p2_rdb/README index cb664a5bd7..cd66e5878d 100644 --- a/board/freescale/p1_p2_rdb/README +++ b/board/freescale/p1_p2_rdb/README @@ -20,8 +20,8 @@ Memory Map 0xef00_0000 - 0xef7f_ffff Alternate bank 8MB 0xe800_0000 - 0xefff_ffff Boot bank 8MB -0xef78_0000 - 0xef7f_ffff Alternate u-boot address 512KB -0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB +0xef74_0000 - 0xef7f_ffff Alternate u-boot address 768KB +0xeff4_0000 - 0xefff_ffff Boot u-boot address 768KB Switch settings to boot from the NOR flash banks ------------------------------------------------ @@ -33,16 +33,16 @@ Flashing Images To place a new u-boot image in the alternate flash bank and then boot with that new image temporarily, use this: tftp 1000000 u-boot.bin - erase ef780000 ef7fffff - cp.b 1000000 ef780000 80000 + erase ef740000 ef7fffff + cp.b 1000000 ef740000 c0000 Now to boot from the alternate bank change the SW4[8] from 0 to 1. To program the image in the boot flash bank: tftp 1000000 u-boot.bin protect off all - erase eff80000 ffffffff - cp.b 1000000 eff80000 80000 + erase eff40000 ffffffff + cp.b 1000000 eff40000 c0000 Using the Device Tree Source File --------------------------------- diff --git a/board/freescale/p2041rdb/README b/board/freescale/p2041rdb/README index 292d0d39cf..9b5539fff3 100644 --- a/board/freescale/p2041rdb/README +++ b/board/freescale/p2041rdb/README @@ -18,8 +18,8 @@ Boot from NOR flash 2. Program image => tftp 1000000 u-boot.bin => protect off all - => erase eff80000 efffffff - => cp.b 1000000 eff80000 80000 + => erase eff40000 efffffff + => cp.b 1000000 eff40000 c0000 3. Program RCW => tftp 1000000 rcw.bin @@ -30,8 +30,8 @@ Boot from NOR flash 4. Program FMAN Firmware ucode => tftp 1000000 ucode.bin => protect off all - => erase ef000000 ef0fffff - => cp.b 1000000 ef000000 2000 + => erase eff00000 eff3ffff + => cp.b 1000000 eff00000 2000 5. Change DIP-switch SW1[1-5] = 10110 @@ -50,11 +50,11 @@ Boot from SDCard 3. Program the PBL image to SDCard => tftp 1000000 pbl_sd.bin => mmcinfo - => mmc write 1000000 8 441 + => mmc write 1000000 8 672 4. Program FMAN Firmware ucode => tftp 1000000 ucode.bin - => mmc write 1000000 46a 10 + => mmc write 1000000 690 10 5. Change DIP-switch SW1[1-5] = 01100 diff --git a/board/freescale/t1040qds/README b/board/freescale/t1040qds/README index f8b53b4212..6d380ae86d 100644 --- a/board/freescale/t1040qds/README +++ b/board/freescale/t1040qds/README @@ -118,16 +118,16 @@ Start Address End Address Description Size NOR Flash memory Map on T1040QDS -------------------------------- Start End Definition Size -0xEFF80000 0xEFFFFFFF u-boot (current bank) 512KB -0xEFF60000 0xEFF7FFFF u-boot env (current bank) 128KB -0xEFF40000 0xEFF5FFFF FMAN Ucode (current bank) 128KB +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 0xED300000 0xEFF3FFFF rootfs (alt bank) 44MB + 256KB 0xEC800000 0xEC8FFFF Hardware device tree (alt bank) 1MB 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB -0xEBF80000 0xEBFFFFFF u-boot (alt bank) 512KB -0xEBF60000 0xEBF7FFFF u-boot env (alt bank) 128KB -0xEBF40000 0xEBF5FFFF FMAN ucode (alt bank) 128KB +0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB 0xE9300000 0xEBF3FFFF rootfs (current bank) 44MB + 256KB 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB 0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README index 2cd8219c84..11e03bd300 100644 --- a/board/freescale/t104xrdb/README +++ b/board/freescale/t104xrdb/README @@ -161,16 +161,16 @@ Start Address End Address Description Size NOR Flash memory Map --------------------- Start End Definition Size -0xEFF80000 0xEFFFFFFF u-boot (current bank) 512KB -0xEFF60000 0xEFF7FFFF u-boot env (current bank) 128KB -0xEFF40000 0xEFF5FFFF FMAN Ucode (current bank) 128KB +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 0xED300000 0xEFF3FFFF rootfs (alt bank) 44MB + 256KB 0xEC800000 0xEC8FFFF Hardware device tree (alt bank) 1MB 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB -0xEBF80000 0xEBFFFFFF u-boot (alt bank) 512KB -0xEBF60000 0xEBF7FFFF u-boot env (alt bank) 128KB -0xEBF40000 0xEBF5FFFF FMAN ucode (alt bank) 128KB +0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB 0xE9300000 0xEBF3FFFF rootfs (current bank) 44MB + 256KB 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB 0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB diff --git a/boards.cfg b/boards.cfg index 9276214441..07ae05b799 100644 --- a/boards.cfg +++ b/boards.cfg @@ -778,12 +778,12 @@ Active powerpc mpc85xx - - sbc8548 Active powerpc mpc85xx - - socrates socrates - - Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 - -Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 - -Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND BSC9131RDB:BSC9131RDB,NAND Poonam Aggrwal Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND_SYSCLK100 BSC9131RDB:BSC9131RDB,NAND,SYS_CLK_100 Poonam Aggrwal Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH BSC9131RDB:BSC9131RDB,SPIFLASH Poonam Aggrwal @@ -800,26 +800,26 @@ Active powerpc mpc85xx - freescale c29xpcie Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu Active powerpc mpc85xx - freescale corenet_ds P3041DS - - -Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale corenet_ds P3041DS_SECURE_BOOT P3041DS:SECURE_BOOT - -Active powerpc mpc85xx - freescale corenet_ds P3041DS_SPIFLASH P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P3041DS_SRIO_PCIE_BOOT P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale corenet_ds P3041DS_SPIFLASH P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P3041DS_SRIO_PCIE_BOOT P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale corenet_ds P4080DS - - -Active powerpc mpc85xx - freescale corenet_ds P4080DS_SDCARD P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale corenet_ds P4080DS_SDCARD P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale corenet_ds P4080DS_SECURE_BOOT P4080DS:SECURE_BOOT - -Active powerpc mpc85xx - freescale corenet_ds P4080DS_SPIFLASH P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P4080DS_SRIO_PCIE_BOOT P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale corenet_ds P4080DS_SPIFLASH P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P4080DS_SRIO_PCIE_BOOT P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale corenet_ds P5020DS - - -Active powerpc mpc85xx - freescale corenet_ds P5020DS_NAND P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P5020DS_SDCARD P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale corenet_ds P5020DS_NAND P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P5020DS_SDCARD P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale corenet_ds P5020DS_SECURE_BOOT P5020DS:SECURE_BOOT - -Active powerpc mpc85xx - freescale corenet_ds P5020DS_SPIFLASH P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P5020DS_SRIO_PCIE_BOOT P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale corenet_ds P5020DS_SPIFLASH P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P5020DS_SRIO_PCIE_BOOT P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale corenet_ds P5040DS - - -Active powerpc mpc85xx - freescale corenet_ds P5040DS_NAND P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P5040DS_SDCARD P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale corenet_ds P5040DS_SPIFLASH P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale corenet_ds P5040DS_NAND P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P5040DS_SDCARD P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale corenet_ds P5040DS_SPIFLASH P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS MPC8536DS - Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_36BIT MPC8536DS:36BIT - Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_NAND MPC8536DS:NAND - @@ -964,28 +964,28 @@ Active powerpc mpc85xx - freescale p2020ds Active powerpc mpc85xx - freescale p2020ds P2020DS_SDCARD P2020DS:SDCARD - Active powerpc mpc85xx - freescale p2020ds P2020DS_SPIFLASH P2020DS:SPIFLASH - Active powerpc mpc85xx - freescale p2041rdb P2041RDB - - -Active powerpc mpc85xx - freescale p2041rdb P2041RDB_NAND P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SDCARD P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale p2041rdb P2041RDB_NAND P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SDCARD P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SECURE_BOOT P2041RDB:SECURE_BOOT - -Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 - -Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 - -Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - +Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal Active powerpc mpc85xx - freescale t2080qds T2080QDS T2080QDS:PPC_T2080 -Active powerpc mpc85xx - freescale t2080qds T2080QDS_SDCARD T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -Active powerpc mpc85xx - freescale t2080qds T2080QDS_SPIFLASH T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -Active powerpc mpc85xx - freescale t2080qds T2080QDS_NAND T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -Active powerpc mpc85xx - freescale t2080qds T2080QDS_SRIO_PCIE_BOOT T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 +Active powerpc mpc85xx - freescale t2080qds T2080QDS_SDCARD T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 +Active powerpc mpc85xx - freescale t2080qds T2080QDS_SPIFLASH T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 +Active powerpc mpc85xx - freescale t2080qds T2080QDS_NAND T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 +Active powerpc mpc85xx - freescale t2080qds T2080QDS_SRIO_PCIE_BOOT T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach diff --git a/doc/README.b4860qds b/doc/README.b4860qds index 48ece4b835..f8a79dbb25 100644 --- a/doc/README.b4860qds +++ b/doc/README.b4860qds @@ -227,16 +227,16 @@ Start Address End Address Description Size NOR Flash memory Map on B4860 and B4420QDS ------------------------------------------ Start End Definition Size -0xEFF80000 0xEFFFFFFF u-boot (current bank) 512KB -0xEFF60000 0xEFF7FFFF u-boot env (current bank) 128KB -0xEFF40000 0xEFF5FFFF FMAN Ucode (current bank) 128KB +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 0xEF300000 0xEFF3FFFF rootfs (alternate bank) 12MB + 256KB 0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB 0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB 0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB -0xEDF80000 0xEDFFFFFF u-boot (alternate bank) 512KB -0xEDF60000 0xEDF7FFFF u-boot env (alternate bank) 128KB -0xEDF40000 0xEDF5FFFF FMAN ucode (alternate bank) 128KB +0xEDF40000 0xEDFFFFFF u-boot (alternate bank) 768KB +0xEDF20000 0xEDF3FFFF u-boot env (alternate bank) 128KB +0xEDF00000 0xEDF1FFFF FMAN ucode (alternate bank) 128KB 0xED300000 0xEDF3FFFF rootfs (current bank) 12MB+256MB 0xEC800000 0xEC8FFFFF device tree (current bank) 1MB 0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index c66722946e..39c0b6d8c7 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -38,7 +38,7 @@ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -115,7 +115,7 @@ #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -608,7 +608,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -621,7 +621,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 584aba8d0e..fa89d13944 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -21,7 +21,7 @@ #define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #ifdef CONFIG_NAND @@ -38,7 +38,7 @@ #define CONFIG_SPL_MAX_SIZE 8192 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 #define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 @@ -326,7 +326,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_ENV_IS_IN_NAND #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) #elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 6170cbc81f..a973a49147 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -22,7 +22,7 @@ #define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1 #ifdef CONFIG_SPIFLASH @@ -30,7 +30,7 @@ #define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #ifdef CONFIG_NAND @@ -47,7 +47,7 @@ #define CONFIG_SPL_MAX_SIZE 8192 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 #define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 @@ -55,7 +55,7 @@ #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x8ff80000 +#define CONFIG_SYS_TEXT_BASE 0x8ff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -540,6 +540,7 @@ combinations. this should be removed later */ #if defined(CONFIG_RAMBOOT_SDCARD) #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #elif defined(CONFIG_RAMBOOT_SPIFLASH) @@ -554,7 +555,7 @@ combinations. this should be removed later #elif defined(CONFIG_NAND) #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) #elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ @@ -562,13 +563,9 @@ combinations. this should be removed later #define CONFIG_ENV_SIZE 0x2000 #else #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#define CONFIG_ENV_SECT_SIZE 0x20000 #endif #define CONFIG_LOADS_ECHO /* echo on for serial download */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 8ec5cee8c1..69ca0a13e4 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -20,7 +20,7 @@ #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #ifdef CONFIG_NAND @@ -42,7 +42,7 @@ #define CONFIG_SPL_MAX_SIZE (128 << 10) #define CONFIG_SPL_TEXT_BASE 0xf8f81000 #define CONFIG_SYS_MPC85XX_NO_RESETVEC -#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) +#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) @@ -67,7 +67,7 @@ #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -488,11 +488,7 @@ #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE #else #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 #endif diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index ea5cb6501b..62d7a84f4c 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -23,13 +23,13 @@ #ifdef CONFIG_SDCARD #define CONFIG_RAMBOOT_SDCARD #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #ifdef CONFIG_NAND @@ -46,7 +46,7 @@ #define CONFIG_SPL_MAX_SIZE 8192 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 #define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 @@ -57,11 +57,11 @@ #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ #define CONFIG_RAMBOOT_NAND #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -661,18 +661,14 @@ extern unsigned long get_sdram_size(void); #define CONFIG_ENV_SIZE (16 * 1024) #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ #endif -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #define CONFIG_ENV_SIZE 0x2000 #else #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 934a6cb7a6..9c9d72b605 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -32,7 +32,7 @@ #define CONFIG_SPL_TEXT_BASE 0xf8f81000 #define CONFIG_SPL_PAD_TO 0x18000 #define CONFIG_SPL_MAX_SIZE (96 * 1024) -#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) @@ -62,7 +62,7 @@ #define CONFIG_SPL_TEXT_BASE 0xf8f81000 #define CONFIG_SPL_PAD_TO 0x18000 #define CONFIG_SPL_MAX_SIZE (96 * 1024) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) @@ -96,7 +96,7 @@ #define CONFIG_SPL_MAX_SIZE (128 << 10) #define CONFIG_SPL_TEXT_BASE 0xf8f81000 #define CONFIG_SYS_MPC85XX_NO_RESETVEC -#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) +#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) @@ -128,7 +128,7 @@ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -653,11 +653,7 @@ #define CONFIG_ENV_SIZE 0x2000 #else #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index 7de6814a03..78a0aa2a7b 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -11,7 +11,7 @@ #define __CONFIG_H #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_SYS_MONITOR_BASE @@ -260,11 +260,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ @@ -365,7 +361,7 @@ extern unsigned long get_clock_freq(void); /* Default address of microcode for the Linux Fman driver */ /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xeff40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index 11c74ff5f5..d2aaf98113 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -32,7 +32,7 @@ #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_SYS_MONITOR_BASE @@ -220,7 +220,7 @@ extern unsigned long get_clock_freq(void); /* NAND boot: 4K NAND loader config */ #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + CONFIG_SYS_NAND_SPL_SIZE) #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE) #define CONFIG_SYS_NAND_U_BOOT_START 0x11000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) @@ -386,7 +386,7 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_RAMBOOT_NAND) #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x4000) @@ -394,11 +394,7 @@ extern unsigned long get_clock_freq(void); #endif #else #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif @@ -506,7 +502,7 @@ extern unsigned long get_clock_freq(void); /* Default address of microcode for the Linux Fman driver */ /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x1f00000 diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 85cb0767ef..726014a563 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -46,17 +46,17 @@ #ifdef CONFIG_SDCARD #define CONFIG_RAMBOOT_SDCARD 1 #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH 1 #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -267,7 +267,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* NAND boot: 4K NAND loader config */ #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) #define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) @@ -495,7 +495,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if defined(CONFIG_RAMBOOT_NAND) #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE - #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) + #define CONFIG_ENV_OFFSET ((768*1024)+CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_RAMBOOT_SDCARD) #define CONFIG_ENV_IS_IN_MMC #define CONFIG_FSL_FIXED_MMC_LOCATION @@ -513,11 +513,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif #else #define CONFIG_ENV_IS_IN_FLASH 1 - #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 - #define CONFIG_ENV_ADDR 0xfff80000 - #else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) - #endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index ada6c7b871..7ef165e152 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -20,14 +20,14 @@ #ifdef CONFIG_SDCARD #define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_SYS_TEXT_BASE 0xf8f40000 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc #endif #ifdef CONFIG_SPIFLASH #define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_SYS_TEXT_BASE 0xf8f40000 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc #endif @@ -40,7 +40,7 @@ #define CONFIG_MP 1 /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -578,11 +578,7 @@ #define CONFIG_ENV_SECT_SIZE 0x10000 #else #define CONFIG_ENV_IS_IN_FLASH 1 -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 2b81cbe111..6934c616bb 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -41,7 +41,7 @@ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -94,12 +94,12 @@ #define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 - #define CONFIG_ENV_OFFSET (512 * 1097) + #define CONFIG_ENV_OFFSET (512 * 1658) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -512,14 +512,14 @@ unsigned long get_board_sys_clk(unsigned long dummy); #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -532,7 +532,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index a639530eeb..91b511bf5e 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -45,7 +45,7 @@ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -93,12 +93,12 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1105) +#define CONFIG_ENV_OFFSET (512 * 1658) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) @@ -583,17 +583,17 @@ unsigned long get_board_ddr_clk(void); #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h index d721139a1f..65b4b26a09 100644 --- a/include/configs/T1040RDB.h +++ b/include/configs/T1040RDB.h @@ -44,7 +44,7 @@ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -92,12 +92,12 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1105) +#define CONFIG_ENV_OFFSET (512 * 1658) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) @@ -521,17 +521,17 @@ #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h index 2c02d9da58..104bb929ef 100644 --- a/include/configs/T1042RDB_PI.h +++ b/include/configs/T1042RDB_PI.h @@ -44,7 +44,7 @@ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -92,12 +92,12 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1105) +#define CONFIG_ENV_OFFSET (512 * 1658) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) @@ -529,17 +529,17 @@ #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T2080QDS.h b/include/configs/T2080QDS.h index b35e1073bf..d6d1f93684 100644 --- a/include/configs/T2080QDS.h +++ b/include/configs/T2080QDS.h @@ -60,7 +60,7 @@ #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -103,12 +103,12 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1105) +#define CONFIG_ENV_OFFSET (512 * 1658) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -544,14 +544,14 @@ unsigned long get_board_ddr_clk(void); #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -564,7 +564,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/T4240EMU.h b/include/configs/T4240EMU.h index 5e228f3556..c81c4577e3 100644 --- a/include/configs/T4240EMU.h +++ b/include/configs/T4240EMU.h @@ -98,7 +98,7 @@ #define CONFIG_SYS_INTERLAKEN #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) @@ -122,7 +122,7 @@ "bank_intlv=auto;" \ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ +"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=t4240emu/ramdisk.uboot\0" \ diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 1f1177be60..22019dcd2b 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -64,12 +64,12 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1097) +#define CONFIG_ENV_OFFSET (512 * 1658) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -376,14 +376,14 @@ unsigned long get_board_ddr_clk(void); #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -396,7 +396,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 3a1826dddd..fa748f71cb 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -49,7 +49,7 @@ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -95,12 +95,12 @@ #define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1097) +#define CONFIG_ENV_OFFSET (512 * 1658) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -518,14 +518,14 @@ #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -538,7 +538,7 @@ #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index c6df11b8f1..95e23ac585 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -161,7 +161,7 @@ #define CONFIG_SPL_TEXT_BASE 0xf8f81000 #define CONFIG_SPL_PAD_TO 0x18000 #define CONFIG_SPL_MAX_SIZE (96 * 1024) -#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) @@ -191,7 +191,7 @@ #define CONFIG_SPL_TEXT_BASE 0xf8f81000 #define CONFIG_SPL_PAD_TO 0x18000 #define CONFIG_SPL_MAX_SIZE (96 * 1024) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) @@ -221,7 +221,7 @@ #define CONFIG_SPL_MAX_SIZE (128 << 10) #define CONFIG_SPL_TEXT_BASE 0xf8f81000 #define CONFIG_SYS_MPC85XX_NO_RESETVEC -#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) +#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) @@ -247,7 +247,7 @@ #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -842,11 +842,7 @@ #define CONFIG_ENV_SIZE 0x2000 #else #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index 9837100e31..a7fe90ff3b 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -24,11 +24,11 @@ #define CONFIG_SYS_RAMBOOT #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS @@ -407,11 +407,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif #else #define CONFIG_ENV_IS_IN_FLASH -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 54a5e3e260..74fef67f23 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -21,7 +21,7 @@ #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS -- cgit v1.2.3 From f28bea0003536976ebe2fb299cfc140702fec489 Mon Sep 17 00:00:00 2001 From: "Haijun.Zhang" Date: Fri, 10 Jan 2014 13:52:19 +0800 Subject: eSDHC: Calculate envaddr accroding to the address format On BSC9131, BSC9132, P1010 : For High Capacity SD Cards (> 2 GBytes), the 32-bit source address specifies the memory address in block address format. Block length is fixed to 512 bytes as per the SD High Capacity specification. So we need to convert the block address format to byte address format to calculate the envaddr. If there is no enough space for environment variables or envaddr is larger than 4GiB, we relocate the envaddr to 0x400. The address relocated is in the front of the first partition that is assigned for sdboot only. Signed-off-by: Haijun Zhang Acked-by: Pantelis Antoniou Reviewed-by: York Sun --- arch/powerpc/include/asm/config_mpc85xx.h | 3 +++ board/freescale/common/sdhc_boot.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) (limited to 'board') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 54ce2f053c..be1d9d2a67 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -152,6 +152,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 +#define CONFIG_ESDHC_HC_BLK_ADDR /* P1011 is single core version of P1020 */ #elif defined(CONFIG_P1011) @@ -552,6 +553,7 @@ #define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_ESDHC_HC_BLK_ADDR #elif defined(CONFIG_BSC9132) #define CONFIG_MAX_CPUS 2 @@ -575,6 +577,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 +#define CONFIG_ESDHC_HC_BLK_ADDR #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) #define CONFIG_E6500 diff --git a/board/freescale/common/sdhc_boot.c b/board/freescale/common/sdhc_boot.c index f6e2b2bbd6..022f38b117 100644 --- a/board/freescale/common/sdhc_boot.c +++ b/board/freescale/common/sdhc_boot.c @@ -16,6 +16,8 @@ #define ESDHC_BOOT_IMAGE_SIZE 0x48 #define ESDHC_BOOT_IMAGE_ADDR 0x50 +#define ESDHC_DEFAULT_ENVADDR 0x400 + int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) { u8 *tmp_buf; @@ -39,6 +41,33 @@ int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) /* Get the code size from offset 0x48 */ code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE); +#ifdef CONFIG_ESDHC_HC_BLK_ADDR + /* + * On soc BSC9131, BSC9132: + * In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and + * code length of these soc specify the memory address in block address + * format. Block length is fixed to 512 bytes as per the SD High + * Capacity specification. + */ + u64 tmp; + + if (mmc->high_capacity) { + tmp = (u64)code_offset * blklen; + tmp += code_len * blklen; + } else + tmp = code_offset + code_len; + + if ((tmp + CONFIG_ENV_SIZE > mmc->capacity) || + (tmp > 0xFFFFFFFFU)) + *env_addr = ESDHC_DEFAULT_ENVADDR; + else + *env_addr = tmp; + + free(tmp_buf); + + return 0; +#endif + *env_addr = code_offset + code_len; free(tmp_buf); -- cgit v1.2.3 From e81f63f0d2acb130df68da52e711f9178592a012 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Tue, 7 Aug 2012 14:59:52 +0530 Subject: ARM: OMAP4/5: Remove dead code against CONFIG_SYS_ENABLE_PADS_ALL The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code. Signed-off-by: Jassi Brar --- arch/arm/cpu/armv7/omap-common/hwinit-common.c | 6 - arch/arm/include/asm/arch-omap4/sys_proto.h | 1 - arch/arm/include/asm/arch-omap5/sys_proto.h | 1 - board/ti/omap5_uevm/evm.c | 13 -- board/ti/omap5_uevm/mux_data.h | 234 ------------------------- board/ti/panda/panda.c | 30 ---- board/ti/panda/panda_mux_data.h | 186 -------------------- board/ti/sdp4430/sdp.c | 20 --- board/ti/sdp4430/sdp4430_mux_data.h | 197 --------------------- 9 files changed, 688 deletions(-) (limited to 'board') diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 85d375432f..bf2951031d 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -43,16 +43,10 @@ static void set_mux_conf_regs(void) set_muxconf_regs_essential(); break; case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: -#ifdef CONFIG_SYS_ENABLE_PADS_ALL - set_muxconf_regs_non_essential(); -#endif break; case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: set_muxconf_regs_essential(); -#ifdef CONFIG_SYS_ENABLE_PADS_ALL - set_muxconf_regs_non_essential(); -#endif break; } } diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index ce8217f697..fc9472544d 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -30,7 +30,6 @@ void watchdog_init(void); u32 get_device_type(void); void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); -void set_muxconf_regs_non_essential(void); void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 9e70d48f43..43011a4acd 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -31,7 +31,6 @@ void watchdog_init(void); u32 get_device_type(void); void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); -void set_muxconf_regs_non_essential(void); void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index af854dac1a..b549d72900 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -157,19 +157,6 @@ void set_muxconf_regs_essential(void) sizeof(struct pad_conf_entry)); } -void set_muxconf_regs_non_essential(void) -{ - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential, - sizeof(core_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential, - sizeof(wkup_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); -} - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { diff --git a/board/ti/omap5_uevm/mux_data.h b/board/ti/omap5_uevm/mux_data.h index 31ce363b63..de7ce9fe0b 100644 --- a/board/ti/omap5_uevm/mux_data.h +++ b/board/ti/omap5_uevm/mux_data.h @@ -55,238 +55,4 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = { }; -const struct pad_conf_entry core_padconf_array_non_essential[] = { - - {C2C_DATAIN0, (IEN | M0)}, /* C2C_DATAIN0 */ - {C2C_DATAIN1, (IEN | M0)}, /* C2C_DATAIN1 */ - {C2C_DATAIN2, (IEN | M0)}, /* C2C_DATAIN2 */ - {C2C_DATAIN3, (IEN | M0)}, /* C2C_DATAIN3 */ - {C2C_DATAIN4, (IEN | M0)}, /* C2C_DATAIN4 */ - {C2C_DATAIN5, (IEN | M0)}, /* C2C_DATAIN5 */ - {C2C_DATAIN6, (IEN | M0)}, /* C2C_DATAIN6 */ - {C2C_DATAIN7, (IEN | M0)}, /* C2C_DATAIN7 */ - {C2C_CLKIN1, (IEN | M0)}, /* C2C_CLKIN1 */ - {C2C_CLKIN0, (IEN | M0)}, /* C2C_CLKIN0 */ - {C2C_CLKOUT0, (M0)}, /* C2C_CLKOUT0 */ - {C2C_CLKOUT1, (M0)}, /* C2C_CLKOUT1 */ - {C2C_DATAOUT0, (M0)}, /* C2C_DATAOUT0 */ - {C2C_DATAOUT1, (M0)}, /* C2C_DATAOUT1 */ - {C2C_DATAOUT2, (M0)}, /* C2C_DATAOUT2 */ - {C2C_DATAOUT3, (M0)}, /* C2C_DATAOUT3 */ - {C2C_DATAOUT4, (M0)}, /* C2C_DATAOUT4 */ - {C2C_DATAOUT5, (M0)}, /* C2C_DATAOUT5 */ - {C2C_DATAOUT6, (M0)}, /* C2C_DATAOUT6 */ - {C2C_DATAOUT7, (M0)}, /* C2C_DATAOUT7 */ - {C2C_DATA8, (IEN | M0)}, /* C2C_DATA8 */ - {C2C_DATA9, (IEN | M0)}, /* C2C_DATA9 */ - {C2C_DATA10, (IEN | M0)}, /* C2C_DATA10 */ - {C2C_DATA11, (IEN | M0)}, /* C2C_DATA11 */ - {C2C_DATA12, (IEN | M0)}, /* C2C_DATA12 */ - {C2C_DATA13, (IEN | M0)}, /* C2C_DATA13 */ - {C2C_DATA14, (IEN | M0)}, /* C2C_DATA14 */ - {C2C_DATA15, (IEN | M0)}, /* C2C_DATA15 */ - {LLIB_WAKEREQOUT, (PTU | IEN | M6)}, /* GPIO2_32 */ - {LLIA_WAKEREQOUT, (M1)}, /* C2C_WAKEREQOUT */ - {HSI1_ACREADY, (PTD | M6)}, /* GPIO3_64 */ - {HSI1_CAREADY, (PTD | M6)}, /* GPIO3_65 */ - {HSI1_ACWAKE, (PTD | IEN | M6)}, /* GPIO3_66 */ - {HSI1_CAWAKE, (PTU | IEN | M6)}, /* GPIO3_67 */ - {HSI1_ACFLAG, (PTD | IEN | M6)}, /* GPIO3_68 */ - {HSI1_ACDATA, (PTD | M6)}, /* GPIO3_69 */ - {HSI1_CAFLAG, (M6)}, /* GPIO3_70 */ - {HSI1_CADATA, (M6)}, /* GPIO3_71 */ - {UART1_TX, (M0)}, /* UART1_TX */ - {UART1_CTS, (PTU | IEN | M0)}, /* UART1_CTS */ - {UART1_RX, (PTU | IEN | M0)}, /* UART1_RX */ - {UART1_RTS, (M0)}, /* UART1_RTS */ - {HSI2_CAREADY, (IEN | M0)}, /* HSI2_CAREADY */ - {HSI2_ACREADY, (OFF_EN | M0)}, /* HSI2_ACREADY */ - {HSI2_CAWAKE, (IEN | PTD | M0)}, /* HSI2_CAWAKE */ - {HSI2_ACWAKE, (M0)}, /* HSI2_ACWAKE */ - {HSI2_CAFLAG, (IEN | PTD | M0)}, /* HSI2_CAFLAG */ - {HSI2_CADATA, (IEN | PTD | M0)}, /* HSI2_CADATA */ - {HSI2_ACFLAG, (M0)}, /* HSI2_ACFLAG */ - {HSI2_ACDATA, (M0)}, /* HSI2_ACDATA */ - {UART2_RTS, (IEN | M1)}, /* MCSPI3_SOMI */ - {UART2_CTS, (IEN | M1)}, /* MCSPI3_CS0 */ - {UART2_RX, (IEN | M1)}, /* MCSPI3_SIMO */ - {UART2_TX, (IEN | M1)}, /* MCSPI3_CLK */ - {TIMER10_PWM_EVT, (IEN | M0)}, /* TIMER10_PWM_EVT */ - {DSIPORTA_TE0, (IEN | M0)}, /* DSIPORTA_TE0 */ - {DSIPORTA_LANE0X, (IEN | M0)}, /* DSIPORTA_LANE0X */ - {DSIPORTA_LANE0Y, (IEN | M0)}, /* DSIPORTA_LANE0Y */ - {DSIPORTA_LANE1X, (IEN | M0)}, /* DSIPORTA_LANE1X */ - {DSIPORTA_LANE1Y, (IEN | M0)}, /* DSIPORTA_LANE1Y */ - {DSIPORTA_LANE2X, (IEN | M0)}, /* DSIPORTA_LANE2X */ - {DSIPORTA_LANE2Y, (IEN | M0)}, /* DSIPORTA_LANE2Y */ - {DSIPORTA_LANE3X, (IEN | M0)}, /* DSIPORTA_LANE3X */ - {DSIPORTA_LANE3Y, (IEN | M0)}, /* DSIPORTA_LANE3Y */ - {DSIPORTA_LANE4X, (IEN | M0)}, /* DSIPORTA_LANE4X */ - {DSIPORTA_LANE4Y, (IEN | M0)}, /* DSIPORTA_LANE4Y */ - {TIMER9_PWM_EVT, (IEN | M0)}, /* TIMER9_PWM_EVT */ - {DSIPORTC_TE0, (IEN | M0)}, /* DSIPORTC_TE0 */ - {DSIPORTC_LANE0X, (IEN | M0)}, /* DSIPORTC_LANE0X */ - {DSIPORTC_LANE0Y, (IEN | M0)}, /* DSIPORTC_LANE0Y */ - {DSIPORTC_LANE1X, (IEN | M0)}, /* DSIPORTC_LANE1X */ - {DSIPORTC_LANE1Y, (IEN | M0)}, /* DSIPORTC_LANE1Y */ - {DSIPORTC_LANE2X, (IEN | M0)}, /* DSIPORTC_LANE2X */ - {DSIPORTC_LANE2Y, (IEN | M0)}, /* DSIPORTC_LANE2Y */ - {DSIPORTC_LANE3X, (IEN | M0)}, /* DSIPORTC_LANE3X */ - {DSIPORTC_LANE3Y, (IEN | M0)}, /* DSIPORTC_LANE3Y */ - {DSIPORTC_LANE4X, (IEN | M0)}, /* DSIPORTC_LANE4X */ - {DSIPORTC_LANE4Y, (IEN | M0)}, /* DSIPORTC_LANE4Y */ - {RFBI_HSYNC0, (M4)}, /* KBD_COL5 */ - {RFBI_TE_VSYNC0, (PTD | M6)}, /* GPIO6_161 */ - {RFBI_RE, (M4)}, /* KBD_COL4 */ - {RFBI_A0, (PTD | IEN | M6)}, /* GPIO6_165 */ - {RFBI_DATA8, (M4)}, /* KBD_COL3 */ - {RFBI_DATA9, (PTD | M6)}, /* GPIO6_175 */ - {RFBI_DATA10, (PTD | M6)}, /* GPIO6_176 */ - {RFBI_DATA11, (PTD | M6)}, /* GPIO6_177 */ - {RFBI_DATA12, (PTD | M6)}, /* GPIO6_178 */ - {RFBI_DATA13, (PTU | IEN | M6)}, /* GPIO6_179 */ - {RFBI_DATA14, (M4)}, /* KBD_COL7 */ - {RFBI_DATA15, (M4)}, /* KBD_COL6 */ - {GPIO6_182, (M6)}, /* GPIO6_182 */ - {GPIO6_183, (PTD | M6)}, /* GPIO6_183 */ - {GPIO6_184, (M4)}, /* KBD_COL2 */ - {GPIO6_185, (PTD | IEN | M6)}, /* GPIO6_185 */ - {GPIO6_186, (PTD | M6)}, /* GPIO6_186 */ - {GPIO6_187, (PTU | IEN | M4)}, /* KBD_ROW2 */ - {RFBI_DATA0, (PTD | M6)}, /* GPIO6_166 */ - {RFBI_DATA1, (PTD | M6)}, /* GPIO6_167 */ - {RFBI_DATA2, (PTD | M6)}, /* GPIO6_168 */ - {RFBI_DATA3, (PTD | IEN | M6)}, /* GPIO6_169 */ - {RFBI_DATA4, (IEN | M6)}, /* GPIO6_170 */ - {RFBI_DATA5, (IEN | M6)}, /* GPIO6_171 */ - {RFBI_DATA6, (PTD | M6)}, /* GPIO6_172 */ - {RFBI_DATA7, (PTD | M6)}, /* GPIO6_173 */ - {RFBI_CS0, (PTD | IEN | M6)}, /* GPIO6_163 */ - {RFBI_WE, (PTD | M6)}, /* GPIO6_162 */ - {MCSPI2_CS0, (M0)}, /* MCSPI2_CS0 */ - {MCSPI2_CLK, (IEN | M0)}, /* MCSPI2_CLK */ - {MCSPI2_SIMO, (IEN | M0)}, /* MCSPI2_SIMO*/ - {MCSPI2_SOMI, (PTU | IEN | M0)}, /* MCSPI2_SOMI*/ - {I2C4_SCL, (IEN | M0)}, /* I2C4_SCL */ - {I2C4_SDA, (IEN | M0)}, /* I2C4_SDA */ - {HDMI_CEC, (IEN | M0)}, /* HDMI_CEC */ - {HDMI_HPD, (PTD | IEN | M0)}, /* HDMI_HPD */ - {HDMI_DDC_SCL, (IEN | M0)}, /* HDMI_DDC_SCL */ - {HDMI_DDC_SDA, (IEN | M0)}, /* HDMI_DDC_SDA */ - {CSIPORTA_LANE0X, (IEN | M0)}, /* CSIPORTA_LANE0X */ - {CSIPORTA_LANE0Y, (IEN | M0)}, /* CSIPORTA_LANE0Y */ - {CSIPORTA_LANE1Y, (IEN | M0)}, /* CSIPORTA_LANE1Y */ - {CSIPORTA_LANE1X, (IEN | M0)}, /* CSIPORTA_LANE1X */ - {CSIPORTA_LANE2Y, (IEN | M0)}, /* CSIPORTA_LANE2Y */ - {CSIPORTA_LANE2X, (IEN | M0)}, /* CSIPORTA_LANE2X */ - {CSIPORTA_LANE3X, (IEN | M0)}, /* CSIPORTA_LANE3X */ - {CSIPORTA_LANE3Y, (IEN | M0)}, /* CSIPORTA_LANE3Y */ - {CSIPORTA_LANE4X, (IEN | M0)}, /* CSIPORTA_LANE4X */ - {CSIPORTA_LANE4Y, (IEN | M0)}, /* CSIPORTA_LANE4Y */ - {CSIPORTB_LANE0X, (IEN | M0)}, /* CSIPORTB_LANE0X */ - {CSIPORTB_LANE0Y, (IEN | M0)}, /* CSIPORTB_LANE0Y */ - {CSIPORTB_LANE1Y, (IEN | M0)}, /* CSIPORTB_LANE1Y */ - {CSIPORTB_LANE1X, (IEN | M0)}, /* CSIPORTB_LANE1X */ - {CSIPORTB_LANE2Y, (IEN | M0)}, /* CSIPORTB_LANE2Y */ - {CSIPORTB_LANE2X, (IEN | M0)}, /* CSIPORTB_LANE2X */ - {CSIPORTC_LANE0Y, (IEN | M0)}, /* CSIPORTC_LANE0Y */ - {CSIPORTC_LANE0X, (IEN | M0)}, /* CSIPORTC_LANE0X */ - {CSIPORTC_LANE1Y, (IEN | M0)}, /* CSIPORTC_LANE1Y */ - {CSIPORTC_LANE1X, (IEN | M0)}, /* CSIPORTC_LANE1X */ - {CAM_SHUTTER, (M0)}, /* CAM_SHUTTER */ - {CAM_STROBE, (M0)}, /* CAM_STROBE */ - {CAM_GLOBALRESET, (IEN | M0)}, /* CAM_GLOBALRESET */ - {TIMER11_PWM_EVT, (PTD | M6)}, /* GPIO8_227 */ - {TIMER5_PWM_EVT, (PTD | M6)}, /* GPIO8_228 */ - {TIMER6_PWM_EVT, (PTD | M6)}, /* GPIO8_229 */ - {TIMER8_PWM_EVT, (PTU | M6)}, /* GPIO8_230 */ - {I2C3_SCL, (IEN | M0)}, /* I2C3_SCL */ - {I2C3_SDA, (IEN | M0)}, /* I2C3_SDA */ - {GPIO8_233, (IEN | M2)}, /* TIMER8_PWM_EVT */ - {ABE_CLKS, (IEN | M0)}, /* ABE_CLKS */ - {ABEDMIC_DIN1, (IEN | M0)}, /* ABEDMIC_DIN1 */ - {ABEDMIC_DIN2, (IEN | M0)}, /* ABEDMIC_DIN2 */ - {ABEDMIC_DIN3, (IEN | M0)}, /* ABEDMIC_DIN3 */ - {ABEDMIC_CLK1, (M0)}, /* ABEDMIC_CLK1 */ - {ABEDMIC_CLK2, (IEN | M1)}, /* ABEMCBSP1_FSX */ - {ABEDMIC_CLK3, (M1)}, /* ABEMCBSP1_DX */ - {ABESLIMBUS1_CLOCK, (IEN | M1)}, /* ABEMCBSP1_CLKX */ - {ABESLIMBUS1_DATA, (IEN | M1)}, /* ABEMCBSP1_DR */ - {ABEMCBSP2_DR, (IEN | M0)}, /* ABEMCBSP2_DR */ - {ABEMCBSP2_DX, (M0)}, /* ABEMCBSP2_DX */ - {ABEMCBSP2_FSX, (IEN | M0)}, /* ABEMCBSP2_FSX */ - {ABEMCBSP2_CLKX, (IEN | M0)}, /* ABEMCBSP2_CLKX */ - {ABEMCPDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_UL_DATA */ - {ABEMCPDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_DL_DATA */ - {ABEMCPDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_FRAME */ - {ABEMCPDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_LB_CLK */ - {WLSDIO_CLK, (PTU | IEN | M0)}, /* WLSDIO_CLK */ - {WLSDIO_CMD, (PTU | IEN | M0)}, /* WLSDIO_CMD */ - {WLSDIO_DATA0, (PTU | IEN | M0)}, /* WLSDIO_DATA0*/ - {WLSDIO_DATA1, (PTU | IEN | M0)}, /* WLSDIO_DATA1*/ - {WLSDIO_DATA2, (PTU | IEN | M0)}, /* WLSDIO_DATA2*/ - {WLSDIO_DATA3, (PTU | IEN | M0)}, /* WLSDIO_DATA3*/ - {UART5_RX, (PTU | IEN | M0)}, /* UART5_RX */ - {UART5_TX, (M0)}, /* UART5_TX */ - {UART5_CTS, (PTU | IEN | M0)}, /* UART5_CTS */ - {UART5_RTS, (M0)}, /* UART5_RTS */ - {I2C2_SCL, (IEN | M0)}, /* I2C2_SCL */ - {I2C2_SDA, (IEN | M0)}, /* I2C2_SDA */ - {MCSPI1_CLK, (M6)}, /* GPIO5_140 */ - {MCSPI1_SOMI, (IEN | M6)}, /* GPIO5_141 */ - {MCSPI1_SIMO, (PTD | M6)}, /* GPIO5_142 */ - {MCSPI1_CS0, (PTD | M6)}, /* GPIO5_143 */ - {MCSPI1_CS1, (PTD | IEN | M6)}, /* GPIO5_144 */ - {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */ - {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */ - {PERSLIMBUS2_CLOCK, (PTD | M6)}, /* GPIO5_145 */ - {PERSLIMBUS2_DATA, (PTD | IEN | M6)}, /* GPIO5_146 */ - {UART6_TX, (PTU | IEN | M6)}, /* GPIO5_149 */ - {UART6_RX, (PTU | IEN | M6)}, /* GPIO5_150 */ - {UART6_CTS, (PTU | IEN | M6)}, /* GPIO5_151 */ - {UART6_RTS, (PTU | M0)}, /* UART6_RTS */ - {UART3_CTS_RCTX, (PTU | IEN | M6)}, /* GPIO5_153 */ - {UART3_RTS_IRSD, (PTU | IEN | M1)}, /* HDQ_SIO */ - {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */ - {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */ - -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - -/* - * This pad keeps C2C Module always enabled. - * Putting this in safe mode do not cause the issue. - * C2C driver could enable this mux setting if needed. - */ - {LLIA_WAKEREQIN, (M7)}, /* SAFE MODE */ - {LLIB_WAKEREQIN, (M7)}, /* SAFE MODE */ - {DRM_EMU0, (PTU | IEN | M0)}, /* DRM_EMU0 */ - {DRM_EMU1, (PTU | IEN | M0)}, /* DRM_EMU1 */ - {JTAG_NTRST, (IEN | M0)}, /* JTAG_NTRST */ - {JTAG_TCK, (IEN | M0)}, /* JTAG_TCK */ - {JTAG_RTCK, (M0)}, /* JTAG_RTCK */ - {JTAG_TMSC, (IEN | M0)}, /* JTAG_TMSC */ - {JTAG_TDI, (IEN | M0)}, /* JTAG_TDI */ - {JTAG_TDO, (M0)}, /* JTAG_TDO */ - {FREF_CLK_IOREQ, (IEN | M0)}, /* FREF_CLK_IOREQ */ - {FREF_CLK0_OUT, (M0)}, /* FREF_CLK0_OUT */ - {FREF_CLK1_OUT, (M0)}, /* FREF_CLK1_OUT */ - {FREF_CLK2_OUT, (M0)}, /* FREF_CLK2_OUT */ - {FREF_CLK2_REQ, (PTU | IEN | M6)}, /* GPIO1_WK9 */ - {FREF_CLK1_REQ, (PTD | IEN | M6)}, /* GPIO1_WK8 */ - {SYS_NRESPWRON, (IEN | M0)}, /* SYS_NRESPWRON */ - {SYS_NRESWARM, (PTU | IEN | M0)}, /* SYS_NRESWARM */ - {SYS_PWR_REQ, (M0)}, /* SYS_PWR_REQ */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* SYS_NIRQ1 */ - {SYS_NIRQ2, (PTU | IEN | M0)}, /* SYS_NIRQ2 */ - {SYS_BOOT0, (IEN | M0)}, /* SYS_BOOT0 */ - {SYS_BOOT1, (IEN | M0)}, /* SYS_BOOT1 */ - {SYS_BOOT2, (IEN | M0)}, /* SYS_BOOT2 */ - {SYS_BOOT3, (IEN | M0)}, /* SYS_BOOT3 */ - {SYS_BOOT4, (IEN | M0)}, /* SYS_BOOT4 */ - {SYS_BOOT5, (IEN | M0)}, /* SYS_BOOT5 */ - -}; - #endif /* _EVM4430_MUX_DATA_H */ diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index cda09a9125..5ab6db98ac 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -284,36 +284,6 @@ void set_muxconf_regs_essential(void) sizeof(struct pad_conf_entry)); } -void set_muxconf_regs_non_essential(void) -{ - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential, - sizeof(core_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - if (omap_revision() < OMAP4460_ES1_0) - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential_4430, - sizeof(core_padconf_array_non_essential_4430) / - sizeof(struct pad_conf_entry)); - else - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential_4460, - sizeof(core_padconf_array_non_essential_4460) / - sizeof(struct pad_conf_entry)); - - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential, - sizeof(wkup_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - if (omap_revision() < OMAP4460_ES1_0) - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential_4430, - sizeof(wkup_padconf_array_non_essential_4430) / - sizeof(struct pad_conf_entry)); -} - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h index fb83eac9be..53c7080979 100644 --- a/board/ti/panda/panda_mux_data.h +++ b/board/ti/panda/panda_mux_data.h @@ -84,190 +84,4 @@ const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { }; -const struct pad_conf_entry core_padconf_array_non_essential[] = { - {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ - {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ - {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ - {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ - {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ - {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ - {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ - {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ - {GPMC_A16, (M3)}, /* gpio_40 */ - {GPMC_A17, (PTD | M3)}, /* gpio_41 */ - {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ - {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ - {GPMC_A20, (IEN | M3)}, /* gpio_44 */ - {GPMC_A21, (M3)}, /* gpio_45 */ - {GPMC_A22, (M3)}, /* gpio_46 */ - {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ - {GPMC_A24, (PTD | M3)}, /* gpio_48 */ - {GPMC_A25, (PTD | M3)}, /* gpio_49 */ - {GPMC_NCS0, (M3)}, /* gpio_50 */ - {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ - {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ - {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ - {GPMC_NWP, (M3)}, /* gpio_54 */ - {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ - {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ - {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ - {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ - {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ - {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ - {C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101 */ - {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ - {C2C_DATA14, (M1)}, /* dsi2_te0 */ - {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ - {HDMI_HPD, (M0)}, /* hdmi_hpd */ - {HDMI_CEC, (M0)}, /* hdmi_cec */ - {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ - {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ - {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ - {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ - {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ - {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ - {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ - {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ - {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ - {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ - {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ - {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ - {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ - {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ - {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ - {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ - {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ - {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ - {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ - {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ - {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ - {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ - {ABE_MCBSP1_CLKX, (IEN | M0)}, /* abe_mcbsp1_clkx */ - {ABE_MCBSP1_DR, (IEN | M0)}, /* abe_mcbsp1_dr */ - {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ - {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ - {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ - {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ - {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ - {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ - {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ - {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ - {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ - {ABE_DMIC_DIN2, (PTU | IEN | M3)}, /* gpio_121 */ - {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ - {UART2_CTS, (PTU | IEN | M7)}, /* uart2_cts */ - {UART2_RTS, (M7)}, /* uart2_rts */ - {UART2_RX, (PTU | IEN | M7)}, /* uart2_rx */ - {UART2_TX, (M7)}, /* uart2_tx */ - {HDQ_SIO, (M3)}, /* gpio_127 */ - {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ - {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ - {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ - {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ - {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ - {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ - {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ - {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ - {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ - {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ - {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ - {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ - {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ - {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ - {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ - {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ - {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ - {UART4_RX, (IEN | M0)}, /* uart4_rx */ - {UART4_TX, (M0)}, /* uart4_tx */ - {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ - {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ - {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ - {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ - {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ - {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ - {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ - {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ - {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ - {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ - {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ - {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ - {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ - {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ - {UNIPRO_TX0, (PTD | IEN | M3)}, /* gpio_171 */ - {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ - {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ - {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ - {UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */ - {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ - {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ - {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ - {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ - {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ - {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ - {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ - {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ - {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ - {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ - {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ - {SYS_BOOT1, (M3)}, /* gpio_185 */ - {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ - {SYS_BOOT3, (M3)}, /* gpio_187 */ - {SYS_BOOT4, (M3)}, /* gpio_188 */ - {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ - {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ - {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ - {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ - {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ - {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ - {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ - {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ - {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ - {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ - {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ - {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ - {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ - {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ - {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ - {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ - {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ - {DPM_EMU16, (M3)}, /* gpio_27 */ - {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ - {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ - {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ -}; - -const struct pad_conf_entry core_padconf_array_non_essential_4430[] = { - {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ -}; - -const struct pad_conf_entry core_padconf_array_non_essential_4460[] = { - {ABE_MCBSP2_CLKX, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */ -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ - {PAD1_SIM_CLK, (M0)}, /* sim_clk */ - {PAD0_SIM_RESET, (M0)}, /* sim_reset */ - {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ - {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ - {PAD1_FREF_XTAL_IN, (M0)}, /* # */ - {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ - {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ - {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ - {PAD0_FREF_CLK4_OUT, (PTU | M3)}, /* led status_2 */ - {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ - {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ - {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = { - {PAD1_FREF_CLK4_REQ, (PTU | M3)}, /* led status_1 */ -}; - #endif /* _PANDA_MUX_DATA_H_ */ diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 79270a9e94..1e9ef9e38b 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -73,26 +73,6 @@ void set_muxconf_regs_essential(void) sizeof(struct pad_conf_entry)); } -void set_muxconf_regs_non_essential(void) -{ - do_set_mux((*ctrl)->control_padconf_core_base, - core_padconf_array_non_essential, - sizeof(core_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential, - sizeof(wkup_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - if (omap_revision() < OMAP4460_ES1_0) { - do_set_mux((*ctrl)->control_padconf_wkup_base, - wkup_padconf_array_non_essential_4430, - sizeof(wkup_padconf_array_non_essential_4430) / - sizeof(struct pad_conf_entry)); - } -} - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h index 4394dbaa48..9a9efe7a54 100644 --- a/board/ti/sdp4430/sdp4430_mux_data.h +++ b/board/ti/sdp4430/sdp4430_mux_data.h @@ -65,201 +65,4 @@ const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { }; -const struct pad_conf_entry core_padconf_array_non_essential[] = { - {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ - {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ - {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ - {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ - {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ - {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ - {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ - {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ - {GPMC_A16, (M3)}, /* gpio_40 */ - {GPMC_A17, (PTD | M3)}, /* gpio_41 */ - {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ - {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ - {GPMC_A20, (IEN | M3)}, /* gpio_44 */ - {GPMC_A21, (M3)}, /* gpio_45 */ - {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ - {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ - {GPMC_A24, (PTD | M3)}, /* gpio_48 */ - {GPMC_A25, (PTD | M3)}, /* gpio_49 */ - {GPMC_NCS0, (M3)}, /* gpio_50 */ - {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ - {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ - {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ - {GPMC_NWP, (M3)}, /* gpio_54 */ - {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ - {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ - {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ - {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ - {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ - {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ - {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ - {C2C_DATA12, (M1)}, /* dsi1_te0 */ - {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ - {C2C_DATA14, (M1)}, /* dsi2_te0 */ - {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ - {HDMI_HPD, (M0)}, /* hdmi_hpd */ - {HDMI_CEC, (M0)}, /* hdmi_cec */ - {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ - {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ - {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ - {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ - {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ - {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ - {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ - {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ - {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ - {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ - {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ - {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ - {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ - {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ - {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ - {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ - {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ - {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ - {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ - {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */ - {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */ - {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */ - {USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */ - {USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */ - {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ - {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ - {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ - {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ - {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ - {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ - {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ - {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */ - {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */ - {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ - {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ - {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ - {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ - {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ - {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ - {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ - {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ - {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ - {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ - {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ - {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ - {UART2_RTS, (M0)}, /* uart2_rts */ - {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ - {UART2_TX, (M0)}, /* uart2_tx */ - {HDQ_SIO, (M3)}, /* gpio_127 */ - {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ - {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ - {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ - {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ - {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ - {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ - {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ - {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ - {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ - {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ - {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ - {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ - {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ - {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ - {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ - {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ - {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ - {UART4_RX, (IEN | M0)}, /* uart4_rx */ - {UART4_TX, (M0)}, /* uart4_tx */ - {USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */ - {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ - {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ - {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ - {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ - {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ - {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ - {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ - {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ - {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ - {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ - {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ - {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ - {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ - {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ - {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ - {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ - {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ - {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ - {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ - {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ - {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ - {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ - {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ - {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ - {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ - {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ - {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (M7)}, /* sys_nirq2 */ - {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ - {SYS_BOOT1, (M3)}, /* gpio_185 */ - {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ - {SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */ - {SYS_BOOT4, (M3)}, /* gpio_188 */ - {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ - {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ - {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ - {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ - {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ - {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ - {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ - {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ - {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ - {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ - {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ - {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ - {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ - {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ - {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ - {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ - {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ - {DPM_EMU16, (M3)}, /* gpio_27 */ - {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ - {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ - {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ - {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ - {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ - {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ - {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ - {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ - {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ - {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ - {I2C4_SDA, (PTU | IEN | M0)} /* i2c4_sda */ - -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ - {PAD1_SIM_CLK, (M0)}, /* sim_clk */ - {PAD0_SIM_RESET, (M0)}, /* sim_reset */ - {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ - {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ - {PAD1_FREF_XTAL_IN, (M0)}, /* # */ - {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ - {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ - {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 - Debug led-1 */ - {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ - {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 - Debug led-3 */ - {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ - {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ - {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = { - {PAD1_FREF_CLK4_REQ, (M3)} /* gpio_wk7 - Debug led-2 */ -}; - #endif /* _SDP4430_MUX_DATA_H */ -- cgit v1.2.3 From 0df8afdf107268198e706ce84b71820db3572936 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 19 Dec 2013 10:00:28 +0530 Subject: ARM: AM43xx: Enable DDR dynamic IO power down for DDR3 This patch enables dynamically powering down the IO receiver when not performing a read on DDR3 board. This optimizes both active and standby power consumption. This is derived from a patch that is done on AM335x[1] [1] http://arago-project.org/git/projects/?p=u-boot-am33x.git;a=commit;h=6a9ee4bc72ece53fabf01825605fba3d71d5feb2 Signed-off-by: Lokesh Vutla --- board/ti/am43xx/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index ed87cd97b0..4e6846a50a 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -188,7 +188,7 @@ const struct ctrl_ioregs ioregs_ddr3 = { .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, - .emif_sdram_config_ext = 0x0043, + .emif_sdram_config_ext = 0x0143, }; const struct emif_regs ddr3_emif_regs_400Mhz = { -- cgit v1.2.3 From de351d6be6868270db21ed8a0f89d3ef703bc18e Mon Sep 17 00:00:00 2001 From: Darwin Rambo Date: Thu, 19 Dec 2013 15:06:12 -0800 Subject: lib: time: add weak timer_init() function If timer_init() is made a weak stub function, then it allows us to remove several empty timer_init functions for those boards that already have a timer initialized when u-boot starts. Architectures that use the timer framework may also remove the need for timer.c. Signed-off-by: Darwin Rambo Reviewed-by: Tim Kryger --- arch/arm/cpu/arm1176/bcm2835/timer.c | 5 ----- arch/arm/cpu/sa1100/timer.c | 5 ----- board/armltd/vexpress/vexpress_common.c | 5 ----- board/nvidia/common/board.c | 11 ----------- board/sandbox/sandbox/sandbox.c | 5 ----- lib/time.c | 5 +++++ 6 files changed, 5 insertions(+), 31 deletions(-) (limited to 'board') diff --git a/arch/arm/cpu/arm1176/bcm2835/timer.c b/arch/arm/cpu/arm1176/bcm2835/timer.c index 2edd6711da..017907cfb8 100644 --- a/arch/arm/cpu/arm1176/bcm2835/timer.c +++ b/arch/arm/cpu/arm1176/bcm2835/timer.c @@ -18,11 +18,6 @@ #include #include -int timer_init(void) -{ - return 0; -} - ulong get_timer_us(ulong base) { struct bcm2835_timer_regs *regs = diff --git a/arch/arm/cpu/sa1100/timer.c b/arch/arm/cpu/sa1100/timer.c index 4b981e46e7..0a0006b426 100644 --- a/arch/arm/cpu/sa1100/timer.c +++ b/arch/arm/cpu/sa1100/timer.c @@ -13,11 +13,6 @@ #include #include -int timer_init (void) -{ - return 0; -} - ulong get_timer (ulong base) { return get_timer_masked (); diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index da5cb0152b..cb2de2f4dd 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -119,11 +119,6 @@ void dram_init_banksize(void) get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); } -int timer_init(void) -{ - return 0; -} - /* * Start timer: * Setup a 32 bit timer, running at 1KHz diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 1972527e7d..e650feda48 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -48,17 +48,6 @@ const struct tegra_sysinfo sysinfo = { CONFIG_TEGRA_BOARD_STRING }; -#ifndef CONFIG_SPL_BUILD -/* - * Routine: timer_init - * Description: init the timestamp and lastinc value - */ -int timer_init(void) -{ - return 0; -} -#endif - void __pin_mux_usb(void) { } diff --git a/board/sandbox/sandbox/sandbox.c b/board/sandbox/sandbox/sandbox.c index 65dcce804b..95efaffcb1 100644 --- a/board/sandbox/sandbox/sandbox.c +++ b/board/sandbox/sandbox/sandbox.c @@ -23,11 +23,6 @@ unsigned long timer_read_counter(void) return os_get_nsec() / 1000; } -int timer_init(void) -{ - return 0; -} - int dram_init(void) { gd->ram_size = CONFIG_SYS_SDRAM_SIZE; diff --git a/lib/time.c b/lib/time.c index 8085aa40d1..73c3b6ad7f 100644 --- a/lib/time.c +++ b/lib/time.c @@ -60,6 +60,11 @@ static unsigned long long notrace tick_to_time(uint64_t tick) return tick; } +int __weak timer_init(void) +{ + return 0; +} + ulong __weak get_timer(ulong base) { return tick_to_time(get_ticks()) - base; -- cgit v1.2.3 From d937326ffcd6da4c6ba1297a8786cfeaec1812e7 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 6 Jan 2014 15:39:48 +0900 Subject: Remove obsolete _LINUX_CONFIG_H macro Commit 643aae1406c93ddc64fcf8c136b47cdffd9c8ccd deleted include/linux/config.h but missed to delete _LINUX_CONFIG_H macro. It is no longer used at all. Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/mpc5xx/start.S | 1 - arch/powerpc/cpu/mpc5xxx/start.S | 1 - arch/powerpc/cpu/mpc824x/start.S | 2 -- arch/powerpc/cpu/mpc8260/kgdb.S | 1 - arch/powerpc/cpu/mpc8260/start.S | 1 - arch/powerpc/cpu/mpc83xx/start.S | 1 - arch/powerpc/cpu/mpc85xx/release.S | 2 -- arch/powerpc/cpu/mpc85xx/start.S | 2 -- arch/powerpc/cpu/mpc8xx/kgdb.S | 1 - arch/powerpc/cpu/mpc8xx/start.S | 1 - arch/powerpc/cpu/ppc4xx/dcr.S | 2 -- arch/powerpc/cpu/ppc4xx/kgdb.S | 1 - arch/powerpc/cpu/ppc4xx/start.S | 2 -- board/cray/L1/init.S | 2 -- board/csb272/init.S | 2 -- board/csb472/init.S | 2 -- board/mpl/mip405/init.S | 1 - board/mpl/pip405/init.S | 1 - board/sc3/init.S | 2 -- board/w7o/init.S | 2 -- board/w7o/post1.S | 2 -- include/common.h | 3 --- 22 files changed, 35 deletions(-) (limited to 'board') diff --git a/arch/powerpc/cpu/mpc5xx/start.S b/arch/powerpc/cpu/mpc5xx/start.S index 92f956db8d..22fb27418d 100644 --- a/arch/powerpc/cpu/mpc5xx/start.S +++ b/arch/powerpc/cpu/mpc5xx/start.S @@ -20,7 +20,6 @@ #include #define CONFIG_5xx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include #include diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S index 517b5808fe..84ab41e931 100644 --- a/arch/powerpc/cpu/mpc5xxx/start.S +++ b/arch/powerpc/cpu/mpc5xxx/start.S @@ -15,7 +15,6 @@ #include #define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include #include diff --git a/arch/powerpc/cpu/mpc824x/start.S b/arch/powerpc/cpu/mpc824x/start.S index 6f397a44c6..b1fb062a08 100644 --- a/arch/powerpc/cpu/mpc824x/start.S +++ b/arch/powerpc/cpu/mpc824x/start.S @@ -26,8 +26,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/arch/powerpc/cpu/mpc8260/kgdb.S b/arch/powerpc/cpu/mpc8260/kgdb.S index 5a298f9d05..dd04d6bd6f 100644 --- a/arch/powerpc/cpu/mpc8260/kgdb.S +++ b/arch/powerpc/cpu/mpc8260/kgdb.S @@ -10,7 +10,6 @@ #include #define CONFIG_8260 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include #include diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S index 1269291c45..65510fa760 100644 --- a/arch/powerpc/cpu/mpc8260/start.S +++ b/arch/powerpc/cpu/mpc8260/start.S @@ -15,7 +15,6 @@ #include #define CONFIG_8260 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include #include diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 7f74a50bac..36724e5aa5 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -20,7 +20,6 @@ #include #define CONFIG_83XX 1 /* needed for Linux kernel header files*/ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include #include diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index c15e83b521..fcfba7ec19 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -10,8 +10,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index db84d10c5b..dbbd8e588c 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -17,8 +17,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/arch/powerpc/cpu/mpc8xx/kgdb.S b/arch/powerpc/cpu/mpc8xx/kgdb.S index ea27d59a6c..ac1fe8f4e5 100644 --- a/arch/powerpc/cpu/mpc8xx/kgdb.S +++ b/arch/powerpc/cpu/mpc8xx/kgdb.S @@ -10,7 +10,6 @@ #include #define CONFIG_8xx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include #include diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S index 9869bbd183..99cafbd437 100644 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -27,7 +27,6 @@ #include #define CONFIG_8xx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include #include diff --git a/arch/powerpc/cpu/ppc4xx/dcr.S b/arch/powerpc/cpu/ppc4xx/dcr.S index 0d99391dfb..6b13528c9a 100644 --- a/arch/powerpc/cpu/ppc4xx/dcr.S +++ b/arch/powerpc/cpu/ppc4xx/dcr.S @@ -10,8 +10,6 @@ #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/arch/powerpc/cpu/ppc4xx/kgdb.S b/arch/powerpc/cpu/ppc4xx/kgdb.S index dbc4a6c881..f274c5d564 100644 --- a/arch/powerpc/cpu/ppc4xx/kgdb.S +++ b/arch/powerpc/cpu/ppc4xx/kgdb.S @@ -10,7 +10,6 @@ #include #define CONFIG_405GP 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include #include diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 38bbc5a9bc..e72c37c75b 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -31,8 +31,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S index 44c688d1f0..d4723c733f 100644 --- a/board/cray/L1/init.S +++ b/board/cray/L1/init.S @@ -22,8 +22,6 @@ /*-----------------------------------------------------------------------------#include */ #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/board/csb272/init.S b/board/csb272/init.S index 5961978c86..bf1d98680d 100644 --- a/board/csb272/init.S +++ b/board/csb272/init.S @@ -4,8 +4,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/board/csb472/init.S b/board/csb472/init.S index 1ebc9ead3a..7383a708b0 100644 --- a/board/csb472/init.S +++ b/board/csb472/init.S @@ -4,8 +4,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S index 642f17c35b..2ea2e29c3b 100644 --- a/board/mpl/mip405/init.S +++ b/board/mpl/mip405/init.S @@ -19,7 +19,6 @@ * Bank 6 - not used * Bank 7 - PLD Register *-----------------------------------------------------------------------------*/ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include #include diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S index 95fed34fcc..292393ec43 100644 --- a/board/mpl/pip405/init.S +++ b/board/mpl/pip405/init.S @@ -19,7 +19,6 @@ * Bank 6 - used to switch on the 12V for the Multipurpose socket * Bank 7 - Config Register *-----------------------------------------------------------------------------*/ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include #include diff --git a/board/sc3/init.S b/board/sc3/init.S index 46323d2688..097aa4a5e7 100644 --- a/board/sc3/init.S +++ b/board/sc3/init.S @@ -4,8 +4,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/board/w7o/init.S b/board/w7o/init.S index 54eda3299f..dfde149956 100644 --- a/board/w7o/init.S +++ b/board/w7o/init.S @@ -4,8 +4,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/board/w7o/post1.S b/board/w7o/post1.S index 7a411a4920..aae5387212 100644 --- a/board/w7o/post1.S +++ b/board/w7o/post1.S @@ -13,8 +13,6 @@ #include #include -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include #include diff --git a/include/common.h b/include/common.h index d49c51464d..d5ebb25390 100644 --- a/include/common.h +++ b/include/common.h @@ -8,9 +8,6 @@ #ifndef __COMMON_H_ #define __COMMON_H_ 1 -#undef _LINUX_CONFIG_H -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #ifndef __ASSEMBLY__ /* put C only stuff in this section */ typedef unsigned char uchar; -- cgit v1.2.3 From 853ce2ee9c53b97694804e60450c15d40df9b502 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 8 Jan 2014 20:11:02 +0900 Subject: board: delete unused header files Signed-off-by: Masahiro Yamada Acked-by: Stefan Roese Acked-by: Matthias Fuchs --- board/cogent/kbm.h | 79 ----------------- board/cray/L1/L1.h | 28 ------ board/esd/common/s1d13806_640_480_8bpp.h | 120 ------------------------- board/etin/debris/speed.h | 38 -------- board/genietv/genietv.h | 25 ------ board/hidden_dragon/speed.h | 38 -------- board/inka4x0/hyb25d512160bf-5.h | 16 ---- board/prodrive/p3mx/ppc_error_no.h | 148 ------------------------------- board/sandpoint/speed.h | 38 -------- 9 files changed, 530 deletions(-) delete mode 100644 board/cogent/kbm.h delete mode 100644 board/cray/L1/L1.h delete mode 100644 board/esd/common/s1d13806_640_480_8bpp.h delete mode 100644 board/etin/debris/speed.h delete mode 100644 board/genietv/genietv.h delete mode 100644 board/hidden_dragon/speed.h delete mode 100644 board/inka4x0/hyb25d512160bf-5.h delete mode 100644 board/prodrive/p3mx/ppc_error_no.h delete mode 100644 board/sandpoint/speed.h (limited to 'board') diff --git a/board/cogent/kbm.h b/board/cogent/kbm.h deleted file mode 100644 index 7eb419c1d6..0000000000 --- a/board/cogent/kbm.h +++ /dev/null @@ -1,79 +0,0 @@ -/* keyboard/mouse not implemented yet */ - -extern int cma_kbm_not_implemented; - -/**************** DEFINES for H8542B Keyboard/Mouse Controller ***************/ - -/* - * note the auxillary port is used to control the mouse - */ - -/* 8542B Commands (Sent to the Command Port) */ -#define HT8542_CMD_SET_BYTE 0x60 /* Set the command byte */ -#define HT8542_CMD_GET_BYTE 0x20 /* Get the command byte */ -#define HT8542_CMD_KBD_OBUFF 0xD2 /* Write to HT8542 Kbd Output Buffer */ -#define HT8542_CMD_AUX_OBUFF 0xD3 /* Write to HT8542 Mse Output Buffer */ -#define HT8542_CMD_AUX_WRITE 0xD4 /* Write to Mouse Port */ -#define HT8542_CMD_AUX_OFF 0xA7 /* Disable Mouse Port */ -#define HT8542_CMD_AUX_ON 0xA8 /* Re-Enable Mouse Port */ -#define HT8542_CMD_AUX_TEST 0xA9 /* Test for the presence of a Mouse */ -#define HT8542_CMD_DIAG 0xAA /* Start Diagnostics */ -#define HT8542_CMD_KBD_TEST 0xAB /* Test for presence of a keyboard */ -#define HT8542_CMD_KBD_OFF 0xAD /* Disable Kbd Port (use KBD_DAT_ON) */ -#define HT8542_CMD_KBD_ON 0xAE /* Enable Kbd Port (use KBD_DAT_OFF) */ - -/* HT8542B cmd byte set by KBD_CMD_SET_BYTE and retrieved by KBD_CMD_GET_BYTE */ -#define HT8542_CMD_BYTE_TRANS 0x40 -#define HT8542_CMD_BYTE_AUX_OFF 0x20 /* 1 = mse port disabled, 0 = enabled */ -#define HT8542_CMD_BYTE_KBD_OFF 0x10 /* 1 = kbd port disabled, 0 = enabled */ -#define HT8542_CMD_BYTE_OVER 0x08 /* 1 = override keyboard lock */ -#define HT8542_CMD_BYTE_RES 0x04 /* reserved */ -#define HT8542_CMD_BYTE_AUX_INT 0x02 /* 1 = enable mouse interrupt */ -#define HT8542_CMD_BYTE_KBD_INT 0x01 /* 1 = enable keyboard interrupt */ - -/* Keyboard Commands (Sent to the Data Port) */ -#define KBD_CMD_LED 0xED /* Set Keyboard LEDS with next byte */ -#define KBD_CMD_ECHO 0xEE /* Echo - we get 0xFA, 0xEE back */ -#define KBD_CMD_MODE 0xF0 /* set scan code mode with next byte */ -#define KBD_CMD_ID 0xF2 /* get keyboard/mouse ID */ -#define KBD_CMD_RPT 0xF3 /* Set Repeat Rate and Delay 2nd Byte */ -#define KBD_CMD_ON 0xF4 /* Enable keyboard */ -#define KBD_CMD_OFF 0xF5 /* Disables Scanning, Resets to Def */ -#define KBD_CMD_DEF 0xF6 /* Reverts kbd to default settings */ -#define KBD_CMD_RST 0xFF /* Reset - should get 0xFA, 0xAA back */ - -/* Set LED second bit defines */ -#define KBD_CMD_LED_SCROLL 0x01 /* Set SCROLL LOCK LED on */ -#define KBD_CMD_LED_NUM 0x02 /* Set NUM LOCK LED on */ -#define KBD_CMD_LED_CAPS 0x04 /* Set CAPS LOCK LED on */ - -/* Set Mode second byte defines */ -#define KBD_CMD_MODE_STAT 0x00 /* get current scan code mode */ -#define KBD_CMD_MODE_SCAN1 0x01 /* set mode to scan code 1 */ -#define KBD_CMD_MODE_SCAN2 0x02 /* set mode to scan code 2 */ -#define KBD_CMD_MODE_SCAN3 0x03 /* set mode to scan code 3 */ - -/* Keyboard/Mouse ID Codes */ -#define KBD_CMD_ID_1ST 0xAB /* 1st byte is 0xAB, 2nd is actual ID */ -#define KBD_CMD_ID_KBD 0x83 /* Keyboard */ -#define KBD_CMD_ID_MOUSE 0x00 /* Mouse */ - -/* Keyboard Data Return Defines */ -#define KBD_STAT_OVER 0x00 /* Buffer Overrun */ -#define KBD_STAT_DIAG_OK 0x55 /* Internal Self Test OK */ -#define KBD_STAT_RST_OK 0xAA /* Reset Complete */ -#define KBD_STAT_ECHO 0xEE /* Echo Command Return */ -#define KBD_STAT_BRK 0xF0 /* Prefix for Break Key Code */ -#define KBD_STAT_ACK 0xFA /* Received after all commands */ -#define KBD_STAT_DIAG_FAIL 0xFD /* Internal Self Test Failed */ -#define KBD_STAT_RESEND 0xFE /* Resend Last Command */ - -/* HT8542B Status Register Bit Defines */ -#define HT8542_STAT_OBF 0x01 /* 1 = output buffer is full */ -#define HT8542_STAT_IBF 0x02 /* 1 = input buffer is full */ -#define HT8542_STAT_SYS 0x04 /* system flag - unused */ -#define HT8542_STAT_CMD 0x08 /* 1 = cmd in input buffer, 0 = data */ -#define HT8542_STAT_INH 0x10 /* 1 = Inhibit - unused */ -#define HT8542_STAT_TX 0x20 /* 1 = Transmit Timeout has occured */ -#define HT8542_STAT_RX 0x40 /* 1 = Receive Timeout has occured */ -#define HT8542_STAT_PERR 0x80 /* 1 = Parity Error from Keyboard */ diff --git a/board/cray/L1/L1.h b/board/cray/L1/L1.h deleted file mode 100644 index 42c34dd910..0000000000 --- a/board/cray/L1/L1.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/**************************************************************************** - * FLASH Memory Map as used by CRAY L1, 4MB AMD29F032B flash chip - * - * Start Address Length - * +++++++++++++++++++++++++ 0xFFC0_0000 Start of Flash ----------------- - * | Failsafe Linux Image | (1M) - * +=======================+ 0xFFD0_0000 - * | (Reserved FlashFiles) | (1M) - * +=======================+ 0xFFE0_0000 - * | Failsafe RootFS | (1M) - * +=======================+ 0xFFF0_0000 - * | | - * | U N U S E D | - * | | - * +-----------------------+ 0xFFFD_0000 U-Boot image header (64 bytes) - * | environment settings | (64k) - * +-----------------------+ 0xFFFE_0000 U-Boot image header (64 bytes) - * | U-Boot | 0xFFFE_0040 _start of U-Boot - * | | 0xFFFE_FFFC reset vector - branch to _start - * +++++++++++++++++++++++++ 0xFFFF_FFFF End of Flash ----------------- - *****************************************************************************/ diff --git a/board/esd/common/s1d13806_640_480_8bpp.h b/board/esd/common/s1d13806_640_480_8bpp.h deleted file mode 100644 index ddc0289b2e..0000000000 --- a/board/esd/common/s1d13806_640_480_8bpp.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2000,2001 Epson Research and Development, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * File generated by S1D13806CFG.EXE - * Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz) - * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz) - */ - -static S1D_REGS regs_13806_640_320_16bpp[] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x18}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0x18}, /* General IO Pins Control Register 0 */ - {0x0009,0x00}, /* General IO Pins Control Register 1 */ - {0x0010,0x00}, /* Memory Clock Configuration Register */ - {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x03}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x25}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x00}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x24}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x03}, /* LCD Display Mode Register (8bpp) */ - {0x0041,0x00}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x10}, /* TV Output Control Register */ - {0x0060,0x05}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ -}; diff --git a/board/etin/debris/speed.h b/board/etin/debris/speed.h deleted file mode 100644 index f1b10bf25e..0000000000 --- a/board/etin/debris/speed.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*----------------------------------------------------------------------- - * Timer value for timer 2, ICLK = 10 - * - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 - * - * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock - * SPEED_TMR2_PS prescaler - */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ - -/*----------------------------------------------------------------------- - * Timer value for PIT - * - * PIT_TIME = SPEED_PITC / PITRTCLK - * PITRTCLK = 8192 - */ -#define SPEED_PITC (82 << 16) /* start counting from 82 */ - -/* - * The new value for PTA is calculated from - * - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) - * - * gclk CPU clock (not bus clock !) - * Trefresh Refresh cycle * 4 (four word bursts used) - * DFBRG For normal mode (no clock reduction) always 0 - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) - * NCS Number of SDRAM banks (chip selects) on this UPM. - */ diff --git a/board/genietv/genietv.h b/board/genietv/genietv.h deleted file mode 100644 index 7c95b566f9..0000000000 --- a/board/genietv/genietv.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * The GENIETV is using the following physical memorymap (copied from - * the FADS configuration): - * - * ff020000 -> ff02ffff : pcmcia - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM - * ff000000 -> ff00ffff : IMAP internal in the cpu - * 02800000 -> 0287ffff : flash connected to CS0 - * 00000000 -> nnnnnnnn : sdram setup by U-Boot - * - * CS pins are connected as follows: - * - * CS0 -512Kb boot flash - * CS1 - SDRAM #1 - * CS2 - SDRAM #2 - * CS3 - Flash #1 - * CS4 - Flash #2 - * CS5 - LON (if present) - * CS6 - PCMCIA #1 - * CS7 - PCMCIA #2 - * - * Ports are configured as follows: - * - * PA7 - SDRAM banks enable - */ diff --git a/board/hidden_dragon/speed.h b/board/hidden_dragon/speed.h deleted file mode 100644 index f1b10bf25e..0000000000 --- a/board/hidden_dragon/speed.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*----------------------------------------------------------------------- - * Timer value for timer 2, ICLK = 10 - * - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 - * - * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock - * SPEED_TMR2_PS prescaler - */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ - -/*----------------------------------------------------------------------- - * Timer value for PIT - * - * PIT_TIME = SPEED_PITC / PITRTCLK - * PITRTCLK = 8192 - */ -#define SPEED_PITC (82 << 16) /* start counting from 82 */ - -/* - * The new value for PTA is calculated from - * - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) - * - * gclk CPU clock (not bus clock !) - * Trefresh Refresh cycle * 4 (four word bursts used) - * DFBRG For normal mode (no clock reduction) always 0 - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) - * NCS Number of SDRAM banks (chip selects) on this UPM. - */ diff --git a/board/inka4x0/hyb25d512160bf-5.h b/board/inka4x0/hyb25d512160bf-5.h deleted file mode 100644 index f16f450d01..0000000000 --- a/board/inka4x0/hyb25d512160bf-5.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2007 Semihalf - * Written by Marian Balakowicz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714F0F00 -#define SDRAM_CONFIG1 0x73711930 -#define SDRAM_CONFIG2 0x46770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/prodrive/p3mx/ppc_error_no.h b/board/prodrive/p3mx/ppc_error_no.h deleted file mode 100644 index 58a68b5d89..0000000000 --- a/board/prodrive/p3mx/ppc_error_no.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * BK Id: SCCS/s.errno.h 1.9 06/05/01 21:45:21 paulus - */ -#ifndef _MV_PPC_ERRNO_H -#define _MV_PPC_ERRNO_H - -#define EPERM 1 /* Operation not permitted */ -#define ENOENT 2 /* No such file or directory */ -#define ESRCH 3 /* No such process */ -#define EINTR 4 /* Interrupted system call */ -#define EIO 5 /* I/O error */ -#define ENXIO 6 /* No such device or address */ -#define E2BIG 7 /* Arg list too long */ -#define ENOEXEC 8 /* Exec format error */ -#define EBADF 9 /* Bad file number */ -#define ECHILD 10 /* No child processes */ -#define EAGAIN 11 /* Try again */ -#define ENOMEM 12 /* Out of memory */ -#define EACCES 13 /* Permission denied */ -#define EFAULT 14 /* Bad address */ -#define ENOTBLK 15 /* Block device required */ -#define EBUSY 16 /* Device or resource busy */ -#define EEXIST 17 /* File exists */ -#define EXDEV 18 /* Cross-device link */ -#define ENODEV 19 /* No such device */ -#define ENOTDIR 20 /* Not a directory */ -#define EISDIR 21 /* Is a directory */ -#define EINVAL 22 /* Invalid argument */ -#define ENFILE 23 /* File table overflow */ -#define EMFILE 24 /* Too many open files */ -#define ENOTTY 25 /* Not a typewriter */ -#define ETXTBSY 26 /* Text file busy */ -#define EFBIG 27 /* File too large */ -#define ENOSPC 28 /* No space left on device */ -#define ESPIPE 29 /* Illegal seek */ -#define EROFS 30 /* Read-only file system */ -#define EMLINK 31 /* Too many links */ -#define EPIPE 32 /* Broken pipe */ -#define EDOM 33 /* Math argument out of domain of func */ -#define ERANGE 34 /* Math result not representable */ -#define EDEADLK 35 /* Resource deadlock would occur */ -#define ENAMETOOLONG 36 /* File name too long */ -#define ENOLCK 37 /* No record locks available */ -#define ENOSYS 38 /* Function not implemented */ -#define ENOTEMPTY 39 /* Directory not empty */ -#define ELOOP 40 /* Too many symbolic links encountered */ -#define EWOULDBLOCK EAGAIN /* Operation would block */ -#define ENOMSG 42 /* No message of desired type */ -#define EIDRM 43 /* Identifier removed */ -#define ECHRNG 44 /* Channel number out of range */ -#define EL2NSYNC 45 /* Level 2 not synchronized */ -#define EL3HLT 46 /* Level 3 halted */ -#define EL3RST 47 /* Level 3 reset */ -#define ELNRNG 48 /* Link number out of range */ -#define EUNATCH 49 /* Protocol driver not attached */ -#define ENOCSI 50 /* No CSI structure available */ -#define EL2HLT 51 /* Level 2 halted */ -#define EBADE 52 /* Invalid exchange */ -#define EBADR 53 /* Invalid request descriptor */ -#define EXFULL 54 /* Exchange full */ -#define ENOANO 55 /* No anode */ -#define EBADRQC 56 /* Invalid request code */ -#define EBADSLT 57 /* Invalid slot */ -#define EDEADLOCK 58 /* File locking deadlock error */ -#define EBFONT 59 /* Bad font file format */ -#define ENOSTR 60 /* Device not a stream */ -#define ENODATA 61 /* No data available */ -#define ETIME 62 /* Timer expired */ -#define ENOSR 63 /* Out of streams resources */ -#define ENONET 64 /* Machine is not on the network */ -#define ENOPKG 65 /* Package not installed */ -#define EREMOTE 66 /* Object is remote */ -#define ENOLINK 67 /* Link has been severed */ -#define EADV 68 /* Advertise error */ -#define ESRMNT 69 /* Srmount error */ -#define ECOMM 70 /* Communication error on send */ -#define EPROTO 71 /* Protocol error */ -#define EMULTIHOP 72 /* Multihop attempted */ -#define EDOTDOT 73 /* RFS specific error */ -#define EBADMSG 74 /* Not a data message */ -#define EOVERFLOW 75 /* Value too large for defined data type */ -#define ENOTUNIQ 76 /* Name not unique on network */ -#define EBADFD 77 /* File descriptor in bad state */ -#define EREMCHG 78 /* Remote address changed */ -#define ELIBACC 79 /* Can not access a needed shared library */ -#define ELIBBAD 80 /* Accessing a corrupted shared library */ -#define ELIBSCN 81 /* .lib section in a.out corrupted */ -#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ -#define ELIBEXEC 83 /* Cannot exec a shared library directly */ -#define EILSEQ 84 /* Illegal byte sequence */ -#define ERESTART 85 /* Interrupted system call should be restarted */ -#define ESTRPIPE 86 /* Streams pipe error */ -#define EUSERS 87 /* Too many users */ -#define ENOTSOCK 88 /* Socket operation on non-socket */ -#define EDESTADDRREQ 89 /* Destination address required */ -#define EMSGSIZE 90 /* Message too long */ -#define EPROTOTYPE 91 /* Protocol wrong type for socket */ -#define ENOPROTOOPT 92 /* Protocol not available */ -#define EPROTONOSUPPORT 93 /* Protocol not supported */ -#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ -#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ -#define EPFNOSUPPORT 96 /* Protocol family not supported */ -#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ -#define EADDRINUSE 98 /* Address already in use */ -#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ -#define ENETDOWN 100 /* Network is down */ -#define ENETUNREACH 101 /* Network is unreachable */ -#define ENETRESET 102 /* Network dropped connection because of reset */ -#define ECONNABORTED 103 /* Software caused connection abort */ -#define ECONNRESET 104 /* Connection reset by peer */ -#define ENOBUFS 105 /* No buffer space available */ -#define EISCONN 106 /* Transport endpoint is already connected */ -#define ENOTCONN 107 /* Transport endpoint is not connected */ -#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ -#define ETOOMANYREFS 109 /* Too many references: cannot splice */ -#define ETIMEDOUT 110 /* Connection timed out */ -#define ECONNREFUSED 111 /* Connection refused */ -#define EHOSTDOWN 112 /* Host is down */ -#define EHOSTUNREACH 113 /* No route to host */ -#define EALREADY 114 /* Operation already in progress */ -#define EINPROGRESS 115 /* Operation now in progress */ -#define ESTALE 116 /* Stale NFS file handle */ -#define EUCLEAN 117 /* Structure needs cleaning */ -#define ENOTNAM 118 /* Not a XENIX named type file */ -#define ENAVAIL 119 /* No XENIX semaphores available */ -#define EISNAM 120 /* Is a named type file */ -#define EREMOTEIO 121 /* Remote I/O error */ -#define EDQUOT 122 /* Quota exceeded */ - -#define ENOMEDIUM 123 /* No medium found */ -#define EMEDIUMTYPE 124 /* Wrong medium type */ - -/* Should never be seen by user programs */ -#define ERESTARTSYS 512 -#define ERESTARTNOINTR 513 -#define ERESTARTNOHAND 514 /* restart if no handler.. */ -#define ENOIOCTLCMD 515 /* No ioctl command */ - -#define _LAST_ERRNO 515 - -#endif diff --git a/board/sandpoint/speed.h b/board/sandpoint/speed.h deleted file mode 100644 index f1b10bf25e..0000000000 --- a/board/sandpoint/speed.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*----------------------------------------------------------------------- - * Timer value for timer 2, ICLK = 10 - * - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 - * - * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock - * SPEED_TMR2_PS prescaler - */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ - -/*----------------------------------------------------------------------- - * Timer value for PIT - * - * PIT_TIME = SPEED_PITC / PITRTCLK - * PITRTCLK = 8192 - */ -#define SPEED_PITC (82 << 16) /* start counting from 82 */ - -/* - * The new value for PTA is calculated from - * - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) - * - * gclk CPU clock (not bus clock !) - * Trefresh Refresh cycle * 4 (four word bursts used) - * DFBRG For normal mode (no clock reduction) always 0 - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) - * NCS Number of SDRAM banks (chip selects) on this UPM. - */ -- cgit v1.2.3 From c4928c34b0de43e507f6e7287faff1bf02d8427c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 14 Jan 2014 10:55:02 +0900 Subject: board: tec-ng: Do not make directories in a board Makefile Commit e5c5301f refactored the build system not to make directories in board makefiles. But commit 8f380381 create directories again in board/avionic-design/tec-ng/Makefile. Signed-off-by: Masahiro Yamada Cc: Alban Bedel --- board/avionic-design/tec-ng/Makefile | 2 -- 1 file changed, 2 deletions(-) (limited to 'board') diff --git a/board/avionic-design/tec-ng/Makefile b/board/avionic-design/tec-ng/Makefile index f41eb30723..79d8602626 100644 --- a/board/avionic-design/tec-ng/Makefile +++ b/board/avionic-design/tec-ng/Makefile @@ -5,8 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) - obj-y := ../common/tamonten-ng.o include ../../nvidia/common/common.mk -- cgit v1.2.3 From bc0009ebc639d33e15b38b55204cd1532cd5a6c0 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 15 Jan 2014 18:00:25 +0900 Subject: board: delete meaningless serial.h Delete some serial.h files, whole code in which is surrounded by #if 0 ... #endif Signed-off-by: Masahiro Yamada Acked-by: Stefan Roese --- board/Marvell/common/serial.c | 1 - board/Marvell/common/serial.h | 73 ------------------------------------------- board/esd/cpci750/serial.c | 1 - board/esd/cpci750/serial.h | 73 ------------------------------------------- board/evb64260/serial.c | 2 -- board/evb64260/serial.h | 63 ------------------------------------- board/prodrive/p3mx/serial.c | 1 - board/prodrive/p3mx/serial.h | 73 ------------------------------------------- 8 files changed, 287 deletions(-) delete mode 100644 board/Marvell/common/serial.h delete mode 100644 board/esd/cpci750/serial.h delete mode 100644 board/evb64260/serial.h delete mode 100644 board/prodrive/p3mx/serial.h (limited to 'board') diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c index 56ba0daa05..752492fc7d 100644 --- a/board/Marvell/common/serial.c +++ b/board/Marvell/common/serial.c @@ -20,7 +20,6 @@ #include #include "../include/memory.h" -#include "serial.h" #ifdef CONFIG_DB64360 #include "../db64360/mpsc.h" diff --git a/board/Marvell/common/serial.h b/board/Marvell/common/serial.h deleted file mode 100644 index 264e2d236e..0000000000 --- a/board/Marvell/common/serial.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * modified for marvell db64360 eval board by - * Ingo Assmus - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* serial.h - mostly useful for DUART serial_init in serial.c */ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - -#if 0 - -#define B230400 1 -#define B115200 2 -#define B57600 4 -#define B38400 82 -#define B19200 163 -#define B9600 24 -#define B4800 651 -#define B2400 1302 -#define B1200 2604 -#define B600 5208 -#define B300 10417 -#define B150 20833 -#define B110 28409 -#define BDEFAULT B115200 - - /* this stuff is important to initialize - the DUART channels */ - -#define Scale 0x01L /* distance between port addresses */ -#define COM1 0x000003f8 /* Keyboard */ -#define COM2 0x000002f8 /* Host */ - - -/* Port Definitions relative to base COM port addresses */ -#define DataIn (0x00*Scale) /* data input port */ -#define DataOut (0x00*Scale) /* data output port */ -#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ -#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ -#define Ier (0x01*Scale) /* interrupt enable register */ -#define Iir (0x02*Scale) /* interrupt identification register */ -#define Lcr (0x03*Scale) /* line control register */ -#define Mcr (0x04*Scale) /* modem control register */ -#define Lsr (0x05*Scale) /* line status register */ -#define Msr (0x06*Scale) /* modem status register */ - -/* Bit Definitions for above ports */ -#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ -#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ - -#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ -#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ -#define McrDflt (McrRts|McrDtr) - -#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ - /* b6: transmitter empty */ -#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ - -#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ -#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ -#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ - -#define IerRda 0xf /* b0: Enable received data available interrupt */ - -#endif - -#endif /* __SERIAL_H__ */ diff --git a/board/esd/cpci750/serial.c b/board/esd/cpci750/serial.c index f42510545c..6c2cf215ac 100644 --- a/board/esd/cpci750/serial.c +++ b/board/esd/cpci750/serial.c @@ -23,7 +23,6 @@ #include #include "../../Marvell/include/memory.h" -#include "serial.h" #include "mpsc.h" diff --git a/board/esd/cpci750/serial.h b/board/esd/cpci750/serial.h deleted file mode 100644 index 264e2d236e..0000000000 --- a/board/esd/cpci750/serial.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * modified for marvell db64360 eval board by - * Ingo Assmus - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* serial.h - mostly useful for DUART serial_init in serial.c */ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - -#if 0 - -#define B230400 1 -#define B115200 2 -#define B57600 4 -#define B38400 82 -#define B19200 163 -#define B9600 24 -#define B4800 651 -#define B2400 1302 -#define B1200 2604 -#define B600 5208 -#define B300 10417 -#define B150 20833 -#define B110 28409 -#define BDEFAULT B115200 - - /* this stuff is important to initialize - the DUART channels */ - -#define Scale 0x01L /* distance between port addresses */ -#define COM1 0x000003f8 /* Keyboard */ -#define COM2 0x000002f8 /* Host */ - - -/* Port Definitions relative to base COM port addresses */ -#define DataIn (0x00*Scale) /* data input port */ -#define DataOut (0x00*Scale) /* data output port */ -#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ -#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ -#define Ier (0x01*Scale) /* interrupt enable register */ -#define Iir (0x02*Scale) /* interrupt identification register */ -#define Lcr (0x03*Scale) /* line control register */ -#define Mcr (0x04*Scale) /* modem control register */ -#define Lsr (0x05*Scale) /* line status register */ -#define Msr (0x06*Scale) /* modem status register */ - -/* Bit Definitions for above ports */ -#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ -#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ - -#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ -#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ -#define McrDflt (McrRts|McrDtr) - -#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ - /* b6: transmitter empty */ -#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ - -#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ -#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ -#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ - -#define IerRda 0xf /* b0: Enable received data available interrupt */ - -#endif - -#endif /* __SERIAL_H__ */ diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c index 3081fad21a..83a421708b 100644 --- a/board/evb64260/serial.c +++ b/board/evb64260/serial.c @@ -21,8 +21,6 @@ #include #endif -#include "serial.h" - #include "mpsc.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/evb64260/serial.h b/board/evb64260/serial.h deleted file mode 100644 index bac9253852..0000000000 --- a/board/evb64260/serial.h +++ /dev/null @@ -1,63 +0,0 @@ -/* serial.h - mostly useful for DUART serial_init in serial.c */ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - -#if 0 - -#define B230400 1 -#define B115200 2 -#define B57600 4 -#define B38400 82 -#define B19200 163 -#define B9600 24 -#define B4800 651 -#define B2400 1302 -#define B1200 2604 -#define B600 5208 -#define B300 10417 -#define B150 20833 -#define B110 28409 -#define BDEFAULT B115200 - - /* this stuff is important to initialize - the DUART channels */ - -#define Scale 0x01L /* distance between port addresses */ -#define COM1 0x000003f8 /* Keyboard */ -#define COM2 0x000002f8 /* Host */ - - -/* Port Definitions relative to base COM port addresses */ -#define DataIn (0x00*Scale) /* data input port */ -#define DataOut (0x00*Scale) /* data output port */ -#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ -#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ -#define Ier (0x01*Scale) /* interrupt enable register */ -#define Iir (0x02*Scale) /* interrupt identification register */ -#define Lcr (0x03*Scale) /* line control register */ -#define Mcr (0x04*Scale) /* modem control register */ -#define Lsr (0x05*Scale) /* line status register */ -#define Msr (0x06*Scale) /* modem status register */ - -/* Bit Definitions for above ports */ -#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ -#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ - -#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ -#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ -#define McrDflt (McrRts|McrDtr) - -#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ - /* b6: transmitter empty */ -#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ - -#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ -#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ -#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ - -#define IerRda 0xf /* b0: Enable received data available interrupt */ - -#endif - -#endif /* __SERIAL_H__ */ diff --git a/board/prodrive/p3mx/serial.c b/board/prodrive/p3mx/serial.c index 89040a899e..5b7b989860 100644 --- a/board/prodrive/p3mx/serial.c +++ b/board/prodrive/p3mx/serial.c @@ -23,7 +23,6 @@ #include #include "../../Marvell/include/memory.h" -#include "serial.h" #include "mpsc.h" diff --git a/board/prodrive/p3mx/serial.h b/board/prodrive/p3mx/serial.h deleted file mode 100644 index 264e2d236e..0000000000 --- a/board/prodrive/p3mx/serial.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * modified for marvell db64360 eval board by - * Ingo Assmus - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* serial.h - mostly useful for DUART serial_init in serial.c */ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - -#if 0 - -#define B230400 1 -#define B115200 2 -#define B57600 4 -#define B38400 82 -#define B19200 163 -#define B9600 24 -#define B4800 651 -#define B2400 1302 -#define B1200 2604 -#define B600 5208 -#define B300 10417 -#define B150 20833 -#define B110 28409 -#define BDEFAULT B115200 - - /* this stuff is important to initialize - the DUART channels */ - -#define Scale 0x01L /* distance between port addresses */ -#define COM1 0x000003f8 /* Keyboard */ -#define COM2 0x000002f8 /* Host */ - - -/* Port Definitions relative to base COM port addresses */ -#define DataIn (0x00*Scale) /* data input port */ -#define DataOut (0x00*Scale) /* data output port */ -#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ -#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ -#define Ier (0x01*Scale) /* interrupt enable register */ -#define Iir (0x02*Scale) /* interrupt identification register */ -#define Lcr (0x03*Scale) /* line control register */ -#define Mcr (0x04*Scale) /* modem control register */ -#define Lsr (0x05*Scale) /* line status register */ -#define Msr (0x06*Scale) /* modem status register */ - -/* Bit Definitions for above ports */ -#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ -#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ - -#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ -#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ -#define McrDflt (McrRts|McrDtr) - -#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ - /* b6: transmitter empty */ -#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ - -#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ -#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ -#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ - -#define IerRda 0xf /* b0: Enable received data available interrupt */ - -#endif - -#endif /* __SERIAL_H__ */ -- cgit v1.2.3