From 6466b95e7c94a48d8f8093b0a765fd51ab6e84ae Mon Sep 17 00:00:00 2001 From: Camelia Groza Date: Thu, 29 Jul 2021 19:31:20 +0300 Subject: board: freescale: t208xrdb: enable Power-On Reset for rev D boards Starting with board revision D, the MISCCSR CPLD register needs to be configured to enable Power-on Reset for software reset commands. Signed-off-by: Camelia Groza Reviewed-by: Priyanka Jain --- board/freescale/t208xrdb/cpld.h | 4 ++++ board/freescale/t208xrdb/t208xrdb.c | 7 +++++++ 2 files changed, 11 insertions(+) (limited to 'board') diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h index a623b1811f..3139c2b85f 100644 --- a/board/freescale/t208xrdb/cpld.h +++ b/board/freescale/t208xrdb/cpld.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor + * Copyright 2021 NXP */ /* @@ -42,3 +43,6 @@ void cpld_write(unsigned int reg, u8 value); /* RSTCON Register */ #define CPLD_RSTCON_EDC_RST 0x04 + +/* MISCCSR Register */ +#define CPLD_MISC_POR_EN 0x30 diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index 1f0cdee0b8..947dd6aa9f 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -128,6 +128,13 @@ int misc_init_r(void) reg |= CPLD_RSTCON_EDC_RST; CPLD_WRITE(reset_ctl, reg); + /* Enable POR for boards revisions D and up */ + if (get_hw_revision() >= 'D') { + reg = CPLD_READ(misc_csr); + reg |= CPLD_MISC_POR_EN; + CPLD_WRITE(misc_csr, reg); + } + return 0; } -- cgit v1.2.3 From 0dfa9da277a4556f9e7faa0101c7694fe2b78733 Mon Sep 17 00:00:00 2001 From: Kshitiz Varshney Date: Sun, 1 Aug 2021 14:31:45 +0200 Subject: board: fsl_validate: Fix resource leak issue Free dynamically allocated memory before every return statement in calc_img_key_hash() and calc_esbchdr_esbc_hash() function. Verified the secure boot changes using ls1046afrwy board. Signed-off-by: Kshitiz Varshney Reviewed-by: Priyanka Jain --- board/freescale/common/fsl_validate.c | 36 ++++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) (limited to 'board') diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 066aa9a7c3..c90afe2e21 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #include @@ -498,8 +499,11 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv *img) return ret; ret = algo->hash_init(algo, &ctx); - if (ret) + if (ret) { + if (ctx) + free(ctx); return ret; + } /* Update hash for ESBC key */ #ifdef CONFIG_KEY_REVOCATION @@ -518,8 +522,11 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv *img) /* Copy hash at destination buffer */ ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size); - if (ret) + if (ret) { + if (ctx) + free(ctx); return ret; + } for (i = 0; i < SHA256_BYTES; i++) img->img_key_hash[i] = hash_val[i]; @@ -547,14 +554,18 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) ret = algo->hash_init(algo, &ctx); /* Copy hash at destination buffer */ - if (ret) + if (ret) { + free(ctx); return ret; + } /* Update hash for CSF Header */ ret = algo->hash_update(algo, ctx, (u8 *)&img->hdr, sizeof(struct fsl_secboot_img_hdr), 0); - if (ret) + if (ret) { + free(ctx); return ret; + } /* Update the hash with that of srk table if srk flag is 1 * If IE Table is selected, key is not added in the hash @@ -581,22 +592,29 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) key_hash = 1; } #endif - if (ret) + if (ret) { + free(ctx); return ret; - if (!key_hash) + } + if (!key_hash) { + free(ctx); return ERROR_KEY_TABLE_NOT_FOUND; + } /* Update hash for actual Image */ ret = algo->hash_update(algo, ctx, (u8 *)(*(img->img_addr_ptr)), img->img_size, 1); - if (ret) + if (ret) { + free(ctx); return ret; + } /* Copy hash at destination buffer */ ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size); - if (ret) + if (ret) { + free(ctx); return ret; - + } return 0; } -- cgit v1.2.3 From 961928397f75a5099740519d79ef594eeec87238 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Tue, 10 Aug 2021 11:20:09 +0530 Subject: board: ls2088ardb: Extend cs4340_get_fw_addr() functionality LS2088A-RDB supports TFA boot source and has 2 nor banks(default and altbank) and QSPI as boot source. The corresponding defconfig can only have one entry defined and therefore, extend cs4340_get_fw_addr() function to overwrite firmware address which will be later used in cortina firmware. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- board/freescale/ls2080ardb/ls2080ardb.c | 38 +++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'board') diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 6504cf768f..e8722f20c1 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -33,6 +33,9 @@ #endif #include "../common/vid.h" +#define CORTINA_FW_ADDR_IFCNOR 0x580980000 +#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0x584980000 +#define CORTINA_FW_ADDR_QSPI 0x980000 #define PIN_MUX_SEL_SDHC 0x00 #define PIN_MUX_SEL_DSPI 0x0a @@ -235,6 +238,41 @@ int config_board_mux(int ctrl_type) return 0; } +ulong *cs4340_get_fw_addr(void) +{ +#ifdef CONFIG_TFABOOT + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 svr = gur_in32(&gur->svr); +#endif + ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR; + +#ifdef CONFIG_TFABOOT + /* LS2088A TFA boot */ + if (SVR_SOC_VER(svr) == SVR_LS2088A) { + enum boot_src src = get_boot_src(); + u8 sw; + + switch (src) { + case BOOT_SOURCE_IFC_NOR: + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & 0x0f); + if (sw == 0) + cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR; + else if (sw == 4) + cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK; + break; + case BOOT_SOURCE_QSPI_NOR: + /* Only one bank in QSPI */ + cortina_fw_addr = CORTINA_FW_ADDR_QSPI; + break; + default: + printf("WARNING: Boot source not found\n"); + } + } +#endif + return (ulong *)cortina_fw_addr; +} + int board_init(void) { #ifdef CONFIG_FSL_MC_ENET -- cgit v1.2.3 From 8ae83cc5af56abe3334dbe48e03407f7ff641c24 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Tue, 10 Aug 2021 11:20:10 +0530 Subject: board: t208x: Extend cs4340_get_fw_addr() functionality T2080RDB supports booting from 2 nor banks(default and altbank). The corresponding defconfig can only have one entry defined and therefore, extend cs4340_get_fw_addr() function to overwrite firmware address which will be later used in cortina firmware. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- board/freescale/t208xrdb/t208xrdb.c | 20 ++++++++++++++++++++ board/freescale/t208xrdb/t208xrdb.h | 3 +++ 2 files changed, 23 insertions(+) (limited to 'board') diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index 947dd6aa9f..73ebb4a55b 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -165,3 +165,23 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } + +ulong *cs4340_get_fw_addr(void) +{ + ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR; + +#ifdef CONFIG_SYS_CORTINA_FW_IN_NOR + u8 reg; + + reg = CPLD_READ(flash_csr); + if (!(reg & CPLD_BOOT_SEL)) { + reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); + if (reg == 0) + cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR; + else if (reg == 4) + cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK; + } +#endif + + return (ulong *)cortina_fw_addr; +} diff --git a/board/freescale/t208xrdb/t208xrdb.h b/board/freescale/t208xrdb/t208xrdb.h index edbc860c9d..26998898e8 100644 --- a/board/freescale/t208xrdb/t208xrdb.h +++ b/board/freescale/t208xrdb/t208xrdb.h @@ -7,6 +7,9 @@ #ifndef __CORENET_DS_H__ #define __CORENET_DS_H__ +#define CORTINA_FW_ADDR_IFCNOR 0xefe00000 +#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebe00000 + void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); void fdt_fixup_board_fman_ethernet(void *blob); -- cgit v1.2.3 From 3bd5ea566eeec9373c7413d383f02096f5f9aaa4 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Tue, 10 Aug 2021 11:20:11 +0530 Subject: board: T4240rdb: Extend cs4340_get_fw_addr() functionality T4240RDB supports booting from 2 nor banks(default and altbank). The corresponding defconfig can only have one entry defined and therefore, extend cs4340_get_fw_addr() function to overwrite firmware address which will be later used in cortina firmware. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- board/freescale/t4rdb/t4240rdb.c | 19 +++++++++++++++++++ board/freescale/t4rdb/t4rdb.h | 3 +++ 2 files changed, 22 insertions(+) (limited to 'board') diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c index 6ab35ca918..20ce7523e5 100644 --- a/board/freescale/t4rdb/t4240rdb.c +++ b/board/freescale/t4rdb/t4240rdb.c @@ -151,3 +151,22 @@ void board_detail(void) break; } } + +ulong *cs4340_get_fw_addr(void) +{ + ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR; + +#ifdef CONFIG_SYS_CORTINA_FW_IN_NOR + u8 sw; + + sw = CPLD_READ(vbank); + sw = sw & CPLD_BANK_SEL_MASK; + + if (sw == 0) + cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR; + else if (sw == 4) + cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK; +#endif + + return (ulong *)cortina_fw_addr; +} diff --git a/board/freescale/t4rdb/t4rdb.h b/board/freescale/t4rdb/t4rdb.h index 3f1fa7bbd2..06779f552f 100644 --- a/board/freescale/t4rdb/t4rdb.h +++ b/board/freescale/t4rdb/t4rdb.h @@ -11,6 +11,9 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM2_DTSEC 4 +#define CORTINA_FW_ADDR_IFCNOR 0xefe00000 +#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebf00000 + void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); -- cgit v1.2.3