From 26e054c943a7348904a8b432fc9a85185b0861c7 Mon Sep 17 00:00:00 2001
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Mon, 5 Aug 2019 15:54:59 +0530
Subject: arm64: versal: fpga: Add PL bit stream load support

This patch adds PL bitstream load support for Versal platform. The PL
bitstream is loaded by making an SMC to ATF which in turn communicates
with platform firmware which configures and loads PL bitstream on to PL.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 board/xilinx/versal/board.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'board')

diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index b5ddd0c5ad..a2b00aa0b6 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -11,13 +11,23 @@
 #include <asm/arch/hardware.h>
 #include <dm/device.h>
 #include <dm/uclass.h>
+#include <versalpl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_FPGA_VERSALPL)
+static xilinx_desc versalpl = XILINX_VERSAL_DESC;
+#endif
+
 int board_init(void)
 {
 	printf("EL Level:\tEL%d\n", current_el());
 
+#if defined(CONFIG_FPGA_VERSALPL)
+	fpga_init();
+	fpga_add(fpga_xilinx, &versalpl);
+#endif
+
 	return 0;
 }
 
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