From 5668c75ce97d9209d4a0d193b16791a100cc99a8 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Tue, 14 Feb 2023 19:35:34 +0200 Subject: board: tegra30: switch to updated pre-dm i2c write Configure PMIC voltages for early stages using updated early i2c write. Tested-by: Thierry Reding # Beaver T30 Signed-off-by: Svyatoslav Ryhel Reviewed-by: Simon Glass Signed-off-by: Tom --- board/avionic-design/tec-ng/Makefile | 4 ++- board/avionic-design/tec-ng/tec-ng-spl.c | 34 +++++++++++++++++++++++ board/nvidia/beaver/Makefile | 2 ++ board/nvidia/beaver/beaver-spl.c | 43 +++++++++++++++++++++++++++++ board/nvidia/cardhu/Makefile | 4 ++- board/nvidia/cardhu/cardhu-spl.c | 43 +++++++++++++++++++++++++++++ board/toradex/apalis_t30/Makefile | 2 ++ board/toradex/apalis_t30/apalis_t30-spl.c | 34 +++++++++++++++++++++++ board/toradex/colibri_t30/Makefile | 2 ++ board/toradex/colibri_t30/colibri_t30-spl.c | 34 +++++++++++++++++++++++ 10 files changed, 200 insertions(+), 2 deletions(-) create mode 100644 board/avionic-design/tec-ng/tec-ng-spl.c create mode 100644 board/nvidia/beaver/beaver-spl.c create mode 100644 board/nvidia/cardhu/cardhu-spl.c create mode 100644 board/toradex/apalis_t30/apalis_t30-spl.c create mode 100644 board/toradex/colibri_t30/colibri_t30-spl.c (limited to 'board') diff --git a/board/avionic-design/tec-ng/Makefile b/board/avionic-design/tec-ng/Makefile index 46df14d991..d6890e5797 100644 --- a/board/avionic-design/tec-ng/Makefile +++ b/board/avionic-design/tec-ng/Makefile @@ -3,4 +3,6 @@ # (C) Copyright 2013 # Avionic Design GmbH -obj-y := ../common/tamonten-ng.o +obj-$(CONFIG_SPL_BUILD) += tec-ng-spl.o + +obj-y += ../common/tamonten-ng.o diff --git a/board/avionic-design/tec-ng/tec-ng-spl.c b/board/avionic-design/tec-ng/tec-ng-spl.c new file mode 100644 index 0000000000..6e54464183 --- /dev/null +++ b/board/avionic-design/tec-ng/tec-ng-spl.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * (C) Copyright 2021 + * Svyatoslav Ryhel + */ + +#include +#include +#include + +/* I2C addr is in 8 bit */ +#define TPS65911_I2C_ADDR 0x5A +#define TPS65911_VDDCTRL_OP_REG 0x28 +#define TPS65911_VDDCTRL_SR_REG 0x27 +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) + +void pmic_enable_cpu_vdd(void) +{ + /* + * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. + * First set VDD to 1.0125V, then enable the VDD regulator. + */ + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, + TPS65911_VDDCTRL_OP_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, + TPS65911_VDDCTRL_SR_DATA); + udelay(10 * 1000); +} diff --git a/board/nvidia/beaver/Makefile b/board/nvidia/beaver/Makefile index 80cff3eb9c..5e9e70825c 100644 --- a/board/nvidia/beaver/Makefile +++ b/board/nvidia/beaver/Makefile @@ -2,4 +2,6 @@ # # Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. +obj-$(CONFIG_SPL_BUILD) += beaver-spl.o + obj-y = ../cardhu/cardhu.o diff --git a/board/nvidia/beaver/beaver-spl.c b/board/nvidia/beaver/beaver-spl.c new file mode 100644 index 0000000000..b5d0c14854 --- /dev/null +++ b/board/nvidia/beaver/beaver-spl.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * (C) Copyright 2021 + * Svyatoslav Ryhel + */ + +#include +#include +#include + +/* I2C addr is in 8 bit */ +#define TPS65911_I2C_ADDR 0x5A +#define TPS65911_VDDCTRL_OP_REG 0x28 +#define TPS65911_VDDCTRL_SR_REG 0x27 +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) + +#define TPS62366A_I2C_ADDR 0xC0 +#define TPS62366A_SET1_REG 0x01 +#define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG) + +void pmic_enable_cpu_vdd(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(TPS62366A_I2C_ADDR, + TPS62366A_SET1_DATA); + + udelay(1000); + + /* + * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. + * First set VDD to 1.0125V, then enable the VDD regulator. + */ + tegra_i2c_ll_write(TPS65911_I2C_ADDR, + TPS65911_VDDCTRL_OP_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, + TPS65911_VDDCTRL_SR_DATA); + udelay(10 * 1000); +} diff --git a/board/nvidia/cardhu/Makefile b/board/nvidia/cardhu/Makefile index 95971053d9..6f480cdfd3 100644 --- a/board/nvidia/cardhu/Makefile +++ b/board/nvidia/cardhu/Makefile @@ -3,4 +3,6 @@ # (C) Copyright 2010-2012 # NVIDIA Corporation -obj-y := cardhu.o +obj-$(CONFIG_SPL_BUILD) += cardhu-spl.o + +obj-y += cardhu.o diff --git a/board/nvidia/cardhu/cardhu-spl.c b/board/nvidia/cardhu/cardhu-spl.c new file mode 100644 index 0000000000..de2fa300f1 --- /dev/null +++ b/board/nvidia/cardhu/cardhu-spl.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * (C) Copyright 2021 + * Svyatoslav Ryhel + */ + +#include +#include +#include + +/* I2C addr is in 8 bit */ +#define TPS65911_I2C_ADDR 0x5A +#define TPS65911_VDDCTRL_OP_REG 0x28 +#define TPS65911_VDDCTRL_SR_REG 0x27 +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) + +#define TPS62361B_I2C_ADDR 0xC0 +#define TPS62361B_SET3_REG 0x03 +#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG) + +void pmic_enable_cpu_vdd(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(TPS62361B_I2C_ADDR, + TPS62361B_SET3_DATA); + + udelay(1000); + + /* + * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. + * First set VDD to 1.0125V, then enable the VDD regulator. + */ + tegra_i2c_ll_write(TPS65911_I2C_ADDR, + TPS65911_VDDCTRL_OP_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, + TPS65911_VDDCTRL_SR_DATA); + udelay(10 * 1000); +} diff --git a/board/toradex/apalis_t30/Makefile b/board/toradex/apalis_t30/Makefile index 0ea3d8f217..eed607043f 100644 --- a/board/toradex/apalis_t30/Makefile +++ b/board/toradex/apalis_t30/Makefile @@ -1,4 +1,6 @@ # Copyright (c) 2014 Marcel Ziswiler # SPDX-License-Identifier: GPL-2.0+ +obj-$(CONFIG_SPL_BUILD) += apalis_t30-spl.o + obj-y += apalis_t30.o diff --git a/board/toradex/apalis_t30/apalis_t30-spl.c b/board/toradex/apalis_t30/apalis_t30-spl.c new file mode 100644 index 0000000000..6e54464183 --- /dev/null +++ b/board/toradex/apalis_t30/apalis_t30-spl.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * (C) Copyright 2021 + * Svyatoslav Ryhel + */ + +#include +#include +#include + +/* I2C addr is in 8 bit */ +#define TPS65911_I2C_ADDR 0x5A +#define TPS65911_VDDCTRL_OP_REG 0x28 +#define TPS65911_VDDCTRL_SR_REG 0x27 +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) + +void pmic_enable_cpu_vdd(void) +{ + /* + * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. + * First set VDD to 1.0125V, then enable the VDD regulator. + */ + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, + TPS65911_VDDCTRL_OP_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, + TPS65911_VDDCTRL_SR_DATA); + udelay(10 * 1000); +} diff --git a/board/toradex/colibri_t30/Makefile b/board/toradex/colibri_t30/Makefile index 4242902dae..8f333235b1 100644 --- a/board/toradex/colibri_t30/Makefile +++ b/board/toradex/colibri_t30/Makefile @@ -1,4 +1,6 @@ # Copyright (c) 2013-2014 Stefan Agner # SPDX-License-Identifier: GPL-2.0+ +obj-$(CONFIG_SPL_BUILD) += colibri_t30-spl.o + obj-y += colibri_t30.o diff --git a/board/toradex/colibri_t30/colibri_t30-spl.c b/board/toradex/colibri_t30/colibri_t30-spl.c new file mode 100644 index 0000000000..6e54464183 --- /dev/null +++ b/board/toradex/colibri_t30/colibri_t30-spl.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * (C) Copyright 2021 + * Svyatoslav Ryhel + */ + +#include +#include +#include + +/* I2C addr is in 8 bit */ +#define TPS65911_I2C_ADDR 0x5A +#define TPS65911_VDDCTRL_OP_REG 0x28 +#define TPS65911_VDDCTRL_SR_REG 0x27 +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) + +void pmic_enable_cpu_vdd(void) +{ + /* + * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. + * First set VDD to 1.0125V, then enable the VDD regulator. + */ + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, + TPS65911_VDDCTRL_OP_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, + TPS65911_VDDCTRL_SR_DATA); + udelay(10 * 1000); +} -- cgit v1.2.3