From 4d4222d07432faffe3a0fe35c483e116a28eb217 Mon Sep 17 00:00:00 2001 From: Zong Li Date: Wed, 1 Sep 2021 15:01:40 +0800 Subject: common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li Reviewed-by: Rick Chen --- common/board_r.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'common/board_r.c') diff --git a/common/board_r.c b/common/board_r.c index e3e6248a1f..630c2451a2 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -114,7 +114,7 @@ static int initr_reloc(void) return 0; } -#ifdef CONFIG_ARM +#if defined(CONFIG_ARM) || defined(CONFIG_RISCV) /* * Some of these functions are needed purely because the functions they * call return void. If we change them to return 0, these stubs can go away. @@ -607,7 +607,7 @@ static init_fnc_t init_sequence_r[] = { initr_trace, initr_reloc, /* TODO: could x86/PPC have this also perhaps? */ -#ifdef CONFIG_ARM +#if defined(CONFIG_ARM) || defined(CONFIG_RISCV) initr_caches, /* Note: For Freescale LS2 SoCs, new MMU table is created in DDR. * A temporary mapping of IFC high region is since removed, -- cgit v1.2.3