From c0f47562162f7f6ede331514ff2b59bff204a448 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Thu, 16 Jun 2022 14:19:44 +0200 Subject: powerpc: mpc85xx: Set TEXT_BASE addresses to real base values MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently CONFIG_SPL_TEXT_BASE and CONFIG_SYS_TEXT_BASE addresses are manually increased by 0x1000 due to .bootpg section. This section has size of 0x1000 bytes and is manually put by linker script before .text section (and therefore before base address) when CONFIG_SYS_MPC85XX_NO_RESETVEC is set. Due to this fact lot of other config options are manually increased by 0x1000 value to make correct layout. Note that entry point is not on CONFIG_SPL_TEXT_BASE (image+0x1000) but it is really on address CONFIG_SPL_TEXT_BASE-0x1000 (means at the start of the image). Cleanup handling of .bootpg section when CONFIG_SYS_MPC85XX_NO_RESETVEC is set. Put .bootpg code directly into .text section and move text base address to the start of .bootpg code. And finally remove +0x1000 value from lot of config options. With this removal custom PHDRS is not used anymore, so remove it too. After this change entry point would be at CONFIG_SPL_TEXT_BASE and not at address -0x1000 anymore. Tested on P2020 board with SPL and proper U-Boot. Signed-off-by: Pali Rohár --- configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'configs/P1010RDB-PA_36BIT_SDCARD_defconfig') diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 8dd667ff48..b46d62c82f 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -1,12 +1,12 @@ CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 +CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" -CONFIG_SPL_TEXT_BASE=0xD0001000 +CONFIG_SPL_TEXT_BASE=0xD0000000 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y @@ -30,7 +30,7 @@ CONFIG_SPL_MMC_BOOT=y CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y CONFIG_SPL_FLUSH_IMAGE=y CONFIG_SPL_GD_ADDR=0xd0018000 -CONFIG_SPL_RELOC_TEXT_BASE=0xd0001000 +CONFIG_SPL_RELOC_TEXT_BASE=0xd0000000 CONFIG_SPL_RELOC_STACK=0xd001c000 CONFIG_SPL_RELOC_MALLOC=y CONFIG_SPL_RELOC_MALLOC_ADDR=0xd0020000 -- cgit v1.2.3