From a2eb65fcad4c66ee6992e18d8bea15fd0b07886e Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 27 Jul 2015 19:16:08 +0800 Subject: x86: qemu: Add MP initialization Add a cpu1 node to the device tree and enable the MP initialization on QEMU targets (i440fx and q35). Signed-off-by: Bin Meng Acked-by: Simon Glass Tested-by: Simon Glass --- configs/qemu-x86_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'configs') diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 4b18d51738..e579c36200 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -1,5 +1,7 @@ CONFIG_X86=y CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx" +CONFIG_SMP=y +CONFIG_MAX_CPUS=2 CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_CMD_CPU=y -- cgit v1.2.3 From 9b911bed78c3926fe1129dcc6b0ffbca667dff74 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 30 Jul 2015 03:49:17 -0700 Subject: x86: Add Intel Bayley Bay board support Intel Bayley Bay board is a BayTrail based board. Add this board with existing baytrail fsp support. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/dts/Makefile | 3 +- arch/x86/dts/bayleybay.dts | 134 ++++++++++++++++++++++++++++++++++++++ board/intel/Kconfig | 9 +++ board/intel/bayleybay/Kconfig | 27 ++++++++ board/intel/bayleybay/MAINTAINERS | 6 ++ board/intel/bayleybay/Makefile | 7 ++ board/intel/bayleybay/bayleybay.c | 19 ++++++ board/intel/bayleybay/start.S | 9 +++ configs/bayleybay_defconfig | 25 +++++++ include/configs/bayleybay.h | 45 +++++++++++++ 10 files changed, 283 insertions(+), 1 deletion(-) create mode 100644 arch/x86/dts/bayleybay.dts create mode 100644 board/intel/bayleybay/Kconfig create mode 100644 board/intel/bayleybay/MAINTAINERS create mode 100644 board/intel/bayleybay/Makefile create mode 100644 board/intel/bayleybay/bayleybay.c create mode 100644 board/intel/bayleybay/start.S create mode 100644 configs/bayleybay_defconfig create mode 100644 include/configs/bayleybay.h (limited to 'configs') diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index f86514ce83..44e2829f25 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -1,4 +1,5 @@ -dtb-y += chromebook_link.dtb \ +dtb-y += bayleybay.dtb \ + chromebook_link.dtb \ chromebox_panther.dtb \ crownbay.dtb \ galileo.dtb \ diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts new file mode 100644 index 0000000000..cbbdee2730 --- /dev/null +++ b/arch/x86/dts/bayleybay.dts @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2015, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "rtc.dtsi" + +/ { + model = "Intel Bayley Bay"; + compatible = "intel,bayleybay", "intel,baytrail"; + + aliases { + serial0 = &serial; + spi0 = "/spi"; + }; + + config { + silent_console = <0>; + }; + + chosen { + stdout-path = "/serial"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <1>; + intel,apic-id = <2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <2>; + intel,apic-id = <4>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <3>; + intel,apic-id = <6>; + }; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + reg = <0>; + compatible = "winbond,w25q64dw", "spi-flash"; + memory-map = <0xff800000 0x00800000>; + }; + }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x20>; + bank-name = "C"; + }; + + gpiod { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x60 0x20>; + bank-name = "D"; + }; + + gpioe { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x80 0x20>; + bank-name = "E"; + }; + + gpiof { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0xA0 0x20>; + bank-name = "F"; + }; + + pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + }; + + microcode { + update@0 { +#include "microcode/m0230671117.dtsi" + }; + }; + +}; diff --git a/board/intel/Kconfig b/board/intel/Kconfig index 3d9ecf0693..f7d71c3612 100644 --- a/board/intel/Kconfig +++ b/board/intel/Kconfig @@ -10,6 +10,14 @@ choice prompt "Mainboard model" optional +config TARGET_BAYLEYBAY + bool "Bayley Bay" + help + This is the Intel Bayley Bay Customer Reference Board. It contains an + Intel quad-core Atom Processor E3800 with dual-channel DDR3L SODIMM + 4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC, + PCIe and some other sensor interfaces. + config TARGET_CROWNBAY bool "Crown Bay" help @@ -45,6 +53,7 @@ config TARGET_MINNOWMAX endchoice +source "board/intel/bayleybay/Kconfig" source "board/intel/crownbay/Kconfig" source "board/intel/galileo/Kconfig" source "board/intel/minnowmax/Kconfig" diff --git a/board/intel/bayleybay/Kconfig b/board/intel/bayleybay/Kconfig new file mode 100644 index 0000000000..597228fdbc --- /dev/null +++ b/board/intel/bayleybay/Kconfig @@ -0,0 +1,27 @@ +if TARGET_BAYLEYBAY + +config SYS_BOARD + default "bayleybay" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "baytrail" + +config SYS_CONFIG_NAME + default "bayleybay" + +config SYS_TEXT_BASE + default 0xfff00000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + +config PCIE_ECAM_BASE + default 0xe0000000 + +endif diff --git a/board/intel/bayleybay/MAINTAINERS b/board/intel/bayleybay/MAINTAINERS new file mode 100644 index 0000000000..85fa51626a --- /dev/null +++ b/board/intel/bayleybay/MAINTAINERS @@ -0,0 +1,6 @@ +Intel Bayley Bay +M: Bin Meng +S: Maintained +F: board/intel/bayleybay +F: include/configs/bayleybay.h +F: configs/bayleybay_defconfig diff --git a/board/intel/bayleybay/Makefile b/board/intel/bayleybay/Makefile new file mode 100644 index 0000000000..88b5aad634 --- /dev/null +++ b/board/intel/bayleybay/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015, Bin Meng +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += bayleybay.o start.o diff --git a/board/intel/bayleybay/bayleybay.c b/board/intel/bayleybay/bayleybay.c new file mode 100644 index 0000000000..78447965b9 --- /dev/null +++ b/board/intel/bayleybay/bayleybay.c @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) +{ + return; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/intel/bayleybay/start.S b/board/intel/bayleybay/start.S new file mode 100644 index 0000000000..a71db69be9 --- /dev/null +++ b/board/intel/bayleybay/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig new file mode 100644 index 0000000000..e10e86a4c1 --- /dev/null +++ b/configs/bayleybay_defconfig @@ -0,0 +1,25 @@ +CONFIG_X86=y +CONFIG_VENDOR_INTEL=y +CONFIG_DEFAULT_DEVICE_TREE="bayleybay" +CONFIG_TARGET_BAYLEYBAY=y +CONFIG_HAVE_INTEL_ME=y +CONFIG_SMP=y +CONFIG_HAVE_VGA_BIOS=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_OF_CONTROL=y +CONFIG_CPU=y +CONFIG_DM_PCI=y +CONFIG_SPI_FLASH=y +CONFIG_VIDEO_VESA=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_DM_RTC=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_SYS_VSNPRINTF=y diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h new file mode 100644 index 0000000000..cc95aec458 --- /dev/null +++ b/include/configs/bayleybay.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2015, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_X86_SERIAL + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_PCI_PNP +#define CONFIG_E1000 + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA} + +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SDMA +#define CONFIG_CMD_MMC + +/* BayTrail IGD support */ +#define CONFIG_VGA_AS_SINGLE_DEVICE + +/* Environment configuration */ +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x006ff000 + +#endif /* __CONFIG_H */ -- cgit v1.2.3 From fe3fbd302427b3690c4d682c1d7d03ca94771afd Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 30 Jul 2015 03:49:18 -0700 Subject: x86: bayleybay: Configure PCI IRQ Add PCI IRQ routing information in the board device tree and enable writing PIRQ routing table and MP table. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/cpu/baytrail/valleyview.c | 8 +++++ arch/x86/dts/bayleybay.dts | 63 ++++++++++++++++++++++++++++++++++++++ configs/bayleybay_defconfig | 2 ++ include/configs/bayleybay.h | 1 + 4 files changed, 74 insertions(+) (limited to 'configs') diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c index 9915da5bd7..d8d2b8d418 100644 --- a/arch/x86/cpu/baytrail/valleyview.c +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -7,6 +7,7 @@ #include #include #include +#include #include static struct pci_device_id mmc_supported[] = { @@ -35,3 +36,10 @@ int arch_cpu_init(void) return 0; } + +int arch_misc_init(void) +{ + pirq_init(); + + return 0; +} diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index cbbdee2730..9f8fa70f96 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include /include/ "skeleton.dtsi" /include/ "serial.dtsi" @@ -123,6 +124,68 @@ ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + + irq-router@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,irq-router"; + intel,pirq-config = "ibase"; + intel,ibase-offset = <0x50>; + intel,pirq-link = <8 8>; + intel,pirq-mask = <0xdee0>; + intel,pirq-routing = < + /* BayTrail PCI devices */ + PCI_BDF(0, 2, 0) INTA PIRQA + PCI_BDF(0, 3, 0) INTA PIRQA + PCI_BDF(0, 16, 0) INTA PIRQA + PCI_BDF(0, 17, 0) INTA PIRQA + PCI_BDF(0, 18, 0) INTA PIRQA + PCI_BDF(0, 19, 0) INTA PIRQA + PCI_BDF(0, 20, 0) INTA PIRQA + PCI_BDF(0, 21, 0) INTA PIRQA + PCI_BDF(0, 22, 0) INTA PIRQA + PCI_BDF(0, 23, 0) INTA PIRQA + PCI_BDF(0, 24, 0) INTA PIRQA + PCI_BDF(0, 24, 1) INTC PIRQC + PCI_BDF(0, 24, 2) INTD PIRQD + PCI_BDF(0, 24, 3) INTB PIRQB + PCI_BDF(0, 24, 4) INTA PIRQA + PCI_BDF(0, 24, 5) INTC PIRQC + PCI_BDF(0, 24, 6) INTD PIRQD + PCI_BDF(0, 24, 7) INTB PIRQB + PCI_BDF(0, 26, 0) INTA PIRQA + PCI_BDF(0, 27, 0) INTA PIRQA + PCI_BDF(0, 28, 0) INTA PIRQA + PCI_BDF(0, 28, 1) INTB PIRQB + PCI_BDF(0, 28, 2) INTC PIRQC + PCI_BDF(0, 28, 3) INTD PIRQD + PCI_BDF(0, 29, 0) INTA PIRQA + PCI_BDF(0, 30, 0) INTA PIRQA + PCI_BDF(0, 30, 1) INTD PIRQD + PCI_BDF(0, 30, 2) INTB PIRQB + PCI_BDF(0, 30, 3) INTC PIRQC + PCI_BDF(0, 30, 4) INTD PIRQD + PCI_BDF(0, 30, 5) INTB PIRQB + PCI_BDF(0, 31, 3) INTB PIRQB + + /* PCIe root ports downstream interrupts */ + PCI_BDF(1, 0, 0) INTA PIRQA + PCI_BDF(1, 0, 0) INTB PIRQB + PCI_BDF(1, 0, 0) INTC PIRQC + PCI_BDF(1, 0, 0) INTD PIRQD + PCI_BDF(2, 0, 0) INTA PIRQB + PCI_BDF(2, 0, 0) INTB PIRQC + PCI_BDF(2, 0, 0) INTC PIRQD + PCI_BDF(2, 0, 0) INTD PIRQA + PCI_BDF(3, 0, 0) INTA PIRQC + PCI_BDF(3, 0, 0) INTB PIRQD + PCI_BDF(3, 0, 0) INTC PIRQA + PCI_BDF(3, 0, 0) INTD PIRQB + PCI_BDF(4, 0, 0) INTA PIRQD + PCI_BDF(4, 0, 0) INTB PIRQA + PCI_BDF(4, 0, 0) INTC PIRQB + PCI_BDF(4, 0, 0) INTD PIRQC + >; + }; }; microcode { diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index e10e86a4c1..7f92ead9a6 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -5,6 +5,8 @@ CONFIG_TARGET_BAYLEYBAY=y CONFIG_HAVE_INTEL_ME=y CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_MP_TABLE=y CONFIG_CMD_CPU=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h index cc95aec458..740166afd3 100644 --- a/include/configs/bayleybay.h +++ b/include/configs/bayleybay.h @@ -14,6 +14,7 @@ #include #define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_ARCH_MISC_INIT #define CONFIG_X86_SERIAL -- cgit v1.2.3 From ca4435ef28d13371c31b98cfd41fb8fa28aeabc9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Jul 2015 15:47:22 -0600 Subject: x86: Move Chrome OS options to defconfig Drop these from the header file and use Kconfig instead. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- configs/chromebook_link_defconfig | 3 +++ configs/chromebox_panther_defconfig | 3 +++ include/configs/x86-chromebook.h | 3 --- 3 files changed, 6 insertions(+), 3 deletions(-) (limited to 'configs') diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index e394dab719..b987f3f52f 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -14,6 +14,9 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y CONFIG_DM_PCI=y CONFIG_SPI_FLASH=y +CONFIG_CMD_CROS_EC=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_LPC=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index 340510f71a..e82c8ecf64 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -14,6 +14,9 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y CONFIG_DM_PCI=y CONFIG_SPI_FLASH=y +CONFIG_CMD_CROS_EC=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_LPC=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index 408cbb1957..e8f0bac01c 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -45,9 +45,6 @@ #define VIDEO_IO_OFFSET 0 #define CONFIG_X86EMU_RAW_IO -#define CONFIG_CROS_EC -#define CONFIG_CROS_EC_LPC -#define CONFIG_CMD_CROS_EC #define CONFIG_ARCH_EARLY_INIT_R #undef CONFIG_ENV_IS_NOWHERE -- cgit v1.2.3 From cd326a32c9fc317af30d682db2ba8f3242bc1221 Mon Sep 17 00:00:00 2001 From: Ben Stoltz Date: Tue, 4 Aug 2015 12:33:50 -0600 Subject: x86: Add definitions for the x86-efi board and plumb it in Add configuration and Kconfig changes for this board. Signed-off-by: Ben Stoltz Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- configs/efi-x86_defconfig | 16 ++++++++++++++++ include/configs/efi-x86.h | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 configs/efi-x86_defconfig create mode 100644 include/configs/efi-x86.h (limited to 'configs') diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig new file mode 100644 index 0000000000..1aa0655a17 --- /dev/null +++ b/configs/efi-x86_defconfig @@ -0,0 +1,16 @@ +CONFIG_X86=y +CONFIG_VENDOR_EFI=y +CONFIG_TARGET_EFI=y +CONFIG_TSC_CALIBRATION_BYPASS=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DM_PCI=y +CONFIG_DEFAULT_DEVICE_TREE="efi" +CONFIG_EFI=y +CONFIG_EFI_APP=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_EFI_CONSOLE=y +CONFIG_DEBUG_UART_BASE=0 +CONFIG_DEBUG_UART_CLOCK=0 +# CONFIG_CMD_NET is not set +# CONFIG_CMD_BOOTM is not set diff --git a/include/configs/efi-x86.h b/include/configs/efi-x86.h new file mode 100644 index 0000000000..5779cfdb66 --- /dev/null +++ b/include/configs/efi-x86.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#undef CONFIG_CMD_SF_TEST + +#undef CONFIG_TPM +#undef CONFIG_TPM_TIS_LPC +#undef CONFIG_TPM_TIS_BASE_ADDRESS + +#undef CONFIG_CMD_IMLS + +#undef CONFIG_SYS_NS16550 +#undef CONFIG_X86_SERIAL +#undef CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_IS_NOWHERE +#undef CONFIG_VIDEO +#undef CONFIG_CFB_CONSOLE +#undef CONFIG_SCSI_AHCI +#undef CONFIG_CMD_SCSI +#undef CONFIG_INTEL_ICH6_GPIO + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ + "stdout=vga,serial\0" \ + "stderr=vga,serial\0" + +#endif -- cgit v1.2.3