From 5cfa55930b930c270a127bf9136e90cb8508e0b0 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 9 Oct 2021 22:41:07 +0200 Subject: verdin-imx8mm: switch to use binman to pack images Use binman to pack images. Signed-off-by: Marcel Ziswiler Reviewed-by: Heiko Thiery Reviewed-by: Fabio Estevam Reviewed-by: Heiko Schocher --- configs/verdin-imx8mm_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'configs') diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index 98799994ce..1c8b505656 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -23,7 +23,7 @@ CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-verdin-dev.dtb" -- cgit v1.2.3 From 8da72960edf4eac6b49ae39486c9e7569165963d Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Sat, 9 Oct 2021 22:41:08 +0200 Subject: verdin-imx8mm: enable sleep_moci output This powers some peripherals on the carrier board e.g. the USB hub. Related-to: ELB-3206 Signed-off-by: Max Krummenacher Signed-off-by: Marcel Ziswiler Reviewed-by: Fabio Estevam --- arch/arm/dts/imx8mm-verdin.dts | 18 ++++++++++++++++++ configs/verdin-imx8mm_defconfig | 1 + 2 files changed, 19 insertions(+) (limited to 'configs') diff --git a/arch/arm/dts/imx8mm-verdin.dts b/arch/arm/dts/imx8mm-verdin.dts index ac2a4b69d3..a2331627d7 100644 --- a/arch/arm/dts/imx8mm-verdin.dts +++ b/arch/arm/dts/imx8mm-verdin.dts @@ -196,6 +196,18 @@ }; }; +&gpio5 { + ctrl_sleep_moci { + gpio-hog; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; + output-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; + }; +}; + /* On-module I2C */ &i2c1 { clock-frequency = <400000>; @@ -548,6 +560,12 @@ >; }; + pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1c4 /* SODIMM 256 */ + >; + }; + pinctrl_dsi_bkl_en: dsi_bkl_en { fsl,pins = < MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x1c4 /* SODIMM 21 */ diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index 1c8b505656..ced0d0acc3 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -69,6 +69,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y +CONFIG_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_MISC=y -- cgit v1.2.3 From e5505e9ebbc7172905e011513eab5933a97e4695 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Sat, 9 Oct 2021 22:41:12 +0200 Subject: verdin-imx8mm: use preboot for fdtfile evaluation Enable and set preboot var with fdtfile evaluation. It will be checked and run immediately before starting the CONFIG_BOOTDELAY countdown and/or running the auto-boot command resp. entering interactive mode. This provides possibility to use different boot cmds in interactive mode without manual setting fdtfile value, as it it's already evaluated before entering interactive mode. Signed-off-by: Igor Opaniuk Signed-off-by: Marcel Ziswiler Reviewed-by: Fabio Estevam --- configs/verdin-imx8mm_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'configs') diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index ced0d0acc3..ed14ff3b11 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -26,7 +26,8 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y # CONFIG_USE_BOOTCOMMAND is not set -CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-verdin-dev.dtb" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="setenv fdtfile imx8mm-verdin-${variant}-${fdt_board}.dtb" CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -- cgit v1.2.3 From f38b1da8bbef76505f31bb9cd545d833c8499561 Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Wed, 6 Oct 2021 11:56:52 +0200 Subject: board: phytec: phycore-imx8mm: Add SPI-NOR flash support Adds SPI-NOR flash support to erase, read and write in bootloader. Signed-off-by: Teresa Remmet --- arch/arm/dts/phycore-imx8mm.dts | 28 ++++++++++++++++++++++++++++ configs/phycore-imx8mm_defconfig | 19 +++++++++++++++++++ 2 files changed, 47 insertions(+) (limited to 'configs') diff --git a/arch/arm/dts/phycore-imx8mm.dts b/arch/arm/dts/phycore-imx8mm.dts index a4332619e5..e57dfd368d 100644 --- a/arch/arm/dts/phycore-imx8mm.dts +++ b/arch/arm/dts/phycore-imx8mm.dts @@ -54,6 +54,23 @@ }; }; +/* SPI nor flash */ +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: norflash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + /* i2c eeprom */ &i2c1 { clock-frequency = <400000>; @@ -140,6 +157,17 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 91360b7d1a..6cb2d36855 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -29,6 +29,7 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y +CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " @@ -44,6 +45,7 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF_TEST=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -78,6 +80,20 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=3 +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SF_DEFAULT_SPEED=80000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_TI_DP83867=y CONFIG_DM_ETH=y @@ -91,6 +107,9 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y -- cgit v1.2.3 From 454ea0e2c60e06acfe949bc4bc1143040c8d467b Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Wed, 6 Oct 2021 11:56:53 +0200 Subject: configs: phycore-imx8mm_defconfig: Enable clk command Enable clk command to dump clock tree. Signed-off-by: Teresa Remmet --- configs/phycore-imx8mm_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'configs') diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 6cb2d36855..1897cb398f 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -41,6 +41,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SYS_EEPROM_SIZE=4096 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y -- cgit v1.2.3 From 463a01c7e4cd88d95a6cb8b5ae92ae2b19a8dda7 Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Wed, 6 Oct 2021 11:56:54 +0200 Subject: board: phytec: imx8mm-phycore: Switch to binman Use binman for image creation. Signed-off-by: Teresa Remmet --- arch/arm/dts/phycore-imx8mm-u-boot.dtsi | 122 ++++++++++++++++++++++++ arch/arm/mach-imx/imx8m/Kconfig | 1 + board/phytec/phycore_imx8mm/Kconfig | 2 +- board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg | 9 ++ configs/phycore-imx8mm_defconfig | 2 +- 5 files changed, 134 insertions(+), 2 deletions(-) create mode 100644 board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg (limited to 'configs') diff --git a/arch/arm/dts/phycore-imx8mm-u-boot.dtsi b/arch/arm/dts/phycore-imx8mm-u-boot.dtsi index 7c2dfb4a27..f842e02c77 100644 --- a/arch/arm/dts/phycore-imx8mm-u-boot.dtsi +++ b/arch/arm/dts/phycore-imx8mm-u-boot.dtsi @@ -7,6 +7,10 @@ #include "imx8mm-u-boot.dtsi" / { + binman: binman { + multiple-images; + }; + wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>; @@ -69,3 +73,121 @@ &wdog1 { u-boot,dm-spl; }; + +&binman { + u-boot-spl-ddr { + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + align-size = <4>; + align = <4>; + + u-boot-spl { + align-end = <4>; + }; + + blob_1: blob-ext@1 { + filename = "lpddr4_pmu_train_1d_imem.bin"; + size = <0x8000>; + }; + + blob_2: blob-ext@2 { + filename = "lpddr4_pmu_train_1d_dmem.bin"; + size = <0x4000>; + }; + + blob_3: blob-ext@3 { + filename = "lpddr4_pmu_train_2d_imem.bin"; + size = <0x8000>; + }; + + blob_4: blob-ext@4 { + filename = "lpddr4_pmu_train_2d_dmem.bin"; + size = <0x4000>; + }; + }; + + spl { + filename = "spl.bin"; + + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000"; + + blob { + filename = "u-boot-spl-ddr.bin"; + }; + }; + }; + + itb { + filename = "u-boot.itb"; + + fit { + description = "Configuration to load ATF before U-Boot"; + #address-cells = <1>; + fit,external-offset = ; + + images { + uboot { + description = "U-Boot (64-bit)"; + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = ; + + uboot_blob: blob-ext { + filename = "u-boot-nodtb.bin"; + }; + }; + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x920000>; + entry = <0x920000>; + + atf_blob: blob-ext { + filename = "bl31.bin"; + }; + }; + + fdt { + description = "NAME"; + type = "flat_dt"; + compression = "none"; + + uboot_fdt_blob: blob-ext { + filename = "u-boot.dtb"; + }; + }; + }; + + configurations { + default = "conf"; + + conf { + description = "NAME"; + firmware = "uboot"; + loadables = "atf"; + fdt = "fdt"; + }; + }; + }; + }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl: blob-ext@1 { + filename = "spl.bin"; + offset = <0x0>; + }; + + uboot: blob-ext@2 { + filename = "u-boot.itb"; + offset = <0x57c00>; + }; + }; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index c68053b282..276b8bd974 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -129,6 +129,7 @@ config TARGET_IMX8MN_BEACON config TARGET_PHYCORE_IMX8MM bool "PHYTEC PHYCORE i.MX8MM" + select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 diff --git a/board/phytec/phycore_imx8mm/Kconfig b/board/phytec/phycore_imx8mm/Kconfig index 9868e98487..25e4bf2f83 100644 --- a/board/phytec/phycore_imx8mm/Kconfig +++ b/board/phytec/phycore_imx8mm/Kconfig @@ -10,6 +10,6 @@ config SYS_CONFIG_NAME default "phycore_imx8mm" config IMX_CONFIG - default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" + default "board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg" endif diff --git a/board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg b/board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg new file mode 100644 index 0000000000..ea74fb7e59 --- /dev/null +++ b/board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 Phytec Messtechnik GmbH + */ + +#define __ASSEMBLY__ + +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x7E1000 diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 1897cb398f..c221398747 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -21,7 +21,7 @@ CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_BOARD_LATE_INIT=y -- cgit v1.2.3 From 80ef6926e7be7bbe72dd73306182e46827f61949 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Wed, 6 Oct 2021 18:55:36 +0200 Subject: colibri-imx6ull: add emmc variant Add code to build the eMMC variant of the Colibri iMX6ULL, i.e. the 'Colibri iMX6ULL 1GB' which has a eMMC instead of the raw NAND used on other SKUs. Related-to: ELB-4056, ELB-4057 Signed-off-by: Max Krummenacher Signed-off-by: Marcel Ziswiler --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx6ull-colibri-emmc.dts | 49 ++++++++++++++ arch/arm/dts/imx6ull-colibri.dts | 34 +++++++++- arch/arm/dts/imx6ull-colibri.dtsi | 32 +-------- board/toradex/colibri-imx6ull/Kconfig | 48 +++++++++++++- board/toradex/colibri-imx6ull/MAINTAINERS | 4 +- board/toradex/colibri-imx6ull/colibri-imx6ull.c | 29 +++++++- configs/colibri-imx6ull-emmc_defconfig | 88 +++++++++++++++++++++++++ configs/colibri-imx6ull_defconfig | 2 +- include/configs/colibri-imx6ull.h | 51 ++++++++++---- 10 files changed, 290 insertions(+), 48 deletions(-) create mode 100644 arch/arm/dts/imx6ull-colibri-emmc.dts create mode 100644 configs/colibri-imx6ull-emmc_defconfig (limited to 'configs') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6168d8d459..d56c665071 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -822,6 +822,7 @@ dtb-$(CONFIG_MX6UL) += \ dtb-$(CONFIG_MX6ULL) += \ imx6ull-14x14-evk.dtb \ imx6ull-colibri.dtb \ + imx6ull-colibri-emmc.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ imx6ull-seeed-npi-imx6ull-dev-board.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ diff --git a/arch/arm/dts/imx6ull-colibri-emmc.dts b/arch/arm/dts/imx6ull-colibri-emmc.dts new file mode 100644 index 0000000000..cbb561ffb4 --- /dev/null +++ b/arch/arm/dts/imx6ull-colibri-emmc.dts @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 Toradex AG + */ + +#include "imx6ull-colibri.dtsi" +#include "imx6ull-colibri-u-boot.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 1GB (eMMC)"; + compatible = "toradex,colibri-imx6ull-emmc", "toradex,colibri-imx6ull", "fsl,imx6ull"; + + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc1; + }; +}; + +/* eMMC */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2emmc>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; + bus-width = <8>; + keep-power-in-suspend; + no-1-8-v; + non-removable; + vmmc-supply = <®_module_3v3>; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc2emmc: usdhc2emmcgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; +}; diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts index 15338a1ae3..dbe3e0206e 100644 --- a/arch/arm/dts/imx6ull-colibri.dts +++ b/arch/arm/dts/imx6ull-colibri.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2018-2019 Toradex AG + * Copyright 2018-2021 Toradex AG */ #include "imx6ull-colibri.dtsi" @@ -10,3 +10,35 @@ model = "Toradex Colibri iMX6ULL"; compatible = "toradex,colibri-imx6ull", "fsl,imx6ull"; }; + +/* NAND */ +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + status = "okay"; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpmi-nand-grp { + fsl,pins = < + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9 + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9 + >; + }; +}; diff --git a/arch/arm/dts/imx6ull-colibri.dtsi b/arch/arm/dts/imx6ull-colibri.dtsi index b7bf79f28c..1fa9d10412 100644 --- a/arch/arm/dts/imx6ull-colibri.dtsi +++ b/arch/arm/dts/imx6ull-colibri.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2019 Toradex AG + * Copyright 2019-2021 Toradex AG */ /dts-v1/; @@ -92,17 +92,6 @@ }; }; -/* NAND */ -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - nand-ecc-mode = "hw"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - status = "okay"; -}; - /* * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */ @@ -340,25 +329,6 @@ >; }; - pinctrl_gpmi_nand: gpmi-nand-grp { - fsl,pins = < - MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 - MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 - MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9 - MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9 - MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9 - MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9 - MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9 - MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9 - MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9 - MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9 - MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9 - MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9 - MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9 - MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9 - >; - }; - pinctrl_i2c1: i2c1-grp { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 diff --git a/board/toradex/colibri-imx6ull/Kconfig b/board/toradex/colibri-imx6ull/Kconfig index e5e4af3364..9fbc30f6b3 100644 --- a/board/toradex/colibri-imx6ull/Kconfig +++ b/board/toradex/colibri-imx6ull/Kconfig @@ -1,5 +1,24 @@ if TARGET_COLIBRI_IMX6ULL +choice + prompt "Colibri iMX6ULL variant" + optional + +config TARGET_COLIBRI_IMX6ULL_NAND + bool "Support Colibri iMX6ULL 256MB / 512MB (raw NAND) modules" + imply NAND_MXS + help + Choose this option if you build for a Toradex Colibri iMX6ULL + 256MB or 512MB module which do have raw NAND on-module. + +config TARGET_COLIBRI_IMX6ULL_EMMC + bool "Support Colibri iMX6ULL 1GB (eMMC) modules" + help + Choose this option if you build for a Toradex Colibri iMX6ULL + 1GB module which does have eMMC on-module. + +endchoice + config SYS_BOARD default "colibri-imx6ull" @@ -7,11 +26,16 @@ config SYS_VENDOR default "toradex" config SYS_CONFIG_NAME - default "colibri-imx6ull" + default "colibri-imx6ull-tezi-recovery" if (!TARGET_COLIBRI_IMX6ULL_NAND && !TARGET_COLIBRI_IMX6ULL_EMMC) config TDX_CFG_BLOCK default y +if TARGET_COLIBRI_IMX6ULL_NAND + +config SYS_CONFIG_NAME + default "colibri-imx6ull" + config TDX_HAVE_NAND default y @@ -21,6 +45,28 @@ config TDX_CFG_BLOCK_OFFSET config TDX_CFG_BLOCK_OFFSET2 default "133120" +endif + +if TARGET_COLIBRI_IMX6ULL_EMMC + +config SYS_CONFIG_NAME + default "colibri-imx6ull" + +config TDX_HAVE_MMC + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +config TDX_CFG_BLOCK_PART + default "1" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +endif + config TDX_CFG_BLOCK_2ND_ETHADDR default y diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS b/board/toradex/colibri-imx6ull/MAINTAINERS index eb491c273d..500c787b8e 100644 --- a/board/toradex/colibri-imx6ull/MAINTAINERS +++ b/board/toradex/colibri-imx6ull/MAINTAINERS @@ -4,8 +4,10 @@ W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained F: arch/arm/dts/imx6ull-colibri.dts -F: arch/arm/dts/imx6ull-colibri-u-boot.dtsi F: arch/arm/dts/imx6ull-colibri.dtsi +F: arch/arm/dts/imx6ull-colibri-emmc.dts +F: arch/arm/dts/imx6ull-colibri-u-boot.dtsi F: board/toradex/colibri-imx6ull/ F: configs/colibri-imx6ull_defconfig +F: configs/colibri-imx6ull-emmc_defconfig F: include/configs/colibri-imx6ull.h diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c index fd54688272..02ab5889b9 100644 --- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c +++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c @@ -43,6 +43,14 @@ DECLARE_GLOBAL_DATA_PTR; #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP) +#define FLASH_DETECTION_CTRL (PAD_CTL_HYS | PAD_CTL_PUE) +#define FLASH_DET_GPIO IMX_GPIO_NR(4, 1) +static const iomux_v3_cfg_t flash_detection_pads[] = { + MX6_PAD_NAND_WE_B__GPIO4_IO01 | MUX_PAD_CTRL(FLASH_DETECTION_CTRL), +}; + +static bool is_emmc; + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -60,7 +68,7 @@ static void setup_gpmi_nand(void) #endif /* CONFIG_NAND_MXS */ #ifdef CONFIG_DM_VIDEO -static iomux_v3_cfg_t const backlight_pads[] = { +static const iomux_v3_cfg_t backlight_pads[] = { /* Backlight On */ MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* Backlight PWM (multiplexed pin) */ @@ -121,6 +129,16 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + /* + * Enable GPIO on NAND_WE_B/eMMC_RST with 100k pull-down. eMMC_RST + * is pulled high with 4.7k for eMMC devices. This allows to reliably + * detect eMMC/NAND flash + */ + imx_iomux_v3_setup_multiple_pads(flash_detection_pads, ARRAY_SIZE(flash_detection_pads)); + gpio_request(FLASH_DET_GPIO, "flash-detection-gpio"); + is_emmc = gpio_get_value(FLASH_DET_GPIO); + gpio_free(FLASH_DET_GPIO); + #ifdef CONFIG_FEC_MXC setup_fec(); #endif @@ -149,8 +167,15 @@ int board_late_init(void) * Wi-Fi/Bluetooth make sure we use the -wifi device tree. */ if (tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT_IT || - tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT) + tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT) { env_set("variant", "-wifi"); + } else { + if (is_emmc) + env_set("variant", "-emmc"); + } +#else + if (is_emmc) + env_set("variant", "-emmc"); #endif /* diff --git a/configs/colibri-imx6ull-emmc_defconfig b/configs/colibri-imx6ull-emmc_defconfig new file mode 100644 index 0000000000..4b346a9879 --- /dev/null +++ b/configs/colibri-imx6ull-emmc_defconfig @@ -0,0 +1,88 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_MX6ULL=y +CONFIG_TARGET_COLIBRI_IMX6ULL=y +CONFIG_DM_GPIO=y +CONFIG_TARGET_COLIBRI_IMX6ULL_EMMC=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri-emmc" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=1 +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="setenv fdtfile imx6ull-colibri${variant}-${fdt_board}.dtb" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SYS_PROMPT="Colibri iMX6ULL # " +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_ASKENV=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_BMP=y +CONFIG_CMD_BOOTCOUNT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y +CONFIG_IP_DEFRAG=y +CONFIG_TFTP_BLOCKSIZE=16352 +CONFIG_TFTP_TSIZE=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Toradex" +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index 0af56f438a..e2f168ba35 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -10,6 +10,7 @@ CONFIG_MX6ULL=y CONFIG_TARGET_COLIBRI_IMX6ULL=y CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y +CONFIG_TARGET_COLIBRI_IMX6ULL_NAND=y CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri" CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y @@ -71,7 +72,6 @@ CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y -CONFIG_NAND_MXS=y CONFIG_NAND_MXS_DT=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_MTD_UBI_FASTMAP=y diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 85c855c098..2495193f05 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2018-2019 Toradex AG + * Copyright 2018-2021 Toradex AG * * Configuration settings for the Colibri iMX6ULL module. * @@ -26,6 +26,22 @@ #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_SERVERIP 192.168.10.1 +#if defined(CONFIG_TARGET_COLIBRI_IMX6ULL_EMMC) +#define UBOOT_UPDATE \ + "uboot_hwpart=1\0" \ + "uboot_blk=2\0" \ + "set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \ + "setexpr blkcnt ${blkcnt} / 0x200\0" \ + "update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \ + "mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" +#elif defined(CONFIG_TARGET_COLIBRI_IMX6ULL_NAND) +#define UBOOT_UPDATE \ + "update_uboot=nand erase.part u-boot1 && " \ + "nand write ${loadaddr} u-boot1 ${filesize} && " \ + "nand erase.part u-boot2 && " \ + "nand write ${loadaddr} u-boot2 ${filesize}\0" +#endif + #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "fdt_addr_r=0x82100000\0" \ @@ -34,12 +50,6 @@ "ramdisk_addr_r=0x82200000\0" \ "scriptaddr=0x87000000\0" -#define UBOOT_UPDATE \ - "update_uboot=nand erase.part u-boot1 && " \ - "nand write ${loadaddr} u-boot1 ${filesize} && " \ - "nand erase.part u-boot2 && " \ - "nand write ${loadaddr} u-boot2 ${filesize}\0" - #define NFS_BOOTCMD \ "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ "nfsboot=run setup; " \ @@ -60,17 +70,32 @@ "ubi read ${fdt_addr_r} dtb && " \ "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ +#if defined(CONFIG_TARGET_COLIBRI_IMX6ULL_NAND) /* Run Distro Boot script if ubiboot fails */ #define CONFIG_BOOTCOMMAND "run ubiboot || run distro_bootcmd;" +#define DFU_ALT_NAND_INFO "imx6ull-bcb part 0,1;u-boot1 part 0,2;u-boot2 part 0,3;u-boot-env part 0,4;ubi partubi 0,5" +#define MODULE_EXTRA_ENV_SETTINGS \ + "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + UBI_BOOTCMD +#else +#define MODULE_EXTRA_ENV_SETTINGS "" +#endif +#if defined(CONFIG_TARGET_COLIBRI_IMX6ULL_NAND) +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#elif defined(CONFIG_TARGET_COLIBRI_IMX6ULL_EMMC) #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(DHCP, dhcp, na) +#endif #include -#define DFU_ALT_NAND_INFO "imx6ull-bcb part 0,1;u-boot1 part 0,2;u-boot2 part 0,3;u-boot-env part 0,4;ubi partubi 0,5" - #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ @@ -80,12 +105,10 @@ "bootubipart=ubi\0" \ "console=ttymxc0\0" \ "defargs=user_debug=30\0" \ - "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ "fdt_board=eval-v3\0" \ "fdt_fixup=;\0" \ "ip_dyn=yes\0" \ "kernel_file=zImage\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ "${board}/flash_eth.img && source ${loadaddr}\0" \ @@ -117,10 +140,16 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) +/* environment organization */ + +/* Environment in eMMC, before config block at the end of 1st "boot sector" */ + +#ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */ #define CONFIG_SYS_NAND_BASE -1 +#endif /* USB Configs */ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET -- cgit v1.2.3 From b65dc989a779d17a140685e823aa875943956442 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 16 Aug 2021 18:44:32 +0800 Subject: imx8mp_evk: Enable the DWC EQoS iMX driver Enable the EQoS i.MX driver in defconfig, also enable the PHYLIB to facilitate the case that only has FEC enabled. Signed-off-by: Ye Li --- configs/imx8mp_evk_defconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'configs') diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 0abe137027..c507b5823c 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -73,9 +73,12 @@ CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y CONFIG_PHY_REALTEK=y +CONFIG_PHYLIB=y CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y CONFIG_PHY_GIGE=y CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y -- cgit v1.2.3