From 92309aacda21cbdbb2c68bed9275006b2b7bade9 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Sat, 24 Jul 2021 10:40:34 -0700 Subject: imx: ventana: replace hard-coded LED config with dt based config Use device-tree LED config instead of hard-coded board-specific config. Signed-off-by: Tim Harvey --- configs/gwventana_emmc_defconfig | 3 +++ configs/gwventana_gw5904_defconfig | 3 +++ configs/gwventana_nand_defconfig | 3 +++ 3 files changed, 9 insertions(+) (limited to 'configs') diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index 4017467acc..9e764f40a2 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -80,6 +80,9 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index cbf1d3d990..bab61e7daa 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -80,6 +80,9 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index baeef2b958..e59efebab7 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -82,6 +82,9 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y -- cgit v1.2.3 From a8a72c3ce9edc3fa9d9bb729cebbf77a445cb662 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 27 Jul 2021 15:19:41 -0700 Subject: board: gateworks: venice: add imx8mm-gw7902 support The GW7902 is based on the i.MX 8M Mini / Nano SoC featuring: - LPDDR4 DRAM - eMMC FLASH - Gateworks System Controller - LTE CAT M1 modem - USB 2.0 HUB - M.2 Socket with USB2.0, PCIe, and dual-SIM - IMX8M FEC - PCIe based GbE - RS232/RS485/RS422 serial transceiver - GPS - CAN bus - WiFi / Bluetooth - MIPI header (DSI/CSI/GPIO/PWM/I2S) - PMIC Do the following to add support for it: - add dts - add PMIC config Signed-off-by: Tim Harvey --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi | 80 +++ arch/arm/dts/imx8mm-venice-gw7902.dts | 927 ++++++++++++++++++++++++++ board/gateworks/venice/lpddr4_timing.c | 516 ++++++++++++++ board/gateworks/venice/lpddr4_timing.h | 1 + board/gateworks/venice/spl.c | 11 +- configs/imx8mm_venice_defconfig | 2 +- 7 files changed, 1535 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mm-venice-gw7902.dts (limited to 'configs') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 537c96bf5b..bec349f17e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -870,6 +870,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-venice-gw72xx-0x.dtb \ imx8mm-venice-gw73xx-0x.dtb \ imx8mm-venice-gw7901.dtb \ + imx8mm-venice-gw7902.dtb \ imx8mm-verdin.dtb \ phycore-imx8mm.dtb \ imx8mn-ddr4-evk.dtb \ diff --git a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi new file mode 100644 index 0000000000..361ddaa78f --- /dev/null +++ b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Gateworks Corporation + */ + +#include "imx8mm-u-boot.dtsi" + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&usdhc3 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&i2c2 { + u-boot,dm-spl; +}; + +&pinctrl_i2c2 { + u-boot,dm-spl; +}; + +&fec1 { + phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + phy-reset-post-delay = <1>; +}; + +&pinctrl_fec1 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mm-venice-gw7902.dts b/arch/arm/dts/imx8mm-venice-gw7902.dts new file mode 100644 index 0000000000..2948821644 --- /dev/null +++ b/arch/arm/dts/imx8mm-venice-gw7902.dts @@ -0,0 +1,927 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 Gateworks Corporation + */ + +/dts-v1/; + +#include +#include +#include +#include + +#include "imx8mm.dtsi" + +/ { + model = "Gateworks Venice GW7902 i.MX8MM board"; + compatible = "gw,imx8mm-gw7902", "fsl,imx8mm"; + + aliases { + usb0 = &usbotg1; + usb1 = &usbotg2; + }; + + chosen { + stdout-path = &uart2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + can20m: can20m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + clock-output-names = "can20m"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key_erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = ; + label = "panel1"; + gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + label = "panel2"; + gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-2 { + function = LED_FUNCTION_STATUS; + color = ; + label = "panel3"; + gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-3 { + function = LED_FUNCTION_STATUS; + color = ; + label = "panel4"; + gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-4 { + function = LED_FUNCTION_STATUS; + color = ; + label = "panel5"; + gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb1_vbus: regulator-usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1>; + compatible = "regulator-fixed"; + regulator-name = "usb_usb1_vbus"; + gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_wifi: regulator-wifi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wl>; + compatible = "regulator-fixed"; + regulator-name = "wifi"; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&can20m>; + oscillator-frequency = <20000000>; + interrupt-parent = <&gpio2>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <10000000>; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + local-mac-address = [00 00 00 00 00 00]; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + tx-fifo-depth = ; + rx-fifo-depth = ; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + pinctrl-0 = <&pinctrl_gsc>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <1>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vin"; + gw,voltage-divider-ohms = <22100 1000>; + gw,voltage-offset-microvolt = <700000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vin_4p0"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_0p9"; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_soc"; + }; + + channel@8e { + gw,mode = <2>; + reg = <0x8e>; + label = "vdd_arm"; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_1p8"; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_dram"; + }; + + channel@98 { + gw,mode = <2>; + reg = <0x98>; + label = "vdd_1p0"; + }; + + channel@9a { + gw,mode = <2>; + reg = <0x9a>; + label = "vdd_2p5"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + }; + + gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio3>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + #clock-cells = <0>; + clocks = <&osc_32k 0>; + clock-output-names = "clk-32k-out"; + + regulators { + /* vdd_soc: 0.805-0.900V (typ=0.8V) */ + BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + /* vdd_arm: 0.805-1.0V (typ=0.9V) */ + buck2: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ + BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_3p3 */ + BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_1p8 */ + BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_dram */ + BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + /* nvcc_snvs_1p8 */ + LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_snvs_0p8 */ + LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdda_1p8 */ + LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + accelerometer@19 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + compatible = "st,lis2de12"; + reg = <0x19>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "INT1"; + }; + + secure-element@60 { + compatible = "nxp,se050"; + reg = <0x60>; + }; +}; + +/* off-board header */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +/* off-board header */ +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +/* off-board header */ +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +/* RS232/RS485/RS422 selectable */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; + rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* RS232 console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* bluetooth HCI */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; + rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + }; +}; + +/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + vbus-supply = <®_usb1_vbus>; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +/* SDIO WiFi */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wifi>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* M2_RST# */ + MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */ + MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */ + MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */ + MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */ + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */ + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */ + >; + }; + + pinctrl_accel: accelgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ + MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141 + MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141 + >; + }; + + pinctrl_gsc: gscgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x40000019 + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x40000019 + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x40000019 + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x40000019 + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000019 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */ + >; + }; + + pinctrl_reg_wl: regwlgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */ + >; + }; + + pinctrl_reg_usb1: regusb1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + >; + }; + + pinctrl_spi1: spi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40 + MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */ + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 /* RTS */ + MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 /* CTS */ + >; + }; + + pinctrl_uart1_gpio: uart1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */ + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */ + MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3_gpio: uart3_gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */ + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */ + MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x140 /* CTS */ + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x140 /* RTS */ + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* DTR */ + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x140 /* DSR */ + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* DCD */ + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* RI */ + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x140 /* GNSS_PPS */ + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; + +&cpu_alert0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; +}; + +&cpu_crit0 { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; +}; diff --git a/board/gateworks/venice/lpddr4_timing.c b/board/gateworks/venice/lpddr4_timing.c index 47e93e1236..f362d9741c 100644 --- a/board/gateworks/venice/lpddr4_timing.c +++ b/board/gateworks/venice/lpddr4_timing.c @@ -2503,3 +2503,519 @@ struct dram_timing_info dram_timing_4gb = { .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), .fsp_table = { 3000, 400, 100, }, }; + +static struct dram_cfg_param lpddr4_ddrc_cfg_2gb[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x223 }, + { 0x3d400024, 0x3a980 }, + { 0x3d400064, 0x5b00d2 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x66004d }, + { 0x3d4000ec, 0x16004d }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x1f }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d400250, 0x29001701 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x21 }, + { 0x3d402024, 0x7d00 }, + { 0x3d402050, 0x20d040 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004d }, + { 0x3d4020ec, 0x16004d }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x21 }, + { 0x3d403024, 0x1f40 }, + { 0x3d403050, 0x20d040 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x310000 }, + { 0x3d4030e8, 0x66004d }, + { 0x3d4030ec, 0x16004d }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param lpddr4_ddrphy_cfg_2gb[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x2 }, + { 0x110a3, 0x3 }, + { 0x110a4, 0x4 }, + { 0x110a5, 0x5 }, + { 0x110a6, 0x6 }, + { 0x110a7, 0x7 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x5 }, + { 0x130a3, 0x2 }, + { 0x130a4, 0x3 }, + { 0x130a5, 0x4 }, + { 0x130a6, 0x7 }, + { 0x130a7, 0x6 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x120024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x220024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0xdc }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0xdc }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0xdc }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x200c7, 0x21 }, + { 0x1200c7, 0x21 }, + { 0x2200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x1200ca, 0x24 }, + { 0x2200ca, 0x24 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_cfg_2gb[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp1_cfg_2gb[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp2_cfg_2gb[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_2d_cfg_2gb[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_fsp_msg lpddr4_dram_fsp_msg_2gb[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg_2gb, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg_2gb), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg_2gb, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg_2gb), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp2_cfg_2gb, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg_2gb), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg_2gb, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg_2gb), + }, +}; + +/* lpddr4 timing config params */ +struct dram_timing_info dram_timing_2gb = { + .ddrc_cfg = lpddr4_ddrc_cfg_2gb, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_2gb), + .ddrphy_cfg = lpddr4_ddrphy_cfg_2gb, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg_2gb), + .fsp_msg = lpddr4_dram_fsp_msg_2gb, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg_2gb), + .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; diff --git a/board/gateworks/venice/lpddr4_timing.h b/board/gateworks/venice/lpddr4_timing.h index 94445f86a4..b73d067f7d 100644 --- a/board/gateworks/venice/lpddr4_timing.h +++ b/board/gateworks/venice/lpddr4_timing.h @@ -7,6 +7,7 @@ #define __LPDDR4_TIMING_H__ extern struct dram_timing_info dram_timing_1gb; +extern struct dram_timing_info dram_timing_2gb; extern struct dram_timing_info dram_timing_4gb; #endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index aada55ee27..b819c6846d 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -44,6 +44,9 @@ static void spl_dram_init(int size) case 1: dram_timing = &dram_timing_1gb; break; + case 2: + dram_timing = &dram_timing_2gb; + break; case 4: dram_timing = &dram_timing_4gb; break; @@ -133,8 +136,12 @@ static int power_init_board(void) BIT(7) | MP5416_VSET_SW3_SVAL(920000)); } - else if (!strncmp(model, "GW7901", 6)) { - ret = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus); + else if ((!strncmp(model, "GW7901", 6)) || + (!strncmp(model, "GW7902", 6))) { + if (!strncmp(model, "GW7901", 6)) + ret = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus); + else + ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); if (ret) { printf("PMIC : failed I2C2 probe: %d\n", ret); return ret; diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index e10f1b2f80..3da3fad7a0 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -58,7 +58,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x imx8mm-venice-gw7901" +CONFIG_OF_LIST="imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x imx8mm-venice-gw7901 imx8mm-venice-gw7902" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -- cgit v1.2.3 From 0ac226b3c6b7517763c52bb00907dbca08392ee8 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 29 Jul 2021 21:24:58 -0300 Subject: mx7dsabresd: Select CONFIG_IMX_HAB Select CONFIG_IMX_HAB so that the "hab_status" command becomes available, which is useful for checking if the chip has been correctly setup to run in secure boot mode. Signed-off-by: Fabio Estevam --- configs/mx7dsabresd_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'configs') diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index d3079c1d9e..39e73042bf 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -11,6 +11,7 @@ CONFIG_TARGET_MX7DSABRESD=y # CONFIG_ARMV7_VIRT is not set CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y +CONFIG_IMX_HAB=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" -- cgit v1.2.3 From 1d1f3c809973ce8b107b43cab0bec946251b1d3c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 17 Feb 2021 23:39:28 -0300 Subject: mx28evk: Convert to driver model Make the conversion to driver model as it is mandatory. Successfully tested booting Linux from the SD card. Dropped support for networking and splash screen as these need to be properly converted to DM and tested. Signed-off-by: Fabio Estevam --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx28-evk-u-boot.dtsi | 10 +++++ board/freescale/mx28evk/MAINTAINERS | 1 + board/freescale/mx28evk/mx28evk.c | 77 ------------------------------------- configs/mx28evk_defconfig | 18 +++++++-- include/configs/mx28evk.h | 7 ---- 6 files changed, 26 insertions(+), 88 deletions(-) create mode 100644 arch/arm/dts/imx28-evk-u-boot.dtsi (limited to 'configs') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index bec349f17e..e62f7fc1c5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -680,6 +680,7 @@ dtb-$(CONFIG_TARGET_MX23_OLINUXINO) += \ imx23-olinuxino.dtb dtb-$(CONFIG_MX28) += \ + imx28-evk.dtb \ imx28-xea.dtb dtb-$(CONFIG_MX51) += \ diff --git a/arch/arm/dts/imx28-evk-u-boot.dtsi b/arch/arm/dts/imx28-evk-u-boot.dtsi new file mode 100644 index 0000000000..6adbae68d2 --- /dev/null +++ b/arch/arm/dts/imx28-evk-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + */ + +#include "imx28-u-boot.dtsi" + diff --git a/board/freescale/mx28evk/MAINTAINERS b/board/freescale/mx28evk/MAINTAINERS index 597118d3f6..c565010ccf 100644 --- a/board/freescale/mx28evk/MAINTAINERS +++ b/board/freescale/mx28evk/MAINTAINERS @@ -2,6 +2,7 @@ MX28EVK BOARD M: Fabio Estevam S: Maintained F: board/freescale/mx28evk/ +F: arch/arm/dts/imx28-evk.dts F: include/configs/mx28evk.h F: configs/mx28evk_defconfig F: configs/mx28evk_auart_console_defconfig diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c index 21c9cb1128..88c3bf3608 100644 --- a/board/freescale/mx28evk/mx28evk.c +++ b/board/freescale/mx28evk/mx28evk.c @@ -72,80 +72,3 @@ int board_init(void) return 0; } - -#ifdef CONFIG_CMD_MMC -static int mx28evk_mmc_wp(int id) -{ - if (id != 0) { - printf("MXS MMC: Invalid card selected (card id = %d)\n", id); - return 1; - } - - return gpio_get_value(MX28_PAD_SSP1_SCK__GPIO_2_12); -} - -int board_mmc_init(struct bd_info *bis) -{ - /* Configure WP as input */ - gpio_direction_input(MX28_PAD_SSP1_SCK__GPIO_2_12); - - /* Configure MMC0 Power Enable */ - gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); - - return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp, NULL); -} -#endif - -#ifdef CONFIG_CMD_NET - -int board_eth_init(struct bd_info *bis) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - struct eth_device *dev; - int ret; - - ret = cpu_eth_init(bis); - if (ret) - return ret; - - /* MX28EVK uses ENET_CLK PAD to drive FEC clock */ - writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, - &clkctrl_regs->hw_clkctrl_enet); - - /* Power-on FECs */ - gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0); - - /* Reset FEC PHYs */ - gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); - udelay(200); - gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); - - ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); - if (ret) { - puts("FEC MXS: Unable to init FEC0\n"); - return ret; - } - - ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE); - if (ret) { - puts("FEC MXS: Unable to init FEC1\n"); - return ret; - } - - dev = eth_get_dev_by_name("FEC0"); - if (!dev) { - puts("FEC MXS: Unable to get FEC0 device entry\n"); - return -EINVAL; - } - - dev = eth_get_dev_by_name("FEC1"); - if (!dev) { - puts("FEC MXS: Unable to get FEC1 device entry\n"); - return -EINVAL; - } - - return ret; -} - -#endif diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig index 300ab08c82..3345ec611a 100644 --- a/configs/mx28evk_defconfig +++ b/configs/mx28evk_defconfig @@ -7,10 +7,12 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x40000 +CONFIG_DM_GPIO=y CONFIG_SPL_TEXT_BASE=0x00001000 CONFIG_TARGET_MX28EVK=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx28-evk" CONFIG_FIT=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set @@ -18,13 +20,11 @@ CONFIG_ARCH_MISC_INIT=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT4=y @@ -35,18 +35,28 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_SPL_DM=y CONFIG_MXS_GPIO=y +CONFIG_DM_MMC=y CONFIG_MMC_MXS=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_MXS=y CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MXS=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_CONS_INDEX=0 CONFIG_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_SPLASH_SCREEN=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index a65df48608..21f3277d5c 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -31,13 +31,6 @@ /* UBI and NAND partitioning */ -/* FEC Ethernet on SoC */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_MDIO_BASE MXS_ENET0_BASE -#define CONFIG_MX28_FEC_MAC_IN_OCOTP -#endif - /* RTC */ #ifdef CONFIG_CMD_DATE #define CONFIG_RTC_MXS -- cgit v1.2.3 From c10bf27615a07e07722c66fd28b57ae5db969288 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 27 Jul 2021 15:19:33 -0700 Subject: configs: imx8mm_venice_defconfig: remove unused SPL features remove unused SPL features to shink the size of the SPL which otherwise would no longer fit into IMX8M Mini OCRAM. Signed-off-by: Tim Harvey --- configs/imx8mm_venice_defconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'configs') diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 3da3fad7a0..d8d930ab4d 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -26,7 +26,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_LOAD_FIT_FULL=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" -- cgit v1.2.3 From 2eb85647c0e76a3be9616d67765eb8fa74ea7481 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 27 Jul 2021 15:19:40 -0700 Subject: board: gateworks: venice: add board model to dt Add the specific board model from EEPROM config to the device-tree to make it easier to access from Linux userspace. Signed-off-by: Tim Harvey --- board/gateworks/venice/imx8mm_venice.c | 8 ++++++++ configs/imx8mm_venice_defconfig | 1 + 2 files changed, 9 insertions(+) (limited to 'configs') diff --git a/board/gateworks/venice/imx8mm_venice.c b/board/gateworks/venice/imx8mm_venice.c index ca01e75d0d..2a97d55d32 100644 --- a/board/gateworks/venice/imx8mm_venice.c +++ b/board/gateworks/venice/imx8mm_venice.c @@ -152,3 +152,11 @@ int board_mmc_get_env_dev(int devno) { return devno; } + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* set board model dt prop */ + fdt_setprop_string(blob, 0, "board", gsc_get_model()); + + return 0; +} diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index d8d930ab4d..44ff5f84da 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -27,6 +27,7 @@ CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" # CONFIG_USE_BOOTCOMMAND is not set -- cgit v1.2.3 From 3f2b4d7220c3a957f6dc0a0954fde40e94b25b8a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sat, 7 Aug 2021 16:01:13 +0800 Subject: arm: imx: add i.MX8ULP EVK support Add i.MX8ULP EVK basic support, support SD/I2C/ENET/LPUART Log as below: I would keep some debug info for now, and after we move to be stable and production launch, we could drop that. U-Boot SPL 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) Normal Boot upower_init: soc_id=48 upower_init: version:11.11.6 upower_init: start uPower RAM service user_upwr_rdy_callb: soc=b user_upwr_rdy_callb: RAM version:12.6 Turn on switches ok Turn on memories ok Clear DDR retention ok Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F0 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. complete De-Skew PLL is locked and ready WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x3a800 by ROM_API NOTICE: BL31: v2.4(release):imx_5.10.35_2.0.0_imx8ulp_er-10-gf37e59b94 NOTICE: BL31: Built : 01:56:58, Jun 29 2021 NOTICE: upower_init: start uPower RAM service NOTICE: user_upwr_rdy_callb: soc=b NOTICE: user_upwr_rdy_callb: RAM version:12.6 U-Boot 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) CPU: Freescale i.MX8ULP rev1.0 at 744 MHz Reset cause: POR Boot mode: Single boot Model: FSL i.MX8ULP EVK DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@293a0000 Out: serial@293a0000 Err: serial@293a0000 Net: Warning: ethernet@29950000 (eth0) using random MAC address - 96:35:88:62:e0:44 eth0: ethernet@29950000 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan --- arch/arm/dts/Makefile | 3 + arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 40 + arch/arm/dts/imx8ulp-evk.dts | 223 ++++++ arch/arm/mach-imx/imx8ulp/Kconfig | 7 + board/freescale/imx8ulp_evk/Kconfig | 14 + board/freescale/imx8ulp_evk/MAINTAINERS | 6 + board/freescale/imx8ulp_evk/Makefile | 7 + board/freescale/imx8ulp_evk/ddr_init.c | 207 +++++ board/freescale/imx8ulp_evk/imx8ulp_evk.c | 67 ++ board/freescale/imx8ulp_evk/lpddr4_timing.c | 1158 +++++++++++++++++++++++++++ board/freescale/imx8ulp_evk/spl.c | 105 +++ configs/imx8ulp_evk_defconfig | 103 +++ include/configs/imx8ulp_evk.h | 107 +++ 13 files changed, 2047 insertions(+) create mode 100644 arch/arm/dts/imx8ulp-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx8ulp-evk.dts create mode 100644 board/freescale/imx8ulp_evk/Kconfig create mode 100644 board/freescale/imx8ulp_evk/MAINTAINERS create mode 100644 board/freescale/imx8ulp_evk/Makefile create mode 100644 board/freescale/imx8ulp_evk/ddr_init.c create mode 100644 board/freescale/imx8ulp_evk/imx8ulp_evk.c create mode 100644 board/freescale/imx8ulp_evk/lpddr4_timing.c create mode 100644 board/freescale/imx8ulp_evk/spl.c create mode 100644 configs/imx8ulp_evk_defconfig create mode 100644 include/configs/imx8ulp_evk.h (limited to 'configs') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e62f7fc1c5..c42715ead4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -862,6 +862,9 @@ dtb-$(CONFIG_ARCH_IMX8) += \ imx8-deneb.dtb \ imx8-giedi.dtb +dtb-$(CONFIG_ARCH_IMX8ULP) += \ + imx8ulp-evk.dtb + dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-evk.dtb \ imx8mm-icore-mx8mm-ctouch2.dtb \ diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi new file mode 100644 index 0000000000..7c1dab2acf --- /dev/null +++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 NXP + */ + +&{/soc@0} { + u-boot,dm-spl; +}; + +&per_bridge3 { + u-boot,dm-spl; +}; + +&per_bridge4 { + u-boot,dm-spl; +}; + +&iomuxc1 { + u-boot,dm-spl; +}; + +&pinctrl_lpuart5 { + u-boot,dm-spl; +}; + +&s400_mu { + u-boot,dm-spl; +}; + +&lpuart5 { + u-boot,dm-spl; +}; + +&usdhc0 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc0 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8ulp-evk.dts b/arch/arm/dts/imx8ulp-evk.dts new file mode 100644 index 0000000000..da09ff48ff --- /dev/null +++ b/arch/arm/dts/imx8ulp-evk.dts @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 NXP + */ + +/dts-v1/; + +#include "imx8ulp.dtsi" + +/ { + model = "FSL i.MX8ULP EVK"; + compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp"; + + chosen { + stdout-path = &lpuart5; + bootargs = "console=ttyLP1,115200 earlycon"; + }; + + usdhc2_pwrseq: usdhc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6408 2 GPIO_ACTIVE_LOW>; + }; +}; + +&lpuart5 { + /* console */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpuart5>; + pinctrl-1 = <&pinctrl_lpuart5>; + status = "okay"; +}; + +&iomuxc1 { + pinctrl_lpuart5: lpuart5grp { + fsl,pins = < + MX8ULP_PAD_PTF14__LPUART5_TX 0x03 + MX8ULP_PAD_PTF15__LPUART5_RX 0x03 + >; + }; + + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins = < + MX8ULP_PAD_PTE12__LPI2C7_SCL 0x27 + MX8ULP_PAD_PTE13__LPI2C7_SDA 0x27 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x43 + MX8ULP_PAD_PTD1__SDHC0_CMD 0x43 + MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042 + MX8ULP_PAD_PTD10__SDHC0_D0 0x43 + MX8ULP_PAD_PTD9__SDHC0_D1 0x43 + MX8ULP_PAD_PTD8__SDHC0_D2 0x43 + MX8ULP_PAD_PTD7__SDHC0_D3 0x43 + MX8ULP_PAD_PTD6__SDHC0_D4 0x43 + MX8ULP_PAD_PTD5__SDHC0_D5 0x43 + MX8ULP_PAD_PTD4__SDHC0_D6 0x43 + MX8ULP_PAD_PTD3__SDHC0_D7 0x43 + MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042 + >; + }; + + pinctrl_usdhc2_pte: usdhc2ptegrp { + fsl,pins = < + MX8ULP_PAD_PTE1__SDHC2_D0 0x43 + MX8ULP_PAD_PTE0__SDHC2_D1 0x43 + MX8ULP_PAD_PTE5__SDHC2_D2 0x43 + MX8ULP_PAD_PTE4__SDHC2_D3 0x43 + MX8ULP_PAD_PTE2__SDHC2_CLK 0x10042 + MX8ULP_PAD_PTE3__SDHC2_CMD 0x43 + MX8ULP_PAD_PTE7__PTE7 0x10003 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8ULP_PAD_PTE14__ENET0_MDIO 0x43 + MX8ULP_PAD_PTE15__ENET0_MDC 0x43 + MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43 + MX8ULP_PAD_PTE17__ENET0_RXER 0x43 + MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 + MX8ULP_PAD_PTE20__ENET0_RXD1 0x43 + MX8ULP_PAD_PTE16__ENET0_TXEN 0x43 + MX8ULP_PAD_PTE23__ENET0_TXD0 0x43 + MX8ULP_PAD_PTE22__ENET0_TXD1 0x43 + MX8ULP_PAD_PTE19__ENET0_REFCLK 0x10043 + MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x10043 + >; + }; + + pinctrl_usbotg0_id: otg0idgrp { + fsl,pins = < + MX8ULP_PAD_PTF2__USB0_ID 0x10003 + >; + }; + + pinctrl_usbotg1_id: otg1idgrp { + fsl,pins = < + MX8ULP_PAD_PTD23__USB1_ID 0x10003 + >; + }; +}; + +&usdhc0 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2_pte>; + pinctrl-1 = <&pinctrl_usdhc2_pte>; + pinctrl-2 = <&pinctrl_usdhc2_pte>; + pinctrl-3 = <&pinctrl_usdhc2_pte>; + mmc-pwrseq = <&usdhc2_pwrseq>; + max-frequency = <100000000>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&gpioe>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&lpi2c7 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c7>; + status = "okay"; + + pcal6408: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&flexspi0 { + status = "okay"; + + flash0: atxp032@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <66000000>; + }; +}; + +&flexspi2 { + status = "okay"; + + flash1: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-handle = <ðphy>; + status = "okay"; + + phy-reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@1 { + reg = <1>; + micrel,led-mode = <1>; + }; + }; +}; + +&usbotg0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg0_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphy0 { + fsl,tx-d-cal = <88>; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <88>; +}; diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-imx/imx8ulp/Kconfig index 167dbb3fb1..963fc93d34 100644 --- a/arch/arm/mach-imx/imx8ulp/Kconfig +++ b/arch/arm/mach-imx/imx8ulp/Kconfig @@ -11,6 +11,13 @@ choice prompt "i.MX8ULP board select" optional +config TARGET_IMX8ULP_EVK + bool "imx8ulp_evk" + select IMX8ULP + select SUPPORT_SPL + endchoice +source "board/freescale/imx8ulp_evk/Kconfig" + endif diff --git a/board/freescale/imx8ulp_evk/Kconfig b/board/freescale/imx8ulp_evk/Kconfig new file mode 100644 index 0000000000..1e461ee1da --- /dev/null +++ b/board/freescale/imx8ulp_evk/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8ULP_EVK + +config SYS_BOARD + default "imx8ulp_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8ulp_evk" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8ulp_evk/MAINTAINERS b/board/freescale/imx8ulp_evk/MAINTAINERS new file mode 100644 index 0000000000..267b7b0caa --- /dev/null +++ b/board/freescale/imx8ulp_evk/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8ULP EVK BOARD +M: Peng Fan +S: Maintained +F: board/freescale/imx8ulp_evk/ +F: include/configs/imx8ulp_evk.h +F: configs/imx8ulp_evk_defconfig diff --git a/board/freescale/imx8ulp_evk/Makefile b/board/freescale/imx8ulp_evk/Makefile new file mode 100644 index 0000000000..b2e72b4e85 --- /dev/null +++ b/board/freescale/imx8ulp_evk/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += imx8ulp_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o ddr_init.o lpddr4_timing.o +endif diff --git a/board/freescale/imx8ulp_evk/ddr_init.c b/board/freescale/imx8ulp_evk/ddr_init.c new file mode 100644 index 0000000000..f4238d29b3 --- /dev/null +++ b/board/freescale/imx8ulp_evk/ddr_init.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2021 NXP + */ +#include +#include +#include +#include +#include + +#define DENALI_CTL_00 (DDR_CTL_BASE_ADDR) +#define CTL_START 0x1 + +#define DENALI_CTL_03 (DDR_CTL_BASE_ADDR + 4 * 3) +#define DENALI_CTL_197 (DDR_CTL_BASE_ADDR + 4 * 197) +#define DENALI_CTL_250 (DDR_CTL_BASE_ADDR + 4 * 250) +#define DENALI_CTL_251 (DDR_CTL_BASE_ADDR + 4 * 251) +#define DENALI_CTL_266 (DDR_CTL_BASE_ADDR + 4 * 266) +#define DFI_INIT_COMPLETE 0x2 + +#define DENALI_CTL_614 (DDR_CTL_BASE_ADDR + 4 * 614) +#define DENALI_CTL_615 (DDR_CTL_BASE_ADDR + 4 * 615) + +#define DENALI_PI_00 (DDR_PI_BASE_ADDR) +#define PI_START 0x1 + +#define DENALI_PI_04 (DDR_PI_BASE_ADDR + 4 * 4) +#define DENALI_PI_11 (DDR_PI_BASE_ADDR + 4 * 11) +#define DENALI_PI_12 (DDR_PI_BASE_ADDR + 4 * 12) +#define DENALI_CTL_23 (DDR_CTL_BASE_ADDR + 4 * 23) +#define DENALI_CTL_25 (DDR_CTL_BASE_ADDR + 4 * 25) + +#define DENALI_PHY_1624 (DDR_PHY_BASE_ADDR + 4 * 1624) +#define DENALI_PHY_1537 (DDR_PHY_BASE_ADDR + 4 * 1537) +#define PHY_FREQ_SEL_MULTICAST_EN(X) ((X) << 8) +#define PHY_FREQ_SEL_INDEX(X) ((X) << 16) + +#define DENALI_PHY_1547 (DDR_PHY_BASE_ADDR + 4 * 1547) +#define DENALI_PHY_1555 (DDR_PHY_BASE_ADDR + 4 * 1555) +#define DENALI_PHY_1564 (DDR_PHY_BASE_ADDR + 4 * 1564) +#define DENALI_PHY_1565 (DDR_PHY_BASE_ADDR + 4 * 1565) + +int ddr_calibration(unsigned int fsp_table[3]) +{ + u32 reg_val; + u32 int_status_init, phy_freq_req, phy_freq_type; + u32 lock_0, lock_1, lock_2; + u32 freq_chg_pt, freq_chg_cnt; + + reg_val = readl(DENALI_CTL_250); + if (((reg_val >> 16) & 0x3) == 1) + freq_chg_cnt = 2; + else + freq_chg_cnt = 3; + + reg_val = readl(DENALI_PI_12); + if (reg_val == 0x3) { + freq_chg_pt = 1; + } else if (reg_val == 0x7) { + freq_chg_pt = 2; + } else { + printf("frequency map(0x%x) is wrong, please check!\r\n", reg_val); + return -1; + } + + debug("%s\n", __func__); + + /* Assert PI_START parameter and then assert START parameter in Controller. */ + reg_val = readl(DENALI_PI_00) | PI_START; + writel(reg_val, DENALI_PI_00); + + reg_val = readl(DENALI_CTL_00) | CTL_START; + writel(reg_val, DENALI_CTL_00); + + /* Poll for init_done_bit in Controller interrupt status register (INT_STATUS_INIT) */ + do { + if (!freq_chg_cnt) { + int_status_init = (readl(DENALI_CTL_266) >> 8) & 0xff; + /* DDR subsystem is ready for traffic. */ + if (int_status_init & DFI_INIT_COMPLETE) { + printf("complete\n"); + break; + } + } + + /* + * During leveling, PHY will request for freq change and SoC clock + * logic should provide requested frequency, Polling SIM LPDDR_CTRL2 + * Bit phy_freq_chg_req until be 1'b1 + */ + reg_val = readl(AVD_SIM_LPDDR_CTRL2); + phy_freq_req = (reg_val >> 7) & 0x1; + + if (phy_freq_req) { + phy_freq_type = reg_val & 0x1F; + if (!phy_freq_type) { + printf("Poll for freq_chg_req on SIM register and change to F0 frequency.\n"); + set_ddr_clk(fsp_table[phy_freq_type] >> 1); + + /* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */ + reg_val = readl(AVD_SIM_LPDDR_CTRL2); + writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2); + } else if (phy_freq_type == 0x01) { + printf("Poll for freq_chg_req on SIM register and change to F1 frequency.\n"); + set_ddr_clk(fsp_table[phy_freq_type] >> 1); + + /* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */ + reg_val = readl(AVD_SIM_LPDDR_CTRL2); + writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2); + if (freq_chg_pt == 1) + freq_chg_cnt--; + } else if (phy_freq_type == 0x02) { + printf("Poll for freq_chg_req on SIM register and change to F2 frequency.\n"); + set_ddr_clk(fsp_table[phy_freq_type] >> 1); + + /* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */ + reg_val = readl(AVD_SIM_LPDDR_CTRL2); + writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2); + if (freq_chg_pt == 2) + freq_chg_cnt--; + } + reg_val = readl(AVD_SIM_LPDDR_CTRL2); + } + } while (1); + + /* Check PLL lock status */ + lock_0 = readl(DENALI_PHY_1564) & 0xffff; + lock_1 = (readl(DENALI_PHY_1564) >> 16) & 0xffff; + lock_2 = readl(DENALI_PHY_1565) & 0xffff; + + if ((lock_0 & 0x3) != 0x3 || (lock_1 & 0x3) != 0x3 || (lock_2 & 0x3) != 0x3) { + printf("De-Skew PLL failed to lock\n"); + printf("lock_0=0x%x, lock_1=0x%x, lock_2=0x%x\n", lock_0, lock_1, lock_2); + return -1; + } + + printf("De-Skew PLL is locked and ready\n"); + return 0; +} + +int ddr_init(struct dram_timing_info2 *dram_timing) +{ + int i; + + debug("%s\n", __func__); + + set_ddr_clk(dram_timing->fsp_table[0] >> 1); /* Set to boot freq */ + + /* Initialize CTL registers */ + for (i = 0; i < dram_timing->ctl_cfg_num; i++) + writel(dram_timing->ctl_cfg[i].val, (ulong)dram_timing->ctl_cfg[i].reg); + + /* Initialize PI registers */ + for (i = 0; i < dram_timing->pi_cfg_num; i++) + writel(dram_timing->pi_cfg[i].val, (ulong)dram_timing->pi_cfg[i].reg); + + /* Write PHY regiters for all 3 frequency points (48Mhz/384Mhz/528Mhz): f1_index=0 */ + writel(PHY_FREQ_SEL_MULTICAST_EN(1) | PHY_FREQ_SEL_INDEX(0), DENALI_PHY_1537); + for (i = 0; i < dram_timing->phy_f1_cfg_num; i++) + writel(dram_timing->phy_f1_cfg[i].val, (ulong)dram_timing->phy_f1_cfg[i].reg); + + /* Write PHY regiters for freqency point 2 (528Mhz): f2_index=1 */ + writel(PHY_FREQ_SEL_MULTICAST_EN(0) | PHY_FREQ_SEL_INDEX(1), DENALI_PHY_1537); + for (i = 0; i < dram_timing->phy_f2_cfg_num; i++) + writel(dram_timing->phy_f2_cfg[i].val, (ulong)dram_timing->phy_f2_cfg[i].reg); + + /* Re-enable MULTICAST mode */ + writel(PHY_FREQ_SEL_MULTICAST_EN(1) | PHY_FREQ_SEL_INDEX(0), DENALI_PHY_1537); + + return ddr_calibration(dram_timing->fsp_table); +} + +void enable_bypass_mode(void) +{ + u32 reg_val; + + /* PI_INIT_LVL_EN=0x0 (DENALI_PI_04) */ + reg_val = readl(DENALI_PI_04) & ~0x1; + writel(reg_val, DENALI_PI_04); + + /* PI_FREQ_MAP=0x1 (DENALI_PI_12) */ + writel(0x1, DENALI_PI_12); + + /* PI_INIT_WORK_FREQ=0x0 (DENALI_PI_11) */ + reg_val = readl(DENALI_PI_11) & ~(0x1f << 8); + writel(reg_val, DENALI_PI_11); + + /* DFIBUS_FREQ_INIT=0x0 (DENALI_CTL_23) */ + reg_val = readl(DENALI_CTL_23) & ~(0x3 << 24); + writel(reg_val, DENALI_CTL_23); + + /* PHY_LP4_BOOT_DISABLE=0x0 (DENALI_PHY_1547) */ + reg_val = readl(DENALI_PHY_1547) & ~(0x1 << 8); + writel(reg_val, DENALI_PHY_1547); + + /* PHY_PLL_BYPASS=0x1 (DENALI_PHY_1624) */ + reg_val = readl(DENALI_PHY_1624) | 0x1; + writel(reg_val, DENALI_PHY_1624); + + /* PHY_LP4_BOOT_PLL_BYPASS to 0x1 (DENALI_PHY_1555) */ + reg_val = readl(DENALI_PHY_1555) | 0x1; + writel(reg_val, DENALI_PHY_1555); + + /* FREQ_CHANGE_TYPE_F0 = 0x0/FREQ_CHANGE_TYPE_F1 = 0x1/FREQ_CHANGE_TYPE_F2 = 0x2 */ + reg_val = 0x020100; + writel(reg_val, DENALI_CTL_25); +} diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c new file mode 100644 index 0000000000..3ff4d43c99 --- /dev/null +++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if IS_ENABLED(CONFIG_FEC_MXC) +#define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_UP | PAD_CTL_DSE | PAD_CTL_IBE_ENABLE) +static iomux_cfg_t const enet_clk_pads[] = { + IMX8ULP_PAD_PTE19__ENET0_REFCLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + IMX8ULP_PAD_PTF10__ENET0_1588_CLKIN | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), +}; + +static int setup_fec(void) +{ + /* + * Since ref clock and timestamp clock are from external, + * set the iomux prior the clock enablement + */ + imx8ulp_iomux_setup_multiple_pads(enet_clk_pads, ARRAY_SIZE(enet_clk_pads)); + + /* Select enet time stamp clock: 001 - External Timestamp Clock */ + cgc1_enet_stamp_sel(1); + + /* enable FEC PCC */ + pcc_clock_enable(4, ENET_PCC4_SLOT, true); + pcc_reset_peripheral(4, ENET_PCC4_SLOT, false); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_FEC_MXC)) + setup_fec(); + + return 0; +} + +int board_early_init_f(void) +{ + return 0; +} + +int board_late_init(void) +{ + return 0; +} diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c b/board/freescale/imx8ulp_evk/lpddr4_timing.c new file mode 100644 index 0000000000..4546e92b01 --- /dev/null +++ b/board/freescale/imx8ulp_evk/lpddr4_timing.c @@ -0,0 +1,1158 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2021 NXP + * + * Generated code from MX8M_DDR_tool + * + */ + +#include +#include + +/** CTL settings **/ +struct dram_cfg_param ddr_ctl_cfg[] = { + { 0x2e060000, 0xb00 }, /* 0 */ + { 0x2e060028, 0x258100 }, /* 10 */ + { 0x2e06002c, 0x17702 }, /* 11 */ + { 0x2e060030, 0x5 }, /* 12 */ + { 0x2e060034, 0x61 }, /* 13 */ + { 0x2e060038, 0xce3f }, /* 14 */ + { 0x2e06003c, 0x80e70 }, /* 15 */ + { 0x2e060040, 0x5 }, /* 16 */ + { 0x2e060044, 0x210 }, /* 17 */ + { 0x2e060048, 0x19c7d }, /* 18 */ + { 0x2e06004c, 0x101cdf }, /* 19 */ + { 0x2e060050, 0x5 }, /* 20 */ + { 0x2e060054, 0x420 }, /* 21 */ + { 0x2e060058, 0x1010000 }, /* 22 */ + { 0x2e06005c, 0x2011001 }, /* 23 */ + { 0x2e060060, 0x2010000 }, /* 24 */ + { 0x2e060064, 0x102 }, /* 25 */ + { 0x2e060068, 0xa }, /* 26 */ + { 0x2e06006c, 0x19 }, /* 27 */ + { 0x2e060078, 0x2020200 }, /* 30 */ + { 0x2e06007c, 0x160b }, /* 31 */ + { 0x2e060090, 0x10 }, /* 36 */ + { 0x2e0600a4, 0x40c040c }, /* 41 */ + { 0x2e0600a8, 0x8040614 }, /* 42 */ + { 0x2e0600ac, 0x604 }, /* 43 */ + { 0x2e0600b0, 0x3090003 }, /* 44 */ + { 0x2e0600b4, 0x40002 }, /* 45 */ + { 0x2e0600b8, 0xc0011 }, /* 46 */ + { 0x2e0600bc, 0xb0509 }, /* 47 */ + { 0x2e0600c0, 0x2106 }, /* 48 */ + { 0x2e0600c4, 0xa090017 }, /* 49 */ + { 0x2e0600c8, 0x8200016 }, /* 50 */ + { 0x2e0600cc, 0xa0a }, /* 51 */ + { 0x2e0600d0, 0x4000694 }, /* 52 */ + { 0x2e0600d4, 0xa0a0804 }, /* 53 */ + { 0x2e0600d8, 0x4002432 }, /* 54 */ + { 0x2e0600dc, 0xa0a0804 }, /* 55 */ + { 0x2e0600e0, 0x4004864 }, /* 56 */ + { 0x2e0600e4, 0x2030404 }, /* 57 */ + { 0x2e0600e8, 0x5040400 }, /* 58 */ + { 0x2e0600ec, 0x80b0a06 }, /* 59 */ + { 0x2e0600f0, 0x7010100 }, /* 60 */ + { 0x2e0600f4, 0x4150b }, /* 61 */ + { 0x2e0600fc, 0x1010000 }, /* 63 */ + { 0x2e060100, 0x1000000 }, /* 64 */ + { 0x2e060104, 0xe0403 }, /* 65 */ + { 0x2e060108, 0xb3 }, /* 66 */ + { 0x2e06010c, 0x4a }, /* 67 */ + { 0x2e060110, 0x3fd }, /* 68 */ + { 0x2e060114, 0x94 }, /* 69 */ + { 0x2e060118, 0x803 }, /* 70 */ + { 0x2e06011c, 0x5 }, /* 71 */ + { 0x2e060120, 0x70000 }, /* 72 */ + { 0x2e060124, 0x25000f }, /* 73 */ + { 0x2e060128, 0x4a0078 }, /* 74 */ + { 0x2e06012c, 0x4000f9 }, /* 75 */ + { 0x2e060130, 0x120103 }, /* 76 */ + { 0x2e060134, 0x50005 }, /* 77 */ + { 0x2e060138, 0x8070005 }, /* 78 */ + { 0x2e06013c, 0x505010d }, /* 79 */ + { 0x2e060140, 0x101030a }, /* 80 */ + { 0x2e060144, 0x30a0505 }, /* 81 */ + { 0x2e060148, 0x5050101 }, /* 82 */ + { 0x2e06014c, 0x1030a }, /* 83 */ + { 0x2e060150, 0xe000e }, /* 84 */ + { 0x2e060154, 0x4c004c }, /* 85 */ + { 0x2e060158, 0x980098 }, /* 86 */ + { 0x2e06015c, 0x3050505 }, /* 87 */ + { 0x2e060160, 0x3010403 }, /* 88 */ + { 0x2e060164, 0x4050505 }, /* 89 */ + { 0x2e060168, 0x3010403 }, /* 90 */ + { 0x2e06016c, 0x8050505 }, /* 91 */ + { 0x2e060170, 0x3010403 }, /* 92 */ + { 0x2e060174, 0x3010000 }, /* 93 */ + { 0x2e060178, 0x10000 }, /* 94 */ + { 0x2e060180, 0x1000000 }, /* 96 */ + { 0x2e060184, 0x80104002 }, /* 97 */ + { 0x2e060188, 0x40003 }, /* 98 */ + { 0x2e06018c, 0x40005 }, /* 99 */ + { 0x2e060190, 0x30000 }, /* 100 */ + { 0x2e060194, 0x50004 }, /* 101 */ + { 0x2e060198, 0x4 }, /* 102 */ + { 0x2e06019c, 0x40003 }, /* 103 */ + { 0x2e0601a0, 0x40005 }, /* 104 */ + { 0x2e0601a8, 0x2cc0 }, /* 106 */ + { 0x2e0601ac, 0x2cc0 }, /* 107 */ + { 0x2e0601b0, 0x2cc0 }, /* 108 */ + { 0x2e0601b4, 0x2cc0 }, /* 109 */ + { 0x2e0601b8, 0x2cc0 }, /* 110 */ + { 0x2e0601c0, 0x4e5 }, /* 112 */ + { 0x2e0601c4, 0xff40 }, /* 113 */ + { 0x2e0601c8, 0xff40 }, /* 114 */ + { 0x2e0601cc, 0xff40 }, /* 115 */ + { 0x2e0601d0, 0xff40 }, /* 116 */ + { 0x2e0601d4, 0xff40 }, /* 117 */ + { 0x2e0601dc, 0x1beb }, /* 119 */ + { 0x2e0601e0, 0x200c0 }, /* 120 */ + { 0x2e0601e4, 0x200c0 }, /* 121 */ + { 0x2e0601e8, 0x200c0 }, /* 122 */ + { 0x2e0601ec, 0x200c0 }, /* 123 */ + { 0x2e0601f0, 0x200c0 }, /* 124 */ + { 0x2e0601f8, 0x3815 }, /* 126 */ + { 0x2e06021c, 0x5000000 }, /* 135 */ + { 0x2e060220, 0x5030503 }, /* 136 */ + { 0x2e060224, 0x3 }, /* 137 */ + { 0x2e060228, 0x7010a09 }, /* 138 */ + { 0x2e06022c, 0xe0a09 }, /* 139 */ + { 0x2e060230, 0x10a0900 }, /* 140 */ + { 0x2e060234, 0xe0a0907 }, /* 141 */ + { 0x2e060238, 0xa090000 }, /* 142 */ + { 0x2e06023c, 0xa090701 }, /* 143 */ + { 0x2e060240, 0x101000e }, /* 144 */ + { 0x2e060244, 0x40003 }, /* 145 */ + { 0x2e060248, 0x7 }, /* 146 */ + { 0x2e060264, 0x4040100 }, /* 153 */ + { 0x2e060268, 0x1000000 }, /* 154 */ + { 0x2e06026c, 0x100000c0 }, /* 155 */ + { 0x2e060270, 0x100000c0 }, /* 156 */ + { 0x2e060274, 0x100000c0 }, /* 157 */ + { 0x2e06027c, 0x1600 }, /* 159 */ + { 0x2e060284, 0x1 }, /* 161 */ + { 0x2e060288, 0x2 }, /* 162 */ + { 0x2e06028c, 0x100e }, /* 163 */ + { 0x2e0602a4, 0xa0000 }, /* 169 */ + { 0x2e0602a8, 0xd0005 }, /* 170 */ + { 0x2e0602ac, 0x404 }, /* 171 */ + { 0x2e0602b0, 0xd }, /* 172 */ + { 0x2e0602b4, 0x1b0035 }, /* 173 */ + { 0x2e0602b8, 0x4040042 }, /* 174 */ + { 0x2e0602bc, 0x42 }, /* 175 */ + { 0x2e0602c0, 0x35006a }, /* 176 */ + { 0x2e0602c4, 0x4040084 }, /* 177 */ + { 0x2e0602c8, 0x84 }, /* 178 */ + { 0x2e0602d8, 0x40004 }, /* 182 */ + { 0x2e0602dc, 0x30000914 }, /* 183 */ + { 0x2e0602e0, 0x3030 }, /* 184 */ + { 0x2e0602e4, 0x44440000 }, /* 185 */ + { 0x2e0602e8, 0x19191944 }, /* 186 */ + { 0x2e0602ec, 0x19191908 }, /* 187 */ + { 0x2e0602f0, 0x4000000 }, /* 188 */ + { 0x2e0602f4, 0x40404 }, /* 189 */ + { 0x2e0602f8, 0x9140004 }, /* 190 */ + { 0x2e0602fc, 0x30303000 }, /* 191 */ + { 0x2e060304, 0x19444444 }, /* 193 */ + { 0x2e060308, 0x19081919 }, /* 194 */ + { 0x2e06030c, 0x1919 }, /* 195 */ + { 0x2e060310, 0x4040400 }, /* 196 */ + { 0x2e060314, 0x1010120 }, /* 197 */ + { 0x2e060318, 0x1000100 }, /* 198 */ + { 0x2e06031c, 0x1 }, /* 199 */ + { 0x2e060324, 0x1000000 }, /* 201 */ + { 0x2e060328, 0x1 }, /* 202 */ + { 0x2e060354, 0x11000000 }, /* 213 */ + { 0x2e060358, 0x40c1815 }, /* 214 */ + { 0x2e060390, 0x30000 }, /* 228 */ + { 0x2e060394, 0x1000200 }, /* 229 */ + { 0x2e060398, 0x310040 }, /* 230 */ + { 0x2e06039c, 0x20002 }, /* 231 */ + { 0x2e0603a0, 0x400100 }, /* 232 */ + { 0x2e0603a4, 0x80108 }, /* 233 */ + { 0x2e0603a8, 0x1000200 }, /* 234 */ + { 0x2e0603ac, 0x2100040 }, /* 235 */ + { 0x2e0603b0, 0x10 }, /* 236 */ + { 0x2e0603b4, 0xe0003 }, /* 237 */ + { 0x2e0603b8, 0x100001b }, /* 238 */ + { 0x2e0603d8, 0xffff0b00 }, /* 246 */ + { 0x2e0603dc, 0x1010001 }, /* 247 */ + { 0x2e0603e0, 0x1010101 }, /* 248 */ + { 0x2e0603e4, 0x10b0101 }, /* 249 */ + { 0x2e0603e8, 0x10000 }, /* 250 */ + { 0x2e0603ec, 0x4010101 }, /* 251 */ + { 0x2e0603f0, 0x1010000 }, /* 252 */ + { 0x2e0603f4, 0x4 }, /* 253 */ + { 0x2e0603fc, 0x3030101 }, /* 255 */ + { 0x2e060400, 0x103 }, /* 256 */ + { 0x2e0604a4, 0x2020101 }, /* 297 */ + { 0x2e0604a8, 0x10100 }, /* 298 */ + { 0x2e0604ac, 0x1000101 }, /* 299 */ + { 0x2e0604b0, 0x1010101 }, /* 300 */ + { 0x2e0604b4, 0x4030300 }, /* 301 */ + { 0x2e0604b8, 0x8080505 }, /* 302 */ + { 0x2e0604bc, 0x8020808 }, /* 303 */ + { 0x2e0604c0, 0x8020e00 }, /* 304 */ + { 0x2e0604c4, 0xa020e00 }, /* 305 */ + { 0x2e0604c8, 0x8000f00 }, /* 306 */ + { 0x2e0604cc, 0xa08 }, /* 307 */ + { 0x2e0604d0, 0x1010101 }, /* 308 */ + { 0x2e0604d4, 0x102 }, /* 309 */ + { 0x2e0604d8, 0x404 }, /* 310 */ + { 0x2e0604dc, 0x40400 }, /* 311 */ + { 0x2e0604e0, 0x4040000 }, /* 312 */ + { 0x2e0604e4, 0x4000000 }, /* 313 */ + { 0x2e0604e8, 0x10004 }, /* 314 */ + { 0x2e0604f0, 0xfffff }, /* 316 */ + { 0x2e0604f8, 0xfffff }, /* 318 */ + { 0x2e060500, 0xfffff }, /* 320 */ + { 0x2e060508, 0xfffff }, /* 322 */ + { 0x2e060510, 0xfffff }, /* 324 */ + { 0x2e060518, 0xfffff }, /* 326 */ + { 0x2e060520, 0xfffff }, /* 328 */ + { 0x2e060528, 0xfffff }, /* 330 */ + { 0x2e060530, 0xfffff }, /* 332 */ + { 0x2e060538, 0xfffff }, /* 334 */ + { 0x2e060540, 0xfffff }, /* 336 */ + { 0x2e060548, 0xfffff }, /* 338 */ + { 0x2e060550, 0xfffff }, /* 340 */ + { 0x2e060558, 0xfffff }, /* 342 */ + { 0x2e060560, 0xfffff }, /* 344 */ + { 0x2e060568, 0xfffff }, /* 346 */ + { 0x2e060570, 0xfffff }, /* 348 */ + { 0x2e060578, 0xfffff }, /* 350 */ + { 0x2e060580, 0xfffff }, /* 352 */ + { 0x2e060588, 0xfffff }, /* 354 */ + { 0x2e060590, 0xfffff }, /* 356 */ + { 0x2e060598, 0xfffff }, /* 358 */ + { 0x2e0605a0, 0xfffff }, /* 360 */ + { 0x2e0605a8, 0xfffff }, /* 362 */ + { 0x2e0605b0, 0xfffff }, /* 364 */ + { 0x2e0605b8, 0xfffff }, /* 366 */ + { 0x2e0605c0, 0xfffff }, /* 368 */ + { 0x2e0605c8, 0xfffff }, /* 370 */ + { 0x2e0605d0, 0xfffff }, /* 372 */ + { 0x2e0605d8, 0xfffff }, /* 374 */ + { 0x2e0605e0, 0xfffff }, /* 376 */ + { 0x2e0605e8, 0xfffff }, /* 378 */ + { 0x2e0605f0, 0xfffff }, /* 380 */ + { 0x2e0605f8, 0xfffff }, /* 382 */ + { 0x2e060600, 0xfffff }, /* 384 */ + { 0x2e060608, 0xfffff }, /* 386 */ + { 0x2e060610, 0xfffff }, /* 388 */ + { 0x2e060618, 0xfffff }, /* 390 */ + { 0x2e060620, 0xfffff }, /* 392 */ + { 0x2e060628, 0xfffff }, /* 394 */ + { 0x2e060630, 0xfffff }, /* 396 */ + { 0x2e060638, 0xfffff }, /* 398 */ + { 0x2e060640, 0xfffff }, /* 400 */ + { 0x2e060648, 0xfffff }, /* 402 */ + { 0x2e060650, 0xfffff }, /* 404 */ + { 0x2e060658, 0xfffff }, /* 406 */ + { 0x2e060660, 0xfffff }, /* 408 */ + { 0x2e060668, 0xfffff }, /* 410 */ + { 0x2e060670, 0xfffff }, /* 412 */ + { 0x2e060678, 0xfffff }, /* 414 */ + { 0x2e060680, 0xfffff }, /* 416 */ + { 0x2e060688, 0xfffff }, /* 418 */ + { 0x2e060690, 0xfffff }, /* 420 */ + { 0x2e060698, 0xfffff }, /* 422 */ + { 0x2e0606a0, 0xfffff }, /* 424 */ + { 0x2e0606a8, 0xfffff }, /* 426 */ + { 0x2e0606b0, 0xfffff }, /* 428 */ + { 0x2e0606b8, 0xfffff }, /* 430 */ + { 0x2e0606c0, 0xfffff }, /* 432 */ + { 0x2e0606c8, 0xfffff }, /* 434 */ + { 0x2e0606d0, 0xfffff }, /* 436 */ + { 0x2e0606d8, 0xfffff }, /* 438 */ + { 0x2e0606e0, 0xfffff }, /* 440 */ + { 0x2e0606e8, 0x30fffff }, /* 442 */ + { 0x2e0606ec, 0xffffffff }, /* 443 */ + { 0x2e0606f0, 0x30f0f }, /* 444 */ + { 0x2e0606f4, 0xffffffff }, /* 445 */ + { 0x2e0606f8, 0x30f0f }, /* 446 */ + { 0x2e0606fc, 0xffffffff }, /* 447 */ + { 0x2e060700, 0x30f0f }, /* 448 */ + { 0x2e060704, 0xffffffff }, /* 449 */ + { 0x2e060708, 0x30f0f }, /* 450 */ + { 0x2e06070c, 0xffffffff }, /* 451 */ + { 0x2e060710, 0x30f0f }, /* 452 */ + { 0x2e060714, 0xffffffff }, /* 453 */ + { 0x2e060718, 0x30f0f }, /* 454 */ + { 0x2e06071c, 0xffffffff }, /* 455 */ + { 0x2e060720, 0x30f0f }, /* 456 */ + { 0x2e060724, 0xffffffff }, /* 457 */ + { 0x2e060728, 0x30f0f }, /* 458 */ + { 0x2e06072c, 0xffffffff }, /* 459 */ + { 0x2e060730, 0x30f0f }, /* 460 */ + { 0x2e060734, 0xffffffff }, /* 461 */ + { 0x2e060738, 0x30f0f }, /* 462 */ + { 0x2e06073c, 0xffffffff }, /* 463 */ + { 0x2e060740, 0x30f0f }, /* 464 */ + { 0x2e060744, 0xffffffff }, /* 465 */ + { 0x2e060748, 0x30f0f }, /* 466 */ + { 0x2e06074c, 0xffffffff }, /* 467 */ + { 0x2e060750, 0x30f0f }, /* 468 */ + { 0x2e060754, 0xffffffff }, /* 469 */ + { 0x2e060758, 0x30f0f }, /* 470 */ + { 0x2e06075c, 0xffffffff }, /* 471 */ + { 0x2e060760, 0x30f0f }, /* 472 */ + { 0x2e060764, 0xffffffff }, /* 473 */ + { 0x2e060768, 0x30f0f }, /* 474 */ + { 0x2e06076c, 0xffffffff }, /* 475 */ + { 0x2e060770, 0x30f0f }, /* 476 */ + { 0x2e060774, 0xffffffff }, /* 477 */ + { 0x2e060778, 0x30f0f }, /* 478 */ + { 0x2e06077c, 0xffffffff }, /* 479 */ + { 0x2e060780, 0x30f0f }, /* 480 */ + { 0x2e060784, 0xffffffff }, /* 481 */ + { 0x2e060788, 0x30f0f }, /* 482 */ + { 0x2e06078c, 0xffffffff }, /* 483 */ + { 0x2e060790, 0x30f0f }, /* 484 */ + { 0x2e060794, 0xffffffff }, /* 485 */ + { 0x2e060798, 0x30f0f }, /* 486 */ + { 0x2e06079c, 0xffffffff }, /* 487 */ + { 0x2e0607a0, 0x30f0f }, /* 488 */ + { 0x2e0607a4, 0xffffffff }, /* 489 */ + { 0x2e0607a8, 0x30f0f }, /* 490 */ + { 0x2e0607ac, 0xffffffff }, /* 491 */ + { 0x2e0607b0, 0x30f0f }, /* 492 */ + { 0x2e0607b4, 0xffffffff }, /* 493 */ + { 0x2e0607b8, 0x30f0f }, /* 494 */ + { 0x2e0607bc, 0xffffffff }, /* 495 */ + { 0x2e0607c0, 0x30f0f }, /* 496 */ + { 0x2e0607c4, 0xffffffff }, /* 497 */ + { 0x2e0607c8, 0x30f0f }, /* 498 */ + { 0x2e0607cc, 0xffffffff }, /* 499 */ + { 0x2e0607d0, 0x30f0f }, /* 500 */ + { 0x2e0607d4, 0xffffffff }, /* 501 */ + { 0x2e0607d8, 0x30f0f }, /* 502 */ + { 0x2e0607dc, 0xffffffff }, /* 503 */ + { 0x2e0607e0, 0x30f0f }, /* 504 */ + { 0x2e0607e4, 0xffffffff }, /* 505 */ + { 0x2e0607e8, 0x30f0f }, /* 506 */ + { 0x2e0607ec, 0xffffffff }, /* 507 */ + { 0x2e0607f0, 0x30f0f }, /* 508 */ + { 0x2e0607f4, 0xffffffff }, /* 509 */ + { 0x2e0607f8, 0x30f0f }, /* 510 */ + { 0x2e0607fc, 0xffffffff }, /* 511 */ + { 0x2e060800, 0x30f0f }, /* 512 */ + { 0x2e060804, 0xffffffff }, /* 513 */ + { 0x2e060808, 0x30f0f }, /* 514 */ + { 0x2e06080c, 0xffffffff }, /* 515 */ + { 0x2e060810, 0x30f0f }, /* 516 */ + { 0x2e060814, 0xffffffff }, /* 517 */ + { 0x2e060818, 0x30f0f }, /* 518 */ + { 0x2e06081c, 0xffffffff }, /* 519 */ + { 0x2e060820, 0x30f0f }, /* 520 */ + { 0x2e060824, 0xffffffff }, /* 521 */ + { 0x2e060828, 0x30f0f }, /* 522 */ + { 0x2e06082c, 0xffffffff }, /* 523 */ + { 0x2e060830, 0x30f0f }, /* 524 */ + { 0x2e060834, 0xffffffff }, /* 525 */ + { 0x2e060838, 0x30f0f }, /* 526 */ + { 0x2e06083c, 0xffffffff }, /* 527 */ + { 0x2e060840, 0x30f0f }, /* 528 */ + { 0x2e060844, 0xffffffff }, /* 529 */ + { 0x2e060848, 0x30f0f }, /* 530 */ + { 0x2e06084c, 0xffffffff }, /* 531 */ + { 0x2e060850, 0x30f0f }, /* 532 */ + { 0x2e060854, 0xffffffff }, /* 533 */ + { 0x2e060858, 0x30f0f }, /* 534 */ + { 0x2e06085c, 0xffffffff }, /* 535 */ + { 0x2e060860, 0x30f0f }, /* 536 */ + { 0x2e060864, 0xffffffff }, /* 537 */ + { 0x2e060868, 0x30f0f }, /* 538 */ + { 0x2e06086c, 0xffffffff }, /* 539 */ + { 0x2e060870, 0x30f0f }, /* 540 */ + { 0x2e060874, 0xffffffff }, /* 541 */ + { 0x2e060878, 0x30f0f }, /* 542 */ + { 0x2e06087c, 0xffffffff }, /* 543 */ + { 0x2e060880, 0x30f0f }, /* 544 */ + { 0x2e060884, 0xffffffff }, /* 545 */ + { 0x2e060888, 0x30f0f }, /* 546 */ + { 0x2e06088c, 0xffffffff }, /* 547 */ + { 0x2e060890, 0x30f0f }, /* 548 */ + { 0x2e060894, 0xffffffff }, /* 549 */ + { 0x2e060898, 0x30f0f }, /* 550 */ + { 0x2e06089c, 0xffffffff }, /* 551 */ + { 0x2e0608a0, 0x30f0f }, /* 552 */ + { 0x2e0608a4, 0xffffffff }, /* 553 */ + { 0x2e0608a8, 0x30f0f }, /* 554 */ + { 0x2e0608ac, 0xffffffff }, /* 555 */ + { 0x2e0608b0, 0x30f0f }, /* 556 */ + { 0x2e0608b4, 0xffffffff }, /* 557 */ + { 0x2e0608b8, 0x30f0f }, /* 558 */ + { 0x2e0608bc, 0xffffffff }, /* 559 */ + { 0x2e0608c0, 0x30f0f }, /* 560 */ + { 0x2e0608c4, 0xffffffff }, /* 561 */ + { 0x2e0608c8, 0x30f0f }, /* 562 */ + { 0x2e0608cc, 0xffffffff }, /* 563 */ + { 0x2e0608d0, 0x30f0f }, /* 564 */ + { 0x2e0608d4, 0xffffffff }, /* 565 */ + { 0x2e0608d8, 0x30f0f }, /* 566 */ + { 0x2e0608dc, 0xffffffff }, /* 567 */ + { 0x2e0608e0, 0x30f0f }, /* 568 */ + { 0x2e0608e4, 0xffffffff }, /* 569 */ + { 0x2e0608e8, 0x32070f0f }, /* 570 */ + { 0x2e0608ec, 0x1320001 }, /* 571 */ + { 0x2e0608f0, 0x13200 }, /* 572 */ + { 0x2e0608f4, 0x132 }, /* 573 */ + { 0x2e0608fc, 0x1d1b0000 }, /* 575 */ + { 0x2e060900, 0x21 }, /* 576 */ + { 0x2e060904, 0xa }, /* 577 */ + { 0x2e060908, 0x166 }, /* 578 */ + { 0x2e06090c, 0x200 }, /* 579 */ + { 0x2e060910, 0x200 }, /* 580 */ + { 0x2e060914, 0x200 }, /* 581 */ + { 0x2e060918, 0x200 }, /* 582 */ + { 0x2e06091c, 0x432 }, /* 583 */ + { 0x2e060920, 0xdfc }, /* 584 */ + { 0x2e060924, 0x204 }, /* 585 */ + { 0x2e060928, 0x7fa }, /* 586 */ + { 0x2e06092c, 0x200 }, /* 587 */ + { 0x2e060930, 0x200 }, /* 588 */ + { 0x2e060934, 0x200 }, /* 589 */ + { 0x2e060938, 0x200 }, /* 590 */ + { 0x2e06093c, 0x17ee }, /* 591 */ + { 0x2e060940, 0x4fc4 }, /* 592 */ + { 0x2e060944, 0x204 }, /* 593 */ + { 0x2e060948, 0x1006 }, /* 594 */ + { 0x2e06094c, 0x200 }, /* 595 */ + { 0x2e060950, 0x200 }, /* 596 */ + { 0x2e060954, 0x200 }, /* 597 */ + { 0x2e060958, 0x200 }, /* 598 */ + { 0x2e06095c, 0x3012 }, /* 599 */ + { 0x2e060960, 0xa03c }, /* 600 */ + { 0x2e060964, 0x2020406 }, /* 601 */ + { 0x2e060968, 0x2030202 }, /* 602 */ + { 0x2e06096c, 0x1000202 }, /* 603 */ + { 0x2e060970, 0x3040100 }, /* 604 */ + { 0x2e060974, 0x10105 }, /* 605 */ + { 0x2e060978, 0x10101 }, /* 606 */ + { 0x2e06097c, 0x10101 }, /* 607 */ + { 0x2e060980, 0x10001 }, /* 608 */ + { 0x2e060984, 0x101 }, /* 609 */ + { 0x2e060988, 0x2000201 }, /* 610 */ + { 0x2e06098c, 0x2010000 }, /* 611 */ + { 0x2e060990, 0x6000200 }, /* 612 */ + { 0x2e060994, 0x3000a06 }, /* 613 */ + { 0x2e060998, 0x2000c06 }, /* 614 */ +}; + +/** PI settings **/ +struct dram_cfg_param ddr_pi_cfg[] = { + { 0x2e062000, 0xb00 }, /* 0 */ + { 0x2e062004, 0xbeedb66f }, /* 1 */ + { 0x2e062008, 0xabef6bd }, /* 2 */ + { 0x2e06200c, 0x1001387 }, /* 3 */ + { 0x2e062010, 0x1 }, /* 4 */ + { 0x2e062014, 0x10064 }, /* 5 */ + { 0x2e06202c, 0x201 }, /* 11 */ + { 0x2e062030, 0x7 }, /* 12 */ + { 0x2e062034, 0x50001 }, /* 13 */ + { 0x2e062038, 0x3030800 }, /* 14 */ + { 0x2e06203c, 0x1 }, /* 15 */ + { 0x2e062040, 0x5 }, /* 16 */ + { 0x2e062064, 0x1000000 }, /* 25 */ + { 0x2e062068, 0xa000001 }, /* 26 */ + { 0x2e06206c, 0x28 }, /* 27 */ + { 0x2e062070, 0x1 }, /* 28 */ + { 0x2e062074, 0x320005 }, /* 29 */ + { 0x2e062080, 0x10102 }, /* 32 */ + { 0x2e062084, 0x1 }, /* 33 */ + { 0x2e062088, 0xaa }, /* 34 */ + { 0x2e06208c, 0x55 }, /* 35 */ + { 0x2e062090, 0xb5 }, /* 36 */ + { 0x2e062094, 0x4a }, /* 37 */ + { 0x2e062098, 0x56 }, /* 38 */ + { 0x2e06209c, 0xa9 }, /* 39 */ + { 0x2e0620a0, 0xa9 }, /* 40 */ + { 0x2e0620a4, 0xb5 }, /* 41 */ + { 0x2e0620a8, 0x10000 }, /* 42 */ + { 0x2e0620ac, 0x100 }, /* 43 */ + { 0x2e0620b0, 0x5050000 }, /* 44 */ + { 0x2e0620b4, 0x13 }, /* 45 */ + { 0x2e0620b8, 0x7d0 }, /* 46 */ + { 0x2e0620bc, 0x300 }, /* 47 */ + { 0x2e0620c8, 0x1000000 }, /* 50 */ + { 0x2e0620cc, 0x10101 }, /* 51 */ + { 0x2e0620d8, 0x10003 }, /* 54 */ + { 0x2e0620dc, 0x170500 }, /* 55 */ + { 0x2e0620ec, 0xa140a01 }, /* 59 */ + { 0x2e0620f0, 0x204010a }, /* 60 */ + { 0x2e0620f4, 0x21010 }, /* 61 */ + { 0x2e0620f8, 0x40401 }, /* 62 */ + { 0x2e0620fc, 0x10e0005 }, /* 63 */ + { 0x2e062100, 0x5000001 }, /* 64 */ + { 0x2e062104, 0x204 }, /* 65 */ + { 0x2e062108, 0x34 }, /* 66 */ + { 0x2e062114, 0x1000000 }, /* 69 */ + { 0x2e062118, 0x1000000 }, /* 70 */ + { 0x2e06211c, 0x80200 }, /* 71 */ + { 0x2e062120, 0x2000200 }, /* 72 */ + { 0x2e062124, 0x1000100 }, /* 73 */ + { 0x2e062128, 0x1000000 }, /* 74 */ + { 0x2e06212c, 0x2000200 }, /* 75 */ + { 0x2e062130, 0x200 }, /* 76 */ + { 0x2e062164, 0x400 }, /* 89 */ + { 0x2e062168, 0x2010000 }, /* 90 */ + { 0x2e06216c, 0x80103 }, /* 91 */ + { 0x2e062174, 0x10008 }, /* 93 */ + { 0x2e06217c, 0xaa00 }, /* 95 */ + { 0x2e062188, 0x10000 }, /* 98 */ + { 0x2e0621ec, 0x8 }, /* 123 */ + { 0x2e062218, 0xf0000 }, /* 134 */ + { 0x2e06221c, 0xa }, /* 135 */ + { 0x2e062220, 0x19 }, /* 136 */ + { 0x2e062224, 0x100 }, /* 137 */ + { 0x2e062228, 0x100 }, /* 138 */ + { 0x2e062238, 0x1000000 }, /* 142 */ + { 0x2e06223c, 0x10003 }, /* 143 */ + { 0x2e062240, 0x2000101 }, /* 144 */ + { 0x2e062244, 0x1030001 }, /* 145 */ + { 0x2e062248, 0x10400 }, /* 146 */ + { 0x2e06224c, 0x6000105 }, /* 147 */ + { 0x2e062250, 0x1070001 }, /* 148 */ + { 0x2e062260, 0x10001 }, /* 152 */ + { 0x2e062274, 0x401 }, /* 157 */ + { 0x2e06227c, 0x10000 }, /* 159 */ + { 0x2e062284, 0x6010000 }, /* 161 */ + { 0x2e062288, 0xb }, /* 162 */ + { 0x2e06228c, 0x34 }, /* 163 */ + { 0x2e062290, 0x36 }, /* 164 */ + { 0x2e062294, 0x2003c }, /* 165 */ + { 0x2e062298, 0x2000200 }, /* 166 */ + { 0x2e06229c, 0xc040c04 }, /* 167 */ + { 0x2e0622a0, 0xe1406 }, /* 168 */ + { 0x2e0622a4, 0xb3 }, /* 169 */ + { 0x2e0622a8, 0x4a }, /* 170 */ + { 0x2e0622ac, 0x3fd }, /* 171 */ + { 0x2e0622b0, 0x94 }, /* 172 */ + { 0x2e0622b4, 0x4000803 }, /* 173 */ + { 0x2e0622b8, 0x1010404 }, /* 174 */ + { 0x2e0622bc, 0x1501 }, /* 175 */ + { 0x2e0622c0, 0x1a0018 }, /* 176 */ + { 0x2e0622c4, 0x1000100 }, /* 177 */ + { 0x2e0622c8, 0x100 }, /* 178 */ + { 0x2e0622d0, 0x5040303 }, /* 180 */ + { 0x2e0622d4, 0x1010805 }, /* 181 */ + { 0x2e0622d8, 0x1010101 }, /* 182 */ + { 0x2e0622e8, 0x2060404 }, /* 186 */ + { 0x2e0622ec, 0x2020402 }, /* 187 */ + { 0x2e0622f0, 0x3102 }, /* 188 */ + { 0x2e0622f4, 0x340009 }, /* 189 */ + { 0x2e0622f8, 0x36000c }, /* 190 */ + { 0x2e0622fc, 0x101000e }, /* 191 */ + { 0x2e062300, 0xd0101 }, /* 192 */ + { 0x2e062304, 0x1004201 }, /* 193 */ + { 0x2e062308, 0x1000084 }, /* 194 */ + { 0x2e06230c, 0xe000e }, /* 195 */ + { 0x2e062310, 0x430100 }, /* 196 */ + { 0x2e062314, 0x1000043 }, /* 197 */ + { 0x2e062318, 0x850085 }, /* 198 */ + { 0x2e06231c, 0x220f220f }, /* 199 */ + { 0x2e062320, 0x101220f }, /* 200 */ + { 0x2e062324, 0xa070601 }, /* 201 */ + { 0x2e062328, 0xa07060d }, /* 202 */ + { 0x2e06232c, 0xa07070d }, /* 203 */ + { 0x2e062330, 0xc00d }, /* 204 */ + { 0x2e062334, 0xc01000 }, /* 205 */ + { 0x2e062338, 0xc01000 }, /* 206 */ + { 0x2e06233c, 0x21000 }, /* 207 */ + { 0x2e062340, 0x11000d }, /* 208 */ + { 0x2e062344, 0x140042 }, /* 209 */ + { 0x2e062348, 0x190084 }, /* 210 */ + { 0x2e06234c, 0x220f0056 }, /* 211 */ + { 0x2e062350, 0x101 }, /* 212 */ + { 0x2e062354, 0x560019 }, /* 213 */ + { 0x2e062358, 0x101220f }, /* 214 */ + { 0x2e06235c, 0x1b00 }, /* 215 */ + { 0x2e062360, 0x220f0056 }, /* 216 */ + { 0x2e062364, 0x8000101 }, /* 217 */ + { 0x2e062368, 0x4090403 }, /* 218 */ + { 0x2e06236c, 0x5eb }, /* 219 */ + { 0x2e062370, 0x20010003 }, /* 220 */ + { 0x2e062374, 0x80a0a03 }, /* 221 */ + { 0x2e062378, 0x6090506 }, /* 222 */ + { 0x2e06237c, 0x2093 }, /* 223 */ + { 0x2e062380, 0x2001000c }, /* 224 */ + { 0x2e062384, 0x80a0a04 }, /* 225 */ + { 0x2e062388, 0xb090a0c }, /* 226 */ + { 0x2e06238c, 0x4126 }, /* 227 */ + { 0x2e062390, 0x20020017 }, /* 228 */ + { 0x2e062394, 0xa0a08 }, /* 229 */ + { 0x2e062398, 0x166 }, /* 230 */ + { 0x2e06239c, 0xdfc }, /* 231 */ + { 0x2e0623a0, 0x7fa }, /* 232 */ + { 0x2e0623a4, 0x4fc4 }, /* 233 */ + { 0x2e0623a8, 0x1006 }, /* 234 */ + { 0x2e0623ac, 0xa03c }, /* 235 */ + { 0x2e0623b0, 0x4c000e }, /* 236 */ + { 0x2e0623b4, 0x3030098 }, /* 237 */ + { 0x2e0623b8, 0x258103 }, /* 238 */ + { 0x2e0623bc, 0x17702 }, /* 239 */ + { 0x2e0623c0, 0x5 }, /* 240 */ + { 0x2e0623c4, 0x61 }, /* 241 */ + { 0x2e0623c8, 0xe }, /* 242 */ + { 0x2e0623cc, 0xce3f }, /* 243 */ + { 0x2e0623d0, 0x80e70 }, /* 244 */ + { 0x2e0623d4, 0x5 }, /* 245 */ + { 0x2e0623d8, 0x210 }, /* 246 */ + { 0x2e0623dc, 0x4c }, /* 247 */ + { 0x2e0623e0, 0x19c7d }, /* 248 */ + { 0x2e0623e4, 0x101cdf }, /* 249 */ + { 0x2e0623e8, 0x5 }, /* 250 */ + { 0x2e0623ec, 0x420 }, /* 251 */ + { 0x2e0623f0, 0x1000098 }, /* 252 */ + { 0x2e0623f4, 0x310040 }, /* 253 */ + { 0x2e0623f8, 0x10002 }, /* 254 */ + { 0x2e0623fc, 0x1080040 }, /* 255 */ + { 0x2e062400, 0x10008 }, /* 256 */ + { 0x2e062404, 0x2100040 }, /* 257 */ + { 0x2e062408, 0x310 }, /* 258 */ + { 0x2e06240c, 0x1b000e }, /* 259 */ + { 0x2e062410, 0x1010101 }, /* 260 */ + { 0x2e062414, 0x2020101 }, /* 261 */ + { 0x2e062418, 0x8080404 }, /* 262 */ + { 0x2e06241c, 0x5508 }, /* 263 */ + { 0x2e062420, 0x83c5a00 }, /* 264 */ + { 0x2e062424, 0x55 }, /* 265 */ + { 0x2e062428, 0x55083c5a }, /* 266 */ + { 0x2e06242c, 0x5a000000 }, /* 267 */ + { 0x2e062430, 0x55083c }, /* 268 */ + { 0x2e062434, 0x3c5a0000 }, /* 269 */ + { 0x2e062438, 0xf0e0d0c }, /* 270 */ + { 0x2e06243c, 0xb0a0908 }, /* 271 */ + { 0x2e062440, 0x7060504 }, /* 272 */ + { 0x2e062444, 0x3020100 }, /* 273 */ + { 0x2e06244c, 0x2020101 }, /* 275 */ + { 0x2e062450, 0x8080404 }, /* 276 */ + { 0x2e062454, 0x44300004 }, /* 277 */ + { 0x2e062458, 0x4041919 }, /* 278 */ + { 0x2e06245c, 0x19443000 }, /* 279 */ + { 0x2e062460, 0x9140419 }, /* 280 */ + { 0x2e062464, 0x19194430 }, /* 281 */ + { 0x2e062468, 0x30000404 }, /* 282 */ + { 0x2e06246c, 0x4191944 }, /* 283 */ + { 0x2e062470, 0x44300004 }, /* 284 */ + { 0x2e062474, 0x14041919 }, /* 285 */ + { 0x2e062478, 0x19443009 }, /* 286 */ + { 0x2e06247c, 0x40419 }, /* 287 */ + { 0x2e062480, 0x19194430 }, /* 288 */ + { 0x2e062484, 0x30000404 }, /* 289 */ + { 0x2e062488, 0x4191944 }, /* 290 */ + { 0x2e06248c, 0x44300914 }, /* 291 */ + { 0x2e062490, 0x44041919 }, /* 292 */ + { 0x2e062494, 0x19443000 }, /* 293 */ + { 0x2e062498, 0x40419 }, /* 294 */ + { 0x2e06249c, 0x19194430 }, /* 295 */ + { 0x2e0624a0, 0x30091404 }, /* 296 */ + { 0x2e0624a4, 0x4191944 }, /* 297 */ +}; + +/** PHY_F1 settings **/ +struct dram_cfg_param ddr_phy_f1_cfg[] = { + { 0x2e064000, 0x4f0 }, /* 0 */ + { 0x2e064008, 0x1030200 }, /* 2 */ + { 0x2e064014, 0x3000000 }, /* 5 */ + { 0x2e064018, 0x1000001 }, /* 6 */ + { 0x2e06401c, 0x3000400 }, /* 7 */ + { 0x2e064020, 0x1 }, /* 8 */ + { 0x2e064024, 0x1 }, /* 9 */ + { 0x2e064030, 0x10000 }, /* 12 */ + { 0x2e064038, 0xc00004 }, /* 14 */ + { 0x2e06403c, 0xcc0008 }, /* 15 */ + { 0x2e064040, 0x660601 }, /* 16 */ + { 0x2e064044, 0x3 }, /* 17 */ + { 0x2e06404c, 0x1 }, /* 19 */ + { 0x2e064050, 0xaaaa }, /* 20 */ + { 0x2e064054, 0x5555 }, /* 21 */ + { 0x2e064058, 0xb5b5 }, /* 22 */ + { 0x2e06405c, 0x4a4a }, /* 23 */ + { 0x2e064060, 0x5656 }, /* 24 */ + { 0x2e064064, 0xa9a9 }, /* 25 */ + { 0x2e064068, 0xb7b7 }, /* 26 */ + { 0x2e06406c, 0x4848 }, /* 27 */ + { 0x2e064078, 0x8000000 }, /* 30 */ + { 0x2e06407c, 0x4010008 }, /* 31 */ + { 0x2e064080, 0x408 }, /* 32 */ + { 0x2e064084, 0x3102000 }, /* 33 */ + { 0x2e064088, 0xc0020 }, /* 34 */ + { 0x2e06408c, 0x10000 }, /* 35 */ + { 0x2e064090, 0x55555555 }, /* 36 */ + { 0x2e064094, 0xaaaaaaaa }, /* 37 */ + { 0x2e064098, 0x55555555 }, /* 38 */ + { 0x2e06409c, 0xaaaaaaaa }, /* 39 */ + { 0x2e0640a0, 0x5555 }, /* 40 */ + { 0x2e0640a4, 0x1000100 }, /* 41 */ + { 0x2e0640a8, 0x800180 }, /* 42 */ + { 0x2e0640ac, 0x1 }, /* 43 */ + { 0x2e064100, 0x4 }, /* 64 */ + { 0x2e06411c, 0x41f07ff }, /* 71 */ + { 0x2e064120, 0x1 }, /* 72 */ + { 0x2e064124, 0x1cc0800 }, /* 73 */ + { 0x2e064128, 0x3003cc08 }, /* 74 */ + { 0x2e06412c, 0x2000014e }, /* 75 */ + { 0x2e064130, 0x7ff0200 }, /* 76 */ + { 0x2e064134, 0x301 }, /* 77 */ + { 0x2e064140, 0x30000 }, /* 80 */ + { 0x2e064154, 0x2000000 }, /* 85 */ + { 0x2e064158, 0x51515042 }, /* 86 */ + { 0x2e06415c, 0x31c06000 }, /* 87 */ + { 0x2e064160, 0x9bf000a }, /* 88 */ + { 0x2e064164, 0xc0c000 }, /* 89 */ + { 0x2e064168, 0x1000000 }, /* 90 */ + { 0x2e06416c, 0x10001000 }, /* 91 */ + { 0x2e064170, 0xc043242 }, /* 92 */ + { 0x2e064174, 0xf0c1201 }, /* 93 */ + { 0x2e064178, 0x1000140 }, /* 94 */ + { 0x2e06417c, 0xc000120 }, /* 95 */ + { 0x2e064180, 0x143 }, /* 96 */ + { 0x2e064184, 0x1000203 }, /* 97 */ + { 0x2e064188, 0x56417032 }, /* 98 */ + { 0x2e06418c, 0x8 }, /* 99 */ + { 0x2e064190, 0x2c302c3 }, /* 100 */ + { 0x2e064194, 0x2c302c3 }, /* 101 */ + { 0x2e064198, 0x2c302c3 }, /* 102 */ + { 0x2e06419c, 0x2c302c3 }, /* 103 */ + { 0x2e0641a0, 0x2c3 }, /* 104 */ + { 0x2e0641a4, 0x8000 }, /* 105 */ + { 0x2e0641a8, 0x800080 }, /* 106 */ + { 0x2e0641ac, 0x800080 }, /* 107 */ + { 0x2e0641b0, 0x800080 }, /* 108 */ + { 0x2e0641b4, 0x800080 }, /* 109 */ + { 0x2e0641b8, 0x800080 }, /* 110 */ + { 0x2e0641bc, 0x800080 }, /* 111 */ + { 0x2e0641c0, 0x800080 }, /* 112 */ + { 0x2e0641c4, 0x800080 }, /* 113 */ + { 0x2e0641c8, 0x6b0080 }, /* 114 */ + { 0x2e0641cc, 0x1a00001 }, /* 115 */ + { 0x2e0641d4, 0x10000 }, /* 117 */ + { 0x2e0641d8, 0x80200 }, /* 118 */ + { 0x2e064400, 0x4f0 }, /* 256 */ + { 0x2e064408, 0x1030200 }, /* 258 */ + { 0x2e064414, 0x3000000 }, /* 261 */ + { 0x2e064418, 0x1000001 }, /* 262 */ + { 0x2e06441c, 0x3000400 }, /* 263 */ + { 0x2e064420, 0x1 }, /* 264 */ + { 0x2e064424, 0x1 }, /* 265 */ + { 0x2e064430, 0x10000 }, /* 268 */ + { 0x2e064438, 0xc00004 }, /* 270 */ + { 0x2e06443c, 0xcc0008 }, /* 271 */ + { 0x2e064440, 0x660601 }, /* 272 */ + { 0x2e064444, 0x3 }, /* 273 */ + { 0x2e06444c, 0x1 }, /* 275 */ + { 0x2e064450, 0xaaaa }, /* 276 */ + { 0x2e064454, 0x5555 }, /* 277 */ + { 0x2e064458, 0xb5b5 }, /* 278 */ + { 0x2e06445c, 0x4a4a }, /* 279 */ + { 0x2e064460, 0x5656 }, /* 280 */ + { 0x2e064464, 0xa9a9 }, /* 281 */ + { 0x2e064468, 0xb7b7 }, /* 282 */ + { 0x2e06446c, 0x4848 }, /* 283 */ + { 0x2e064478, 0x8000000 }, /* 286 */ + { 0x2e06447c, 0x4010008 }, /* 287 */ + { 0x2e064480, 0x408 }, /* 288 */ + { 0x2e064484, 0x3102000 }, /* 289 */ + { 0x2e064488, 0xc0020 }, /* 290 */ + { 0x2e06448c, 0x10000 }, /* 291 */ + { 0x2e064490, 0x55555555 }, /* 292 */ + { 0x2e064494, 0xaaaaaaaa }, /* 293 */ + { 0x2e064498, 0x55555555 }, /* 294 */ + { 0x2e06449c, 0xaaaaaaaa }, /* 295 */ + { 0x2e0644a0, 0x5555 }, /* 296 */ + { 0x2e0644a4, 0x1000100 }, /* 297 */ + { 0x2e0644a8, 0x800180 }, /* 298 */ + { 0x2e064500, 0x4 }, /* 320 */ + { 0x2e06451c, 0x41f07ff }, /* 327 */ + { 0x2e064520, 0x1 }, /* 328 */ + { 0x2e064524, 0x1cc0800 }, /* 329 */ + { 0x2e064528, 0x3003cc08 }, /* 330 */ + { 0x2e06452c, 0x2000014e }, /* 331 */ + { 0x2e064530, 0x7ff0200 }, /* 332 */ + { 0x2e064534, 0x301 }, /* 333 */ + { 0x2e064540, 0x30000 }, /* 336 */ + { 0x2e064554, 0x2000000 }, /* 341 */ + { 0x2e064558, 0x51515042 }, /* 342 */ + { 0x2e06455c, 0x31c06000 }, /* 343 */ + { 0x2e064560, 0x9bf000a }, /* 344 */ + { 0x2e064564, 0xc0c000 }, /* 345 */ + { 0x2e064568, 0x1000000 }, /* 346 */ + { 0x2e06456c, 0x10001000 }, /* 347 */ + { 0x2e064570, 0xc043242 }, /* 348 */ + { 0x2e064574, 0xf0c1201 }, /* 349 */ + { 0x2e064578, 0x1000140 }, /* 350 */ + { 0x2e06457c, 0xc000120 }, /* 351 */ + { 0x2e064580, 0x143 }, /* 352 */ + { 0x2e064584, 0x1000203 }, /* 353 */ + { 0x2e064588, 0x30217465 }, /* 354 */ + { 0x2e06458c, 0x8 }, /* 355 */ + { 0x2e064590, 0x2c302c3 }, /* 356 */ + { 0x2e064594, 0x2c302c3 }, /* 357 */ + { 0x2e064598, 0x2c302c3 }, /* 358 */ + { 0x2e06459c, 0x2c302c3 }, /* 359 */ + { 0x2e0645a0, 0x2c3 }, /* 360 */ + { 0x2e0645a4, 0x8000 }, /* 361 */ + { 0x2e0645a8, 0x800080 }, /* 362 */ + { 0x2e0645ac, 0x800080 }, /* 363 */ + { 0x2e0645b0, 0x800080 }, /* 364 */ + { 0x2e0645b4, 0x800080 }, /* 365 */ + { 0x2e0645b8, 0x800080 }, /* 366 */ + { 0x2e0645bc, 0x800080 }, /* 367 */ + { 0x2e0645c0, 0x800080 }, /* 368 */ + { 0x2e0645c4, 0x800080 }, /* 369 */ + { 0x2e0645c8, 0x6b0080 }, /* 370 */ + { 0x2e0645cc, 0x1a00001 }, /* 371 */ + { 0x2e0645d4, 0x10000 }, /* 373 */ + { 0x2e0645d8, 0x80200 }, /* 374 */ + { 0x2e064800, 0x4f0 }, /* 512 */ + { 0x2e064808, 0x1030200 }, /* 514 */ + { 0x2e064814, 0x3000000 }, /* 517 */ + { 0x2e064818, 0x1000001 }, /* 518 */ + { 0x2e06481c, 0x3000400 }, /* 519 */ + { 0x2e064820, 0x1 }, /* 520 */ + { 0x2e064824, 0x1 }, /* 521 */ + { 0x2e064830, 0x10000 }, /* 524 */ + { 0x2e064838, 0xc00004 }, /* 526 */ + { 0x2e06483c, 0xcc0008 }, /* 527 */ + { 0x2e064840, 0x660601 }, /* 528 */ + { 0x2e064844, 0x3 }, /* 529 */ + { 0x2e06484c, 0x1 }, /* 531 */ + { 0x2e064850, 0xaaaa }, /* 532 */ + { 0x2e064854, 0x5555 }, /* 533 */ + { 0x2e064858, 0xb5b5 }, /* 534 */ + { 0x2e06485c, 0x4a4a }, /* 535 */ + { 0x2e064860, 0x5656 }, /* 536 */ + { 0x2e064864, 0xa9a9 }, /* 537 */ + { 0x2e064868, 0xb7b7 }, /* 538 */ + { 0x2e06486c, 0x4848 }, /* 539 */ + { 0x2e064878, 0x8000000 }, /* 542 */ + { 0x2e06487c, 0x4010008 }, /* 543 */ + { 0x2e064880, 0x408 }, /* 544 */ + { 0x2e064884, 0x3102000 }, /* 545 */ + { 0x2e064888, 0xc0020 }, /* 546 */ + { 0x2e06488c, 0x10000 }, /* 547 */ + { 0x2e064890, 0x55555555 }, /* 548 */ + { 0x2e064894, 0xaaaaaaaa }, /* 549 */ + { 0x2e064898, 0x55555555 }, /* 550 */ + { 0x2e06489c, 0xaaaaaaaa }, /* 551 */ + { 0x2e0648a0, 0x5555 }, /* 552 */ + { 0x2e0648a4, 0x1000100 }, /* 553 */ + { 0x2e0648a8, 0x800180 }, /* 554 */ + { 0x2e0648ac, 0x1 }, /* 555 */ + { 0x2e064900, 0x4 }, /* 576 */ + { 0x2e06491c, 0x41f07ff }, /* 583 */ + { 0x2e064920, 0x1 }, /* 584 */ + { 0x2e064924, 0x1cc0800 }, /* 585 */ + { 0x2e064928, 0x3003cc08 }, /* 586 */ + { 0x2e06492c, 0x2000014e }, /* 587 */ + { 0x2e064930, 0x7ff0200 }, /* 588 */ + { 0x2e064934, 0x301 }, /* 589 */ + { 0x2e064940, 0x30000 }, /* 592 */ + { 0x2e064954, 0x2000000 }, /* 597 */ + { 0x2e064958, 0x51515042 }, /* 598 */ + { 0x2e06495c, 0x31c06000 }, /* 599 */ + { 0x2e064960, 0x9bf000a }, /* 600 */ + { 0x2e064964, 0xc0c000 }, /* 601 */ + { 0x2e064968, 0x1000000 }, /* 602 */ + { 0x2e06496c, 0x10001000 }, /* 603 */ + { 0x2e064970, 0xc043242 }, /* 604 */ + { 0x2e064974, 0xf0c1201 }, /* 605 */ + { 0x2e064978, 0x1000140 }, /* 606 */ + { 0x2e06497c, 0xc000120 }, /* 607 */ + { 0x2e064980, 0x143 }, /* 608 */ + { 0x2e064984, 0x1000203 }, /* 609 */ + { 0x2e064988, 0x75436012 }, /* 610 */ + { 0x2e06498c, 0x8 }, /* 611 */ + { 0x2e064990, 0x2c302c3 }, /* 612 */ + { 0x2e064994, 0x2c302c3 }, /* 613 */ + { 0x2e064998, 0x2c302c3 }, /* 614 */ + { 0x2e06499c, 0x2c302c3 }, /* 615 */ + { 0x2e0649a0, 0x2c3 }, /* 616 */ + { 0x2e0649a4, 0x8000 }, /* 617 */ + { 0x2e0649a8, 0x800080 }, /* 618 */ + { 0x2e0649ac, 0x800080 }, /* 619 */ + { 0x2e0649b0, 0x800080 }, /* 620 */ + { 0x2e0649b4, 0x800080 }, /* 621 */ + { 0x2e0649b8, 0x800080 }, /* 622 */ + { 0x2e0649bc, 0x800080 }, /* 623 */ + { 0x2e0649c0, 0x800080 }, /* 624 */ + { 0x2e0649c4, 0x800080 }, /* 625 */ + { 0x2e0649c8, 0x6b0080 }, /* 626 */ + { 0x2e0649cc, 0x1a00001 }, /* 627 */ + { 0x2e0649d4, 0x10000 }, /* 629 */ + { 0x2e0649d8, 0x80200 }, /* 630 */ + { 0x2e064c00, 0x4f0 }, /* 768 */ + { 0x2e064c08, 0x1030200 }, /* 770 */ + { 0x2e064c14, 0x3000000 }, /* 773 */ + { 0x2e064c18, 0x1000001 }, /* 774 */ + { 0x2e064c1c, 0x3000400 }, /* 775 */ + { 0x2e064c20, 0x1 }, /* 776 */ + { 0x2e064c24, 0x1 }, /* 777 */ + { 0x2e064c30, 0x10000 }, /* 780 */ + { 0x2e064c38, 0xc00004 }, /* 782 */ + { 0x2e064c3c, 0xcc0008 }, /* 783 */ + { 0x2e064c40, 0x660601 }, /* 784 */ + { 0x2e064c44, 0x3 }, /* 785 */ + { 0x2e064c4c, 0x1 }, /* 787 */ + { 0x2e064c50, 0xaaaa }, /* 788 */ + { 0x2e064c54, 0x5555 }, /* 789 */ + { 0x2e064c58, 0xb5b5 }, /* 790 */ + { 0x2e064c5c, 0x4a4a }, /* 791 */ + { 0x2e064c60, 0x5656 }, /* 792 */ + { 0x2e064c64, 0xa9a9 }, /* 793 */ + { 0x2e064c68, 0xb7b7 }, /* 794 */ + { 0x2e064c6c, 0x4848 }, /* 795 */ + { 0x2e064c78, 0x8000000 }, /* 798 */ + { 0x2e064c7c, 0x4010008 }, /* 799 */ + { 0x2e064c80, 0x408 }, /* 800 */ + { 0x2e064c84, 0x3102000 }, /* 801 */ + { 0x2e064c88, 0xc0020 }, /* 802 */ + { 0x2e064c8c, 0x10000 }, /* 803 */ + { 0x2e064c90, 0x55555555 }, /* 804 */ + { 0x2e064c94, 0xaaaaaaaa }, /* 805 */ + { 0x2e064c98, 0x55555555 }, /* 806 */ + { 0x2e064c9c, 0xaaaaaaaa }, /* 807 */ + { 0x2e064ca0, 0x5555 }, /* 808 */ + { 0x2e064ca4, 0x1000100 }, /* 809 */ + { 0x2e064ca8, 0x800180 }, /* 810 */ + { 0x2e064d00, 0x4 }, /* 832 */ + { 0x2e064d1c, 0x41f07ff }, /* 839 */ + { 0x2e064d20, 0x1 }, /* 840 */ + { 0x2e064d24, 0x1cc0800 }, /* 841 */ + { 0x2e064d28, 0x3003cc08 }, /* 842 */ + { 0x2e064d2c, 0x2000014e }, /* 843 */ + { 0x2e064d30, 0x7ff0200 }, /* 844 */ + { 0x2e064d34, 0x301 }, /* 845 */ + { 0x2e064d40, 0x30000 }, /* 848 */ + { 0x2e064d54, 0x2000000 }, /* 853 */ + { 0x2e064d58, 0x51515042 }, /* 854 */ + { 0x2e064d5c, 0x31c06000 }, /* 855 */ + { 0x2e064d60, 0x9bf000a }, /* 856 */ + { 0x2e064d64, 0xc0c000 }, /* 857 */ + { 0x2e064d68, 0x1000000 }, /* 858 */ + { 0x2e064d6c, 0x10001000 }, /* 859 */ + { 0x2e064d70, 0xc043242 }, /* 860 */ + { 0x2e064d74, 0xf0c1201 }, /* 861 */ + { 0x2e064d78, 0x1000140 }, /* 862 */ + { 0x2e064d7c, 0xc000120 }, /* 863 */ + { 0x2e064d80, 0x143 }, /* 864 */ + { 0x2e064d84, 0x1000203 }, /* 865 */ + { 0x2e064d88, 0x32017465 }, /* 866 */ + { 0x2e064d8c, 0x8 }, /* 867 */ + { 0x2e064d90, 0x2c302c3 }, /* 868 */ + { 0x2e064d94, 0x2c302c3 }, /* 869 */ + { 0x2e064d98, 0x2c302c3 }, /* 870 */ + { 0x2e064d9c, 0x2c302c3 }, /* 871 */ + { 0x2e064da0, 0x2c3 }, /* 872 */ + { 0x2e064da4, 0x8000 }, /* 873 */ + { 0x2e064da8, 0x800080 }, /* 874 */ + { 0x2e064dac, 0x800080 }, /* 875 */ + { 0x2e064db0, 0x800080 }, /* 876 */ + { 0x2e064db4, 0x800080 }, /* 877 */ + { 0x2e064db8, 0x800080 }, /* 878 */ + { 0x2e064dbc, 0x800080 }, /* 879 */ + { 0x2e064dc0, 0x800080 }, /* 880 */ + { 0x2e064dc4, 0x800080 }, /* 881 */ + { 0x2e064dc8, 0x6b0080 }, /* 882 */ + { 0x2e064dcc, 0x1a00001 }, /* 883 */ + { 0x2e064dd4, 0x10000 }, /* 885 */ + { 0x2e064dd8, 0x80200 }, /* 886 */ + { 0x2e065014, 0x100 }, /* 1029 */ + { 0x2e065018, 0x201 }, /* 1030 */ + { 0x2e06502c, 0x400000 }, /* 1035 */ + { 0x2e065030, 0x80 }, /* 1036 */ + { 0x2e065034, 0xdcba98 }, /* 1037 */ + { 0x2e065038, 0x3000000 }, /* 1038 */ + { 0x2e06504c, 0x2a }, /* 1043 */ + { 0x2e065050, 0x15 }, /* 1044 */ + { 0x2e065054, 0x15 }, /* 1045 */ + { 0x2e065058, 0x2a }, /* 1046 */ + { 0x2e06505c, 0x33 }, /* 1047 */ + { 0x2e065060, 0xc }, /* 1048 */ + { 0x2e065064, 0xc }, /* 1049 */ + { 0x2e065068, 0x33 }, /* 1050 */ + { 0x2e06506c, 0x543210 }, /* 1051 */ + { 0x2e065070, 0x3f0000 }, /* 1052 */ + { 0x2e065074, 0xf013f }, /* 1053 */ + { 0x2e065078, 0xf }, /* 1054 */ + { 0x2e06507c, 0x3cc }, /* 1055 */ + { 0x2e065080, 0x30000 }, /* 1056 */ + { 0x2e065084, 0x300 }, /* 1057 */ + { 0x2e065088, 0x300 }, /* 1058 */ + { 0x2e06508c, 0x300 }, /* 1059 */ + { 0x2e065090, 0x300 }, /* 1060 */ + { 0x2e065094, 0x300 }, /* 1061 */ + { 0x2e065098, 0x42080010 }, /* 1062 */ + { 0x2e06509c, 0x332 }, /* 1063 */ + { 0x2e0650a0, 0x2 }, /* 1064 */ + { 0x2e065414, 0x100 }, /* 1285 */ + { 0x2e065418, 0x201 }, /* 1286 */ + { 0x2e06542c, 0x400000 }, /* 1291 */ + { 0x2e065430, 0x80 }, /* 1292 */ + { 0x2e065434, 0xdcba98 }, /* 1293 */ + { 0x2e065438, 0x3000000 }, /* 1294 */ + { 0x2e06544c, 0x2a }, /* 1299 */ + { 0x2e065450, 0x15 }, /* 1300 */ + { 0x2e065454, 0x15 }, /* 1301 */ + { 0x2e065458, 0x2a }, /* 1302 */ + { 0x2e06545c, 0x33 }, /* 1303 */ + { 0x2e065460, 0xc }, /* 1304 */ + { 0x2e065464, 0xc }, /* 1305 */ + { 0x2e065468, 0x33 }, /* 1306 */ + { 0x2e06546c, 0x543210 }, /* 1307 */ + { 0x2e065470, 0x3f0000 }, /* 1308 */ + { 0x2e065474, 0xf013f }, /* 1309 */ + { 0x2e065478, 0xf }, /* 1310 */ + { 0x2e06547c, 0x3cc }, /* 1311 */ + { 0x2e065480, 0x30000 }, /* 1312 */ + { 0x2e065484, 0x300 }, /* 1313 */ + { 0x2e065488, 0x300 }, /* 1314 */ + { 0x2e06548c, 0x300 }, /* 1315 */ + { 0x2e065490, 0x300 }, /* 1316 */ + { 0x2e065494, 0x300 }, /* 1317 */ + { 0x2e065498, 0x42080010 }, /* 1318 */ + { 0x2e06549c, 0x332 }, /* 1319 */ + { 0x2e0654a0, 0x2 }, /* 1320 */ + { 0x2e065804, 0x100 }, /* 1537 */ + { 0x2e065814, 0x50000 }, /* 1541 */ + { 0x2e065818, 0x4000100 }, /* 1542 */ + { 0x2e06581c, 0x55 }, /* 1543 */ + { 0x2e06582c, 0xf0001 }, /* 1547 */ + { 0x2e065830, 0x280040 }, /* 1548 */ + { 0x2e065834, 0x5002 }, /* 1549 */ + { 0x2e065838, 0x10101 }, /* 1550 */ + { 0x2e065840, 0x90e0000 }, /* 1552 */ + { 0x2e065844, 0x101010f }, /* 1553 */ + { 0x2e065848, 0x10f0004 }, /* 1554 */ + { 0x2e065854, 0x64 }, /* 1557 */ + { 0x2e06585c, 0x1000000 }, /* 1559 */ + { 0x2e065860, 0x8040201 }, /* 1560 */ + { 0x2e065864, 0x2010201 }, /* 1561 */ + { 0x2e065868, 0xf0f0f }, /* 1562 */ + { 0x2e06586c, 0x241b42 }, /* 1563 */ + { 0x2e065874, 0x1020000 }, /* 1565 */ + { 0x2e065878, 0x701 }, /* 1566 */ + { 0x2e06587c, 0x54 }, /* 1567 */ + { 0x2e065880, 0x4102000 }, /* 1568 */ + { 0x2e065884, 0x24410 }, /* 1569 */ + { 0x2e065888, 0x4410 }, /* 1570 */ + { 0x2e06588c, 0x4410 }, /* 1571 */ + { 0x2e065890, 0x4410 }, /* 1572 */ + { 0x2e065894, 0x4410 }, /* 1573 */ + { 0x2e065898, 0x4410 }, /* 1574 */ + { 0x2e06589c, 0x4410 }, /* 1575 */ + { 0x2e0658a0, 0x4410 }, /* 1576 */ + { 0x2e0658a4, 0x4410 }, /* 1577 */ + { 0x2e0658b0, 0x60000 }, /* 1580 */ + { 0x2e0658b8, 0x96 }, /* 1582 */ + { 0x2e0658bc, 0x10000 }, /* 1583 */ + { 0x2e0658c0, 0x8 }, /* 1584 */ + { 0x2e0658d8, 0x3000000 }, /* 1590 */ + { 0x2e0658e8, 0x4102006 }, /* 1594 */ + { 0x2e0658ec, 0x41020 }, /* 1595 */ + { 0x2e0658f0, 0x1c98c98 }, /* 1596 */ + { 0x2e0658f4, 0x3f400000 }, /* 1597 */ + { 0x2e0658f8, 0x3f3f1f3f }, /* 1598 */ + { 0x2e0658fc, 0x1f }, /* 1599 */ + { 0x2e06590c, 0x1 }, /* 1603 */ + { 0x2e06591c, 0x1 }, /* 1607 */ + { 0x2e065920, 0x76543210 }, /* 1608 */ + { 0x2e065924, 0x10198 }, /* 1609 */ + { 0x2e065934, 0x40700 }, /* 1613 */ + { 0x2e06594c, 0x2 }, /* 1619 */ + { 0x2e065958, 0xf3c3 }, /* 1622 */ + { 0x2e065964, 0x11542 }, /* 1625 */ + { 0x2e065968, 0x30209bf }, /* 1626 */ + { 0x2e06596c, 0x30000 }, /* 1627 */ + { 0x2e065970, 0x3000300 }, /* 1628 */ + { 0x2e065974, 0x3000300 }, /* 1629 */ + { 0x2e065978, 0x3000300 }, /* 1630 */ + { 0x2e06597c, 0x3000300 }, /* 1631 */ + { 0x2e065980, 0x300 }, /* 1632 */ + { 0x2e065984, 0x300 }, /* 1633 */ + { 0x2e065988, 0x300 }, /* 1634 */ + { 0x2e06598c, 0x4bf77 }, /* 1635 */ + { 0x2e065990, 0x77 }, /* 1636 */ + { 0x2e065994, 0x27f }, /* 1637 */ + { 0x2e06599c, 0x27f }, /* 1639 */ + { 0x2e0659a4, 0x27f00 }, /* 1641 */ + { 0x2e0659a8, 0x1980000 }, /* 1642 */ + { 0x2e0659ac, 0x27fcc }, /* 1643 */ + { 0x2e0659b4, 0x27f00 }, /* 1645 */ + { 0x2e0659b8, 0x1980000 }, /* 1646 */ + { 0x2e0659bc, 0x27f00 }, /* 1647 */ + { 0x2e0659c0, 0x1980000 }, /* 1648 */ + { 0x2e0659c4, 0x27f00 }, /* 1649 */ + { 0x2e0659c8, 0x1980000 }, /* 1650 */ + { 0x2e0659cc, 0x27f00 }, /* 1651 */ + { 0x2e0659d0, 0x1980000 }, /* 1652 */ + { 0x2e0659d4, 0x20040003 }, /* 1653 */ +}; + +/** PHY_F2 settings **/ +struct dram_cfg_param ddr_phy_f2_cfg[] = { + { 0x2e064168, 0x3020000 }, /* 90 */ + { 0x2e064170, 0xc043e42 }, /* 92 */ + { 0x2e064174, 0xf0c1701 }, /* 93 */ + { 0x2e064180, 0x187 }, /* 96 */ + { 0x2e064184, 0x3010203 }, /* 97 */ + { 0x2e064190, 0x3070307 }, /* 100 */ + { 0x2e064194, 0x3070307 }, /* 101 */ + { 0x2e064198, 0x3070307 }, /* 102 */ + { 0x2e06419c, 0x3070307 }, /* 103 */ + { 0x2e0641a0, 0x307 }, /* 104 */ + { 0x2e0641c8, 0x1bd0080 }, /* 114 */ + { 0x2e064568, 0x3020000 }, /* 346 */ + { 0x2e064570, 0xc043e42 }, /* 348 */ + { 0x2e064574, 0xf0c1701 }, /* 349 */ + { 0x2e064580, 0x187 }, /* 352 */ + { 0x2e064584, 0x3010203 }, /* 353 */ + { 0x2e064590, 0x3070307 }, /* 356 */ + { 0x2e064594, 0x3070307 }, /* 357 */ + { 0x2e064598, 0x3070307 }, /* 358 */ + { 0x2e06459c, 0x3070307 }, /* 359 */ + { 0x2e0645a0, 0x307 }, /* 360 */ + { 0x2e0645c8, 0x1bd0080 }, /* 370 */ + { 0x2e064968, 0x3020000 }, /* 602 */ + { 0x2e064970, 0xc043e42 }, /* 604 */ + { 0x2e064974, 0xf0c1701 }, /* 605 */ + { 0x2e064980, 0x187 }, /* 608 */ + { 0x2e064984, 0x3010203 }, /* 609 */ + { 0x2e064990, 0x3070307 }, /* 612 */ + { 0x2e064994, 0x3070307 }, /* 613 */ + { 0x2e064998, 0x3070307 }, /* 614 */ + { 0x2e06499c, 0x3070307 }, /* 615 */ + { 0x2e0649a0, 0x307 }, /* 616 */ + { 0x2e0649c8, 0x1bd0080 }, /* 626 */ + { 0x2e064d68, 0x3020000 }, /* 858 */ + { 0x2e064d70, 0xc043e42 }, /* 860 */ + { 0x2e064d74, 0xf0c1701 }, /* 861 */ + { 0x2e064d80, 0x187 }, /* 864 */ + { 0x2e064d84, 0x3010203 }, /* 865 */ + { 0x2e064d90, 0x3070307 }, /* 868 */ + { 0x2e064d94, 0x3070307 }, /* 869 */ + { 0x2e064d98, 0x3070307 }, /* 870 */ + { 0x2e064d9c, 0x3070307 }, /* 871 */ + { 0x2e064da0, 0x307 }, /* 872 */ + { 0x2e064dc8, 0x1bd0080 }, /* 882 */ + { 0x2e06509c, 0x33e }, /* 1063 */ + { 0x2e06549c, 0x33e }, /* 1319 */ + { 0x2e065878, 0x10703 }, /* 1566 */ + { 0x2e065964, 0x1342 }, /* 1625 */ +}; + +/* ddr timing config params */ +struct dram_timing_info2 dram_timing = { + .ctl_cfg = ddr_ctl_cfg, + .ctl_cfg_num = ARRAY_SIZE(ddr_ctl_cfg), + .pi_cfg = ddr_pi_cfg, + .pi_cfg_num = ARRAY_SIZE(ddr_pi_cfg), + .phy_f1_cfg = ddr_phy_f1_cfg, + .phy_f1_cfg_num = ARRAY_SIZE(ddr_phy_f1_cfg), + .phy_f2_cfg = ddr_phy_f2_cfg, + .phy_f2_cfg_num = ARRAY_SIZE(ddr_phy_f2_cfg), + .fsp_table = { 96, 528, 1056 }, +}; diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c new file mode 100644 index 0000000000..faece336ef --- /dev/null +++ b/board/freescale/imx8ulp_evk/spl.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_dram_init(void) +{ + init_clk_ddr(); + ddr_init(&dram_timing); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOOTROM; +} + +int power_init_board(void) +{ + u32 pmic_reg; + + /* PMIC set bucks1-4 to PWM mode */ + upower_pmic_i2c_read(0x10, &pmic_reg); + upower_pmic_i2c_read(0x14, &pmic_reg); + upower_pmic_i2c_read(0x21, &pmic_reg); + upower_pmic_i2c_read(0x2e, &pmic_reg); + + upower_pmic_i2c_write(0x10, 0x3d); + upower_pmic_i2c_write(0x14, 0x7d); + upower_pmic_i2c_write(0x21, 0x7d); + upower_pmic_i2c_write(0x2e, 0x3d); + + upower_pmic_i2c_read(0x10, &pmic_reg); + upower_pmic_i2c_read(0x14, &pmic_reg); + upower_pmic_i2c_read(0x21, &pmic_reg); + upower_pmic_i2c_read(0x2e, &pmic_reg); + + /* Set buck3 to 1.1v OD */ + upower_pmic_i2c_write(0x22, 0x28); + return 0; +} + +void spl_board_init(void) +{ + struct udevice *dev; + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + board_early_init_f(); + + preloader_console_init(); + + puts("Normal Boot\n"); + + /* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */ + + upower_init(); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + /* This must place after upower init, so access to MDA and MRC are valid */ + /* Init XRDC MDA */ + xrdc_init_mda(); + + /* Init XRDC MRC for VIDEO, DSP domains */ + xrdc_init_mrc(); +} + +void board_init_f(ulong dummy) +{ + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + board_init_r(NULL, 0); +} diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig new file mode 100644 index 0000000000..464e30601d --- /dev/null +++ b/configs/imx8ulp_evk_defconfig @@ -0,0 +1,103 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8ULP=y +CONFIG_SYS_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_IMX8ULP_EVK=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_SPL_TEXT_BASE=0x22020000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTDELAY=0 +CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk" +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +#CONFIG_SPL_RAM_SUPPORT=y +#CONFIG_SPL_RAM_DEVICE=y +#CONFIG_SPL_MMC_SUPPORT=y + +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 + +CONFIG_HUSH_PARSER=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk" +CONFIG_SPL_DM=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8ULP=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y +CONFIG_CMD_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_MISC=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" + +CONFIG_CMD_I2C=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_READ=y +CONFIG_BAUDRATE=115200 + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MMC_ENV_DEV=0 + +CONFIG_ULP_WATCHDOG=y +CONFIG_SPL_WATCHDOG=y + +CONFIG_CMD_SF=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_IMX_RGPIO2P=y +CONFIG_USE_ARCH_MEMCPY=y + +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_CMD_NET=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_NET_RANDOM_ETHADDR=y + +CONFIG_EFI_PARTITION=y + +CONFIG_DM_PCA953X=y diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h new file mode 100644 index 0000000000..32f8773b24 --- /dev/null +++ b/include/configs/imx8ulp_evk.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __IMX8ULP_EVK_H +#define __IMX8ULP_EVK_H + +#include +#include + +#define CONFIG_SYS_BOOTM_LEN (SZ_64M) +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x22050000 +#define CONFIG_SPL_BSS_START_ADDR 0x22048000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x22040000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x8000 /* 32 KB */ + +#define CONFIG_MALLOC_F_ADDR 0x22040000 + +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x95000000 /* SPL_RAM needed */ + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ + +#endif + +#define CONFIG_SERIAL_TAG + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +/* ENET Config */ +#if defined(CONFIG_FEC_MXC) +#define CONFIG_ETHPRIME "FEC" +#define PHY_ANEG_TIMEOUT 20000 + +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_FEC_MXC_PHYADDR 1 + +#define IMX_FEC_BASE 0x29950000 +#endif + +#ifdef CONFIG_DISTRO_DEFAULTS +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#include +#else +#define BOOTENV +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "image=Image\0" \ + "console=ttyLP1,115200 earlycon\0" \ + "fdt_addr_r=0x83000000\0" \ + "boot_fit=no\0" \ + "fdtfile=imx8ulp-evk.dtb\0" \ + "initrd_addr=0x83800000\0" \ + "bootm_size=0x10000000\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_MMCROOT "/dev/mmcblk2p2" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_16M) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG3_RBASE +#endif -- cgit v1.2.3