From e45fcb0e76b51d1e805f077ec160f99ff2edfa36 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Thu, 4 May 2023 15:54:59 +0800 Subject: doc: Add info for building Xen target with Clang When build Xen target with Clang, the linker reports failure. This patch adds the related info in the documentation as a known issue and gives details for how to dismiss the building failure with Clang. Signed-off-by: Leo Yan --- doc/build/clang.rst | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'doc') diff --git a/doc/build/clang.rst b/doc/build/clang.rst index 1d35616eb5..cc265506c2 100644 --- a/doc/build/clang.rst +++ b/doc/build/clang.rst @@ -74,3 +74,39 @@ simplified with a simple wrapper script - saved as #!/bin/sh exec clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd "$@" + + +Known Issues +------------ + +When build U-boot for `xenguest_arm64_defconfig` target, it reports linkage +error: + +.. code-block:: bash + + aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `do_hypervisor_callback': + /home/leoy/Dev2/u-boot/drivers/xen/hypervisor.c:188: undefined reference to `__aarch64_swp8_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_set_bit': + /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:40: undefined reference to `__aarch64_ldset1_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_clear_bit': + /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:28: undefined reference to `__aarch64_ldclr1_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_set_bit': + /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:40: undefined reference to `__aarch64_ldset1_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_clear_bit': + /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:28: undefined reference to `__aarch64_ldclr1_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/events.o: in function `synch_test_and_clear_bit': + /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:28: undefined reference to `__aarch64_ldclr1_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/events.o: in function `synch_test_and_set_bit': + /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:40: undefined reference to `__aarch64_ldset1_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/gnttab.o: in function `gnttab_end_access': + /home/leoy/Dev2/u-boot/drivers/xen/gnttab.c:109: undefined reference to `__aarch64_cas2_acq_rel' + Segmentation fault + +To fix the failure, we need to append option `-mno-outline-atomics` in Clang +command to not generate local calls to out-of-line atomic operations: + +.. code-block:: bash + + make HOSTCC=clang xenguest_arm64_defconfig + make HOSTCC=clang CROSS_COMPILE=aarch64-linux-gnu- \ + CC="clang -target aarch64-linux-gnueabi -mno-outline-atomics" -j8 -- cgit v1.2.3 From db7af51020f84c41e5c759567fbe5bbe83c8ab8f Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Thu, 11 May 2023 14:47:48 +0530 Subject: doc: board: ti: add documenation for j7200 This patch adds documentation for j7200. TRM link https://www.ti.com/lit/pdf/spruiu1 Signed-off-by: Udit Kumar Tested-by: Heinrich Schuchardt --- doc/board/ti/j7200_evm.rst | 332 +++++++++++++++++++++++++++++++++++++++++++++ doc/board/ti/k3.rst | 1 + 2 files changed, 333 insertions(+) create mode 100644 doc/board/ti/j7200_evm.rst (limited to 'doc') diff --git a/doc/board/ti/j7200_evm.rst b/doc/board/ti/j7200_evm.rst new file mode 100644 index 0000000000..0d3a526516 --- /dev/null +++ b/doc/board/ti/j7200_evm.rst @@ -0,0 +1,332 @@ +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +.. sectionauthor:: Udit Kumar + +J7200 Platforms +=============== + +Introduction: +------------- +The J7200 family of SoCs are part of K3 Multicore SoC architecture platform +targeting automotive applications. They are designed as a low power, high +performance and highly integrated device architecture, adding significant +enhancement on processing power, graphics capability, video and imaging +processing, virtualization and coherent memory support. + +The device is partitioned into three functional domains, each containing +specific processing cores and peripherals: + +1. Wake-up (WKUP) domain: + * Device Management and Security Controller (DMSC) + +2. Microcontroller (MCU) domain: + * Dual Core ARM Cortex-R5F processor + +3. MAIN domain: + * Dual core 64-bit ARM Cortex-A72 + +More info can be found in TRM: https://www.ti.com/lit/pdf/spruiu1 + +Boot Flow: +---------- +Below is the pictorial representation of boot flow: + +.. code-block:: text + + +------------------------------------------------------------------------+-----------------------+ + | DMSC | MCU R5 | A72 | MAIN R5/C7x | + +------------------------------------------------------------------------+-----------------------+ + | +--------+ | | | | + | | Reset | | | | | + | +--------+ | | | | + | : | | | | + | +--------+ | +-----------+ | | | + | | *ROM* |----------|-->| Reset rls | | | | + | +--------+ | +-----------+ | | | + | | | | : | | | + | | ROM | | : | | | + | |services| | : | | | + | | | | +-------------+ | | | + | | | | | *R5 ROM* | | | | + | | | | +-------------+ | | | + | | |<---------|---|Load and auth| | | | + | | | | | tiboot3.bin | | | | + | | Start | | +-------------+ | | | + | | TIFS |<---------|---| Start | | | | + | | | | | TIFS | | | | + | +--------+ | +-------------+ | | | + | : | | | | | | + | +---------+ | | Load | | | | + | | *TIFS* | | | system | | | | + | +---------+ | | Config data | | | | + | | |<--------|---| | | | | + | | | | +-------------+ | | | + | | | | : | | | + | | | | : | | | + | | | | : | | | + | | | | +-------------+ | | | + | | | | | *R5 SPL* | | | | + | | | | +-------------+ | | | + | | | | | DDR | | | | + | | | | | config | | | | + | | | | +-------------+ | | | + | | | | | Load | | | | + | | | | | tispl.bin | | | | + | | | | +-------------+ | | | + | | | | | Load R5 | | | | + | | | | | firmware | | | | + | | | | +-------------+ | | | + | | |<--------|---| Start A72 | | | | + | | | | | and jump to | | | | + | | | | | DM fw image | | | | + | | | | +-------------+ | | | + | | | | | +-----------+ | | + | | |---------|-----------------------|---->| Reset rls | | | + | | | | | +-----------+ | | + | | TIFS | | | : | | + | |Services | | | +-----------+ | | + | | |<--------|-----------------------|---->|*ATF/OPTEE*| | | + | | | | | +-----------+ | | + | | | | | : | | + | | | | | +-----------+ | | + | | |<--------|-----------------------|---->| *A72 SPL* | | | + | | | | | +-----------+ | | + | | | | | | Load | | | + | | | | | | u-boot.img| | | + | | | | | +-----------+ | | + | | | | | : | | + | | | | | +-----------+ | | + | | |<--------|-----------------------|---->| *U-Boot* | | | + | | | | | +-----------+ | | + | | | | | | prompt | | | + | | | | | +-----------+ | | + | | | | | | Load R5 | | | + | | | | | | Firmware | | | + | | | | | +-----------+ | | + | | |<--------|-----------------------|-----| Start R5 | | +-----------+ | + | | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | | + | | | | | | Load C7 | | +-----------+ | + | | | | | | Firmware | | | + | | | | | +-----------+ | | + | | |<--------|-----------------------|-----| Start C7 | | +-----------+ | + | | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | | + | | | | | | +-----------+ | + | | | | | | | + | +---------+ | | | | + | | | | | + +------------------------------------------------------------------------+-----------------------+ + +- Here DMSC acts as master and provides all the critical services. R5/A72 + requests DMSC to get these services done as shown in the above diagram. + +Sources: +-------- +1. SYSFW: + Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git + Branch: master + +2. ATF: + Tree: https://github.com/ARM-software/arm-trusted-firmware.git + Branch: master + +3. OPTEE: + Tree: https://github.com/OP-TEE/optee_os.git + Branch: master + +4. DM Firmware: + Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git + Branch: ti-linux-firmware + +5. U-Boot: + Tree: https://source.denx.de/u-boot/u-boot + Branch: master + +Build procedure: +---------------- +1. SYSFW: + +.. code-block:: bash + + make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- SOC=j7200 SBL=u-boot-spl.bin SYSFW_PATH=/ti-fs-firmware-j7200-gp.bin + u-boot-spl.bin is generated at step 4. + +2. ATF: + +.. code-block:: bash + + make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed + +3. OPTEE: + +.. code-block:: bash + + make PLATFORM=k3-j7200 CFG_ARM64_core=y + +4. U-Boot: + +* 4.1 R5: + +.. code-block:: bash + + make CROSS_COMPILE=arm-linux-gnueabihf- j7200_evm_r5_defconfig O=build/r5 + make CROSS_COMPILE=arm-linux-gnueabihf- O=build/r5 + +* 4.2 A72: + +.. code-block:: bash + + make CROSS_COMPILE=aarch64-linux-gnu- j7200_evm_a72_defconfig O=build/a72 + make CROSS_COMPILE=aarch64-linux-gnu- ATF=/build/k3/generic/release/bl31.bin TEE=/out/arm-plat-k3/core/tee-pager_v2.bin DM=/ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f O=build/a72 + +Target Images +-------------- +Copy the below images to an SD card and boot: + - tiboot3.bin from step 1 + - tispl.bin, u-boot.img from 4.2 + +Image formats: +-------------- + +- tiboot3.bin: + +.. code-block:: console + + +-----------------------+ + | X.509 | + | Certificate | + | +-------------------+ | + | | | | + | | R5 | | + | | u-boot-spl.bin | | + | | | | + | +-------------------+ | + | | | | + | | FIT header | | + | | +---------------+ | | + | | | | | | + | | | DTB 1...N | | | + | | +---------------+ | | + | +-------------------+ | + | | | | + | | FIT HEADER | | + | | +---------------+ | | + | | | | | | + | | | sysfw.bin | | | + | | +---------------+ | | + | | | | | | + | | | board config | | | + | | +---------------+ | | + | | | | | | + | | | PM config | | | + | | +---------------+ | | + | | | | | | + | | | RM config | | | + | | +---------------+ | | + | | | | | | + | | | Secure config | | | + | | +---------------+ | | + | +-------------------+ | + +-----------------------+ + +- tispl.bin + +.. code-block:: console + + +-----------------------+ + | | + | FIT HEADER | + | +-------------------+ | + | | | | + | | A72 ATF | | + | +-------------------+ | + | | | | + | | A72 OPTEE | | + | +-------------------+ | + | | | | + | | R5 DM FW | | + | +-------------------+ | + | | | | + | | A72 SPL | | + | +-------------------+ | + | | | | + | | SPL DTB 1...N | | + | +-------------------+ | + +-----------------------+ + + +Switch Setting for Boot Mode +---------------------------- + +Boot Mode pins provide means to select the boot mode and options before the +device is powered up. After every POR, they are the main source to populate +the Boot Parameter Tables. + +The following table shows some common boot modes used on J7200 platform. More +details can be found in the Technical Reference Manual: +https://www.ti.com/lit/pdf/spruiu1 under the `Boot Mode Pins` section. + + +*Boot Modes* + +============ ============= ============= +Switch Label SW9: 12345678 SW8: 12345678 +============ ============= ============= +SD 00000000 10000010 +EMMC 01000000 10000000 +OSPI 01000000 00000110 +UART 01110000 00000000 +USB DFU 00100000 10000000 +============ ============= ============= + +For SW8 and SW9, the switch state in the "ON" position = 1. + +eMMC: +----- +ROM supports booting from eMMC raw read or UDA FS mode. + +Below is memory layout in case of booting from +boot 0/1 partition in raw mode. + +Current allocated size for tiboot3 size is 1MB, tispl is 2MB. + +Size of u-boot.img is taken 4MB for refernece, +But this is subject to change depending upon atf, optee size + +.. code-block:: console + + boot0/1 partition (8 MB) user partition + 0x0+----------------------------------+ 0x0+------------------------+ + | tiboot3.bin (1 MB) | | | + 0x800+----------------------------------+ | | + | tispl.bin (2 MB) | | | + 0x1800+----------------------------------+ | | + | u-boot.img (4MB) | | | + 0x3800+----------------------------------+ | | + | | | | + 0x3900+ environment | | | + | | | | + 0x3A00+----------------------------------+ +-------------------------+ + +In case of UDA FS mode booting, following is layout. + +All boot images tiboot3.bin, tispl and u-boot should be written to +fat formatted UDA FS as file. + +.. code-block:: console + + boot0/1 partition (8 MB) user partition + 0x0+---------------------------------+ 0x0+-------------------------+ + | | | tiboot3.bin* | + 0x800+----------------------------------+ | | + | | | tispl.bin | + 0x1800+----------------------------------+ | | + | | | u-boot.img | + 0x3800+----------------------------------+ | | + | | | | + 0x3900+ | | environment | + | | | | + 0x3A00+----------------------------------+ +-------------------------+ + + + +In case of booting from eMMC, write above images into raw or UDA FS. +and set mmc partconf accordingly. diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index b49a60caf1..2b2f4bb8bb 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -31,6 +31,7 @@ K3 Based SoCs :maxdepth: 1 j721e_evm + j7200_evm am62x_sk Boot Flow Overview -- cgit v1.2.3 From 25dc7d5aedfef310a7e49b37e2556dc84b79cb00 Mon Sep 17 00:00:00 2001 From: Masahisa Kojima Date: Wed, 7 Jun 2023 14:41:54 +0900 Subject: efi_loader: get lowest supported version from device tree This commit gets the lowest supported version from device tree, then fills the lowest supported version in FMP->GetImageInfo(). Signed-off-by: Masahisa Kojima Reviewed-by: Ilias Apalodimas --- .../firmware/firmware-version.txt | 22 ++++++++++ lib/efi_loader/efi_firmware.c | 50 +++++++++++++++++++++- 2 files changed, 71 insertions(+), 1 deletion(-) create mode 100644 doc/device-tree-bindings/firmware/firmware-version.txt (limited to 'doc') diff --git a/doc/device-tree-bindings/firmware/firmware-version.txt b/doc/device-tree-bindings/firmware/firmware-version.txt new file mode 100644 index 0000000000..ee90ce3117 --- /dev/null +++ b/doc/device-tree-bindings/firmware/firmware-version.txt @@ -0,0 +1,22 @@ +firmware-version bindings +------------------------------- + +Required properties: +- image-type-id : guid for image blob type +- image-index : image index +- lowest-supported-version : lowest supported version + +Example: + + firmware-version { + image1 { + image-type-id = "09D7CF52-0720-4710-91D1-08469B7FE9C8"; + image-index = <1>; + lowest-supported-version = <3>; + }; + image2 { + image-type-id = "5A7021F5-FEF2-48B4-AABA-832E777418C0"; + image-index = <2>; + lowest-supported-version = <7>; + }; + }; diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c index 5b71a2fcc9..ae631f49f7 100644 --- a/lib/efi_loader/efi_firmware.c +++ b/lib/efi_loader/efi_firmware.c @@ -144,6 +144,51 @@ efi_status_t EFIAPI efi_firmware_set_package_info_unsupported( return EFI_EXIT(EFI_UNSUPPORTED); } +/** + * efi_firmware_get_lsv_from_dtb - get lowest supported version from dtb + * @image_index: Image index + * @image_type_id: Image type id + * @lsv: Pointer to store the lowest supported version + * + * Read the firmware version information from dtb. + */ +static void efi_firmware_get_lsv_from_dtb(u8 image_index, + efi_guid_t *image_type_id, u32 *lsv) +{ + const void *fdt = gd->fdt_blob; + const fdt32_t *val; + const char *guid_str; + int len, offset, index; + int parent; + + *lsv = 0; + + parent = fdt_subnode_offset(fdt, 0, "firmware-version"); + if (parent < 0) + return; + + fdt_for_each_subnode(offset, fdt, parent) { + efi_guid_t guid; + + guid_str = fdt_getprop(fdt, offset, "image-type-id", &len); + if (!guid_str) + continue; + uuid_str_to_bin(guid_str, guid.b, UUID_STR_FORMAT_GUID); + + val = fdt_getprop(fdt, offset, "image-index", &len); + if (!val) + continue; + index = fdt32_to_cpu(*val); + + if (!guidcmp(&guid, image_type_id) && index == image_index) { + val = fdt_getprop(fdt, offset, + "lowest-supported-version", &len); + if (val) + *lsv = fdt32_to_cpu(*val); + } + } +} + /** * efi_firmware_fill_version_info - fill the version information * @image_info: Image information @@ -171,8 +216,11 @@ void efi_firmware_fill_version_info(struct efi_firmware_image_descriptor *image_ else image_info->version = 0; + efi_firmware_get_lsv_from_dtb(fw_array->image_index, + &fw_array->image_type_id, + &image_info->lowest_supported_image_version); + image_info->version_name = NULL; /* not supported */ - image_info->lowest_supported_image_version = 0; image_info->last_attempt_version = 0; image_info->last_attempt_status = LAST_ATTEMPT_STATUS_SUCCESS; } -- cgit v1.2.3 From 000806f76b18262d456d98184592703a1bae016d Mon Sep 17 00:00:00 2001 From: Masahisa Kojima Date: Wed, 7 Jun 2023 14:41:56 +0900 Subject: mkeficapsule: add FMP Payload Header Current mkeficapsule tool does not provide firmware version management. EDK II reference implementation inserts the FMP Payload Header right before the payload. It coutains the fw_version and lowest supported version. This commit adds a new parameters required to generate the FMP Payload Header for mkeficapsule tool. '-v' indicates the firmware version. When mkeficapsule tool is invoked without '-v' option, FMP Payload Header is not inserted, the behavior is same as current implementation. The lowest supported version included in the FMP Payload Header is not used, the value stored in the device tree is used instead. Signed-off-by: Masahisa Kojima Acked-by: Ilias Apalodimas --- doc/mkeficapsule.1 | 10 ++++++++++ tools/eficapsule.h | 30 ++++++++++++++++++++++++++++++ tools/mkeficapsule.c | 37 +++++++++++++++++++++++++++++++++---- 3 files changed, 73 insertions(+), 4 deletions(-) (limited to 'doc') diff --git a/doc/mkeficapsule.1 b/doc/mkeficapsule.1 index 1ca245a10f..c4c2057d5c 100644 --- a/doc/mkeficapsule.1 +++ b/doc/mkeficapsule.1 @@ -61,6 +61,16 @@ Specify an image index .BI "-I\fR,\fB --instance " instance Specify a hardware instance +.PP +FMP Payload Header is inserted right before the payload if +.BR --fw-version +is specified + + +.TP +.BI "-v\fR,\fB --fw-version " firmware-version +Specify a firmware version, 0 if omitted + .PP For generation of firmware accept empty capsule .BR --guid diff --git a/tools/eficapsule.h b/tools/eficapsule.h index 072a4b5598..753fb73313 100644 --- a/tools/eficapsule.h +++ b/tools/eficapsule.h @@ -113,4 +113,34 @@ struct efi_firmware_image_authentication { struct win_certificate_uefi_guid auth_info; } __packed; +/* fmp payload header */ +#define SIGNATURE_16(A, B) ((A) | ((B) << 8)) +#define SIGNATURE_32(A, B, C, D) \ + (SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16)) + +#define FMP_PAYLOAD_HDR_SIGNATURE SIGNATURE_32('M', 'S', 'S', '1') + +/** + * struct fmp_payload_header - EDK2 header for the FMP payload + * + * This structure describes the header which is preprended to the + * FMP payload by the edk2 capsule generation scripts. + * + * @signature: Header signature used to identify the header + * @header_size: Size of the structure + * @fw_version: Firmware versions used + * @lowest_supported_version: Lowest supported version (not used) + */ +struct fmp_payload_header { + uint32_t signature; + uint32_t header_size; + uint32_t fw_version; + uint32_t lowest_supported_version; +}; + +struct fmp_payload_header_params { + bool have_header; + uint32_t fw_version; +}; + #endif /* _EFI_CAPSULE_H */ diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c index b71537beee..52be1f122e 100644 --- a/tools/mkeficapsule.c +++ b/tools/mkeficapsule.c @@ -41,6 +41,7 @@ static struct option options[] = { {"guid", required_argument, NULL, 'g'}, {"index", required_argument, NULL, 'i'}, {"instance", required_argument, NULL, 'I'}, + {"fw-version", required_argument, NULL, 'v'}, {"private-key", required_argument, NULL, 'p'}, {"certificate", required_argument, NULL, 'c'}, {"monotonic-count", required_argument, NULL, 'm'}, @@ -60,6 +61,7 @@ static void print_usage(void) "\t-g, --guid guid for image blob type\n" "\t-i, --index update image index\n" "\t-I, --instance update hardware instance\n" + "\t-v, --fw-version firmware version\n" "\t-p, --private-key private key file\n" "\t-c, --certificate signer's certificate file\n" "\t-m, --monotonic-count monotonic count\n" @@ -402,6 +404,7 @@ static void free_sig_data(struct auth_context *ctx) */ static int create_fwbin(char *path, char *bin, efi_guid_t *guid, unsigned long index, unsigned long instance, + struct fmp_payload_header_params *fmp_ph_params, uint64_t mcount, char *privkey_file, char *cert_file, uint16_t oemflags) { @@ -410,10 +413,11 @@ static int create_fwbin(char *path, char *bin, efi_guid_t *guid, struct efi_firmware_management_capsule_image_header image; struct auth_context auth_context; FILE *f; - uint8_t *data; + uint8_t *data, *new_data, *buf; off_t bin_size; uint64_t offset; int ret; + struct fmp_payload_header payload_header; #ifdef DEBUG fprintf(stderr, "For output: %s\n", path); @@ -423,6 +427,7 @@ static int create_fwbin(char *path, char *bin, efi_guid_t *guid, auth_context.sig_size = 0; f = NULL; data = NULL; + new_data = NULL; ret = -1; /* @@ -431,12 +436,30 @@ static int create_fwbin(char *path, char *bin, efi_guid_t *guid, if (read_bin_file(bin, &data, &bin_size)) goto err; + buf = data; + + /* insert fmp payload header right before the payload */ + if (fmp_ph_params->have_header) { + new_data = malloc(bin_size + sizeof(payload_header)); + if (!new_data) + goto err; + + payload_header.signature = FMP_PAYLOAD_HDR_SIGNATURE; + payload_header.header_size = sizeof(payload_header); + payload_header.fw_version = fmp_ph_params->fw_version; + payload_header.lowest_supported_version = 0; /* not used */ + memcpy(new_data, &payload_header, sizeof(payload_header)); + memcpy(new_data + sizeof(payload_header), data, bin_size); + buf = new_data; + bin_size += sizeof(payload_header); + } + /* first, calculate signature to determine its size */ if (privkey_file && cert_file) { auth_context.key_file = privkey_file; auth_context.cert_file = cert_file; auth_context.auth.monotonic_count = mcount; - auth_context.image_data = data; + auth_context.image_data = buf; auth_context.image_size = bin_size; if (create_auth_data(&auth_context)) { @@ -536,7 +559,7 @@ static int create_fwbin(char *path, char *bin, efi_guid_t *guid, /* * firmware binary */ - if (write_capsule_file(f, data, bin_size, "Firmware binary")) + if (write_capsule_file(f, buf, bin_size, "Firmware binary")) goto err; ret = 0; @@ -545,6 +568,7 @@ err: fclose(f); free_sig_data(&auth_context); free(data); + free(new_data); return ret; } @@ -644,6 +668,7 @@ int main(int argc, char **argv) unsigned long oemflags; char *privkey_file, *cert_file; int c, idx; + struct fmp_payload_header_params fmp_ph_params = { 0 }; guid = NULL; index = 0; @@ -679,6 +704,10 @@ int main(int argc, char **argv) case 'I': instance = strtoul(optarg, NULL, 0); break; + case 'v': + fmp_ph_params.fw_version = strtoul(optarg, NULL, 0); + fmp_ph_params.have_header = true; + break; case 'p': if (privkey_file) { fprintf(stderr, @@ -751,7 +780,7 @@ int main(int argc, char **argv) exit(EXIT_FAILURE); } } else if (create_fwbin(argv[argc - 1], argv[argc - 2], guid, - index, instance, mcount, privkey_file, + index, instance, &fmp_ph_params, mcount, privkey_file, cert_file, (uint16_t)oemflags) < 0) { fprintf(stderr, "Creating firmware capsule failed\n"); exit(EXIT_FAILURE); -- cgit v1.2.3 From 83be41049b35056c3e0062743aa804671321597f Mon Sep 17 00:00:00 2001 From: Masahisa Kojima Date: Wed, 7 Jun 2023 14:41:57 +0900 Subject: doc: uefi: add firmware versioning documentation This commit describes the procedure to add the firmware version into the capsule file. Signed-off-by: Masahisa Kojima --- doc/develop/uefi/uefi.rst | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'doc') diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst index ffe25ca231..30b90a09d5 100644 --- a/doc/develop/uefi/uefi.rst +++ b/doc/develop/uefi/uefi.rst @@ -318,6 +318,33 @@ Run the following command --guid \ +The UEFI specification does not define the firmware versioning mechanism. +EDK II reference implementation inserts the FMP Payload Header right before +the payload. It coutains the fw_version and lowest supported version, +EDK II reference implementation uses these information to implement the +firmware versioning and anti-rollback protection, the firmware version and +lowest supported version is stored into EFI non-volatile variable. + +In U-Boot, the firmware versioning is implemented utilizing +the FMP Payload Header same as EDK II reference implementation, +reads the FMP Payload Header and stores the firmware version into +"FmpStateXXXX" EFI non-volatile variable. XXXX indicates the image index, +since FMP protocol handles multiple image indexes. + +To add the fw_version into the FMP Payload Header, +add --fw-version option in mkeficapsule tool. + +.. code-block:: console + + $ mkeficapsule \ + --index --instance 0 \ + --guid \ + --fw-version 5 \ + + +If the --fw-version option is not set, FMP Payload Header is not inserted +and fw_version is set as 0. + Performing the update ********************* -- cgit v1.2.3 From 027f8a82ea3671a5ffcd5183550cde12bd45da39 Mon Sep 17 00:00:00 2001 From: Masahisa Kojima Date: Wed, 7 Jun 2023 14:41:58 +0900 Subject: doc: uefi: add anti-rollback documentation This commit describe the procedure to configure lowest supported version in the device tree for anti-rollback protection. Signed-off-by: Masahisa Kojima --- doc/develop/uefi/uefi.rst | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'doc') diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst index 30b90a09d5..ffd13cebe9 100644 --- a/doc/develop/uefi/uefi.rst +++ b/doc/develop/uefi/uefi.rst @@ -537,6 +537,45 @@ where signature.dts looks like:: }; }; +Anti-rollback Protection +************************ + +Anti-rollback prevents unintentional installation of outdated firmware. +To enable anti-rollback, you must add the lowest-supported-version property +to dtb and specify --fw-version when creating a capsule file with the +mkeficapsule tool. +When executing capsule update, U-Boot checks if fw_version is greater than +or equal to lowest-supported-version. If fw_version is less than +lowest-supported-version, the update will fail. +For example, if lowest-supported-version is set to 7 and you run capsule +update using a capsule file with --fw-version of 5, the update will fail. +When the --fw-version in the capsule file is updated, lowest-supported-version +in the dtb might be updated accordingly. + +To insert the lowest supported version into a dtb + +.. code-block:: console + + $ dtc -@ -I dts -O dtb -o version.dtbo version.dts + $ fdtoverlay -i orig.dtb -o new.dtb -v version.dtbo + +where version.dts looks like:: + + /dts-v1/; + /plugin/; + &{/} { + firmware-version { + image1 { + image-type-id = "09D7CF52-0720-4710-91D1-08469B7FE9C8"; + image-index = <1>; + lowest-supported-version = <3>; + }; + }; + }; + +The properties of image-type-id and image-index must match the value +defined in the efi_fw_image array as image_type_id and image_index. + Executing the boot manager ~~~~~~~~~~~~~~~~~~~~~~~~~~ -- cgit v1.2.3 From 5f4e26964cba6c7f36b240792e52e67427c195f0 Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Tue, 23 Apr 2019 23:44:57 +0300 Subject: ARM: renesas: Add R8A77970 V3MSK board and CPLD code Add board code for the R8A77970 V3MSK board. Add CPLD sysreset driver to the R-Car V3M SK board. Extracted from a larger patch by Valentine Barshak. Reviewed-by: Marek Vasut Signed-off-by: Valentine Barshak Signed-off-by: Hai Pham Signed-off-by: Tam Nguyen Signed-off-by: Marek Vasut [Marek: Sync configs and board code with V3M Eagle, squash CPLD driver in] --- arch/arm/dts/Makefile | 1 + arch/arm/dts/r8a77970-v3msk-u-boot.dts | 65 ++++++ arch/arm/mach-rmobile/Kconfig.rcar3 | 6 + board/renesas/v3msk/Kconfig | 15 ++ board/renesas/v3msk/MAINTAINERS | 6 + board/renesas/v3msk/Makefile | 15 ++ board/renesas/v3msk/cpld.c | 368 +++++++++++++++++++++++++++++++++ configs/r8a77970_v3msk_defconfig | 87 ++++++++ doc/README.rmobile | 1 + 9 files changed, 564 insertions(+) create mode 100644 arch/arm/dts/r8a77970-v3msk-u-boot.dts create mode 100644 board/renesas/v3msk/Kconfig create mode 100644 board/renesas/v3msk/MAINTAINERS create mode 100644 board/renesas/v3msk/Makefile create mode 100644 board/renesas/v3msk/cpld.c create mode 100644 configs/r8a77970_v3msk_defconfig (limited to 'doc') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 35f50f4b15..dd917ae1b3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1050,6 +1050,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \ r8a77965-ulcb-u-boot.dtb \ r8a77965-salvator-x-u-boot.dtb \ r8a77970-eagle-u-boot.dtb \ + r8a77970-v3msk-u-boot.dtb \ r8a77980-condor-u-boot.dtb \ r8a77990-ebisu-u-boot.dtb \ r8a77995-draak-u-boot.dtb diff --git a/arch/arm/dts/r8a77970-v3msk-u-boot.dts b/arch/arm/dts/r8a77970-v3msk-u-boot.dts new file mode 100644 index 0000000000..6ee06d7c00 --- /dev/null +++ b/arch/arm/dts/r8a77970-v3msk-u-boot.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the V3MSK board + * + * Copyright (C) 2019 Cogent Embedded, Inc. + */ + +#include "r8a77970-v3msk.dts" +#include "r8a77970-u-boot.dtsi" +#include + +/ { + aliases { + spi0 = &rpc; + }; + + cpld { + compatible = "renesas,v3msk-cpld"; + status = "okay"; + gpio-mdc = <&gpio1 21 0>; + gpio-mosi = <&gpio1 22 0>; + gpio-miso = <&gpio1 23 0>; + gpio-enablez = <&gpio1 19 0>; + /* Disable V3MSK Videobox Mini CANFD PHY */ + gpios = <&gpio0 12 0>, <&gpio0 14 0>; + }; +}; + +&avb { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + +}; + +&phy0 { + reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +}; + +&pfc { + avb0_pins: avb { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; + function = "avb0"; + }; + }; +}; + +&rpc { + num-cs = <1>; + status = "okay"; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + + flash0: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "s25fs512s", "spi-flash", "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + reg = <0>; + status = "okay"; + }; +}; diff --git a/arch/arm/mach-rmobile/Kconfig.rcar3 b/arch/arm/mach-rmobile/Kconfig.rcar3 index 5f338219b4..46d274273a 100644 --- a/arch/arm/mach-rmobile/Kconfig.rcar3 +++ b/arch/arm/mach-rmobile/Kconfig.rcar3 @@ -111,6 +111,11 @@ config TARGET_EAGLE help Support for Renesas R-Car Gen3 Eagle platform +config TARGET_V3MSK + bool "V3MSK board" + help + Support for Renesas R-Car Gen3 V3MSK platform + config TARGET_EBISU bool "Ebisu board" imply R8A77990 @@ -166,6 +171,7 @@ source "board/renesas/eagle/Kconfig" source "board/renesas/ebisu/Kconfig" source "board/renesas/salvator-x/Kconfig" source "board/renesas/ulcb/Kconfig" +source "board/renesas/v3msk/Kconfig" source "board/beacon/beacon-rzg2m/Kconfig" source "board/hoperun/hihope-rzg2/Kconfig" source "board/silinux/ek874/Kconfig" diff --git a/board/renesas/v3msk/Kconfig b/board/renesas/v3msk/Kconfig new file mode 100644 index 0000000000..fe037fd98f --- /dev/null +++ b/board/renesas/v3msk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_V3MSK + +config SYS_SOC + default "rmobile" + +config SYS_BOARD + default "v3msk" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "rcar-gen3-common" + +endif diff --git a/board/renesas/v3msk/MAINTAINERS b/board/renesas/v3msk/MAINTAINERS new file mode 100644 index 0000000000..12822a4571 --- /dev/null +++ b/board/renesas/v3msk/MAINTAINERS @@ -0,0 +1,6 @@ +V3MSK BOARD +M: Cogent Embedded, Inc. +S: Maintained +F: board/renesas/v3msk/ +F: include/configs/v3msk.h +F: configs/r8a77970_v3msk_defconfig diff --git a/board/renesas/v3msk/Makefile b/board/renesas/v3msk/Makefile new file mode 100644 index 0000000000..ec493e572f --- /dev/null +++ b/board/renesas/v3msk/Makefile @@ -0,0 +1,15 @@ +# +# board/renesas/v3msk/Makefile +# +# Copyright (C) 2019 Renesas Electronics Corporation +# Copyright (C) 2019 Cogent Embedded, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y := ../rcar-common/gen3-spl.o +else +obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o +obj-$(CONFIG_SYSRESET) += cpld.o +endif diff --git a/board/renesas/v3msk/cpld.c b/board/renesas/v3msk/cpld.c new file mode 100644 index 0000000000..aed616ac85 --- /dev/null +++ b/board/renesas/v3msk/cpld.c @@ -0,0 +1,368 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * V3MSK board CPLD access support + * + * Copyright (C) 2019 Renesas Electronics Corporation + * Copyright (C) 2019 Cogent Embedded, Inc. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CPLD_ADDR_PRODUCT_L 0x000 /* R */ +#define CPLD_ADDR_PRODUCT_H 0x001 /* R */ +#define CPLD_ADDR_CPLD_VERSION_D 0x002 /* R */ +#define CPLD_ADDR_CPLD_VERSION_Y 0x003 /* R */ +#define CPLD_ADDR_MODE_SET_L 0x004 /* R/W */ +#define CPLD_ADDR_MODE_SET_H 0x005 /* R/W */ +#define CPLD_ADDR_MODE_APPLIED_L 0x006 /* R */ +#define CPLD_ADDR_MODE_APPLIED_H 0x007 /* R */ +#define CPLD_ADDR_DIPSW 0x008 /* R */ +#define CPLD_ADDR_RESET 0x00A /* R/W */ +#define CPLD_ADDR_POWER_CFG 0x00B /* R/W */ +#define CPLD_ADDR_PERI_CFG1 0x00C /* R/W */ +#define CPLD_ADDR_PERI_CFG2 0x00D /* R/W */ +#define CPLD_ADDR_LEDS 0x00E /* R/W */ +#define CPLD_ADDR_PCB_VERSION 0x300 /* R */ +#define CPLD_ADDR_SOC_VERSION 0x301 /* R */ +#define CPLD_ADDR_PCB_SN_L 0x302 /* R */ +#define CPLD_ADDR_PCB_SN_H 0x303 /* R */ + +#define MDIO_DELAY 10 /* microseconds */ + +#define CPLD_MAX_GPIOS 2 + +struct renesas_v3msk_sysreset_priv { + struct gpio_desc miso; + struct gpio_desc mosi; + struct gpio_desc mdc; + struct gpio_desc enablez; + /* + * V3MSK Videobox Mini board has CANFD PHY connected + * we must shutdown this chip to use bb pins + */ + struct gpio_desc gpios[CPLD_MAX_GPIOS]; +}; + +static void mdio_bb_active_mdio(struct renesas_v3msk_sysreset_priv *priv) +{ + dm_gpio_set_dir_flags(&priv->mosi, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); +} + +static void mdio_bb_tristate_mdio(struct renesas_v3msk_sysreset_priv *priv) +{ + dm_gpio_set_dir_flags(&priv->mosi, GPIOD_IS_IN); +} + +static void mdio_bb_set_mdio(struct renesas_v3msk_sysreset_priv *priv, int val) +{ + dm_gpio_set_value(&priv->mosi, val); +} + +static int mdio_bb_get_mdio(struct renesas_v3msk_sysreset_priv *priv) +{ + return dm_gpio_get_value(&priv->miso); +} + +static void mdio_bb_set_mdc(struct renesas_v3msk_sysreset_priv *priv, int val) +{ + dm_gpio_set_value(&priv->mdc, val); +} + +static void mdio_bb_delay(void) +{ + udelay(MDIO_DELAY); +} + +/* Send the preamble, address, and register (common to read and write) */ +static void mdio_bb_pre(struct renesas_v3msk_sysreset_priv *priv, + u8 op, u8 addr, u8 reg) +{ + int i; + + /* 32-bit preamble */ + mdio_bb_active_mdio(priv); + mdio_bb_set_mdio(priv, 1); + for (i = 0; i < 32; i++) { + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + } + /* send the ST (2-bits of '01') */ + mdio_bb_set_mdio(priv, 0); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + mdio_bb_set_mdio(priv, 1); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + /* send the OP (2-bits of Opcode: '10'-read, '01'-write) */ + mdio_bb_set_mdio(priv, op >> 1); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + mdio_bb_set_mdio(priv, op & 1); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + /* send the PA5 (5-bits of PHY address) */ + for (i = 0; i < 5; i++) { + mdio_bb_set_mdio(priv, addr & 0x10); /* MSB first */ + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + addr <<= 1; + } + /* send the RA5 (5-bits of register address) */ + for (i = 0; i < 5; i++) { + mdio_bb_set_mdio(priv, reg & 0x10); /* MSB first */ + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + reg <<= 1; + } +} + +static int mdio_bb_read(struct renesas_v3msk_sysreset_priv *priv, + u8 addr, u8 reg) +{ + int i; + u16 data = 0; + + mdio_bb_pre(priv, 2, addr, reg); + /* tri-state MDIO */ + mdio_bb_tristate_mdio(priv); + /* read TA (2-bits of turn-around, last bit must be '0') */ + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + /* check the turnaround bit: the PHY should drive line to zero */ + if (mdio_bb_get_mdio(priv) != 0) { + printf("PHY didn't drive TA low\n"); + for (i = 0; i < 32; i++) { + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + } + /* There is no PHY, set value to 0xFFFF */ + return 0xFFFF; + } + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + /* read 16-bits of data */ + for (i = 0; i < 16; i++) { + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + data <<= 1; + data |= mdio_bb_get_mdio(priv); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + } + + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + + debug("cpld_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, data); + + return data; +} + +static void mdio_bb_write(struct renesas_v3msk_sysreset_priv *priv, + u8 addr, u8 reg, u16 val) +{ + int i; + + mdio_bb_pre(priv, 1, addr, reg); + /* send the TA (2-bits of turn-around '10') */ + mdio_bb_set_mdio(priv, 1); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + mdio_bb_set_mdio(priv, 0); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + /* write 16-bits of data */ + for (i = 0; i < 16; i++) { + mdio_bb_set_mdio(priv, val & 0x8000); /* MSB first */ + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + val <<= 1; + } + /* tri-state MDIO */ + mdio_bb_tristate_mdio(priv); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); +} + +static u16 cpld_read(struct udevice *dev, u16 addr) +{ + struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev); + + /* random flash reads require 2 reads: first read is unreliable */ + if (addr >= CPLD_ADDR_PCB_VERSION) + mdio_bb_read(priv, addr >> 5, addr & 0x1f); + + return mdio_bb_read(priv, addr >> 5, addr & 0x1f); +} + +static void cpld_write(struct udevice *dev, u16 addr, u16 data) +{ + struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev); + + mdio_bb_write(priv, addr >> 5, addr & 0x1f, data); +} + +static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *dev; + u16 addr, val; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_SYSRESET, + DM_DRIVER_GET(sysreset_renesas_v3msk), + &dev); + if (ret) + return ret; + + if (argc == 2 && strcmp(argv[1], "info") == 0) { + printf("Product: 0x%08x\n", + (cpld_read(dev, CPLD_ADDR_PRODUCT_H) << 16) | + cpld_read(dev, CPLD_ADDR_PRODUCT_L)); + printf("CPLD version: 0x%08x\n", + (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y) << 16) | + cpld_read(dev, CPLD_ADDR_CPLD_VERSION_D)); + printf("Mode setting (MD0..26): 0x%08x\n", + (cpld_read(dev, CPLD_ADDR_MODE_APPLIED_H) << 16) | + cpld_read(dev, CPLD_ADDR_MODE_APPLIED_L)); + printf("DIPSW (SW4, SW5): 0x%02x, 0x%x\n", + (cpld_read(dev, CPLD_ADDR_DIPSW) & 0xff) ^ 0xff, + (cpld_read(dev, CPLD_ADDR_DIPSW) >> 8) ^ 0xf); + printf("Power config: 0x%08x\n", + cpld_read(dev, CPLD_ADDR_POWER_CFG)); + printf("Periferals config: 0x%08x\n", + (cpld_read(dev, CPLD_ADDR_PERI_CFG2) << 16) | + cpld_read(dev, CPLD_ADDR_PERI_CFG1)); + printf("PCB version: %d.%d\n", + cpld_read(dev, CPLD_ADDR_PCB_VERSION) >> 8, + cpld_read(dev, CPLD_ADDR_PCB_VERSION) & 0xff); + printf("SOC version: %d.%d\n", + cpld_read(dev, CPLD_ADDR_SOC_VERSION) >> 8, + cpld_read(dev, CPLD_ADDR_SOC_VERSION) & 0xff); + printf("PCB S/N: %d\n", + (cpld_read(dev, CPLD_ADDR_PCB_SN_H) << 16) | + cpld_read(dev, CPLD_ADDR_PCB_SN_L)); + return 0; + } + + if (argc < 3) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[2], NULL, 16); + if (!(addr >= CPLD_ADDR_PRODUCT_L && addr <= CPLD_ADDR_LEDS)) { + printf("cpld invalid addr\n"); + return CMD_RET_USAGE; + } + + if (argc == 3 && strcmp(argv[1], "read") == 0) { + printf("0x%x\n", cpld_read(dev, addr)); + } else if (argc == 4 && strcmp(argv[1], "write") == 0) { + val = simple_strtoul(argv[3], NULL, 16); + cpld_write(dev, addr, val); + } + + return 0; +} + +U_BOOT_CMD(cpld, 4, 1, do_cpld, + "CPLD access", + "info\n" + "cpld read addr\n" + "cpld write addr val\n" +); + +static int renesas_v3msk_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + cpld_write(dev, CPLD_ADDR_RESET, 1); + + return -EINPROGRESS; +} + +static int renesas_v3msk_sysreset_probe(struct udevice *dev) +{ + struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev); + + if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso, + GPIOD_IS_IN)) + return -EINVAL; + + if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi, + GPIOD_IS_OUT)) + return -EINVAL; + + if (gpio_request_by_name(dev, "gpio-mdc", 0, &priv->mdc, + GPIOD_IS_OUT)) + return -EINVAL; + + if (gpio_request_by_name(dev, "gpio-enablez", 0, &priv->enablez, + GPIOD_IS_OUT)) + return -EINVAL; + + /* V3MSK Videobox Mini board has CANFD PHY connected + * we must shutdown this chip to use bb pins + */ + gpio_request_list_by_name(dev, "gpios", priv->gpios, CPLD_MAX_GPIOS, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + return 0; +} + +static struct sysreset_ops renesas_v3msk_sysreset = { + .request = renesas_v3msk_sysreset_request, +}; + +static const struct udevice_id renesas_v3msk_sysreset_ids[] = { + { .compatible = "renesas,v3msk-cpld" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(sysreset_renesas_v3msk) = { + .name = "renesas_v3msk_sysreset", + .id = UCLASS_SYSRESET, + .ops = &renesas_v3msk_sysreset, + .probe = renesas_v3msk_sysreset_probe, + .of_match = renesas_v3msk_sysreset_ids, + .priv_auto = sizeof(struct renesas_v3msk_sysreset_priv), +}; diff --git a/configs/r8a77970_v3msk_defconfig b/configs/r8a77970_v3msk_defconfig new file mode 100644 index 0000000000..74a140a8a2 --- /dev/null +++ b/configs/r8a77970_v3msk_defconfig @@ -0,0 +1,87 @@ +CONFIG_ARM=y +CONFIG_COUNTER_FREQUENCY=16666666 +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_RMOBILE=y +CONFIG_TEXT_BASE=0x50000000 +CONFIG_SYS_MALLOC_LEN=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="r8a77970-v3msk-u-boot" +CONFIG_SPL_TEXT_BASE=0xe6318000 +CONFIG_RCAR_GEN3=y +CONFIG_R8A77970=y +CONFIG_TARGET_V3MSK=y +CONFIG_SPL_STACK=0xe6304000 +CONFIG_SYS_LOAD_ADDR=0x58000000 +CONFIG_LTO=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 +CONFIG_FIT=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_USE_BOOTARGS=y +CONFIG_DEFAULT_FDT_FILE="r8a77970-v3msk.dtb" +CONFIG_SYS_MALLOC_BOOTPARAMS=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe631f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2068 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DFU=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_OF_DTB_PROPS_REMOVE=y +CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_VERSION_VARIABLE=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_CLK_RENESAS=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_I2C=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_RENESAS_RAVB=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SCIF_CONSOLE=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_RENESAS_RPC_SPI=y +CONFIG_SYSRESET=y diff --git a/doc/README.rmobile b/doc/README.rmobile index ea170a25a6..524d839558 100644 --- a/doc/README.rmobile +++ b/doc/README.rmobile @@ -35,6 +35,7 @@ Currently the following boards are supported: | R8A77965 M3-N | Renesas Electronics ULCB | r8a77965_ulcb |---------------+----------------------------------------+------------------- | R8A77970 V3M | Renesas Electronics Eagle | r8a77970_eagle_defconfig +| R8A77970 V3M | Renesas Electronics V3MSK | r8a77970_v3msk_defconfig |---------------+----------------------------------------+------------------- | R8A77995 D3 | Renesas Electronics Draak | r8a77995_draak_defconfig '===============+========================================+=================== -- cgit v1.2.3 From 56b481c42879ae171c6272f92ff5db7c767929af Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Mon, 6 Mar 2023 17:18:14 -0600 Subject: dt/bindings: fwu-mdata-mtd: drop changes outside FWU Any requirement of FWU should not require changes to bindings of other subsystems. For example, for mtd-backed storage we can do without requiring 'fixed-partitions' children to also carry 'uuid', a property which is non-standard and not in the bindings. There exists no code yet, so we can change the fwu-mtd bindings to contain all properties within the fwu-mdata node. Signed-off-by: Jassi Brar Acked-by: Ilias Apalodimas Tested-by: Sughosh Ganu --- .../firmware/fwu-mdata-mtd.yaml | 105 ++++++++++++++++++--- 1 file changed, 91 insertions(+), 14 deletions(-) (limited to 'doc') diff --git a/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml b/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml index 4f5404f999..6a22aeea30 100644 --- a/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml +++ b/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml @@ -1,13 +1,13 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/firmware/u-boot,fwu-mdata-sf.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# +$id: http://devicetree.org/schemas/firmware/u-boot,fwu-mdata-mtd.yaml# +$schema: http://devicetree.org/meta-schemas/base.yaml# title: FWU metadata on MTD device without GPT maintainers: - - Masami Hiramatsu + - Jassi Brar properties: compatible: @@ -15,24 +15,101 @@ properties: - const: u-boot,fwu-mdata-mtd fwu-mdata-store: - maxItems: 1 - description: Phandle of the MTD device which contains the FWU medatata. + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle of the MTD device which contains the FWU MetaData and Banks. - mdata-offsets: + mdata-parts: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array minItems: 2 - description: Offsets of the primary and secondary FWU metadata in the NOR flash. + maxItems: 2 + description: labels of the primary and secondary FWU metadata partitions in the 'fixed-partitions' subnode of the 'jedec,spi-nor' flash device node. + + patternProperties: + "fwu-bank[0-9]": + type: object + description: List of FWU mtd-backed banks. Typically two banks. + + properties: + id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Index of the bank. + + label: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + minItems: 1 + maxItems: 1 + description: label of the partition, in the 'fixed-partitions' subnode of the 'jedec,spi-nor' flash device node, that holds this bank. + + patternProperties: + "fwu-image[0-9]": + type: object + description: List of images in the FWU mtd-backed bank. + + properties: + id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Index of the bank. + + offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Offset, from start of the bank, where the image is located. + + size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Size reserved for the image. + + uuid: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + minItems: 1 + maxItems: 1 + description: UUID of the image. + + required: + - id + - offset + - size + - uuid + additionalProperties: false + + required: + - id + - label + - fwu-images + additionalProperties: false required: - compatible - fwu-mdata-store - - mdata-offsets - + - mdata-parts + - fwu-banks additionalProperties: false examples: - | - fwu-mdata { - compatible = "u-boot,fwu-mdata-mtd"; - fwu-mdata-store = <&spi-flash>; - mdata-offsets = <0x500000 0x530000>; - }; + fwu-mdata { + compatible = "u-boot,fwu-mdata-mtd"; + fwu-mdata-store = <&flash0>; + mdata-parts = "MDATA-Pri", "MDATA-Sec"; + + fwu-bank0 { + id = <0>; + label = "FIP-Bank0"; + fwu-image0 { + id = <0>; + offset = <0x0>; + size = <0x400000>; + uuid = "5a66a702-99fd-4fef-a392-c26e261a2828"; + }; + }; + fwu-bank1 { + id = <1>; + label = "FIP-Bank1"; + fwu-image0 { + id = <0>; + offset = <0x0>; + size = <0x400000>; + uuid = "a8f868a1-6e5c-4757-878d-ce63375ef2c0"; + }; + }; + }; +... -- cgit v1.2.3 From fdd56bfd3ade5a87a5279b07a164e8aecbd0cf2f Mon Sep 17 00:00:00 2001 From: Masami Hiramatsu Date: Wed, 31 May 2023 00:29:24 -0500 Subject: tools: Add mkfwumdata tool for FWU metadata image Add 'mkfwumdata' tool to generate FWU metadata image for the meta-data partition to be used in A/B Update imeplementation. Signed-off-by: Sughosh Ganu Signed-off-by: Jassi Brar Signed-off-by: Masami Hiramatsu --- doc/mkfwumdata.1 | 89 ++++++++++++++ tools/Kconfig | 9 ++ tools/Makefile | 4 + tools/mkfwumdata.c | 334 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 436 insertions(+) create mode 100644 doc/mkfwumdata.1 create mode 100644 tools/mkfwumdata.c (limited to 'doc') diff --git a/doc/mkfwumdata.1 b/doc/mkfwumdata.1 new file mode 100644 index 0000000000..7dd718b26e --- /dev/null +++ b/doc/mkfwumdata.1 @@ -0,0 +1,89 @@ +.\" SPDX-License-Identifier: GPL-2.0-or-later +.\" Copyright (C) 2023 Jassi Brar +.TH MKFWUMDATA 1 2023-04-10 U-Boot +.SH NAME +mkfwumdata \- create FWU metadata image +. +.SH SYNOPSIS +.SY mkfwumdata +.OP \-a activeidx +.OP \-p previousidx +.OP \-g +.BI \-i\~ imagecount +.BI \-b\~ bankcount +.I UUIDs +.I outputimage +.YS +.SY mkfwumdata +.B \-h +.YS +. +.SH DESCRIPTION +.B mkfwumdata +creates metadata info to be used with FWU. +. +.SH OPTIONS +.TP +.B \-h +Print usage information and exit. +. +.TP +.B \-a +Set +.IR activeidx +as the currently active Bank. Default is 0. +. +.TP +.B \-p +Set +.IR previousidx +as the previous active Bank. Default is +.IR activeidx "-1" +or +.IR bankcount "-1," +whichever is non-negative. +. +.TP +.B \-g +Convert the +.IR UUIDs +as GUIDs before use. +. +.TP +.B \-i +Specify there are +.IR imagecount +images in each bank. +. +.TP +.B \-b +Specify there are a total of +.IR bankcount +banks. +. +.TP +.IR UUIDs +Comma-separated list of UUIDs required to create the metadata :- +location_uuid,image_type_uuid, +. +.TP +.IR outputimage +Specify the name of the metadata image file to be created. +. +.SH BUGS +Please report bugs to the +.UR https://\:source\:.denx\:.de/\:u-boot/\:u-boot/\:issues +U-Boot bug tracker +.UE . +.SH EXAMPLES +Create a metadata image with 2 banks and 1 image/bank, BankAct=0, BankPrev=1: +.PP +.EX +.in +4 +$ \c +.B mkfwumdata \-a 0 \-p 1 \-b 2 \-i 1 \\\\\& +.in +6 +.B 17e86d77-41f9-4fd7-87ec-a55df9842de5,\\\\\& +.B 10c36d7d-ca52-b843-b7b9-f9d6c501d108,\\\\\& +.B 5a66a702-99fd-4fef-a392-c26e261a2828,a8f868a1-6e5c-4757-878d-ce63375ef2c0 \\\\\& +.B fwu-mdata.img diff --git a/tools/Kconfig b/tools/Kconfig index 539708f277..6e23f44d55 100644 --- a/tools/Kconfig +++ b/tools/Kconfig @@ -157,4 +157,13 @@ config LUT_SEQUENCE help Look Up Table Sequence +config TOOLS_MKFWUMDATA + bool "Build mkfwumdata command" + default y if FWU_MULTI_BANK_UPDATE + help + This command allows users to create a raw image of the FWU + metadata for initial installation of the FWU multi bank + update on the board. The installation method depends on + the platform. + endmenu diff --git a/tools/Makefile b/tools/Makefile index 38699b069d..1e3fce0b1c 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -250,6 +250,10 @@ HOSTLDLIBS_mkeficapsule += \ $(shell pkg-config --libs uuid 2> /dev/null || echo "-luuid") hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule +mkfwumdata-objs := mkfwumdata.o lib/crc32.o +HOSTLDLIBS_mkfwumdata += -luuid +hostprogs-$(CONFIG_TOOLS_MKFWUMDATA) += mkfwumdata + # We build some files with extra pedantic flags to try to minimize things # that won't build on some weird host compiler -- though there are lots of # exceptions for files that aren't complaint. diff --git a/tools/mkfwumdata.c b/tools/mkfwumdata.c new file mode 100644 index 0000000000..9732a8ddc5 --- /dev/null +++ b/tools/mkfwumdata.c @@ -0,0 +1,334 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* This will dynamically allocate the fwu_mdata */ +#define CONFIG_FWU_NUM_BANKS 0 +#define CONFIG_FWU_NUM_IMAGES_PER_BANK 0 + +/* Since we can not include fwu.h, redefine version here. */ +#define FWU_MDATA_VERSION 1 + +typedef uint8_t u8; +typedef int16_t s16; +typedef uint16_t u16; +typedef uint32_t u32; +typedef uint64_t u64; + +#include + +/* TODO: Endianness conversion may be required for some arch. */ + +static const char *opts_short = "b:i:a:p:gh"; + +static struct option options[] = { + {"banks", required_argument, NULL, 'b'}, + {"images", required_argument, NULL, 'i'}, + {"guid", required_argument, NULL, 'g'}, + {"active-bank", required_argument, NULL, 'a'}, + {"previous-bank", required_argument, NULL, 'p'}, + {"help", no_argument, NULL, 'h'}, + {NULL, 0, NULL, 0}, +}; + +static void print_usage(void) +{ + fprintf(stderr, "Usage: mkfwumdata [options] \n"); + fprintf(stderr, "Options:\n" + "\t-i, --images Number of images (mandatory)\n" + "\t-b, --banks Number of banks (mandatory)\n" + "\t-a, --active-bank Active bank (default=0)\n" + "\t-p, --previous-bank Previous active bank (default=active_bank - 1)\n" + "\t-g, --guid Use GUID instead of UUID\n" + "\t-h, --help print a help message\n" + ); + fprintf(stderr, " UUIDs list syntax:\n" + "\t ,,\n" + "\t images uuid list syntax:\n" + "\t img_uuid_00,img_uuid_01...img_uuid_0b,\n" + "\t img_uuid_10,img_uuid_11...img_uuid_1b,\n" + "\t ...,\n" + "\t img_uuid_i0,img_uuid_i1...img_uuid_ib,\n" + "\t where 'b' and 'i' are number of banks and number\n" + "\t of images in a bank respectively.\n" + ); +} + +struct fwu_mdata_object { + size_t images; + size_t banks; + size_t size; + struct fwu_mdata *mdata; +}; + +static int previous_bank, active_bank; +static bool __use_guid; + +static struct fwu_mdata_object *fwu_alloc_mdata(size_t images, size_t banks) +{ + struct fwu_mdata_object *mobj; + + mobj = calloc(1, sizeof(*mobj)); + if (!mobj) + return NULL; + + mobj->size = sizeof(struct fwu_mdata) + + (sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * banks) * images; + mobj->images = images; + mobj->banks = banks; + + mobj->mdata = calloc(1, mobj->size); + if (!mobj->mdata) { + free(mobj); + return NULL; + } + + return mobj; +} + +static struct fwu_image_entry * +fwu_get_image(struct fwu_mdata_object *mobj, size_t idx) +{ + size_t offset; + + offset = sizeof(struct fwu_mdata) + + (sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * mobj->banks) * idx; + + return (struct fwu_image_entry *)((char *)mobj->mdata + offset); +} + +static struct fwu_image_bank_info * +fwu_get_bank(struct fwu_mdata_object *mobj, size_t img_idx, size_t bnk_idx) +{ + size_t offset; + + offset = sizeof(struct fwu_mdata) + + (sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * mobj->banks) * img_idx + + sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * bnk_idx; + + return (struct fwu_image_bank_info *)((char *)mobj->mdata + offset); +} + +/** + * convert_uuid_to_guid() - convert UUID to GUID + * @buf: UUID binary + * + * UUID and GUID have the same data structure, but their binary + * formats are different due to the endianness. See lib/uuid.c. + * Since uuid_parse() can handle only UUID, this function must + * be called to get correct data for GUID when parsing a string. + * + * The correct data will be returned in @buf. + */ +static void convert_uuid_to_guid(unsigned char *buf) +{ + unsigned char c; + + c = buf[0]; + buf[0] = buf[3]; + buf[3] = c; + c = buf[1]; + buf[1] = buf[2]; + buf[2] = c; + + c = buf[4]; + buf[4] = buf[5]; + buf[5] = c; + + c = buf[6]; + buf[6] = buf[7]; + buf[7] = c; +} + +static int uuid_guid_parse(char *uuidstr, unsigned char *uuid) +{ + int ret; + + ret = uuid_parse(uuidstr, uuid); + if (ret < 0) + return ret; + + if (__use_guid) + convert_uuid_to_guid(uuid); + + return ret; +} + +static int +fwu_parse_fill_image_uuid(struct fwu_mdata_object *mobj, + size_t idx, char *uuids) +{ + struct fwu_image_entry *image = fwu_get_image(mobj, idx); + struct fwu_image_bank_info *bank; + char *p = uuids, *uuid; + int i; + + if (!image) + return -ENOENT; + + /* Image location UUID */ + uuid = strsep(&p, ","); + if (!uuid) + return -EINVAL; + + if (strcmp(uuid, "0") && + uuid_guid_parse(uuid, (unsigned char *)&image->location_uuid) < 0) + return -EINVAL; + + /* Image type UUID */ + uuid = strsep(&p, ","); + if (!uuid) + return -EINVAL; + + if (uuid_guid_parse(uuid, (unsigned char *)&image->image_type_uuid) < 0) + return -EINVAL; + + /* Fill bank image-UUID */ + for (i = 0; i < mobj->banks; i++) { + bank = fwu_get_bank(mobj, idx, i); + if (!bank) + return -ENOENT; + bank->accepted = 1; + uuid = strsep(&p, ","); + if (!uuid) + return -EINVAL; + + if (strcmp(uuid, "0") && + uuid_guid_parse(uuid, (unsigned char *)&bank->image_uuid) < 0) + return -EINVAL; + } + return 0; +} + +/* Caller must ensure that @uuids[] has @mobj->images entries. */ +static int fwu_parse_fill_uuids(struct fwu_mdata_object *mobj, char *uuids[]) +{ + struct fwu_mdata *mdata = mobj->mdata; + int i, ret; + + mdata->version = FWU_MDATA_VERSION; + mdata->active_index = active_bank; + mdata->previous_active_index = previous_bank; + + for (i = 0; i < mobj->images; i++) { + ret = fwu_parse_fill_image_uuid(mobj, i, uuids[i]); + if (ret < 0) + return ret; + } + + mdata->crc32 = crc32(0, (const unsigned char *)&mdata->version, + mobj->size - sizeof(uint32_t)); + + return 0; +} + +static int +fwu_make_mdata(size_t images, size_t banks, char *uuids[], char *output) +{ + struct fwu_mdata_object *mobj; + FILE *file; + int ret; + + mobj = fwu_alloc_mdata(images, banks); + if (!mobj) + return -ENOMEM; + + ret = fwu_parse_fill_uuids(mobj, uuids); + if (ret < 0) + goto done_make; + + file = fopen(output, "w"); + if (!file) { + ret = -errno; + goto done_make; + } + + ret = fwrite(mobj->mdata, mobj->size, 1, file); + if (ret != mobj->size) + ret = -errno; + else + ret = 0; + + fclose(file); + +done_make: + free(mobj->mdata); + free(mobj); + + return ret; +} + +int main(int argc, char *argv[]) +{ + unsigned long banks = 0, images = 0; + int c, ret; + + /* Explicitly initialize defaults */ + active_bank = 0; + __use_guid = false; + previous_bank = INT_MAX; + + do { + c = getopt_long(argc, argv, opts_short, options, NULL); + switch (c) { + case 'h': + print_usage(); + return 0; + case 'b': + banks = strtoul(optarg, NULL, 0); + break; + case 'i': + images = strtoul(optarg, NULL, 0); + break; + case 'g': + __use_guid = true; + break; + case 'p': + previous_bank = strtoul(optarg, NULL, 0); + break; + case 'a': + active_bank = strtoul(optarg, NULL, 0); + break; + } + } while (c != -1); + + if (!banks || !images) { + fprintf(stderr, "Error: The number of banks and images must not be 0.\n"); + return -EINVAL; + } + + /* This command takes UUIDs * images and output file. */ + if (optind + images + 1 != argc) { + fprintf(stderr, "Error: UUID list or output file is not specified or too much.\n"); + print_usage(); + return -ERANGE; + } + + if (previous_bank == INT_MAX) { + /* set to the earlier bank in round-robin scheme */ + previous_bank = active_bank > 0 ? active_bank - 1 : banks - 1; + } + + ret = fwu_make_mdata(images, banks, argv + optind, argv[argc - 1]); + if (ret < 0) + fprintf(stderr, "Error: Failed to parse and write image: %s\n", + strerror(-ret)); + + return ret; +} -- cgit v1.2.3 From 6b403ca4dcf4c68e2792c4e8b28e03b3cfe5db45 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Wed, 31 May 2023 00:29:56 -0500 Subject: fwu: DeveloperBox: add support for FWU Add code to support FWU_MULTI_BANK_UPDATE. The platform does not have gpt-partition storage for Banks and MetaData, rather it used SPI-NOR backed mtd regions for the purpose. Signed-off-by: Jassi Brar --- board/socionext/developerbox/Makefile | 1 + board/socionext/developerbox/developerbox.c | 8 ++ board/socionext/developerbox/fwu_plat.c | 37 +++++++ configs/synquacer_developerbox_defconfig | 8 ++ doc/board/socionext/developerbox.rst | 154 ++++++++++++++++++++++++++-- include/configs/synquacer.h | 10 ++ 6 files changed, 212 insertions(+), 6 deletions(-) create mode 100644 board/socionext/developerbox/fwu_plat.c (limited to 'doc') diff --git a/board/socionext/developerbox/Makefile b/board/socionext/developerbox/Makefile index 4a46de995a..1acd067a7e 100644 --- a/board/socionext/developerbox/Makefile +++ b/board/socionext/developerbox/Makefile @@ -7,3 +7,4 @@ # obj-y := developerbox.o +obj-$(CONFIG_FWU_MDATA_MTD) += fwu_plat.o diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c index d92e1d0962..204e5a41a5 100644 --- a/board/socionext/developerbox/developerbox.c +++ b/board/socionext/developerbox/developerbox.c @@ -20,6 +20,13 @@ #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) struct efi_fw_image fw_images[] = { +#if CONFIG_IS_ENABLED(FWU_MULTI_BANK_UPDATE) + { + .image_type_id = DEVELOPERBOX_FIP_IMAGE_GUID, + .fw_name = u"DEVELOPERBOX-FIP", + .image_index = 1, + }, +#else { .image_type_id = DEVELOPERBOX_UBOOT_IMAGE_GUID, .fw_name = u"DEVELOPERBOX-UBOOT", @@ -35,6 +42,7 @@ struct efi_fw_image fw_images[] = { .fw_name = u"DEVELOPERBOX-OPTEE", .image_index = 3, }, +#endif }; struct efi_capsule_update_info update_info = { diff --git a/board/socionext/developerbox/fwu_plat.c b/board/socionext/developerbox/fwu_plat.c new file mode 100644 index 0000000000..e724e702bd --- /dev/null +++ b/board/socionext/developerbox/fwu_plat.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include + +#define DFU_ALT_BUF_LEN 256 + +/* Generate dfu_alt_info from partitions */ +void set_dfu_alt_info(char *interface, char *devstr) +{ + ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); + struct mtd_info *mtd; + int ret; + + memset(buf, 0, sizeof(buf)); + + mtd_probe_devices(); + + mtd = get_mtd_device_nm("nor1"); + if (IS_ERR_OR_NULL(mtd)) + return; + + ret = fwu_gen_alt_info_from_mtd(buf, DFU_ALT_BUF_LEN, mtd); + if (ret < 0) { + log_err("Error: Failed to generate dfu_alt_info. (%d)\n", ret); + return; + } + log_debug("Make dfu_alt_info: '%s'\n", buf); + + env_set("dfu_alt_info", buf); +} diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index 0c37897c9a..8e7236b572 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -97,3 +97,11 @@ CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_IGNORE_OSINDICATIONS=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y +CONFIG_FWU_MULTI_BANK_UPDATE=y +CONFIG_FWU_MDATA=y +CONFIG_FWU_MDATA_MTD=y +CONFIG_FWU_NUM_BANKS=2 +CONFIG_FWU_NUM_IMAGES_PER_BANK=1 +CONFIG_CMD_FWU_METADATA=y +CONFIG_TOOLS_MKFWUMDATA=y diff --git a/doc/board/socionext/developerbox.rst b/doc/board/socionext/developerbox.rst index 2d943c23be..aa7080e26c 100644 --- a/doc/board/socionext/developerbox.rst +++ b/doc/board/socionext/developerbox.rst @@ -57,14 +57,20 @@ Installation You can install the SNI_NOR_UBOOT.fd via NOR flash writer. -Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine or other mezzanine which can connect to LS-UART0 port. -Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the board on again. The flash writer program will be started automatically; don’t forget to turn the DSW2-7 off again after flashing. +Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine +or other mezzanine which can connect to the LS-UART0 port. +Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the +board on again. The flash writer program will be started automatically; +don't forget to turn the DSW2-7 off again after flashing. -*!!CAUTION!! If you failed to write the U-Boot image on wrong address, the board can be bricked. See below page if you need to recover the bricked board. See the following page for more detail* +*!!CAUTION!! If you write the U-Boot image on wrong address, the board can +be bricked. See below page if you need to recover the bricked board. See +the following page for more details* https://www.96boards.org/documentation/enterprise/developerbox/installation/board-recovery.md.html -When the serial flasher is running correctly is will show the following boot messages shown via LS-UART0:: +When the serial flasher is running correctly it will show the following boot +messages printed to the LS-UART0 console:: /*------------------------------------------*/ @@ -81,7 +87,143 @@ Once the flasher tool is running we are ready flash the UEFI image:: flash rawwrite 200000 100000 >> Send SPI_NOR_UBOOT.fd via XMODEM (Control-A S in minicom) << -*!!NOTE!! The flasher command parameter is different from the command for board recovery. U-Boot uses the offset 200000 (2-five-0, 2M in hex) and the size 100000 (1-five-0, 1M in hex).* +*!!NOTE!! The flasher command parameter is different from the command for +board recovery. U-Boot uses the offset 200000 (2-five-0, 2M in hex) and the +size 100000 (1-five-0, 1M in hex).* -After transferring the SPI_NOR_UBOOT.fd, turn off the DSW2-7 and reset the board. +After transferring the SPI_NOR_UBOOT.fd, turn off the DSW2-7 and +reset the board. + +Enable FWU Multi Bank Update +============================ + +DeveloperBox supports the FWU Multi Bank Update. You *MUST* update both +*SCP firmware* and *TF-A* for this feature. This will change the layout and +the boot process but you can switch back to the normal one by changing +the DSW 1-4 off. + +Configure U-Boot +---------------- + +To enable the FWU Multi Bank Update on the DeveloperBox board the +configs/synquacer_developerbox_defconfig enables default FWU configuration :: + + CONFIG_FWU_MULTI_BANK_UPDATE=y + CONFIG_FWU_MDATA=y + CONFIG_FWU_MDATA_MTD=y + CONFIG_FWU_NUM_BANKS=2 + CONFIG_FWU_NUM_IMAGES_PER_BANK=1 + CONFIG_CMD_FWU_METADATA=y + +And build it:: + + cd u-boot/ + export ARCH=arm64 + export CROSS_COMPILE=aarch64-linux-gnu- + make synquacer_developerbox_defconfig + make -j `noproc` + cd ../ + +By default, the CONFIG_FWU_NUM_BANKS and CONFIG_FWU_NUM_IMAGES_PER_BANKS are +set to 2 and 1 respectively. This uses FIP (Firmware Image Package) type image +which contains TF-A, U-Boot and OP-TEE (the OP-TEE is optional). +You can use fiptool to compose the FIP image from those firmware images. + +Rebuild SCP firmware +-------------------- + +Rebuild SCP firmware which supports FWU Multi Bank Update as below:: + + cd SCP-firmware/ + OUT=./build/product/synquacer + ROMFW_FILE=$OUT/scp_romfw/$SCP_BUILD_MODE/bin/scp_romfw.bin + RAMFW_FILE=$OUT/scp_ramfw/$SCP_BUILD_MODE/bin/scp_ramfw.bin + ROMRAMFW_FILE=scp_romramfw_release.bin + + make CC=arm-none-eabi-gcc PRODUCT=synquacer MODE=release + tr "\000" "\377" < /dev/zero | dd of=${ROMRAMFW_FILE} bs=1 count=196608 + dd if=${ROMFW_FILE} of=${ROMRAMFW_FILE} bs=1 conv=notrunc seek=0 + dd if=${RAMFW_FILE} of=${ROMRAMFW_FILE} bs=1 seek=65536 + cd ../ + +And you can get the `scp_romramfw_release.bin` file. + +Rebuild OPTEE firmware +---------------------- + +Rebuild OPTEE to use in new-layout FIP as below:: + + cd optee_os/ + make -j`nproc` PLATFORM=synquacer ARCH=arm \ + CROSS_COMPILE64=aarch64-linux-gnu- CFG_ARM64_core=y \ + CFG_CRYPTO_WITH_CE=y CFG_CORE_HEAP_SIZE=524288 CFG_CORE_DYN_SHM=y \ + CFG_CORE_ARM64_PA_BITS=48 CFG_TEE_CORE_LOG_LEVEL=1 CFG_TEE_TA_LOG_LEVEL=1 + cp out/arm-plat-synquacer/core/tee-pager_v2.bin ../arm-trusted-firmware/ + +The produced `tee-pager_v2.bin` is to be used while building TF-A next. + + +Rebuild TF-A and FIP +-------------------- + +Rebuild TF-A which supports FWU Multi Bank Update as below:: + + cd arm-trusted-firmware/ + make CROSS_COMPILE=aarch64-linux-gnu- -j`nproc` PLAT=synquacer \ + TRUSTED_BOARD_BOOT=1 SPD=opteed SQ_RESET_TO_BL2=1 GENERATE_COT=1 \ + MBEDTLS_DIR=../mbedtls BL32=tee-pager_v2.bin \ + BL33=../u-boot/u-boot.bin all fip fiptool + +And make a FIP image.:: + + cp build/synquacer/release/fip.bin SPI_NOR_NEWFIP.fd + tools/fiptool/fiptool update --tb-fw build/synquacer/release/bl2.bin SPI_NOR_NEWFIP.fd + +UUIDs for the FWU Multi Bank Update +----------------------------------- + +FWU multi-bank update requires some UUIDs. The DeveloperBox platform uses +following UUIDs. + + - Location UUID for the FIP image: 17e86d77-41f9-4fd7-87ec-a55df9842de5 + - Image type UUID for the FIP image: 10c36d7d-ca52-b843-b7b9-f9d6c501d108 + - Image UUID for Bank0 : 5a66a702-99fd-4fef-a392-c26e261a2828 + - Image UUID for Bank1 : a8f868a1-6e5c-4757-878d-ce63375ef2c0 + +These UUIDs are used for making a FWU metadata image. + +u-boot$ ./tools/mkfwumdata -i 1 -b 2 \ + 17e86d77-41f9-4fd7-87ec-a55df9842de5,10c36d7d-ca52-b843-b7b9-f9d6c501d108,5a66a702-99fd-4fef-a392-c26e261a2828,a8f868a1-6e5c-4757-878d-ce63375ef2c0 \ + ../devbox-fwu-mdata.img + +Create Accept & Revert capsules + +u-boot$ ./tools/mkeficapsule -A -g 7d6dc310-52ca-43b8-b7b9-f9d6c501d108 NEWFIP_accept.Cap +u-boot$ ./tools/mkeficapsule -R NEWFIP_revert.Cap + +Install via flash writer +------------------------ + +As explained in above section, the new FIP image and the FWU metadata image +can be installed via NOR flash writer. + +Once the flasher tool is running we are ready to flash the images.:: +Write the FIP image to the Bank-0 & 1 at 6MB and 10MB offset.:: + + flash rawwrite 600000 180000 + flash rawwrite a00000 180000 + >> Send SPI_NOR_NEWFIP.fd via XMODEM (Control-A S in minicom) << + + flash rawwrite 500000 1000 + flash rawwrite 530000 1000 + >> Send devbox-fwu-mdata.img via XMODEM (Control-A S in minicom) << + +And write the new SCP firmware.:: + + flash write cm3 + >> Send scp_romramfw_release.bin via XMODEM (Control-A S in minicom) << + +At last, turn on the DSW 3-4 on the board, and reboot. +Note that if DSW 3-4 is turned off, the DeveloperBox will boot from +the original EDK2 firmware (or non-FWU U-Boot if you already installed). diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 8f44c6f66a..cd7359c2f8 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -40,19 +40,29 @@ /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ +#ifdef CONFIG_FWU_MULTI_BANK_UPDATE +#define DEFAULT_DFU_ALT_INFO +#else #define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \ "mtd nor1=u-boot.bin raw 200000 100000;" \ "fip.bin raw 180000 78000;" \ "optee.bin raw 500000 100000\0" +#endif /* GUIDs for capsule updatable firmware images */ #define DEVELOPERBOX_UBOOT_IMAGE_GUID \ EFI_GUID(0x53a92e83, 0x4ef4, 0x473a, 0x8b, 0x0d, \ 0xb5, 0xd8, 0xc7, 0xb2, 0xd6, 0x00) +#ifdef CONFIG_FWU_MULTI_BANK_UPDATE +#define DEVELOPERBOX_FIP_IMAGE_GUID \ + EFI_GUID(0x7d6dc310, 0x52ca, 0x43b8, 0xb7, 0xb9, \ + 0xf9, 0xd6, 0xc5, 0x01, 0xd1, 0x08) +#else #define DEVELOPERBOX_FIP_IMAGE_GUID \ EFI_GUID(0x880866e9, 0x84ba, 0x4793, 0xa9, 0x08, \ 0x33, 0xe0, 0xb9, 0x16, 0xf3, 0x98) +#endif #define DEVELOPERBOX_OPTEE_IMAGE_GUID \ EFI_GUID(0xc1b629f1, 0xce0e, 0x4894, 0x82, 0xbf, \ -- cgit v1.2.3 From 1be82afa807cc3cfacab29e3de0975d2cd99fa5d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 17 May 2023 09:17:16 +0200 Subject: global: Use proper project name U-Boot Use proper project name in comments, Kconfig, readmes. Reviewed-by: Neil Armstrong Acked-by: Ilias Apalodimas Reviewed-by: Stefan Roese Reviewed-by: Qu Wenruo Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/0dbdf0432405c1c38ffca55703b6737a48219e79.1684307818.git.michal.simek@amd.com --- arch/Kconfig.nxp | 2 +- arch/arc/include/asm/io.h | 2 +- arch/arm/cpu/armv7/Kconfig | 2 +- arch/arm/cpu/armv8/Kconfig | 2 +- arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 | 2 +- arch/arm/dts/fsl-ls1028a.dtsi | 2 +- arch/arm/dts/meson-g12-common-u-boot.dtsi | 2 +- arch/arm/dts/meson-gx-u-boot.dtsi | 2 +- arch/arm/dts/rk3328-evb-u-boot.dtsi | 2 +- arch/arm/dts/rk3328.dtsi | 2 +- .../include/asm/arch-fsl-layerscape/stream_id_lsch2.h | 2 +- .../include/asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 +- board/bosch/acc/acc.c | 2 +- board/bosch/shc/README | 2 +- board/compulab/cl-som-imx7/cl-som-imx7.c | 2 +- board/hisilicon/poplar/README | 2 +- board/isee/igep003x/board.c | 2 +- board/isee/igep00x0/igep00x0.c | 2 +- board/keymile/Kconfig | 8 ++++---- board/keymile/README | 2 +- board/kontron/sl-mx6ul/spl.c | 2 +- board/phytec/pcm058/README | 18 +++++++++--------- board/synopsys/hsdk/hsdk.c | 14 +++++++------- boot/boot_fit.c | 2 +- cmd/ufs.c | 2 +- common/spl/spl.c | 2 +- common/spl/spl_mmc.c | 2 +- doc/README.pcap | 2 +- doc/README.s5p4418 | 2 +- doc/SPL/README.spl-secure-boot | 4 ++-- doc/board/amlogic/p201.rst | 2 +- doc/board/amlogic/p212.rst | 2 +- doc/board/amlogic/s400.rst | 2 +- doc/board/emulation/qemu-arm.rst | 2 +- doc/board/nxp/ls1046ardb.rst | 2 +- doc/board/nxp/mx6sabresd.rst | 2 +- doc/board/rockchip/rockchip.rst | 6 +++--- doc/board/sifive/unmatched.rst | 2 +- doc/board/st/stm32mp1.rst | 2 +- doc/board/xen/xenguest_arm64.rst | 10 +++++----- doc/develop/driver-model/bind.rst | 2 +- doc/develop/driver-model/fs_firmware_loader.rst | 6 +++--- doc/develop/uefi/uefi.rst | 2 +- doc/usage/cmd/source.rst | 2 +- doc/usage/dfu.rst | 2 +- drivers/clk/clk-mux.c | 2 +- drivers/gpio/gpio-fxl6408.c | 2 +- drivers/mtd/nand/raw/Kconfig | 6 +++--- drivers/mtd/nand/raw/fsl_ifc_spl.c | 4 ++-- drivers/net/pfe_eth/pfe_hw.c | 2 +- drivers/phy/marvell/comphy_cp110.c | 2 +- drivers/spi/spi-qup.c | 2 +- dts/Kconfig | 4 ++-- fs/btrfs/compat.h | 2 +- fs/btrfs/extent-io.h | 2 +- include/fsl_validate.h | 4 ++-- include/zynqmp_firmware.h | 2 +- test/py/tests/test_android/test_avb.py | 2 +- test/py/tests/test_cat/conftest.py | 2 +- test/py/tests/test_efi_bootmgr/conftest.py | 2 +- test/py/tests/test_efi_capsule/conftest.py | 2 +- test/py/tests/test_efi_secboot/conftest.py | 4 ++-- test/py/tests/test_eficonfig/conftest.py | 2 +- test/py/tests/test_fs/conftest.py | 12 ++++++------ test/py/tests/test_scp03.py | 2 +- test/py/tests/test_xxd/conftest.py | 2 +- 66 files changed, 103 insertions(+), 103 deletions(-) (limited to 'doc') diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp index 6e1c44b7ea..e75226bc43 100644 --- a/arch/Kconfig.nxp +++ b/arch/Kconfig.nxp @@ -90,7 +90,7 @@ config SPL_UBOOT_KEY_HASH default "" help Set the key hash for U-Boot here if public/private key pair used to - sign U-boot are different from the SRK hash put in the fuse. Example + sign U-Boot are different from the SRK hash put in the fuse. Example of a key hash is 41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b. Otherwise leave this empty. diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h index 6adc0ed42b..c818b8bdae 100644 --- a/arch/arc/include/asm/io.h +++ b/arch/arc/include/asm/io.h @@ -80,7 +80,7 @@ static inline void sync(void) /* * We add memory barriers for __raw_readX / __raw_writeX accessors same way as - * it is done for readX and writeX accessors as lots of U-boot driver uses + * it is done for readX and writeX accessors as lots of U-Boot driver uses * __raw_readX / __raw_writeX instead of proper accessor with barrier. */ #define __raw_writeb(v, c) ({ __iowmb(); __arch_putb(v, c); }) diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index e33e53636a..ccc2f20867 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig @@ -110,7 +110,7 @@ config ARMV7_LPAE config ARMV7_SET_CORTEX_SMPEN bool help - Enable the ARM Cortex ACTLR.SMP enable bit in U-boot. + Enable the ARM Cortex ACTLR.SMP enable bit in U-Boot. config SPL_ARMV7_SET_CORTEX_SMPEN bool diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 7d5cf1594d..9f0fb369f7 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -145,7 +145,7 @@ config ARMV8_PSCI bool "Enable PSCI support" if EXPERT help PSCI is Power State Coordination Interface defined by ARM. - The PSCI in U-boot provides a general framework and each platform + The PSCI in U-Boot provides a general framework and each platform can implement their own specific PSCI functions. Say Y here to enable PSCI support on ARMv8 platform. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 index 6f3fe7ca6e..1ddf9473a3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 @@ -125,7 +125,7 @@ mcinitcmd: This environment variable is defined to initiate MC and DPL deploymen from the location where it is stored(NOR, NAND, SD, SATA, USB)during u-boot booting.If this variable is not defined then MC_BOOT_ENV_VAR will be null and MC will not be booted and DPL will not be applied - during U-boot booting.However the MC, DPC and DPL can be applied from + during U-Boot booting.However the MC, DPC and DPL can be applied from console independently. The variable needs to be set from the console once and then on rebooting the parameters set in the variable will automatically be diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 06b36cc658..dde0c4091f 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -51,7 +51,7 @@ idle-states { /* - * PSCI node is not added default, U-boot will add missing + * PSCI node is not added default, U-Boot will add missing * parts if it determines to use PSCI. */ entry-method = "psci"; diff --git a/arch/arm/dts/meson-g12-common-u-boot.dtsi b/arch/arm/dts/meson-g12-common-u-boot.dtsi index efa6a0570b..8070b62af5 100644 --- a/arch/arm/dts/meson-g12-common-u-boot.dtsi +++ b/arch/arm/dts/meson-g12-common-u-boot.dtsi @@ -5,7 +5,7 @@ */ / { - /* Keep HW order from U-boot */ + /* Keep HW order from U-Boot */ aliases { /delete-property/ mmc0; /delete-property/ mmc1; diff --git a/arch/arm/dts/meson-gx-u-boot.dtsi b/arch/arm/dts/meson-gx-u-boot.dtsi index 9f123ab042..9e0620f395 100644 --- a/arch/arm/dts/meson-gx-u-boot.dtsi +++ b/arch/arm/dts/meson-gx-u-boot.dtsi @@ -5,7 +5,7 @@ */ / { - /* Keep HW order from U-boot */ + /* Keep HW order from U-Boot */ aliases { /delete-property/ mmc0; /delete-property/ mmc1; diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi index 4bfa0c2330..95e497970e 100644 --- a/arch/arm/dts/rk3328-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi @@ -41,7 +41,7 @@ }; &gmac2phy { - /* Integrated PHY unsupported by U-boot */ + /* Integrated PHY unsupported by U-Boot */ status = "broken"; }; diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index 27e45d5886..e8d8f00be8 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -984,7 +984,7 @@ }; /* - * U-boot Specific Change + * U-Boot Specific Change * * The OTG controller must come after the USB host pair for it * to work. This is likely due to lack of support for the USB diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h index 1b02d484d9..c18c51ed2c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h @@ -22,7 +22,7 @@ * * -PCIe * -there is a range of stream IDs set aside for PCI in this - * file. U-boot will scan the PCI bus and for each device discovered: + * file. U-Boot will scan the PCI bus and for each device discovered: * -allocate a streamID * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' * -set a msi-map entry in the PEXn controller node in the diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index b36b6d3889..140849d4e1 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -23,7 +23,7 @@ * * -PCIe * -there is a range of stream IDs set aside for PCI in this - * file. U-boot will scan the PCI bus and for each device discovered: + * file. U-Boot will scan the PCI bus and for each device discovered: * -allocate a streamID * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' * -set a msi-map entry in the PEXn controller node in the diff --git a/board/bosch/acc/acc.c b/board/bosch/acc/acc.c index 4a0603d0f3..62388b345e 100644 --- a/board/bosch/acc/acc.c +++ b/board/bosch/acc/acc.c @@ -559,7 +559,7 @@ int board_mmc_init(struct bd_info *bis) gpio_direction_input(USDHC2_CD_GPIO); /* * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 USDHC2 * mmc1 USDHC4 */ diff --git a/board/bosch/shc/README b/board/bosch/shc/README index 2f206e0d55..74704cdc11 100644 --- a/board/bosch/shc/README +++ b/board/bosch/shc/README @@ -68,7 +68,7 @@ Netboot - see also doc/SPL/README.am335x-network - set the jumper into netboot mode -- compile the U-boot sources with: +- compile the U-Boot sources with: make am335x_shc_netboot_defconfig make all - copy the images into your tftp boot directory diff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c index 1b08a2c5ab..af19a658b5 100644 --- a/board/compulab/cl-som-imx7/cl-som-imx7.c +++ b/board/compulab/cl-som-imx7/cl-som-imx7.c @@ -86,7 +86,7 @@ int board_mmc_init(struct bd_info *bis) int i, ret; /* * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 USDHC1 * mmc2 USDHC3 (eMMC) */ diff --git a/board/hisilicon/poplar/README b/board/hisilicon/poplar/README index 99ed6ce295..77dcc3ba11 100644 --- a/board/hisilicon/poplar/README +++ b/board/hisilicon/poplar/README @@ -30,7 +30,7 @@ CONNECTORS One connector for Smart Card One connector for TSI Note of warning: ================ -U-boot has a *strong* dependency with the l-loader and the arm trusted firmware +U-Boot has a *strong* dependency with the l-loader and the arm trusted firmware repositories. The boot sequence is: diff --git a/board/isee/igep003x/board.c b/board/isee/igep003x/board.c index 5462a3dea2..7dbb080089 100644 --- a/board/isee/igep003x/board.c +++ b/board/isee/igep003x/board.c @@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; /* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards * and control IGEP0034 green and red LEDs. - * U-boot configures these pins as input pullup to detect board revision: + * U-Boot configures these pins as input pullup to detect board revision: * IGEP0034-LITE = 0b00 * IGEP0034 (FULL) = 0b01 * IGEP0033 = 0b1X diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index f1599306e6..0f0a9c592f 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -47,7 +47,7 @@ U_BOOT_DRVINFO(igep_uart) = { * IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from * IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because * this functionality is shared by USB HOST. - * Once USB reset is applied, U-boot configures these pins as input pullup to + * Once USB reset is applied, U-Boot configures these pins as input pullup to * detect board and revision: * IGEP0020-RF = 0b00 * IGEP0020-RC = 0b01 diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index bf899d005c..c6576aa652 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -123,7 +123,7 @@ config SYS_IVM_EEPROM_PAGE_LEN Page size of inventory in EEPROM. config PG_WCOM_UBOOT_UPDATE_SUPPORTED - bool "Enable U-boot Field Fail-Safe Update Functionality" + bool "Enable U-Boot Field Fail-Safe Update Functionality" select EVENT default n help @@ -132,7 +132,7 @@ config PG_WCOM_UBOOT_UPDATE_SUPPORTED from parallel NOR flash. config PG_WCOM_UBOOT_BOOTPACKAGE - bool "U-boot Is Part Of Factory Boot-Package Image" + bool "U-Boot Is Part Of Factory Boot-Package Image" default n help Indicates that u-boot will be a part of the factory programmed @@ -140,7 +140,7 @@ config PG_WCOM_UBOOT_BOOTPACKAGE Has to be set for original u-boot programmed at factory. config PG_WCOM_UBOOT_UPDATE_TEXT_BASE - hex "Text Base For U-boot Programmed Outside Factory" + hex "Text Base For U-Boot Programmed Outside Factory" default 0xFFFFFFFF help Text base of an updated u-boot that is not factory programmed but @@ -148,7 +148,7 @@ config PG_WCOM_UBOOT_UPDATE_TEXT_BASE Has to be set for original u-boot programmed at factory. config PG_WCOM_UBOOT_UPDATE - bool "U-boot Is Part Of Factory Boot-Package Image" + bool "U-Boot Is Part Of Factory Boot-Package Image" default n help Indicates that u-boot will be a part of the embedded software and diff --git a/board/keymile/README b/board/keymile/README index 4e5cfb142a..99f27e576a 100644 --- a/board/keymile/README +++ b/board/keymile/README @@ -1,4 +1,4 @@ -Field Fail-Save U-boot Update +Field Fail-Save U-Boot Update ----------------------------- Field Fail-Save u-boot update is a feature that allows save u-boot update of FOX and XMC products that are rolled out in the field. diff --git a/board/kontron/sl-mx6ul/spl.c b/board/kontron/sl-mx6ul/spl.c index bae0e70a65..a9d370bc85 100644 --- a/board/kontron/sl-mx6ul/spl.c +++ b/board/kontron/sl-mx6ul/spl.c @@ -101,7 +101,7 @@ int board_mmc_init(struct bd_info *bis) /* * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 USDHC1 * mmc1 USDHC2 */ diff --git a/board/phytec/pcm058/README b/board/phytec/pcm058/README index 687366bffb..4b6984cd54 100644 --- a/board/phytec/pcm058/README +++ b/board/phytec/pcm058/README @@ -37,12 +37,12 @@ not supported. Flashing U-Boot onto an SD card ------------------------------- -After a successful build, the generated SPL and U-boot binaries can be copied +After a successful build, the generated SPL and U-Boot binaries can be copied to an SD card. Adjust the SD card device as necessary: $ sudo dd if=u-boot-with-spl.imx of=/dev/mmcblk0 bs=1k seek=1 -This is equivalent to separately copying the SPL and U-boot using: +This is equivalent to separately copying the SPL and U-Boot using: $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1 $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=197 @@ -50,11 +50,11 @@ $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=197 The default bootscripts expect a kernel fit-image file named "fitImage" in the first partition and Linux ext4 rootfs in the second partition. -Flashing U-boot to the SPI Flash, for booting Linux from NAND +Flashing U-Boot to the SPI Flash, for booting Linux from NAND ------------------------------------------------------------- -The SD card created above can also be used to install the SPL and U-boot into -the SPI flash. Boot U-boot from the SD card as above, and stop at the autoboot. +The SD card created above can also be used to install the SPL and U-Boot into +the SPI flash. Boot U-Boot from the SD card as above, and stop at the autoboot. Then, clear the SPI flash: @@ -64,13 +64,13 @@ Then, clear the SPI flash: Load the equivalent of u-boot-with-spl.imx from the raw MMC into memory and copy to the SPI. The SPL is expected at an offset of 0x400, and its size is maximum 392*512-byte blocks in size, therefore 0x188 blocks, totaling 0x31000 -bytes. Assume U-boot should fit into 640KiB, therefore 0x500 512-byte blocks, +bytes. Assume U-Boot should fit into 640KiB, therefore 0x500 512-byte blocks, totalling 0xA0000 bytes. Adding these together: => mmc read ${loadaddr} 0x2 0x688 => sf write ${loadaddr} 0x400 0xD1000 -The SPL is located at offset 0x400, and U-boot at 0x31400 in SPI flash, as to +The SPL is located at offset 0x400, and U-Boot at 0x31400 in SPI flash, as to match the SD Card layout. This would allow, instead of reading from the SD Card above, with networking and TFTP correctly configured, the equivalent of: @@ -84,7 +84,7 @@ image) and "root" (which contains a ubifs root filesystem). The "bootm_size" variable in the environment -------------------------------------------- -By default, U-boot relocates the device tree towards the upper end of the RAM, +By default, U-Boot relocates the device tree towards the upper end of the RAM, which kernels using CONFIG_HIGHMEM=y may not be able to access during early -boot. With the bootm_size variable set to 0x30000000, U-boot relocates the +boot. With the bootm_size variable set to 0x30000000, U-Boot relocates the device tree to below this address instead. diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c index 4308c7e440..6cbc89ae78 100644 --- a/board/synopsys/hsdk/hsdk.c +++ b/board/synopsys/hsdk/hsdk.c @@ -583,7 +583,7 @@ enum hsdk_axi_masters { * * Please read ARC HS Development IC Specification, section 17.2 for more * information about apertures configuration. - * NOTE: we intentionally modify default settings in U-boot. Default settings + * NOTE: we intentionally modify default settings in U-Boot. Default settings * are specified in "Table 111 CREG Address Decoder register reset values". */ @@ -942,7 +942,7 @@ static int do_hsdk_go(struct cmd_tbl *cmdtp, int flag, int argc, int ret; if (board_mismatch()) { - printf("ERR: U-boot is not configured for this board!\n"); + printf("ERR: U-Boot is not configured for this board!\n"); return CMD_RET_FAILURE; } @@ -983,10 +983,10 @@ U_BOOT_CMD( /* * We may simply use static variable here to store init status, but we also want - * to avoid the situation when we reload U-boot via MDB after previous + * to avoid the situation when we reload U-Boot via MDB after previous * init is done but HW reset (board reset) isn't done. So let's store the * init status in any unused register (i.e CREG_CPU_0_ENTRY) so status will - * survive after U-boot is reloaded via MDB. + * survive after U-Boot is reloaded via MDB. */ #define INIT_MARKER_REGISTER ((void __iomem *)CREG_CPU_0_ENTRY) /* must be equal to INIT_MARKER_REGISTER reset value */ @@ -1008,7 +1008,7 @@ static int do_hsdk_init(struct cmd_tbl *cmdtp, int flag, int argc, int ret; if (board_mismatch()) { - printf("ERR: U-boot is not configured for this board!\n"); + printf("ERR: U-Boot is not configured for this board!\n"); return CMD_RET_FAILURE; } @@ -1258,11 +1258,11 @@ int checkboard(void) printf("Board: Synopsys %s\n", board_name(get_board_type_runtime())); if (board_mismatch()) - printf("WARN: U-boot is configured NOT for this board but for %s!\n", + printf("WARN: U-Boot is configured NOT for this board but for %s!\n", board_name(get_board_type_config())); reg = readl(CREG_AXI_M_HS_CORE_BOOT) & CREG_CORE_BOOT_IMAGE; - printf("U-boot autostart: %s\n", reg ? "enabled" : "disabled"); + printf("U-Boot autostart: %s\n", reg ? "enabled" : "disabled"); return 0; }; diff --git a/boot/boot_fit.c b/boot/boot_fit.c index 4a493b3684..9d39412656 100644 --- a/boot/boot_fit.c +++ b/boot/boot_fit.c @@ -67,7 +67,7 @@ void *locate_dtb_in_fit(const void *fit) header = (struct legacy_img_hdr *)fit; if (image_get_magic(header) != FDT_MAGIC) { - debug("No FIT image appended to U-boot\n"); + debug("No FIT image appended to U-Boot\n"); return NULL; } diff --git a/cmd/ufs.c b/cmd/ufs.c index d4a1e66c1b..143e946370 100644 --- a/cmd/ufs.c +++ b/cmd/ufs.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /** - * ufs.c - UFS specific U-boot commands + * ufs.c - UFS specific U-Boot commands * * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com * diff --git a/common/spl/spl.c b/common/spl/spl.c index 72078a8ebc..28124a8bdf 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -321,7 +321,7 @@ static int spl_load_fit_image(struct spl_image_info *spl_image, spl_image->fdt_addr = (void *)dt_data; if (spl_image->os == IH_OS_U_BOOT) { - /* HACK: U-boot expects FDT at a specific address */ + /* HACK: U-Boot expects FDT at a specific address */ fdt_hack = spl_image->load_addr + spl_image->size; fdt_hack = (fdt_hack + 3) & ~3; debug("Relocating FDT to %p\n", spl_image->fdt_addr); diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index a072216704..a665091b00 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -250,7 +250,7 @@ static int mmc_load_image_raw_os(struct spl_image_info *spl_image, return ret; if (spl_image->os != IH_OS_LINUX && spl_image->os != IH_OS_TEE) { - puts("Expected image is not found. Trying to start U-boot\n"); + puts("Expected image is not found. Trying to start U-Boot\n"); return -ENOENT; } diff --git a/doc/README.pcap b/doc/README.pcap index 8e30b93c66..10318ef0a9 100644 --- a/doc/README.pcap +++ b/doc/README.pcap @@ -1,6 +1,6 @@ PCAP: -U-boot supports live Ethernet packet capture in PCAP(2.4) format. +U-Boot supports live Ethernet packet capture in PCAP(2.4) format. This is enabled by CONFIG_CMD_PCAP. The capture is stored on physical memory, and should be copied to diff --git a/doc/README.s5p4418 b/doc/README.s5p4418 index ac724d08a0..8ec7b05fd2 100644 --- a/doc/README.s5p4418 +++ b/doc/README.s5p4418 @@ -38,7 +38,7 @@ The source code for (the used?) LUbuntu 16.04 can be found at [5]. Links ===== -[1] FriendlyArm U-boot v2016.01: +[1] FriendlyArm U-Boot v2016.01: https://github.com/friendlyarm/u-boot/tree/nanopi2-v2016.01 diff --git a/doc/SPL/README.spl-secure-boot b/doc/SPL/README.spl-secure-boot index f2f8d78883..982fbec654 100644 --- a/doc/SPL/README.spl-secure-boot +++ b/doc/SPL/README.spl-secure-boot @@ -12,7 +12,7 @@ Methodology The SPL image is responsible for loading the next stage boot loader, which is the main u-boot image. For secure boot process on these platforms ROM verifies -SPL image, so to continue chain of trust SPL image verifies U-boot image using +SPL image, so to continue chain of trust SPL image verifies U-Boot image using spl_validate_uboot(). This function uses QorIQ Trust Architecture header -(appended to U-boot image) to validate the U-boot binary just before passing +(appended to U-Boot image) to validate the U-Boot binary just before passing control to it. diff --git a/doc/board/amlogic/p201.rst b/doc/board/amlogic/p201.rst index 28aae98d99..13b732fc7e 100644 --- a/doc/board/amlogic/p201.rst +++ b/doc/board/amlogic/p201.rst @@ -56,7 +56,7 @@ image but sources have been shared by Linux development contractor, Baylibre: $ make $ export FIPDIR=$PWD/fip -Go back to mainline U-boot source tree then : +Go back to mainline U-Boot source tree then : .. code-block:: bash diff --git a/doc/board/amlogic/p212.rst b/doc/board/amlogic/p212.rst index c1b73e83b1..a872f32f0f 100644 --- a/doc/board/amlogic/p212.rst +++ b/doc/board/amlogic/p212.rst @@ -50,7 +50,7 @@ the git tree published by the board vendor: $ make $ export FIPDIR=$PWD/fip -Go back to mainline U-boot source tree then : +Go back to mainline U-Boot source tree then : .. code-block:: bash diff --git a/doc/board/amlogic/s400.rst b/doc/board/amlogic/s400.rst index 59dda82375..205e7c38fa 100644 --- a/doc/board/amlogic/s400.rst +++ b/doc/board/amlogic/s400.rst @@ -56,7 +56,7 @@ image but sources have been shared by Linux development contractor, Baylibre: $ make $ export FIPDIR=$PWD/fip -Go back to mainline U-boot source tree then : +Go back to mainline U-Boot source tree then : .. code-block:: bash diff --git a/doc/board/emulation/qemu-arm.rst b/doc/board/emulation/qemu-arm.rst index 16f66388eb..b42d924cc6 100644 --- a/doc/board/emulation/qemu-arm.rst +++ b/doc/board/emulation/qemu-arm.rst @@ -54,7 +54,7 @@ Note that for some odd reason qemu-system-aarch64 needs to be explicitly told to use a 64-bit CPU or it will boot in 32-bit mode. The -nographic argument ensures that output appears on the terminal. Use Ctrl-A X to quit. -Additional persistent U-boot environment support can be added as follows: +Additional persistent U-Boot environment support can be added as follows: - Create envstore.img using qemu-img:: diff --git a/doc/board/nxp/ls1046ardb.rst b/doc/board/nxp/ls1046ardb.rst index 35465d0061..49b4842b30 100644 --- a/doc/board/nxp/ls1046ardb.rst +++ b/doc/board/nxp/ls1046ardb.rst @@ -150,7 +150,7 @@ Then, launch openocd like:: openocd -f u-boot.tcl -You should see the U-boot SPL banner followed by the banner for U-Boot proper +You should see the U-Boot SPL banner followed by the banner for U-Boot proper in the output of openocd. The CMSIS-DAP adapter is slow, so this can take a long time. If you don't see it, something has gone wrong. After a while, you should see the prompt. You can load an image using semihosting by running:: diff --git a/doc/board/nxp/mx6sabresd.rst b/doc/board/nxp/mx6sabresd.rst index fe15ba7b79..c9869f4a73 100644 --- a/doc/board/nxp/mx6sabresd.rst +++ b/doc/board/nxp/mx6sabresd.rst @@ -53,7 +53,7 @@ This will generate the SPL and u-boot-dtb.img binaries. - Boot first from SD card as shown in the previous section -In U-boot change the eMMC partition config:: +In U-Boot change the eMMC partition config:: => mmc partconf 2 1 0 0 diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 99376fb54c..4c555e1c9c 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -333,12 +333,12 @@ Note: Unlike later SoC models the rk3066 BootROM doesn't have SDMMC support. If all other boot options fail then it enters into a BootROM mode on the USB OTG port. -This method loads TPL/SPL on NAND with U-boot and kernel on SD card. +This method loads TPL/SPL on NAND with U-Boot and kernel on SD card. SD Card ^^^^^^^ -U-boot expects a GPT partition map and a boot directory structure with files on the SD card. +U-Boot expects a GPT partition map and a boot directory structure with files on the SD card. .. code-block:: none @@ -363,7 +363,7 @@ Boot partition: zImage rk3066a-mk808.dtb -To write a U-boot image to the SD card (assumed to be /dev/sda): +To write a U-Boot image to the SD card (assumed to be /dev/sda): .. code-block:: bash diff --git a/doc/board/sifive/unmatched.rst b/doc/board/sifive/unmatched.rst index de2aab59bb..c515949066 100644 --- a/doc/board/sifive/unmatched.rst +++ b/doc/board/sifive/unmatched.rst @@ -558,7 +558,7 @@ for partitions one through three respectively. --new=3:10280:10535 --change-name=3:env --typecode=3:3DE21764-95BD-54BD-A5C3-4ABE786F38A8 \ /dev/mtdblock0 -Write U-boot SPL and U-boot to their partitions. +Write U-Boot SPL and U-Boot to their partitions. .. code-block:: none diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst index c0b1daa041..63b44776ff 100644 --- a/doc/board/st/stm32mp1.rst +++ b/doc/board/st/stm32mp1.rst @@ -345,7 +345,7 @@ Build Procedure - BL33=u-boot-nodtb.bin - BL33_CFG=u-boot.dtb - You can also update a existing FIP after U-boot compilation with fiptool, + You can also update a existing FIP after U-Boot compilation with fiptool, a tool provided by TF-A_:: # fiptool update --nt-fw u-boot-nodtb.bin --hw-config u-boot.dtb fip-stm32mp157c-ev1.bin diff --git a/doc/board/xen/xenguest_arm64.rst b/doc/board/xen/xenguest_arm64.rst index 1327f88f99..e9bdaf7ffb 100644 --- a/doc/board/xen/xenguest_arm64.rst +++ b/doc/board/xen/xenguest_arm64.rst @@ -6,7 +6,7 @@ Xen guest ARM64 board This board specification ------------------------ -This board is to be run as a virtual Xen [1] guest with U-boot as its primary +This board is to be run as a virtual Xen [1] guest with U-Boot as its primary bootloader. Xen is a type 1 hypervisor that allows multiple operating systems to run simultaneously on a single physical server. Xen is capable of running virtual machines in both full virtualization and para-virtualization (PV) @@ -16,7 +16,7 @@ Paravirtualized drivers are a special type of device drivers that are used in a guest system in the Xen domain and perform I/O operations using a special interface provided by the virtualization system and the host system. -Xen support for U-boot is implemented by introducing a new Xen guest ARM64 +Xen support for U-Boot is implemented by introducing a new Xen guest ARM64 board and porting essential drivers from MiniOS [3] as well as some of the work previously done by NXP [4]: @@ -39,7 +39,7 @@ previously done by NXP [4]: Board limitations ----------------- -1. U-boot runs without MMU enabled at the early stages. +1. U-Boot runs without MMU enabled at the early stages. According to Xen on ARM ABI (xen/include/public/arch-arm.h): all memory which is shared with other entities in the system (including the hypervisor and other guests) must reside in memory which is mapped as Normal Inner @@ -54,14 +54,14 @@ Board limitations 2. No serial console until MMU is up. Because data cache maintenance is required until the MMU setup the early/debug serial console is not implemented. Therefore, we do not have - usual prints like U-boot’s banner etc. until the serial driver is + usual prints like U-Boot’s banner etc. until the serial driver is initialized. 3. Single RAM bank supported. If a Xen guest is given much memory it is possible that Xen allocates two memory banks for it. The first one is allocated under 4GB address space and in some cases may represent the whole guest’s memory. It is assumed that - U-boot most likely won’t require high memory bank for its work andlaunching + U-Boot most likely won’t require high memory bank for its work andlaunching OS, so it is enough to take the first one. diff --git a/doc/develop/driver-model/bind.rst b/doc/develop/driver-model/bind.rst index b19661b5fe..0d0d40734c 100644 --- a/doc/develop/driver-model/bind.rst +++ b/doc/develop/driver-model/bind.rst @@ -7,7 +7,7 @@ Binding/unbinding a driver This document aims to describe the bind and unbind commands. For debugging purpose, it should be useful to bind or unbind a driver from -the U-boot command line. +the U-Boot command line. The unbind command calls the remove device driver callback and unbind the device from its driver. diff --git a/doc/develop/driver-model/fs_firmware_loader.rst b/doc/develop/driver-model/fs_firmware_loader.rst index b0823700a9..149b8b436e 100644 --- a/doc/develop/driver-model/fs_firmware_loader.rst +++ b/doc/develop/driver-model/fs_firmware_loader.rst @@ -92,9 +92,9 @@ For example of getting DT phandle from /chosen and creating instance: if (ret) return ret; -Firmware loader driver is also designed to support U-boot environment +Firmware loader driver is also designed to support U-Boot environment variables, so all these data from FDT can be overwritten -through the U-boot environment variable during run time. +through the U-Boot environment variable during run time. For examples: @@ -110,7 +110,7 @@ fw_ubi_volume: When above environment variables are set, environment values would be used instead of data from FDT. The benefit of this design allows user to change storage attribute data -at run time through U-boot console and saving the setting as default +at run time through U-Boot console and saving the setting as default environment values in the storage for the next power cycle, so no compilation is required for both driver and FDT. diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst index ffe25ca231..ef0987c355 100644 --- a/doc/develop/uefi/uefi.rst +++ b/doc/develop/uefi/uefi.rst @@ -330,7 +330,7 @@ bit in OsIndications variable with => setenv -e -nv -bs -rt -v OsIndications =0x0000000000000004 -Since U-boot doesn't currently support SetVariable at runtime, its value +Since U-Boot doesn't currently support SetVariable at runtime, its value won't be taken over across the reboot. If this is the case, you can skip this feature check with the Kconfig option (CONFIG_EFI_IGNORE_OSINDICATIONS) set. diff --git a/doc/usage/cmd/source.rst b/doc/usage/cmd/source.rst index 61a4505909..a5c5204a28 100644 --- a/doc/usage/cmd/source.rst +++ b/doc/usage/cmd/source.rst @@ -161,7 +161,7 @@ The boot scripts (boot.scr) is created with: mkimage -T script -n 'Test script' -d boot.txt boot.scr -The script can be execute in U-boot like this: +The script can be execute in U-Boot like this: .. code-block:: diff --git a/doc/usage/dfu.rst b/doc/usage/dfu.rst index ed47ff561e..68cacbbef6 100644 --- a/doc/usage/dfu.rst +++ b/doc/usage/dfu.rst @@ -9,7 +9,7 @@ Overview The Device Firmware Upgrade (DFU) allows to download and upload firmware to/from U-Boot connected over USB. -U-boot follows the Universal Serial Bus Device Class Specification for +U-Boot follows the Universal Serial Bus Device Class Specification for Device Firmware Upgrade Version 1.1 the USB forum (DFU v1.1 in www.usb.org). U-Boot implements this DFU capability (CONFIG_DFU) with the command dfu diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 184d426d0b..017f25f7a5 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -184,7 +184,7 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name, if (!mux) return ERR_PTR(-ENOMEM); - /* U-boot specific assignments */ + /* U-Boot specific assignments */ mux->parent_names = parent_names; mux->num_parents = num_parents; diff --git a/drivers/gpio/gpio-fxl6408.c b/drivers/gpio/gpio-fxl6408.c index 902da050fb..ca7aa14eeb 100644 --- a/drivers/gpio/gpio-fxl6408.c +++ b/drivers/gpio/gpio-fxl6408.c @@ -27,7 +27,7 @@ * https://patchwork.kernel.org/patch/9148419/ * - the Toradex version by Max Krummenacher : * http://git.toradex.com/cgit/linux-toradex.git/tree/drivers/gpio/gpio-fxl6408.c?h=toradex_5.4-2.3.x-imx - * - the U-boot PCA953x driver by Peng Fan : + * - the U-Boot PCA953x driver by Peng Fan : * drivers/gpio/pca953x_gpio.c * * TODO: diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index d115fcf841..d624589a89 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -553,7 +553,7 @@ config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS bool "Enable use of 1st stage bootloader timing for NAND" depends on NAND_ZYNQ help - This flag prevent U-boot reconfigure NAND flash controller and reuse + This flag prevent U-Boot reconfigure NAND flash controller and reuse the NAND timing from 1st stage bootloader. config NAND_OCTEONTX @@ -732,10 +732,10 @@ config SYS_NAND_BAD_BLOCK_POS default 5 if HAS_NAND_SMALL_BADBLOCK_POS config SYS_NAND_U_BOOT_LOCATIONS - bool "Define U-boot binaries locations in NAND" + bool "Define U-Boot binaries locations in NAND" help Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. - This option should not be enabled when compiling U-boot for boards + This option should not be enabled when compiling U-Boot for boards defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/.h file. diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c index 60a865b566..c67065eaf8 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_spl.c +++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c @@ -275,8 +275,8 @@ void nand_boot(void) #ifdef CONFIG_CHAIN_OF_TRUST /* - * U-Boot header is appended at end of U-boot image, so - * calculate U-boot header address using U-boot header size. + * U-Boot header is appended at end of U-Boot image, so + * calculate U-Boot header address using U-Boot header size. */ #define FSL_U_BOOT_HDR_ADDR \ ((CFG_SYS_NAND_U_BOOT_START + \ diff --git a/drivers/net/pfe_eth/pfe_hw.c b/drivers/net/pfe_eth/pfe_hw.c index 4db6f3158c..9f2f92d116 100644 --- a/drivers/net/pfe_eth/pfe_hw.c +++ b/drivers/net/pfe_eth/pfe_hw.c @@ -814,7 +814,7 @@ static inline void class_set_config(struct class_cfg *cfg) writel(0x1, CLASS_AXI_CTRL); /*Make Util AXI transactions non-bufferable */ - /*Util is disabled in U-boot, do it from here */ + /*Util is disabled in U-Boot, do it from here */ writel(0x1, UTIL_AXI_CTRL); } diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index e063b51c6d..a7e0099045 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; #define MV_SIP_COMPHY_PLL_LOCK 0x82000003 #define MV_SIP_COMPHY_XFI_TRAIN 0x82000004 -/* Used to distinguish between different possible callers (U-boot/Linux) */ +/* Used to distinguish between different possible callers (U-Boot/Linux) */ #define COMPHY_CALLER_UBOOT (0x1 << 21) #define COMPHY_FW_MODE_FORMAT(mode) ((mode) << 12) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 7b64532e50..572cef1694 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -9,7 +9,7 @@ * Author: Robert Marko * Author: Luka Kovacic * - * Based on stock U-boot and Linux drivers + * Based on stock U-Boot and Linux drivers */ #include diff --git a/dts/Kconfig b/dts/Kconfig index 3b7489f0f8..9152f5885e 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -171,7 +171,7 @@ config OF_LIST default DEFAULT_DEVICE_TREE help This option specifies a list of device tree files to use for DT - control. These will be packaged into a FIT. At run-time, U-boot + control. These will be packaged into a FIT. At run-time, U-Boot or SPL will select the correct DT to use by examining the hardware (e.g. reading a board ID value). This is a list of device tree files (without the directory or .dtb suffix) @@ -254,7 +254,7 @@ config DTB_RESELECT config MULTI_DTB_FIT bool "Support embedding several DTBs in a FIT image for u-boot" help - This option provides hooks to allow U-boot to parse an + This option provides hooks to allow U-Boot to parse an appended FIT image and enable board specific code to then select the correct DTB to be used. Use this if you need to support multiple DTBs but don't use the SPL. diff --git a/fs/btrfs/compat.h b/fs/btrfs/compat.h index 9cf8a10c76..02173dea5f 100644 --- a/fs/btrfs/compat.h +++ b/fs/btrfs/compat.h @@ -46,7 +46,7 @@ /* * Read data from device specified by @desc and @part * - * U-boot equivalent of pread(). + * U-Boot equivalent of pread(). * * Return the bytes of data read. * Return <0 for error. diff --git a/fs/btrfs/extent-io.h b/fs/btrfs/extent-io.h index 6b0c87da96..5c5c579d1e 100644 --- a/fs/btrfs/extent-io.h +++ b/fs/btrfs/extent-io.h @@ -8,7 +8,7 @@ * Use pointer to provide better alignment. * - Remove max_cache_size related interfaces * Includes free_extent_buffer_nocache() - * As we don't cache eb in U-boot. + * As we don't cache eb in U-Boot. * - Include headers * * Write related functions are kept as we still need to modify dummy extent diff --git a/include/fsl_validate.h b/include/fsl_validate.h index fbcbd42496..66a5883f1f 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -275,9 +275,9 @@ int fsl_check_boot_mode_secure(void); int fsl_setenv_chain_of_trust(void); /* - * This function is used to validate the main U-boot binary from + * This function is used to validate the main U-Boot binary from * SPL just before passing control to it using QorIQ Trust - * Architecture header (appended to U-boot image). + * Architecture header (appended to U-Boot image). */ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr); diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index f7a4a39d35..1192d5902d 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -35,7 +35,7 @@ enum pm_api_id { PM_FPGA_LOAD = 22, PM_FPGA_GET_STATUS = 23, PM_GET_CHIPID = 24, - /* ID 25 is been used by U-boot to process secure boot images */ + /* ID 25 is been used by U-Boot to process secure boot images */ /* Secure library generic API functions */ PM_SECURE_SHA = 26, PM_SECURE_RSA = 27, diff --git a/test/py/tests/test_android/test_avb.py b/test/py/tests/test_android/test_avb.py index bc5c5b5582..238b48c90f 100644 --- a/test/py/tests/test_android/test_avb.py +++ b/test/py/tests/test_android/test_avb.py @@ -5,7 +5,7 @@ # Android Verified Boot 2.0 Test """ -This tests Android Verified Boot 2.0 support in U-boot: +This tests Android Verified Boot 2.0 support in U-Boot: For additional details about how to build proper vbmeta partition check doc/android/avb2.rst diff --git a/test/py/tests/test_cat/conftest.py b/test/py/tests/test_cat/conftest.py index 058fe52352..fc396f50d3 100644 --- a/test/py/tests/test_cat/conftest.py +++ b/test/py/tests/test_cat/conftest.py @@ -13,7 +13,7 @@ def cat_data(u_boot_config): """Set up a file system to be used in cat tests Args: - u_boot_config -- U-boot configuration. + u_boot_config -- U-Boot configuration. """ mnt_point = u_boot_config.persistent_data_dir + '/test_cat' image_path = u_boot_config.persistent_data_dir + '/cat.img' diff --git a/test/py/tests/test_efi_bootmgr/conftest.py b/test/py/tests/test_efi_bootmgr/conftest.py index eabafa5429..0eca025058 100644 --- a/test/py/tests/test_efi_bootmgr/conftest.py +++ b/test/py/tests/test_efi_bootmgr/conftest.py @@ -12,7 +12,7 @@ def efi_bootmgr_data(u_boot_config): """Set up a file system to be used in UEFI bootmanager tests. Args: - u_boot_config -- U-boot configuration. + u_boot_config -- U-Boot configuration. Return: A path to disk image to be used for testing diff --git a/test/py/tests/test_efi_capsule/conftest.py b/test/py/tests/test_efi_capsule/conftest.py index a337e62936..3e585b6c3d 100644 --- a/test/py/tests/test_efi_capsule/conftest.py +++ b/test/py/tests/test_efi_capsule/conftest.py @@ -17,7 +17,7 @@ def efi_capsule_data(request, u_boot_config): for testing. request -- Pytest request object. - u_boot_config -- U-boot configuration. + u_boot_config -- U-Boot configuration. """ mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule' data_dir = mnt_point + CAPSULE_DATA_DIR diff --git a/test/py/tests/test_efi_secboot/conftest.py b/test/py/tests/test_efi_secboot/conftest.py index 30ff702943..ff7ac7c810 100644 --- a/test/py/tests/test_efi_secboot/conftest.py +++ b/test/py/tests/test_efi_secboot/conftest.py @@ -14,7 +14,7 @@ def efi_boot_env(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A path to disk image to be used for testing @@ -139,7 +139,7 @@ def efi_boot_env_intca(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A path to disk image to be used for testing diff --git a/test/py/tests/test_eficonfig/conftest.py b/test/py/tests/test_eficonfig/conftest.py index f289df0362..0a82fbefd7 100644 --- a/test/py/tests/test_eficonfig/conftest.py +++ b/test/py/tests/test_eficonfig/conftest.py @@ -14,7 +14,7 @@ def efi_eficonfig_data(u_boot_config): tests Args: - u_boot_config -- U-boot configuration. + u_boot_config -- U-Boot configuration. Return: A path to disk image to be used for testing diff --git a/test/py/tests/test_fs/conftest.py b/test/py/tests/test_fs/conftest.py index 9329ec6f1b..0d87d180c7 100644 --- a/test/py/tests/test_fs/conftest.py +++ b/test/py/tests/test_fs/conftest.py @@ -97,7 +97,7 @@ def pytest_generate_tests(metafunc): # Helper functions # def fstype_to_ubname(fs_type): - """Convert a file system type to an U-boot specific string + """Convert a file system type to an U-Boot specific string A generated string can be used as part of file system related commands or a config name in u-boot. Currently fat16 and fat32 are handled @@ -217,7 +217,7 @@ def fs_obj_basic(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A fixture for basic fs test, i.e. a triplet of file system type, @@ -339,7 +339,7 @@ def fs_obj_ext(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A fixture for extended fs test, i.e. a triplet of file system type, @@ -440,7 +440,7 @@ def fs_obj_mkdir(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A fixture for mkdir test, i.e. a duplet of file system type and @@ -471,7 +471,7 @@ def fs_obj_unlink(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A fixture for unlink test, i.e. a duplet of file system type and @@ -551,7 +551,7 @@ def fs_obj_symlink(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A fixture for basic fs test, i.e. a triplet of file system type, diff --git a/test/py/tests/test_scp03.py b/test/py/tests/test_scp03.py index 1f689252dd..1a104b365f 100644 --- a/test/py/tests/test_scp03.py +++ b/test/py/tests/test_scp03.py @@ -5,7 +5,7 @@ # SCP03 command test """ -This tests SCP03 command in U-boot. +This tests SCP03 command in U-Boot. For additional details check doc/usage/scp03.rst """ diff --git a/test/py/tests/test_xxd/conftest.py b/test/py/tests/test_xxd/conftest.py index 59285aadf4..f35b8f1113 100644 --- a/test/py/tests/test_xxd/conftest.py +++ b/test/py/tests/test_xxd/conftest.py @@ -13,7 +13,7 @@ def xxd_data(u_boot_config): """Set up a file system to be used in xxd tests Args: - u_boot_config -- U-boot configuration. + u_boot_config -- U-Boot configuration. """ mnt_point = u_boot_config.persistent_data_dir + '/test_xxd' image_path = u_boot_config.persistent_data_dir + '/xxd.img' -- cgit v1.2.3 From b1574ddebd34fee83e4c11f9da54b52ba7198fa8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 30 May 2023 15:50:30 -0400 Subject: python: Update requirements.txt for security issues Per GitHub Dependabot: - Use setuptools 65.5.1 to avoid some DoS issue - Use requests 2.31.0 to avoid leaking some proxy information Signed-off-by: Tom Rini Tested-by: Heinrich Schuchardt --- doc/sphinx/requirements.txt | 2 +- test/py/requirements.txt | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'doc') diff --git a/doc/sphinx/requirements.txt b/doc/sphinx/requirements.txt index f9f6cc6e92..aed4492117 100644 --- a/doc/sphinx/requirements.txt +++ b/doc/sphinx/requirements.txt @@ -11,7 +11,7 @@ packaging==21.3 Pygments==2.11.2 pyparsing==3.0.7 pytz==2022.1 -requests==2.27.1 +requests==2.31.0 six==1.16.0 snowballstemmer==2.2.0 Sphinx==3.4.3 diff --git a/test/py/requirements.txt b/test/py/requirements.txt index 86d6266053..f7e76bdb91 100644 --- a/test/py/requirements.txt +++ b/test/py/requirements.txt @@ -20,8 +20,8 @@ pytest==6.2.5 pytest-xdist==2.5.0 python-mimeparse==1.6.0 python-subunit==1.3.0 -requests==2.27.1 -setuptools==58.3.0 +requests==2.31.0 +setuptools==65.5.1 six==1.16.0 testtools==2.3.0 traceback2==1.4.0 -- cgit v1.2.3 From 1444acbd030edc515e4b521d0eb517de7562baa7 Mon Sep 17 00:00:00 2001 From: Ferass El Hafidi Date: Sun, 7 May 2023 12:42:29 +0000 Subject: doc: boards: amlogic: add documentation for KII Pro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add build instructions for the KII Pro set-top box. Signed-off-by: Ferass El Hafidi Link: https://lore.kernel.org/r/20230507124109.31778-4-vitali64pmemail@protonmail.com Signed-off-by: Neil Armstrong --- board/amlogic/p200/MAINTAINERS | 1 + doc/board/amlogic/index.rst | 1 + doc/board/amlogic/videostrong-kii-pro.rst | 112 ++++++++++++++++++++++++++++++ 3 files changed, 114 insertions(+) create mode 100644 doc/board/amlogic/videostrong-kii-pro.rst (limited to 'doc') diff --git a/board/amlogic/p200/MAINTAINERS b/board/amlogic/p200/MAINTAINERS index 19e27def70..5cf0ce05dc 100644 --- a/board/amlogic/p200/MAINTAINERS +++ b/board/amlogic/p200/MAINTAINERS @@ -13,5 +13,6 @@ F: configs/videostrong-kii-pro_defconfig F: doc/board/amlogic/p200.rst F: doc/board/amlogic/nanopi-k2.rst F: doc/board/amlogic/odroid-c2.rst +F: doc/board/amlogic/videostrong-kii-pro.rst F: doc/board/amlogic/wetek-hub.rst F: doc/board/amlogic/wetek-play2.rst diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst index 66b581c837..46f44bf34e 100644 --- a/doc/board/amlogic/index.rst +++ b/doc/board/amlogic/index.rst @@ -118,6 +118,7 @@ Board Documentation sei610 s400 u200 + videostrong-kii-pro wetek-core2 wetek-hub wetek-play2 diff --git a/doc/board/amlogic/videostrong-kii-pro.rst b/doc/board/amlogic/videostrong-kii-pro.rst new file mode 100644 index 0000000000..1c6adac996 --- /dev/null +++ b/doc/board/amlogic/videostrong-kii-pro.rst @@ -0,0 +1,112 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Videostrong KII Pro (S905) +===================================== + +Videostrong KII Pro is an Android STB manufactured by Videostrong and +based on the Amlogic p201 reference board, with the following specification: + + - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - 16GB eMMC + - Gigabit Ethernet + - Boardcom BCM4335 WiFi and BT 4.0 + - HDMI 2.0 4K/60Hz display + - 3x USB 2.0 host + - 1x USB 2.0 otg + - microSD + - Infrared receiver + - Blue LED + - Red LED + - Power button (case, front) + - Reset button (underside) + - DVB Card: DVB-S and DVB-T/C + +Schematics are not publicly available. + +U-Boot Compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make videostrong-kii-pro_defconfig + $ make + +U-Boot Signing with Pre-Built FIP repo +-------------------------------------- + +.. code-block:: bash + + $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1 + $ cd amlogic-boot-fip + $ mkdir my-output-dir + $ ./build-fip.sh wetek-play2 /path/to/u-boot/u-boot.bin my-output-dir + +U-Boot Manual Signing +--------------------- + +Amlogic does not provide sources for the firmware and tools needed to create +a bootloader image and Videostrong has not publicly shared the U-Boot sources +needed to build FIP binaries for signing. However you can use the WeTek +Play2 binaries from the amlogic-boot-fip repo as the WeTek Play2 and the +Videostrong KII Pro share the same RAM chips. + +.. code-block:: bash + + $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1 + $ cd amlogic-boot-fip/wetek-play2 + $ export FIPDIR=$PWD + +Go back to the mainline U-Boot source tree then: + +.. code-block:: bash + + $ mkdir fip + $ cp $FIPDIR/bl2.bin fip/ + $ cp $FIPDIR/acs.bin fip/ + $ cp $FIPDIR/bl21.bin fip/ + $ cp $FIPDIR/bl30.bin fip/ + $ cp $FIPDIR/bl301.bin fip/ + $ cp $FIPDIR/bl31.img fip/ + $ cp u-boot.bin fip/bl33.bin + $ $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin \ + --bl31 fip/bl31.img \ + --bl33 fip/bl33.bin \ + fip/fip.bin + $ sed -i 's/\x73\x02\x08\x91/\x1F\x20\x03\xD5/' fip/bl2.bin + $ python3 $FIPDIR/acs_tool.py fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + $ $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + $ cat fip/bl2_new.bin fip/fip.bin > fip/boot_new.bin + $ $FIPDIR/aml_encrypt_gxb --bootsig \ + --input fip/boot_new.bin + --output fip/u-boot.bin + +Then write U-Boot to SD or eMMC with: + +.. code-block:: bash + + $ DEV=/dev/boot_device + $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 conv=fsync + $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 seek=9 skip=8 count=87 conv=fsync,notrunc + $ dd if=/dev/zero of=fip/u-boot.bin.gxbb bs=512 seek=8 count=1 conv=fsync,notrunc + $ dd if=bl1.bin.hardkernel of=fip/u-boot.bin.gxbb bs=512 seek=2 skip=2 count=1 conv=fsync,notrunc + $ ./aml_chksum fip/u-boot.bin.gxbb + $ dd if=fip/u-boot.bin.gxbb of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.gxbb of=$DEV conv=fsync,notrunc bs=1 count=440 -- cgit v1.2.3 From 5566cf2a6d9ec677684e6200acb4ad39287e9678 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 15 Jun 2023 11:12:42 +0100 Subject: riscv: dts: drop microchip from dts filenames The original names picked for the DT doesn't match Linux's naming scheme and it was renamed there a while ago. Rename it in U-Boot to allow easily syncing dts between the two projects. Reviewed-by: Rick Chen Reviewed-by: Padmarao Begari Signed-off-by: Conor Dooley --- arch/riscv/dts/Makefile | 2 +- .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 - arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 136 ----- arch/riscv/dts/microchip-mpfs.dtsi | 569 --------------------- arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi | 14 + arch/riscv/dts/mpfs-icicle-kit.dts | 136 +++++ arch/riscv/dts/mpfs.dtsi | 569 +++++++++++++++++++++ configs/microchip_mpfs_icicle_defconfig | 2 +- doc/board/microchip/mpfs_icicle.rst | 6 +- 9 files changed, 724 insertions(+), 724 deletions(-) delete mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi delete mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts delete mode 100644 arch/riscv/dts/microchip-mpfs.dtsi create mode 100644 arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi create mode 100644 arch/riscv/dts/mpfs-icicle-kit.dts create mode 100644 arch/riscv/dts/mpfs.dtsi (limited to 'doc') diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 79a58694f5..1d61eb8020 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb -dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi deleted file mode 100644 index f60283fb6b..0000000000 --- a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2020 Microchip Technology Inc. - * Padmarao Begari - */ - -/ { - aliases { - cpu1 = &cpu1; - cpu2 = &cpu2; - cpu3 = &cpu3; - cpu4 = &cpu4; - }; -}; diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts deleted file mode 100644 index c3f58e2d56..0000000000 --- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2021-2022 Microchip Technology Inc. - * Padmarao Begari - */ - -/dts-v1/; - -#include "microchip-mpfs.dtsi" - -/* Clock frequency (in Hz) of the rtcclk */ -#define RTCCLK_FREQ 1000000 - -/ { - model = "Microchip PolarFire-SoC Icicle Kit"; - compatible = "microchip,mpfs-icicle-reference-rtlv2210", - "microchip,mpfs-icicle-kit", "microchip,mpfs"; - - aliases { - serial1 = &uart1; - ethernet0 = &mac1; - spi0 = &qspi; - }; - - chosen { - stdout-path = "serial1"; - }; - - cpus { - timebase-frequency = ; - }; - - ddrc_cache_lo: memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x40000000>; - status = "okay"; - }; - - ddrc_cache_hi: memory@1040000000 { - device_type = "memory"; - reg = <0x10 0x40000000 0x0 0x40000000>; - status = "okay"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hss_payload: region@BFC00000 { - reg = <0x0 0xBFC00000 0x0 0x400000>; - no-map; - }; - }; -}; - -&refclk { - clock-frequency = <125000000>; -}; - -&uart1 { - status = "okay"; -}; - -&mmc { - status = "okay"; - - bus-width = <4>; - disable-wp; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <100000>; - - pac193x: pac193x@10 { - compatible = "microchip,pac1934"; - reg = <0x10>; - samp-rate = <64>; - status = "okay"; - ch1: channel0 { - uohms-shunt-res = <10000>; - rail-name = "VDDREG"; - channel_enabled; - }; - ch2: channel1 { - uohms-shunt-res = <10000>; - rail-name = "VDDA25"; - channel_enabled; - }; - ch3: channel2 { - uohms-shunt-res = <10000>; - rail-name = "VDD25"; - channel_enabled; - }; - ch4: channel3 { - uohms-shunt-res = <10000>; - rail-name = "VDDA_REG"; - channel_enabled; - }; - }; -}; - -&mac1 { - status = "okay"; - phy-mode = "sgmii"; - phy-handle = <&phy1>; - phy1: ethernet-phy@9 { - reg = <9>; - ti,fifo-depth = <0x1>; - }; -}; - -&qspi { - status = "okay"; - num-cs = <1>; - - flash0: flash@0 { - compatible = "spi-nand"; - reg = <0x0>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-max-frequency = <20000000>; - spi-cpol; - spi-cpha; - }; -}; diff --git a/arch/riscv/dts/microchip-mpfs.dtsi b/arch/riscv/dts/microchip-mpfs.dtsi deleted file mode 100644 index 891dd0918b..0000000000 --- a/arch/riscv/dts/microchip-mpfs.dtsi +++ /dev/null @@ -1,569 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* Copyright (c) 2020-2021 Microchip Technology Inc */ - -#include "dt-bindings/clock/microchip-mpfs-clock.h" -#include "dt-bindings/interrupt-controller/microchip-mpfs-plic.h" -#include "dt-bindings/interrupt-controller/riscv-hart.h" - -/ { - #address-cells = <2>; - #size-cells = <2>; - model = "Microchip PolarFire SoC"; - compatible = "microchip,mpfs"; - - chosen { - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "sifive,e51", "sifive,rocket0", "riscv"; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <16384>; - reg = <0>; - riscv,isa = "rv64imac"; - clocks = <&clkcfg CLK_CPU>; - status = "disabled"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; - cpu0_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - - cpu1: cpu@1 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <1>; - riscv,isa = "rv64imafdc"; - clocks = <&clkcfg CLK_CPU>; - tlb-split; - status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - - cpu2: cpu@2 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <2>; - riscv,isa = "rv64imafdc"; - clocks = <&clkcfg CLK_CPU>; - tlb-split; - status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; - cpu2_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - - cpu3: cpu@3 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <3>; - riscv,isa = "rv64imafdc"; - clocks = <&clkcfg CLK_CPU>; - tlb-split; - status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; - cpu3_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - - cpu4: cpu@4 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <4>; - riscv,isa = "rv64imafdc"; - clocks = <&clkcfg CLK_CPU>; - tlb-split; - status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; - cpu4_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - - refclk: refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "microchip,mpfs-soc", "simple-bus"; - ranges; - - clint: clint@2000000 { - compatible = "sifive,clint0"; - reg = <0x0 0x2000000 0x0 0xC000>; - interrupts-extended = - <&cpu0_intc HART_INT_M_SOFT &cpu0_intc HART_INT_M_TIMER - &cpu1_intc HART_INT_M_SOFT &cpu1_intc HART_INT_M_TIMER - &cpu2_intc HART_INT_M_SOFT &cpu2_intc HART_INT_M_TIMER - &cpu3_intc HART_INT_M_SOFT &cpu3_intc HART_INT_M_TIMER - &cpu4_intc HART_INT_M_SOFT &cpu4_intc HART_INT_M_TIMER>; - }; - - cachecontroller: cache-controller@2010000 { - compatible = "sifive,fu540-c000-ccache", "cache"; - reg = <0x0 0x2010000 0x0 0x1000>; - interrupt-parent = <&plic>; - interrupts = ; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <1024>; - cache-size = <2097152>; - cache-unified; - }; - - pdma: pdma@3000000 { - compatible = "microchip,mpfs-pdma-uio","sifive,fu540-c000-pdma"; - reg = <0x0 0x3000000 0x0 0x8000>; - interrupt-parent = <&plic>; - interrupts = ; - #dma-cells = <1>; - }; - - plic: interrupt-controller@c000000 { - compatible = "sifive,plic-1.0.0"; - reg = <0x0 0xc000000 0x0 0x4000000>; - #interrupt-cells = <1>; - riscv,ndev = <186>; - interrupt-controller; - interrupts-extended = <&cpu0_intc HART_INT_M_EXT - &cpu1_intc HART_INT_M_EXT &cpu1_intc HART_INT_S_EXT - &cpu2_intc HART_INT_M_EXT &cpu2_intc HART_INT_S_EXT - &cpu3_intc HART_INT_M_EXT &cpu3_intc HART_INT_S_EXT - &cpu4_intc HART_INT_M_EXT &cpu4_intc HART_INT_S_EXT>; - }; - - clkcfg: clkcfg@20002000 { - compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; - reg-names = "mss_sysreg"; - clocks = <&refclk>; - #clock-cells = <1>; - clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ - "mac0", "mac1", "mmc", "timer", /* 4-7 */ - "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ - "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ - "i2c1", "can0", "can1", "usb", /* 16-19 */ - "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ - "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ - "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ - }; - - /* Common node entry for eMMC/SD */ - mmc: mmc@20008000 { - compatible = "microchip,mpfs-sd4hc","cdns,sd4hc"; - reg = <0x0 0x20008000 0x0 0x1000>; - clocks = <&clkcfg CLK_MMC>; - interrupt-parent = <&plic>; - interrupts = ; - max-frequency = <200000000>; - status = "disabled"; - }; - - uart0: serial@20000000 { - compatible = "ns16550a"; - reg = <0x0 0x20000000 0x0 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupt-parent = <&plic>; - interrupts = ; - clocks = <&clkcfg CLK_MMUART0>; - status = "disabled"; /* Reserved for the HSS */ - }; - - uart1: serial@20100000 { - compatible = "ns16550a"; - reg = <0x0 0x20100000 0x0 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupt-parent = <&plic>; - interrupts = ; - clocks = <&clkcfg CLK_MMUART1>; - status = "disabled"; - }; - - uart2: serial@20102000 { - compatible = "ns16550a"; - reg = <0x0 0x20102000 0x0 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupt-parent = <&plic>; - interrupts = ; - clocks = <&clkcfg CLK_MMUART2>; - status = "disabled"; - }; - - uart3: serial@20104000 { - compatible = "ns16550a"; - reg = <0x0 0x20104000 0x0 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupt-parent = <&plic>; - interrupts = ; - clocks = <&clkcfg CLK_MMUART3>; - status = "disabled"; - }; - - uart4: serial@20106000 { - compatible = "ns16550a"; - reg = <0x0 0x20106000 0x0 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupt-parent = <&plic>; - interrupts = ; - clocks = <&clkcfg CLK_MMUART4>; - status = "disabled"; - }; - - spi0: spi@20108000 { - compatible = "microchip,mpfs-spi"; - reg = <0x0 0x20108000 0x0 0x1000>; - clocks = <&clkcfg CLK_SPI0>; - interrupt-parent = <&plic>; - interrupts = ; - num-cs = <8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@20109000 { - compatible = "microchip,mpfs-spi"; - reg = <0x0 0x20109000 0x0 0x1000>; - clocks = <&clkcfg CLK_SPI1>; - interrupt-parent = <&plic>; - interrupts = ; - num-cs = <8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@2010a000 { - compatible = "microchip,mpfs-i2c"; - reg = <0x0 0x2010a000 0x0 0x1000>; - clocks = <&clkcfg CLK_I2C0>; - interrupt-parent = <&plic>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@2010b000 { - compatible = "microchip,mpfs-i2c"; - reg = <0x0 0x2010b000 0x0 0x1000>; - clocks = <&clkcfg CLK_I2C1>; - interrupt-parent = <&plic>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@2010c000 { - compatible = "microchip,mpfs-can-uio"; - reg = <0x0 0x2010c000 0x0 0x1000>; - clocks = <&clkcfg CLK_CAN0>; - interrupt-parent = <&plic>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can1: can@2010d000 { - compatible = "microchip,mpfs-can-uio"; - reg = <0x0 0x2010d000 0x0 0x1000>; - clocks = <&clkcfg CLK_CAN1>; - interrupt-parent = <&plic>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mac0: ethernet@20110000 { - compatible = "cdns,macb"; - reg = <0x0 0x20110000 0x0 0x2000>; - clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; - clock-names = "pclk", "hclk"; - interrupt-parent = <&plic>; - interrupts = ; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mac1: ethernet@20112000 { - compatible = "cdns,macb"; - reg = <0x0 0x20112000 0x0 0x2000>; - clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; - clock-names = "pclk", "hclk"; - interrupt-parent = <&plic>; - interrupts = ; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gpio0: gpio@20120000 { - compatible = "microchip,mpfs-gpio"; - reg = <0x0 0x20120000 0x0 0x1000>; - reg-names = "control"; - clocks = <&clkcfg CLK_GPIO0>; - interrupt-parent = <&plic>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; - }; - - gpio1: gpio@20121000 { - compatible = "microchip,mpfs-gpio"; - reg = <000 0x20121000 0x0 0x1000>; - reg-names = "control"; - clocks = <&clkcfg CLK_GPIO1>; - interrupt-parent = <&plic>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; - }; - - gpio2: gpio@20122000 { - compatible = "microchip,mpfs-gpio"; - reg = <0x0 0x20122000 0x0 0x1000>; - reg-names = "control"; - clocks = <&clkcfg CLK_GPIO2>; - interrupt-parent = <&plic>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; - }; - - rtc: rtc@20124000 { - compatible = "microchip,mpfs-rtc"; - reg = <0x0 0x20124000 0x0 0x1000>; - clocks = <&clkcfg CLK_RTC>; - clock-names = "rtc"; - interrupt-parent = <&plic>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - usb: usb@20201000 { - compatible = "microchip,mpfs-usb-host"; - reg = <0x0 0x20201000 0x0 0x1000>; - reg-names = "mc","control"; - clocks = <&clkcfg CLK_USB>; - interrupt-parent = <&plic>; - interrupts = ; - interrupt-names = "dma","mc"; - dr_mode = "host"; - status = "disabled"; - }; - - qspi: qspi@21000000 { - compatible = "microchip,mpfs-qspi"; - reg = <0x0 0x21000000 0x0 0x1000>; - clocks = <&clkcfg CLK_QSPI>; - interrupt-parent = <&plic>; - interrupts = ; - num-cs = <8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mbox: mailbox@37020000 { - compatible = "microchip,mpfs-mailbox"; - reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; - interrupt-parent = <&plic>; - interrupts = ; - #mbox-cells = <1>; - status = "disabled"; - }; - - pcie: pcie@2000000000 { - compatible = "microchip,pcie-host-1.0"; - #address-cells = <0x3>; - #interrupt-cells = <0x1>; - #size-cells = <0x2>; - device_type = "pci"; - reg = <0x20 0x0 0x0 0x8000000 0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; - clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>; - clock-names = "fic0", "fic1", "fic3"; - bus-range = <0x0 0x7f>; - interrupt-parent = <&plic>; - interrupts = ; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - interrupt-map-mask = <0 0 0 7>; - ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; - msi-parent = <&pcie>; - msi-controller; - mchp,axi-m-atr0 = <0x10 0x0>; - status = "disabled"; - pcie_intc: legacy-interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - syscontroller: syscontroller { - compatible = "microchip,mpfs-sys-controller"; - #address-cells = <1>; - #size-cells = <1>; - mboxes = <&mbox 0>; - }; - - hwrandom: hwrandom { - compatible = "microchip,mpfs-rng"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; - - serialnum: serialnum { - compatible = "microchip,mpfs-serial-number"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; - - fpgadigest: fpgadigest { - compatible = "microchip,mpfs-digest"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; - - devicecert: cert { - compatible = "microchip,mpfs-device-cert"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; - - signature: signature { - compatible = "microchip,mpfs-signature"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; - }; -}; diff --git a/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi b/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi new file mode 100644 index 0000000000..f60283fb6b --- /dev/null +++ b/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari + */ + +/ { + aliases { + cpu1 = &cpu1; + cpu2 = &cpu2; + cpu3 = &cpu3; + cpu4 = &cpu4; + }; +}; diff --git a/arch/riscv/dts/mpfs-icicle-kit.dts b/arch/riscv/dts/mpfs-icicle-kit.dts new file mode 100644 index 0000000000..3c56400b92 --- /dev/null +++ b/arch/riscv/dts/mpfs-icicle-kit.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021-2022 Microchip Technology Inc. + * Padmarao Begari + */ + +/dts-v1/; + +#include "mpfs.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + model = "Microchip PolarFire-SoC Icicle Kit"; + compatible = "microchip,mpfs-icicle-reference-rtlv2210", + "microchip,mpfs-icicle-kit", "microchip,mpfs"; + + aliases { + serial1 = &uart1; + ethernet0 = &mac1; + spi0 = &qspi; + }; + + chosen { + stdout-path = "serial1"; + }; + + cpus { + timebase-frequency = ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + status = "okay"; + }; + + ddrc_cache_hi: memory@1040000000 { + device_type = "memory"; + reg = <0x10 0x40000000 0x0 0x40000000>; + status = "okay"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hss_payload: region@BFC00000 { + reg = <0x0 0xBFC00000 0x0 0x400000>; + no-map; + }; + }; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&uart1 { + status = "okay"; +}; + +&mmc { + status = "okay"; + + bus-width = <4>; + disable-wp; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; + + pac193x: pac193x@10 { + compatible = "microchip,pac1934"; + reg = <0x10>; + samp-rate = <64>; + status = "okay"; + ch1: channel0 { + uohms-shunt-res = <10000>; + rail-name = "VDDREG"; + channel_enabled; + }; + ch2: channel1 { + uohms-shunt-res = <10000>; + rail-name = "VDDA25"; + channel_enabled; + }; + ch3: channel2 { + uohms-shunt-res = <10000>; + rail-name = "VDD25"; + channel_enabled; + }; + ch4: channel3 { + uohms-shunt-res = <10000>; + rail-name = "VDDA_REG"; + channel_enabled; + }; + }; +}; + +&mac1 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy1>; + phy1: ethernet-phy@9 { + reg = <9>; + ti,fifo-depth = <0x1>; + }; +}; + +&qspi { + status = "okay"; + num-cs = <1>; + + flash0: flash@0 { + compatible = "spi-nand"; + reg = <0x0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-max-frequency = <20000000>; + spi-cpol; + spi-cpha; + }; +}; diff --git a/arch/riscv/dts/mpfs.dtsi b/arch/riscv/dts/mpfs.dtsi new file mode 100644 index 0000000000..891dd0918b --- /dev/null +++ b/arch/riscv/dts/mpfs.dtsi @@ -0,0 +1,569 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* Copyright (c) 2020-2021 Microchip Technology Inc */ + +#include "dt-bindings/clock/microchip-mpfs-clock.h" +#include "dt-bindings/interrupt-controller/microchip-mpfs-plic.h" +#include "dt-bindings/interrupt-controller/riscv-hart.h" + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Microchip PolarFire SoC"; + compatible = "microchip,mpfs"; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "sifive,e51", "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + clocks = <&clkcfg CLK_CPU>; + status = "disabled"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu1: cpu@1 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; + tlb-split; + status = "okay"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu2: cpu@2 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; + tlb-split; + status = "okay"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu3: cpu@3 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; + tlb-split; + status = "okay"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu4: cpu@4 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; + tlb-split; + status = "okay"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + refclk: refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "microchip,mpfs-soc", "simple-bus"; + ranges; + + clint: clint@2000000 { + compatible = "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0xC000>; + interrupts-extended = + <&cpu0_intc HART_INT_M_SOFT &cpu0_intc HART_INT_M_TIMER + &cpu1_intc HART_INT_M_SOFT &cpu1_intc HART_INT_M_TIMER + &cpu2_intc HART_INT_M_SOFT &cpu2_intc HART_INT_M_TIMER + &cpu3_intc HART_INT_M_SOFT &cpu3_intc HART_INT_M_TIMER + &cpu4_intc HART_INT_M_SOFT &cpu4_intc HART_INT_M_TIMER>; + }; + + cachecontroller: cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache", "cache"; + reg = <0x0 0x2010000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = ; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + }; + + pdma: pdma@3000000 { + compatible = "microchip,mpfs-pdma-uio","sifive,fu540-c000-pdma"; + reg = <0x0 0x3000000 0x0 0x8000>; + interrupt-parent = <&plic>; + interrupts = ; + #dma-cells = <1>; + }; + + plic: interrupt-controller@c000000 { + compatible = "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + #interrupt-cells = <1>; + riscv,ndev = <186>; + interrupt-controller; + interrupts-extended = <&cpu0_intc HART_INT_M_EXT + &cpu1_intc HART_INT_M_EXT &cpu1_intc HART_INT_S_EXT + &cpu2_intc HART_INT_M_EXT &cpu2_intc HART_INT_S_EXT + &cpu3_intc HART_INT_M_EXT &cpu3_intc HART_INT_S_EXT + &cpu4_intc HART_INT_M_EXT &cpu4_intc HART_INT_S_EXT>; + }; + + clkcfg: clkcfg@20002000 { + compatible = "microchip,mpfs-clkcfg"; + reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; + reg-names = "mss_sysreg"; + clocks = <&refclk>; + #clock-cells = <1>; + clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ + "mac0", "mac1", "mmc", "timer", /* 4-7 */ + "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ + "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ + "i2c1", "can0", "can1", "usb", /* 16-19 */ + "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ + "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ + "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ + }; + + /* Common node entry for eMMC/SD */ + mmc: mmc@20008000 { + compatible = "microchip,mpfs-sd4hc","cdns,sd4hc"; + reg = <0x0 0x20008000 0x0 0x1000>; + clocks = <&clkcfg CLK_MMC>; + interrupt-parent = <&plic>; + interrupts = ; + max-frequency = <200000000>; + status = "disabled"; + }; + + uart0: serial@20000000 { + compatible = "ns16550a"; + reg = <0x0 0x20000000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = ; + clocks = <&clkcfg CLK_MMUART0>; + status = "disabled"; /* Reserved for the HSS */ + }; + + uart1: serial@20100000 { + compatible = "ns16550a"; + reg = <0x0 0x20100000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = ; + clocks = <&clkcfg CLK_MMUART1>; + status = "disabled"; + }; + + uart2: serial@20102000 { + compatible = "ns16550a"; + reg = <0x0 0x20102000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = ; + clocks = <&clkcfg CLK_MMUART2>; + status = "disabled"; + }; + + uart3: serial@20104000 { + compatible = "ns16550a"; + reg = <0x0 0x20104000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = ; + clocks = <&clkcfg CLK_MMUART3>; + status = "disabled"; + }; + + uart4: serial@20106000 { + compatible = "ns16550a"; + reg = <0x0 0x20106000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = ; + clocks = <&clkcfg CLK_MMUART4>; + status = "disabled"; + }; + + spi0: spi@20108000 { + compatible = "microchip,mpfs-spi"; + reg = <0x0 0x20108000 0x0 0x1000>; + clocks = <&clkcfg CLK_SPI0>; + interrupt-parent = <&plic>; + interrupts = ; + num-cs = <8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@20109000 { + compatible = "microchip,mpfs-spi"; + reg = <0x0 0x20109000 0x0 0x1000>; + clocks = <&clkcfg CLK_SPI1>; + interrupt-parent = <&plic>; + interrupts = ; + num-cs = <8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c@2010a000 { + compatible = "microchip,mpfs-i2c"; + reg = <0x0 0x2010a000 0x0 0x1000>; + clocks = <&clkcfg CLK_I2C0>; + interrupt-parent = <&plic>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@2010b000 { + compatible = "microchip,mpfs-i2c"; + reg = <0x0 0x2010b000 0x0 0x1000>; + clocks = <&clkcfg CLK_I2C1>; + interrupt-parent = <&plic>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can0: can@2010c000 { + compatible = "microchip,mpfs-can-uio"; + reg = <0x0 0x2010c000 0x0 0x1000>; + clocks = <&clkcfg CLK_CAN0>; + interrupt-parent = <&plic>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can1: can@2010d000 { + compatible = "microchip,mpfs-can-uio"; + reg = <0x0 0x2010d000 0x0 0x1000>; + clocks = <&clkcfg CLK_CAN1>; + interrupt-parent = <&plic>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mac0: ethernet@20110000 { + compatible = "cdns,macb"; + reg = <0x0 0x20110000 0x0 0x2000>; + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; + clock-names = "pclk", "hclk"; + interrupt-parent = <&plic>; + interrupts = ; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mac1: ethernet@20112000 { + compatible = "cdns,macb"; + reg = <0x0 0x20112000 0x0 0x2000>; + clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; + clock-names = "pclk", "hclk"; + interrupt-parent = <&plic>; + interrupts = ; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gpio0: gpio@20120000 { + compatible = "microchip,mpfs-gpio"; + reg = <0x0 0x20120000 0x0 0x1000>; + reg-names = "control"; + clocks = <&clkcfg CLK_GPIO0>; + interrupt-parent = <&plic>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpio1: gpio@20121000 { + compatible = "microchip,mpfs-gpio"; + reg = <000 0x20121000 0x0 0x1000>; + reg-names = "control"; + clocks = <&clkcfg CLK_GPIO1>; + interrupt-parent = <&plic>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpio2: gpio@20122000 { + compatible = "microchip,mpfs-gpio"; + reg = <0x0 0x20122000 0x0 0x1000>; + reg-names = "control"; + clocks = <&clkcfg CLK_GPIO2>; + interrupt-parent = <&plic>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + rtc: rtc@20124000 { + compatible = "microchip,mpfs-rtc"; + reg = <0x0 0x20124000 0x0 0x1000>; + clocks = <&clkcfg CLK_RTC>; + clock-names = "rtc"; + interrupt-parent = <&plic>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usb: usb@20201000 { + compatible = "microchip,mpfs-usb-host"; + reg = <0x0 0x20201000 0x0 0x1000>; + reg-names = "mc","control"; + clocks = <&clkcfg CLK_USB>; + interrupt-parent = <&plic>; + interrupts = ; + interrupt-names = "dma","mc"; + dr_mode = "host"; + status = "disabled"; + }; + + qspi: qspi@21000000 { + compatible = "microchip,mpfs-qspi"; + reg = <0x0 0x21000000 0x0 0x1000>; + clocks = <&clkcfg CLK_QSPI>; + interrupt-parent = <&plic>; + interrupts = ; + num-cs = <8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mbox: mailbox@37020000 { + compatible = "microchip,mpfs-mailbox"; + reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; + interrupt-parent = <&plic>; + interrupts = ; + #mbox-cells = <1>; + status = "disabled"; + }; + + pcie: pcie@2000000000 { + compatible = "microchip,pcie-host-1.0"; + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + device_type = "pci"; + reg = <0x20 0x0 0x0 0x8000000 0x0 0x43000000 0x0 0x10000>; + reg-names = "cfg", "apb"; + clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>; + clock-names = "fic0", "fic1", "fic3"; + bus-range = <0x0 0x7f>; + interrupt-parent = <&plic>; + interrupts = ; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent = <&pcie>; + msi-controller; + mchp,axi-m-atr0 = <0x10 0x0>; + status = "disabled"; + pcie_intc: legacy-interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + syscontroller: syscontroller { + compatible = "microchip,mpfs-sys-controller"; + #address-cells = <1>; + #size-cells = <1>; + mboxes = <&mbox 0>; + }; + + hwrandom: hwrandom { + compatible = "microchip,mpfs-rng"; + #address-cells = <1>; + #size-cells = <1>; + syscontroller = <&syscontroller>; + }; + + serialnum: serialnum { + compatible = "microchip,mpfs-serial-number"; + #address-cells = <1>; + #size-cells = <1>; + syscontroller = <&syscontroller>; + }; + + fpgadigest: fpgadigest { + compatible = "microchip,mpfs-digest"; + #address-cells = <1>; + #size-cells = <1>; + syscontroller = <&syscontroller>; + }; + + devicecert: cert { + compatible = "microchip,mpfs-device-cert"; + #address-cells = <1>; + #size-cells = <1>; + syscontroller = <&syscontroller>; + }; + + signature: signature { + compatible = "microchip,mpfs-signature"; + #address-cells = <1>; + #size-cells = <1>; + syscontroller = <&syscontroller>; + }; + }; +}; diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index c03c8ec6ec..fa49d3865f 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x2000 -CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit" +CONFIG_DEFAULT_DEVICE_TREE="mpfs-icicle-kit" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_MEM_TOP_HIDE=0x400000 CONFIG_SYS_LOAD_ADDR=0x80200000 diff --git a/doc/board/microchip/mpfs_icicle.rst b/doc/board/microchip/mpfs_icicle.rst index 09c2c6a9c1..1464e536e9 100644 --- a/doc/board/microchip/mpfs_icicle.rst +++ b/doc/board/microchip/mpfs_icicle.rst @@ -134,7 +134,7 @@ Build OpenSBI .. code-block:: none make PLATFORM=generic FW_PAYLOAD_PATH=/u-boot.bin - FW_FDT_PATH=/arch/riscv/dts/microchip-mpfs-icicle-kit-.dtb + FW_FDT_PATH=/arch/riscv/dts/mpfs-icicle-kit-.dtb 3. Output "fw_payload.bin" file available at "/build/platform/generic/firmware/fw_payload.bin" @@ -277,14 +277,14 @@ load uImage (with initramfs). done Bytes transferred = 14482480 (dcfc30 hex) - RISC-V # tftpboot ${fdt_addr_r} microchip-mpfs-icicle-kit.dtb + RISC-V # tftpboot ${fdt_addr_r} mpfs-icicle-kit.dtb ethernet@20112000: PHY present at 9 ethernet@20112000: Starting autonegotiation... ethernet@20112000: Autonegotiation complete ethernet@20112000: link up, 1000Mbps full-duplex (lpa: 0x7800) Using ethernet@20112000 device TFTP from server 192.168.1.3; our IP address is 192.168.1.5 - Filename 'microchip-mpfs-icicle-kit.dtb'. + Filename 'mpfs-icicle-kit.dtb'. Load address: 0x82200000 Loading: # 2.5 MiB/s -- cgit v1.2.3