From 3e12f7f03656ebab03c97913882abf83ca00c9f6 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 18 Jul 2019 00:34:30 -0700 Subject: doc: arch: Convert README.ARC to reST Convert plain text documentation to reStructuredText format and add it to Sphinx TOC tree. No essential content change. Signed-off-by: Bin Meng --- doc/README.ARC | 27 --------------------------- doc/arch/arc.rst | 32 ++++++++++++++++++++++++++++++++ doc/arch/index.rst | 1 + 3 files changed, 33 insertions(+), 27 deletions(-) delete mode 100644 doc/README.ARC create mode 100644 doc/arch/arc.rst (limited to 'doc') diff --git a/doc/README.ARC b/doc/README.ARC deleted file mode 100644 index 5f414fb2fa..0000000000 --- a/doc/README.ARC +++ /dev/null @@ -1,27 +0,0 @@ -Synopsys' DesignWare(r) ARC(r) Processors are a family of 32-bit CPUs -that SoC designers can optimize for a wide range of uses, from deeply embedded -to high-performance host applications. - -More information on ARC cores avaialble here: -http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx - -Designers can differentiate their products by using patented configuration -technology to tailor each ARC processor instance to meet specific performance, -power and area requirements. - -The DesignWare ARC processors are also extendable, allowing designers to add -their own custom instructions that dramatically increase performance. - -Synopsys' ARC processors have been used by over 170 customers worldwide who -collectively ship more than 1 billion ARC-based chips annually. - -All DesignWare ARC processors utilize a 16-/32-bit ISA that provides excellent -performance and code density for embedded and host SoC applications. - -The RISC microprocessors are synthesizable and can be implemented in any foundry -or process, and are supported by a complete suite of development tools. - -The ARC GNU toolchain with support for all ARC Processors can be downloaded -from here (available pre-built toolchains as well): - -https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases diff --git a/doc/arch/arc.rst b/doc/arch/arc.rst new file mode 100644 index 0000000000..f8e04a34f1 --- /dev/null +++ b/doc/arch/arc.rst @@ -0,0 +1,32 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +ARC +=== + +Synopsys' DesignWare(r) ARC(r) Processors are a family of 32-bit CPUs +that SoC designers can optimize for a wide range of uses, from deeply embedded +to high-performance host applications. + +More information on ARC cores avaialble here: +http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx + +Designers can differentiate their products by using patented configuration +technology to tailor each ARC processor instance to meet specific performance, +power and area requirements. + +The DesignWare ARC processors are also extendable, allowing designers to add +their own custom instructions that dramatically increase performance. + +Synopsys' ARC processors have been used by over 170 customers worldwide who +collectively ship more than 1 billion ARC-based chips annually. + +All DesignWare ARC processors utilize a 16-/32-bit ISA that provides excellent +performance and code density for embedded and host SoC applications. + +The RISC microprocessors are synthesizable and can be implemented in any foundry +or process, and are supported by a complete suite of development tools. + +The ARC GNU toolchain with support for all ARC Processors can be downloaded +from here (available pre-built toolchains as well): + +https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases diff --git a/doc/arch/index.rst b/doc/arch/index.rst index 000f5de634..93fbb7ea66 100644 --- a/doc/arch/index.rst +++ b/doc/arch/index.rst @@ -6,6 +6,7 @@ Architecture-specific doc .. toctree:: :maxdepth: 2 + arc arm64 mips nds32 -- cgit v1.2.3