From 53f27dda29913631c42af498e266e17442e44972 Mon Sep 17 00:00:00 2001 From: Hai Pham Date: Tue, 28 Feb 2023 22:37:02 +0100 Subject: clk: renesas: Add R8A779G0 V4H clock tables Add clock tables for R8A779G0 V4H SoC from Linux next commit 058f4df42121 ("Add linux-next specific files for 20230228") There is an adjustment to the clock tables to make them easier suitable for U-Boot, PLL2 is not treated as GEN4 PLL type PLL2_VAR, but rather a plain PLL2. This should be sufficient until PLL2_VAR is implemented in the clock core. Reviewed-by: Marek Vasut Signed-off-by: Hai Pham Signed-off-by: Marek Vasut [Marek: Sync with Linux next 20230228 . Update from CLK to CPG core driver Treat PLL2 as non-PLL2_VAR for now] --- drivers/clk/renesas/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/clk/renesas/Kconfig') diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index cf28aed7c4..45671c6925 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -137,3 +137,9 @@ config CLK_R8A779F0 depends on CLK_RCAR_GEN3 help Enable this to support the clocks on Renesas R8A779F0 SoC. + +config CLK_R8A779G0 + bool "Renesas R8A779G0 clock driver" + depends on CLK_RCAR_GEN3 + help + Enable this to support the clocks on Renesas R8A779G0 SoC. -- cgit v1.2.3