From 217273cd441fe3d00a1bdad143dcb656854963f9 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 27 Jul 2017 12:54:02 +0800 Subject: rockchip: clk: remove RATE_TO_DIV Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC clock driver. Add or fix the div-field overflow check at the same time. Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich Acked-by: Philipp Tomsich --- drivers/clk/rockchip/clk_rk322x.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers/clk/rockchip/clk_rk322x.c') diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index a1a0aff8a9..d7f6a3c313 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -26,9 +26,6 @@ enum { OUTPUT_MIN_HZ = 24 * 1000000, }; -#define RATE_TO_DIV(input_rate, output_rate) \ - ((input_rate) / (output_rate) - 1); - #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ @@ -253,8 +250,9 @@ static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate, /* mmc clock defaulg div 2 internal, need provide double in cru */ src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); - if (src_clk_div > 0x7f) { + if (src_clk_div > 128) { src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); + assert(src_clk_div - 1 < 128); mux = EMMC_SEL_24M; } else { mux = EMMC_SEL_GPLL; -- cgit v1.2.3