From 526aa92960cfea5d6799b5a6aae89e4e646acc67 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 8 Feb 2018 17:20:46 +0100 Subject: clk: clk_stm32f: Fix RCC_PLLSAICFGR mask defines Use the correct name for RCC_PLLSAICFGR_PLLSAIx_MASK masks. Signed-off-by: Patrice Chotard --- drivers/clk/clk_stm32f.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index 41d8b5e5c8..7d89906379 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -55,8 +55,8 @@ #define RCC_CFGR_PPRE1_SHIFT 10 #define RCC_CFGR_PPRE2_SHIFT 13 -#define RCC_PLLCFGR_PLLSAIN_MASK GENMASK(14, 6) -#define RCC_PLLCFGR_PLLSAIP_MASK GENMASK(17, 16) +#define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6) +#define RCC_PLLSAICFGR_PLLSAIP_MASK GENMASK(17, 16) #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16 #define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16) @@ -247,9 +247,9 @@ static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv, if (pllsai) { /* PLL48CLK is selected from PLLSAI, get PLLSAI value */ pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); - pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIN_MASK) + pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK) >> RCC_PLLSAICFGR_PLLSAIN_SHIFT); - pllsaip = ((((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK) + pllsaip = ((((readl(®s->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIP_MASK) >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1); return ((priv->hse_rate / pllm) * pllsain) / pllsaip; } -- cgit v1.2.3