From 4a41a1a6f06ed86feae9f52d2e8ece5cce0a850d Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 30 Dec 2019 09:58:52 +0800 Subject: ddr: imx8m: Add DRAM PLL to generate 1000Mhz output We will generate DRAM 4000MT/s as default for i.MX8MP. So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller. Signed-off-by: Peng Fan --- drivers/ddr/imx/imx8m/ddrphy_utils.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/ddr') diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c index 863fb43897..9ac7ca923c 100644 --- a/drivers/ddr/imx/imx8m/ddrphy_utils.c +++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c @@ -106,6 +106,10 @@ int wait_ddrphy_training_complete(void) void ddrphy_init_set_dfi_clk(unsigned int drate) { switch (drate) { + case 4000: + dram_pll_init(MHZ(1000)); + dram_disable_bypass(); + break; case 3200: dram_pll_init(MHZ(800)); dram_disable_bypass(); -- cgit v1.2.3